EV2018 Gbit/s Differential Crosspoint Switch Evaluation Boar

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EV2018 Gbit/s Differential Crosspoint Switch Evaluation Boar

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Part Number EV2018 September 1999
EV2018
Gbit/s Differential Crosspoint Switch
Evaluation Board Overview
EVALUATION BOARD
This document describes operation usage S2018 Evaluation Board. evaluation board allows users become familiar with functionality S2018 Differential Crosspoint Switch. Specifically, cross-talk, propagation delay, rise/fall time basic performance tested using evaluation board. This document provides complete board description, explains various test configurations, contains bill materials with corresponding schematic. This document should used conjunction with S2018 data sheet application note. Figure shows outline S2018 Evaluation Board.
Figure S2018 Evaluation Board
DIN9P
DIN9N
DIN9P
DIN9
IADDR0 IADDR1 IADDR2 IADDR3 IADDR4
OADDR0 OADDR1 OADDR2 OADDR3 OADDR4 V-ADJ1 V-ADJ2 V-ADJ3 CONFIGN LOADN
IADDR0 IADDR1 IADDR2 IADDR3 IADDR4 TO-DUT FROM-SW CONFIGN LOADN
S2018TB
DOUT1
DOUT15P
TO-DUT FROM-SW
DOUT16
TO-DUT FROM-SW OADDR0 OADDR1 OADDR2 OADDR3 OADDR4
T16N
6290 SEQUENCE DRIVE DIEGO, 92121 APPLIED MICRO CIRCUITS CORPORATION S2018 GBITS/S 17X17 DIFFERENTIAL CROSSPOINT SWITCH
DOUT7P
DOUT7N
DIN7N
EV2018 Gbit/s Differential Crosspoint Switch Evaluation Board Description
September 1999
EVALUATION BOARD
This section describes functionality connectors setting recommended S2018 Evaluation Boards. Brief descriptions connectors board, switch descriptions settings, power ground, header settings, probes presented. letters "A", "B", "C", correspond specific parts evaluation board shown Figure described following section according their letter designation Figure Connectors connectors provided differential data input signals differential data output signals. Additional connectors provided probe points. differential data input signals, DIN9P/N DIN14P/N, probed during testing. Note that differential inputs have connectors. minimize board size, inputs DINXXP DINXXN shorted rest differential inputs. minimizing board size, length traces board also minimized. Table gives description connectors.
Table Connectors
Connectors DIN2P/N, DIN7P/N, DIN9P/N, DIN14P/N, DINXXP/N, DIN16P/N DOUT0P, DOUT1P, DOUT2P, DOUT3P, DOUT4P/N, DOUT5P, DOUT6P, DOUT7P/N, DOUT8P, DOUT9P, DOUT10P, DOUT11P, DOUT12P, DOUT13P, DOUT14P, DOUT15P, DOUT16P/N DIN9PS, DIN9NS, DIN14PS, DIN14NS Description Differential inputs. Serial data inputs S2018. Differential outputs. Serial data outputs S2018.
Probing points differential data inputs.
Switches Evaluation Board equipped with switches control static control functions on-board device. arrays, (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Table shows functional switch descriptions.
Table Switch Functional Description
Name (CSN) (IADDR[4:0]) (OADDR[4:0]) (VADJUST[3:1]) Description Chip Select control signal. Active Low. When active chip enabled. Input Address. Active High. IADDR[4:0] selects input pair connect output pair selected OADDR[4:0]. Output Address. Active High. Used select output configuration register configuration register file. Used adjust output swing from differential 1400 differential.
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Table Switch Setting Adjustable Output Swing
VADJUST1 VADJUST2 VADJUST3
September 1999
EVALUATION BOARD
Output Swing (mVpp diff) 1000 1200 1400
Table Switch Settings Input Addresses S2018
Input DIN0P/N DIN1P/N DIN2P/N DIN3P/N DIN4P/N DIN5P/N DIN6P/N DIN7P/N DIN8P/N DIN9P/N DIN10P/N DIN11P/N DIN12P/N DIN13P/N DIN14P/N DIN15P/N DIN16P/N IADDR4 IADDR3 IADDR2 IADDR1 IADDR0
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
September 1999
EVALUATION BOARD
Table Switch Settings Output Addresses S2018
Output DOUT0P/N DOUT1P/N DOUT2P/N DOUT3P/N DOUT4P/N DOUT5P/N DOUT6P/N DOUT7P/N DOUT8P/N DOUT9P/N DOUT10P/N DOUT11P/N DOUT12P/N DOUT13P/N DOUT14P/N DOUT15P/N DOUT16P/N OADDR4 OADDR3 OADDR2 ODDR1 OADDR0
configure S2018, control signal kept active Low. switches IADDR[4:0] OADDR[4:0] then desired input output, respectively. LOADN then toggled load input output addresses into Configuration Register File. process repeated until desired input output addresses loaded into registers. Then CONFIGN toggled load configurations into Active Configuration Latch, which results simultaneous configuration crosspoint. Active Configuration Latch made transparent setting CONFIGN Low. configuration loaded into Configuration Register File LOADN will immediately loaded into Active Configuration Latch crosspoint will immediately reconfigured.
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EV2018 Gbit/s Differential Crosspoint Switch
Power Ground
September 1999
EVALUATION BOARD
power ground terminal provided bottom-left edge board Vee. S2018 specified
Table S2018 Power Ground Values
Terminal Post Terminal Post Output Termination 0.01 both positive negative outputs with line-to-line.
Headers Headers provided probe points, connectors signal generators connectors switches. jumpers headers enable user choose from using switches signal generators configuration signals. Headers used probe points must left unjumpered. headers labeled allow switches labeled signal generators provide configuration inputs IADDR[4:0]. Similarly, headers labeled allow switches labeled signal generators provide configuration inputs OADDR[4:0]. other hand, headers labeled allow momentary push-button switches signal generators provide inputs control signals CONFIGN LOADN, respectively. headers also allow switch from switches labeled signal generator provide input control signal CSN. desired, Active Configuration Latch made transparent connecting CONFIGN jumper header.
Table Evaluation Board Header Description
Header Description Either connects IADDR[4:0] configuration inputs switches signal generators Either connects OADDR[4:0] configuration inputs switches signal generators. Either connects CSN, LOADN CONFIGN control signals switches signal generators. Probing point input address IADDR0. Probing point output address OADDR0. Probing point control signal CSN. Probing point control signal CONFIGN. Probing point control signal LOADN.
remaining headers labeled JP4, JP5, JP6, probe points. Table shows which signals probed each these headers. Momentary Switches Momentary Push Button Switches provided control signals CONFIGN LOADN. switches labeled CONFIGN LOADN, respectively. These switches used because required inputs momentary pulses. pulse needed LOADN load input address output address into Configuration Register File. Then pulse needed load configuration into Active Configuration Latch reconfigure crosspoint (unless Active Configuration Latch made transparent). Table shows description momentary switches.
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EV2018 Gbit/s Differential Crosspoint Switch
Table Momentary Switch Description
Switch Name
September 1999
EVALUATION BOARD
Description Used Control signal CONFIGN Control signal LOADN
Schematic/Bill Materials
Figures provide schematic representation evaluation board. Table lists Bill Materials evaluation board.
Figure Signal Connections
S2018 DIN15P DIN15N DIN13P DIN13N DIN12P DIN12N DIN11P DIN11N DIN10P DIN10N DIN8P DIN8N DIN6P DIN6N DIN5P DIN5N DIN4P DIN4N DIN3P DIN3N DIN1P DIN1N DIN0P DIN0N DOUT15N DOUT13P DOUT13N DOUT12P DOUT12N DOUT11P DOUT11N DOUT10P DOUT10N DOUT8P DOUT8N DOUT6P DOUT6N DOUT5P DOUT5N DOUT4P DOUT4N DOUT3P DOUT3N DIN15P DOUT1P DOUT1N DOUT0P DOUT0N DIN9P DIN9N DOUT9P DOUT9N DOUT15P DIN14N DOUT14N S2018 DIN14P DOUT14P DIN2N DOUT2N DIN2P DOUT2P DIN7N DOUT7N DIN16N DIN7P DOUT16N DOUT7P DOUT15P S2018 DIN16P DOUT16P
Note:
0.01
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Figure Signal Connections (Continued)
September 1999
EVALUATION BOARD
S2018 IADDR0 IADDR1 IADDR2 IADDR3 IADDR4 VCSHIGH V-ADJ3 V-ADJ2 LOADN V-ADJ1 CONFIGN S2018
OADDR0 OADDR1 OADDR2 OADDR3 OADDR4 S2018
Figure Power Ground Connections
POWER TERMINATOR S2018 TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC TTLVCC VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
S2018 VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN
GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN GNDIN
TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND TTLGND
GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCCORE GNDCORE VCCADJ GNDADJ
S2018
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Table Bill Materials
Part Number S2018 Evaluation Board S2018 J502-ND A5408-ND S2011-05-ND S1011-05-ND S1011-02-ND SJ002-ND P8002SCT-ND PCC1033NCT-ND PCC1828CT-ND PCS5106TR-ND P51GTR-ND P100GTR-ND P430GTR-ND P10KGTR-ND P10KDCT-ND 277-1236-ND Description
September 1999
EVALUATION BOARD
Quantity
board platform used house S2018 testing applications Gbps Differential Crosspoint Switch (Edge Mount) Switch Switch Prong Header Prong Header Prong Header Prong Header Jumpers Light Touch Momentary Push Button Switch 0.01 Capacitor (Surface Mount) Capacitor (Surface Mount) Capacitor (Surface Mount) Resistor (Surface Mount) Resistor (Surface Mount) Resistor (Surface Mount) Resistor (Surface Mount) Resistor (Surface Mount) Terminal Power Connector
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EV2018 Gbit/s Differential Crosspoint Switch Test Configurations
September 1999
EVALUATION BOARD
This section deals with testing S2018, various test setups used ensure verify that S2018 meets required specifications. following will discuss Cross-Talk, Propagation Delay Rise Fall Time. Cross-Talk Testing Cross-Talk Test setup provides evaluate effects cross-talk single channel. This setup allows user monitor degradation signal channel cross-talk from other neighboring channels. Degradation signal cross-talk measured pattern. greater opening means lesser cross-talk lesser opening means greater cross-talk. start test, channel chosen victim other channels assault. worst case cross-talk, slowest path chosen victim (DIN14P/N DOUT4P/N). Then input DINXXP/N configured rest outputs assault. Before assault, pattern measurements made determine opening without effects cross-talk. These results will then compared opening measurement taken with effect cross-talk from assault. Note that this will asynchronous test.
Figure Cross-Talk Test Setup
70843A ERROR PERFORMANCE ANALYSER 70004 DISPLAY DATA INPUT TRIGGER
DIN14 DINX
ANRITSU MP1650A PULSE PATTERN GENERATOR DATA DATA
83752A SYNTHESIZED SWEEPER
S2018 EVAL BOARD TEKTRONIX 11801A DIGITAL SAMPLING OSCILLOSCOPE
OUTPUT
TRIGGER
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Cross-Talk Test Setup
September 1999
EVALUATION BOARD
Figure shows S2018 evaluation board Cross-Talk Test setup. letters through following data path description correspond letter designations (A-G) shown Figure pattern generator outputs desired signal that user chosen assault. this test data rate assault will 1.0Gbits/s, 2.5Gbits/s 3.2Gbits/s consecutively each data rate setting victim. output pattern generator goes DINXXP/N inputs evaluation board. board programmed that DINXXP/N configured rest differential outputs. analyzer, which also pattern generator, outputs desired signal that user chosen victim. this test data rate victim will 2.5Gbits/s, 3.2Gbits/s 4.0Gbits/s consecutively. output pattern generator goes DIN14P/N inputs evaluation board. board programmed that DIN14P/N configured DOUT4P/N. synthesized sweeper provides reference clock analyzer. Then output data from evaluation board sent oscilloscope viewing measurements. analyzer, which also pattern generator, provides trigger oscilloscope. Table describes equipment list Cross-Talk setup.
Table Cross-Talk Test Setup Equipment List
Part Number EV2018TB Anritsu 1650A 70843A with 70004 Display 83752A Tektronix 11801A S2018 Evaluation Board Pulse Pattern Generator. Generates input pattern send through device under test. This pattern generator will provide assault signal. Error Performance Analyzer. This also pattern generator. Generates input pattern send through device under test. This pattern generator will provide victim signal. Synthesized Sweeper. Generates reference clock 70843A Error Performance Analyzer. Digital Sampling Oscilloscope. Used visual output verification measurements signals under testing. Cables Description Quantity
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Propagation Delay Test
September 1999
EVALUATION BOARD
Propagation Delay Test setup allows user verify that propagation delay each channel within specification. properly measure propagation delay, user must careful include delay from cables. figure three pairs cables labeled. first pair cables labeled CS1, second pair cables labeled third pair cables labeled CS3. order accurate measure propagation delay without adding delay from cables, length must equal lengths (CS1 CS3). This will ensure that delay measured oscilloscope will only delay through data path S2018.
Figure Propagation Delay Test Setup
ANRITSU MP1650A PULSE PATTERN GENERATOR DATA
DIN14
PATTERN
S2018 EVAL BOARD TEKTRONIX 11801A DIGITAL SAMPLING OSCILLOSCOPE
TRIGGER
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Propagation Delay Test Setup
September 1999
EVALUATION BOARD
following description data path propagation delay test setup shown Figure letters through following data path description correspond letter designations (A-E) shown Figure pattern generator provides desired signal that user chosen. this test input signal will 3.2Gbits/s. output pattern generator then routed DIN14P/N input. board programmed that DIN14P/N configured DOUT4P/N. This slowest data path. output pattern generator also routed oscilloscope viewing measurements. Then output data from DOUT4P/N sent oscilloscope. oscilloscope takes both differential signals measures propagation delay. pattern generator also provides trigger input oscilloscope. Table describes equipment list propagation delay test setup.
Table Propagation Delay Test Setup Equipment List
Part Number EV2018TB Anritsu 1650A Tektronix 11801A S2018 Evaluation Board Pulse Pattern Generator. Generates input pattern send through device under test. Digital Sampling Oscilloscope. Used visual output verification measurements signals under testing. Cables Description Quantity
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Rise/Fall Time Test
September 1999
EVALUATION BOARD
Rise/Fall Time Test provides evaluate timing performance S2018. This setup allows user verify that device meets specified timing requirements. this test both slow path fast path will tested rise/fall time. stated previously, slowest data path between DIN14P/N DOUT4P/N fastest data path between DIN7P/N DOUT7P/N. slowest data path will tested first fastest data path second. However, since same procedure used both data path, only first test will described.
Figure Rise/Fall Time Test Setup
70843A ERROR PERFORMANCE ANALYSER 70004 DISPLAY DATA INPUT TRIGGER
DINX
DIN14
83752A SYNTHESIZED SWEEPER
S2018 EVAL BOARD TEKTRONIX 11801A DIGITAL SAMPLING OSCILLOSCOPE
DOUT
OUTPUT
TRIGGER
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Rise/Fall Time Test Setup
September 1999
EVALUATION BOARD
following description data path rise/fall time test setup shown Figure letters through following data path description correspond letter designations (A-E) shown Figure error performance analyzer, which also pattern generator, provides desired signal test. this test input signal will 3.2Gbits/s. output pattern generator sent DIN14P/N inputs evaluation board. Then board programmed that DIN14P/N configured DOUT4P/N. data output from DIN4P/N routed oscilloscope viewing measurements. analyzer provides trigger oscilloscope. Similarly, synthesized sweeper provides reference clock analyzer. Table describes equipment list setup/hold propagation delay test setup.
Table Setup/Hold Propagation Delay Test Setup Equipment List
Part Number EV2018TB 70843A with 70004 Display 83752A Tektronix 11801A S2018 Evaluation Board Error Performance Analyzer. This also pattern generator. Generates input pattern send through device under test. Synthesized Sweeper. Generates reference clock 70843A Error Performance Analyzer. Digital Sampling Oscilloscope. Used visual output verification measurements signals under testing. Cables Description Quantity
AMCC
EV2018 Gbit/s Differential Crosspoint Switch Evaluation Board Layout
This section provides layer layer design layout S2018 evaluation board.
September 1999
EVALUATION BOARD
Figure
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EV2018 Gbit/s Differential Crosspoint Switch
Figure
September 1999
EVALUATION BOARD
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Figure
September 1999
EVALUATION BOARD
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Figure
September 1999
EVALUATION BOARD
AMCC
EV2018 Gbit/s Differential Crosspoint Switch
Ordering Information
Prefix Evaluation Board Device 2018 Package SBGA
September 1999
EVALUATION BOARD
Prefix
XXXX
Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPO APPLICATIO DEVICES SYSTEMS THER CRIT ICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation.
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EV2018 Gbit/s Differential Crosspoint Switch Evaluation Boar

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