ASSP Screen Display Control CMOS ON-Screen Display Controlle

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ASSP Screen Display Control CMOS ON-Screen Display Controlle

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DS04-28824-3E
ASSP Screen Display Control
CMOS
ON-Screen Display Controller
MB90092
DESCRIPTION
MB90092 display controller displaying text graphics screen. MB90092 incorporates display memory (VRAM), font memory interface, video signal generator, allowing text graphics displayed conjunction with small number external components. MB90092 provide screens, called main screen sub-screen, either independently overlayed other. main screen consists characters lines allows data each character. subscreen consists characters lines characters lines. Data either each line former configuration collectively entire screen latter configuration. output video signals, MB90092 composite video signal, Y/C-separated video signal, digital output pins. MB90092 also video signal input pins, allowing superimpose display over either composite video signals Y/C-separated video signals.
PACKAGE
80-pin Plastic
(FPT-80P-M06)
MB90092
FEATURES
Main Screen Display Screen display capacity:24 characters lines characters) Character configuration:24 dots (per character) Character types: 16384 different characters (when using external clock) Character sizes: Standard, double width, double height, double width double height, quadruple width double height (Setting possible each line) Display position control :Horizontal display position :Set 1/3-character units Vertical display position :Set raster units Line spacing control :Set raster units rasters) Display priority control:Capable controlling display priority over sub-screen (for each line) Sub-Screen Display Screen display position: Settable horizontally vertically 2-dot units Normal screen mode:Screen capacity:32 characters lines characters) horizontal dots vertical dots (graphics characters only) (The actual display screen depends television system clock frequency.) Normal character/graphic character display selectable each line (Header display character code specified each line.) Character string length:Selectable from among digits Full-screen mode Screen capacity: characters lines characters) horizontal dots vertical dots (The actual display screen depends television system clock frequency.) Virtual screen capacity:Mode A:32 characters lines screens) horizontal dots vertical dots Mode B:512 characters lines 4096 horizontal dots 1024 vertical dots Screen Background Display Screen background color: colors (set entire screen) Analog Inputs Composite video signal input Y/C-separated inputs Analog Outputs Composite video signal output Y/C-separated outputs Digital Outputs (Green), (Red), (Blue) output (character) output, (character background) output Characters, character background, line background, screen background each capable being displayed eight colors Internal Synchronization Control (Video Signal Generator) Internal video signal generator supporting NTSC systems Interlaced/noninterlaced display selectable
(Continued)
MB90092
(Continued)
External Synchronization Control Separated sync signal input/composite sync signal input selectable External Interface 8-bit serial inputs signal input pins) Chip select: Serial clock: SCLK Serial data: Package QFP-80 Miscellaneous Internal power-on reset circuit
MB90092
ASSIGNMENT
(TOP VIEW) TEST ADR20 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 ADR11 TESTI SCLK EXHSYN EXVSYN HSYNC VSYNC VBLNK TEST1 FSCO CBCK AVSS
ADR10 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 READ AVCC1
TEST2 TEST3 TEST4 TEST5 AVSS AVSS YOUT AVCC2 COUT AVSS VOUT VKIN VKOUT (FPT-80P-M06)
MB90092
DESCRIPTION
name Circuit type Function Test signal input pin. Input High level signal during normal operation. This also used reset signal input Low-level input TEST pin. That effective only after release power-on reset. This hysteresis input with internal pull-up resistor. Character interval signal output pin. output signal represents character output interval. Character/background internal signal output pin. During internal synchronization control operation, output signal represents character, character background, line background, screen background output interval. Color signal output pins. These pins output character, character background, line background, screen background color signals. Chip select pin. serial transfer, this level. This also used release power-on reset. hysteresis input with internal pull-up resistor. Shift clock input serial transfer. This hysteresis input with internal pull-up resistor. Serial data input pin. hysteresis input with internal pull-up resistor. External horizontal sync signal input pin. Input negative logic signal. This also serve composite sync signal input depending internal register setting. hysteresis input with internal pull-up resistor. External vertical sync signal input pin. Input negative logic signal. Input this disabled when composite sync signal input been selected setting internal register. hysteresis input with internal pull-up resistor. Horizontal sync signal output pin. This also output composite sync signals depending internal register setting. outputs signal (FSC) resulting from dividing 4FSC clock frequency setting TEST level. Vertical sync signal output pin. This fixed High level when composite sync signal output been selected setting internal register. outputs clock oscillator signal when TEST goes into Low. Vertical blanking interval signal output pin. This outputs Low-level signal vertical blanking interval.
TESTI
SCLK
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
(Continued)
MB90092
name
Circuit type
Function External circuit pins color burst clock generator. Connect external crystal oscillator (14.31818 NTSC 17.734475 PAL) load capacitance these pins form crystal oscillator circuit. Internal color burst clock output pin. This controls internal color burst clock output depending command External color burst clock input output result color burst clock phase comparison Luminance signal output pin. This outputs signal VP-P (pedestal level 1.57 sync level Luminance signal input superimpose display. This inputs DC-reproduced (DC-clamped) signal VP-P (pedestal level 1.57 sync level Saturation signal output pin. This outputs signal 1.57 color burst signal amplitude 0.57 VP-P. Saturation signal input superimpose display. This inputs signal 1.57 color burst signal amplitude 0.57 VP-P. Composite video signal output pin. This outputs signal VP-P (pedestal level 1.57 sync level Background level control input halftone background display external input composite video signals (input output from VOUT pin). Halftone background display controlled setting command "1". Background level control output halftone background display external input composite video signals (input output from VOUT pin). Halftone background display controlled setting command "1". Composite video signal input superimpose display. This inputs DC-reproduced (DC-clamped) signal VP-P (pedestal level 1.57 sync level External font memory read control pin. This outputs Low-level signal font memory read period. enters high impedance state when inputs Low-level signal.
FSCO CBCK YOUT
COUT
VOUT
VKIN
VKOUT
READ
(Continued)
MB90092
name
Circuit type
Function
External font memory data input pins. These pins inputs with internal pull-up resistor.
ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20
External font memory address output pins. These pins enter high impedance state when inputs Low-level signal. ADR0 ADR1 ADR2 Raster address ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 Character code (Lower bits) ADR9 ADR10 ADR11 ADR12 Data distinction bits ADR13 (12,13 Left, Center, Right) ADR14 ADR15 ADR16 ADR17 Character code (Higher bits) ADR18 ADR19 ADR20 control bits main screen character control data setting (the commands 2-1) control bits sub-screen character control data setting (the commands 2-2) Tristate control input external font memory control bus. When this inputs Low-level signal, ADR0 ADR20 pins READ enter high impedance state. hysteresis input with internal pull-up resistor. Test signal input pin. This usually inputs High-level (fixed) signal. External circuit pins display clock generator. Connect these pins external form oscillator circuit.
TEST
(Continued)
MB90092
(Continued)
name TEST1 TEST2 TEST3 TEST4 TEST5 Circuit type Function
Leave these pins unconnected.
Power-supply pins
Ground pins
AVCC1 AVCC2
Analog power composite video signals (VIN-VOUT) Analog power luminance (YIN-YOUT) chroma (CIN-COUT) signals Analog circuit ground pins. these pins same level pin.
AVSS
MB90092
CIRCUIT TYPE
Type Circuit Remarks
CMOS level input With pull-up resistor: approximately
CMOS level, hysteresis input With pull-up resistor: approximately
CMOS output
CMOS three state output
(Continued)
MB90092
(Continued)
Control signal Analog input Analog input CMOS analog
Control signal Analog output Analog output CMOS analog
Control signal CMOS level, hysteresis input
Crystal oscillation circuit
Control signal
oscillation circuit
Control signal
Inside clock signal
MB90092
BLOCK DIAGRAM
SCLK TEST
Serial input control
Each control data
VKIN EXHSYN EXVSYN
Analog
VOUT YOUT COUT VKOUT
separation circuit
HSYNC VSYNC VBLNK
NTSC/PAL signal generator
Video signal generator
Display memory control
Output control
Display memory (VRAM)
Font memory control
ADR0 ADR20 READ
4FSC clock oscillator
Each block
Phase comparator (color burst)
CBCK FSCO
clock oscillator
Each block
MB90092
DISPLAY CONTROL COMMANDS
Command First byte Function
VRAM address setting
Second byte Data
Command code/data 76543 10000 10001 10010
Main screen character control data setting Main screen character control data setting Sub-screen line control data setting Sub-screen line control data setting Main screen line control data setting Main screen line control data setting
(GR)* (BS)* (MD)*
10001
10010 10001 10010 10011 10100
VRAM write control Screen control Screen control Main screen line control
Main screen vertical display position control
Main screen horizontal display position control
10101 10110 10111 11000 11001 11010
Main screen display mode control Color control Sub-screen control
Sub-screen vertical display position control
Sub-screen horizontal display position control
11011 11100 11101 11110 11111
(Reserved) (Reserved)
Parenthesized names used extended graphics mode. Note: screen control (command initialized display reset. command data VRAM needed after release power-on reset.
MB90092
COMMAND
VRAM Address Setting (Command
First byte Second byte
VRAM write control VRAM address setting VRAM column address setting (00H 17H)
VRAM Data Settings (Commands
Writing main screen character control data (when command
Command (Main screen character control data setting First byte Second byte (GR) (BS) (MD)
Parenthesized names used extended graphics mode.
Command (Main screen character control data setting First byte Second byte
(MD), (GR) (BS)
Character code Specify character attribute display. Character colors Character background colors Specify normal character/graphic character display. Specify shaded background display.
MB90092
Writing sub-screen line control data (when command
Command (Sub-screen line control data setting First byte Second byte
Command (Sub-screen line control data setting First byte Second byte
SCR,
Sub-screen line first character code Sub-screen line output control Sub-screen line character display control Sub-screen line character colors (when Sub-screen line graphic color transparency control (when Sub-screen line graphic color phase control (when
MB90092
Writing main screen control data (when command
Command (Main screen line control data setting First byte Second byte
Command (Main screen line control data setting First byte Second byte
OF1,
Character color phase control Shaded pattern background color/monochrome control Shaded pattern background color Character size control Output priority control Video signal output control Digital signal output control Line background color/monochrome control Line background color
VRAM Write Control (Command
First byte Second byte
FIL: VRAM fill control
MB90092
Screen Control (Command
First byte Second byte
Internal/external synchronization control Interlaced/noninterlaced display control Screen background display control Field control Color/monochrome display control Zoom-in control NTSC/PAL control Pattern background control Display control
Screen Control (Command
First byte Second byte
Halftone control Reserve* Main screen line enlargement control Reserve* Main screen line spacing control
Reserve must
MB90092
Main Screen Line Control (Command
First byte Second byte
Character size control Output priority control Video signal output control Digital signal output control Line specification
Main Screen Vertical Display Position Control (Command
First byte Second byte
Sync signal output control Simple NTSC/PAL control Color phase signal output control Main screen vertical display position control
Main Screen Horizontal Display Position Control (Command
First byte Second byte
Sync signal input control Sync signal input filter control Main screen horizontal display position control
MB90092
Main Screen Display Mode Control (Command
First byte Second byte
GRM: Main screen display mode control RP1, Reserve Reserve Reserve Reserve RM1, Reserve Reserve reserve must "0".
Color Control (Command
First byte Second byte
Main screen solid-fill background display control Main screen blink display control Main screen character color/monochrome control Main screen character background color/monochrome control (Main screen graphic color/monochrome control) Screen background color/monochrome control Screen background color
MB90092
Sub-Screen Control (Command
First byte Second byte
SBG, SBR,
Sub-screen configuration control Sub-screen character color/monochrome control Sub-screen character background color/monochrome control Sub-screen graphic color/monochrome control Sub-screen pattern background color
Sub-Screen Vertical Display Position Control (Command
First byte Second byte
Sub-screen full-screen mode control Sub-screen vertical display position
Sub-Screen Horizontal Display Position Control (Command
First byte Second byte
Sub-screen horizontal display position
MB90092
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Supply voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature AVCC1 AVCC2 VOUT Tstg Rating Min. Max. +150 Unit Remarks
AVSS must have equal potential. Neither VOUT must exceed "VCC WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
(VSS AVSS Parameter Symbol Supply voltage AVCC1 AVCC2 level input voltage level input voltage Operating temperature Analog input voltage VIHS1 VIHS2 VILS1 VILS2 AVIN Value Min. -0.3 -0.3 Max. Unit Remarks Specification guarantee range Except Except
AVSS must have equal potential. "AVCC1 AVSS" allowed composite video signals (VIN-VOUT pins) used. "AVCC2 AVSS" allowed Y/C-separated video signals (YIN-YOUT CIN-COUT pins) used. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MB90092
ELECTRICAL CHARACTERISTICS
Characteristics
-40°C +85°C, AVSS
Parameter Symbol Conditions Value Min. Typ. Max. Unit Remarks
level output voltage level output voltage
VOC, VOB, HSYNC, VSYNC, VBLNK, FSCO, READ, ADR0 ADR20 TESTI, SCLK, SIN, EXHSYN, EXVSYN, CBCK, DA7, TSC, TEST VCC, AVCC1, AVCC2
Input current
-200
Supply current
AVCC1 AVCC2 4fsc 17.734475 16.0 load AVCC1 AVCC2 4fsc AVIN 1.65 load
Analog supply current
AVCC1, AVCC2
resistance
VIN-VOUT, YIN-YOUT, CIN-COUT, VIN-VKOUT, VKIN-VOUT VIN, YIN, CIN, VKIN VOUT, YOUT, COUT, VKOUT
AVCC1 AVCC2
leakage current Output resistance
IOFF
AVCC1 AVCC2 AVIN AVCC1 AVCC2
ROUT
1800
(Continued)
MB90092
-40°C +85°C, AVSS
Parameter Symbol Conditions Value Min. Typ. Max. Unit Remarks
Yellow High level Yellow level Cyan High level Cyan level Green High level Green level Magenta High level Magenta level High level level Blue High level Blue level Color burst High level Color burst level
VYELH VYELL VCYAH VCYAL VGREH VGREL VMAGH VOUT VMAGL VREDH VREDL VBLUH VBLUL VBSTH VBSTL AVCC1 AVCC2
2.89 2.03 2.89 1.63 2.66 1.63 2.49 1.46 2.49 1.23 2.15 1.23 1.80 1.12
3.00 2.14 3.00 1.74 2.77 1.74 2.60 1.57 2.60 1.34 2.26 1.34 1.91 1.23
3.11 2.25 3.11 1.85 2.88 1.85 2.71 1.68 2.71 1.45 2.37 1.45 2.02 1.34
Figure "VOUT output"
(Continued)
MB90092
-40°C +85°C, AVSS
Parameter Symbol Conditions Values Min. Typ. Max. Unit Remarks
White level 270° White level 180° White level White level Gray level Gray level Gray level Gray level Gray level Gray level Black level 270° Black level 180° Black level Black level Pedestal level SYNC level
VWHT3 YWHT3 VWHT2 YWHT2 VWHT1 YWHT1 VWHT0 YWHT0 VGRY6 YGRY6 VGRY5 YGRY5 VGRY4 YGRY4 VGRY3 YGRY3 VGRY2 YGRY2 VGRY1 YGRY1 VBLK3 YBLK3 VBLK2 YBLK2 VBLK1 YBLK1 VBLK0 YBLK0 VPDS YPDS VTIP YTIP VOUT, YOUT AVCC1 AVCC2
2.83 2.72 2.60 2.49 2.43 2.26 2.15 1.98 1.86 1.69
2.94 2.83 2.71 2.60 2.54 2.37 2.26 2.09 1.97 1.80
3.05 2.94 2.82 2.71 2.65 2.48 2.37 2.20 2.08 1.91
Figures "VOUT Output" "YOUT Output".
1.92
2.03
2.14
1.80
1.91
2.02
1.69
1.80
1.91
1.57
1.68
1.79
1.46 0.84
1.57 1.00
1.68 1.16
(Continued)
MB90092
(Continued)
Symbol CYELH CYELL CCYAH CCYAL CGREH CGREL CMAGH CMAGL CREDH CREDL CBLUH CBLUL CBSTH CBSTL CPDSC COUT AVCC1 AVCC2 -40°C +85°C, AVSS Value Unit Remarks Min. Typ. Max. 1.92 1.00 2.09 0.89 1.98 0.95 1.98 0.95 2.09 0.89 1.92 1.00 1.80 1.12 1.46 2.03 1.11 2.20 1.00 2.09 1.06 2.09 1.06 2.20 1.00 2.03 1.11 1.91 1.23 1.57 2.14 1.22 2.31 1.11 2.20 1.17 2.20 1.17 2.31 1.11 2.14 1.22 2.02 1.34 1.68 Figure "COUT Output"
Parameter Yellow High level Yellow level Cyan High level Cyan level Green High level Green level Magenta High level Magenta level High level level Blue High level Blue level Color burst High level Color burst level Pedestal level
Conditions
MB90092
VOUT Output
VYELH VWHT0 VGRY6 VGRY5 VGRY4 VYELL VBSTH VPDS VBSTL VTIP VCYAL VGREL VMAGL VREDL VBLUL VCYAH VGREH VMAGH VREDH VBLUH VGRY3 VGRY2 VGRY1 VBLK0 VPDS
YOUT Output
YWHT0 YGRY6 YGRY5 YGRY4 YGRY3 YGRY2 YPDS YGRY1 YBLK0 YPDS
YTIP
COUT Output
CCYAH CYELH CBSTH CPDS CBSTL CYELL CCYAL
CGREH
CMAGH
CREDH CBLUH
CBLUL CGREL CMAGL CREDL
MB90092
Characteristics
-40°C +85°C, V±10%,
Parameter Symbol Value Min. Max. Unit Remarks
Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select time Chip select signal rise/fall time Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width*1 Vertical sync signal pulse width Vertical sync detection pulse width*2 Reset input pulse width read cycle Address valid delay READ active delay Read data setup time Read data hold time Address invalid delay READ inactive delay Tristate address delay Tristate READ delay
tCYC SCLK tWCH tWCL tCRC tCFC SCLK SCLK SCLK EXHSYN EXHSYN EXVSYN EXVSYN EXHSYN EXVSYN
1000
Figure "Vertical Horizontal Sync Signal Input Timings". Figure "Composite Sync Signal input Timings". Figure "Address READ Signal Delays Signal Input" Figure "Address Data Hold Timings". Figure "Reset Signal Input Timing". Figure "Serial Input Timings".
Horizontal sync detection pulse width tWCSH EXHSYN tWCSV EXHSYN trcyc ttad ttrd READ ADR0 ADR20 READ ADR0 ADR20 READ TESTI (TEST Low)*3 ADR0 ADR20
values assume H/V-separated sync signal input. values assume composite sync signal input. When TEST Low-level input, TESTI serves reset input. (The TESTI TEST pins level same time.) Depends clock oscillation frequency. (trcyc 4/fDC)
MB90092
Serial Input Timings
tCFC
tCRC tCYC
SCLK
tWCH tWCL
Vertical Horizontal Sync Signal Input Timings
EXHSYN
EXVSYN
MB90092
Composite Sync Signal Input Timings
EXHSYN
tWCSH
EXHSYN
tWCSV
EXHSYN
tWCSV
Vertical sync signal interval (3H)
Reset Signal Input Timing
TESTI
MB90092
Address Data Hold Timings
trcyc
ADR0 ADR20
Main screen data address
Sub-screen data address
READ Main screen data Sub-screen data
main screen sub-screen have same address data timings.
Address READ Signal Delays Signal Input
ADR0 ADR20
READ
ttrd ttad
MB90092
Clock Timing Specifications
Parameter Display clock* Color burst clock (NTSC)* Color burst clock (PAL)* Symbol EXD, EXS, Value Min. Typ. 14.318185 17.734475 Max. Unit Remarks
Input signal with duty cycle 50%.
Power-on Reset Specifications
-40°C +85°C) Parameter Symbol Value Min. 0.05 Power-supply time Time after power-supply rise Reset cancel pulse width toff tWIT tWRH tWRL Max. Unit Remarks Conditions which activate power-on reset circuit (See Figure "Power Timing"). Conditions which circuit repeatedly operate normally (See Figure "Power ON/OFF Timing"). Power-on reset cancel timing (See Figure "Power-on Reset Cancel Timing").
Power-supply rise time
MB90092
Power ON/OFF Timing
toff
Note: power supply must activated smoothly.
Power-on Reset Cancel Timing
Internal reset
tWIT
tWRL tCRC* tWRH tCFC*
Section Characteristics".
MB90092
Recommended Input Timings
Composite sync signal input timing Parameter Number frame scan lines Field frequency Line frequency Vertical retrace blanking interval First equalizing pulse interval Vertical sync pulse interval Second equalizing pulse interval Equalizing pulse width Equalizing pulse cycle Cut-in pulse width Cut-in pulse cycle Horizontal sync signal cycle Horizontal sync signal pulse width NTSC (59.94) 15750 (15734.264) 2.29 2.54 3.81 5.34 63.492 (63.5555) 4.19 5.71 (4.7±0.1) 15625 2.34 2.36 11.7 12.3 Unit Lines Remarks
Horizontal retrace blanking interval 10.2 11.4 (10.5 11.4) Parenthesized values specifications color information display. assumed horizontal sync signal period. H/V-separated sync signal input timing Parameter Vertical sync signal frequency Vertical sync signal pulse width Horizontal sync signal cycle Horizontal sync signal pulse width NTSC (59.94) 63.492 (63.5555) 4.19 5.71 (4.7±0.1)
Unit
Remarks
Parenthesized values specifications color information display. assumed horizontal sync signal period.
MB90092
Output Timings
Horizontal timing Symbol EQP1E BSTS BSTE HBLKE SEP1S EQP2S EQP2E SEP2S HBLKS IHCLR NTSC 1050 1106 1135 (1137)* Figure "NTSC/PAL Horizontal Timings". Remarks
Parenthesized values assume last raster each cycle (field). Note: values above list 4fSC count values. Vertical timing Symbol EQPE VBLKE VBLKS NTSC Interlaced Noninterlaced Interlaced Noninterlaced Figures "NTSC Vertical Timings" "PAL Vertical Timings". Remarks
Note: values above list 1/2H count values.
MB90092
NTSC/PAL Horizontal Timings
Video signal
Horizontal sync signal
Horizontal retrace blanking interval
Burst flag
Equalizing pulse
Cut-in pulse
EQP2E EQP2S SEP1S HBLKE BSTE BSTS EQP1E HBLKS
IHCLR HBLKS SEP2S
NTSC Vertical Timings
Even-numbered field
Composite video signal
Horizontal scanning line
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
VBLKS
EQPE
VBLKE
VBLKS
Odd-numbered field
Composite video signal
Horizontal scanning line
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
VBLKS
EQPE
VBLKE
VBLKS
MB90092
Note1 Note
First field
MB90092
Vertical Timings
Color burst phase Composite video signal Horizontal scanning line Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval
BSTE VBLKS
EQPE BSTS
VBLKE
BSTE VBLKS
Second field
Color burst phase Composite video signal Horizontal scanning line Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval
BSTE
VBLKS
EQPE BSTS
VBLKE
BSTE
VBLKS
Third field
Color burst phase Composite video signal Horizontal scanning line Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval
BSTE
VBLKS
EQPE, BSTS
VBLKE
BSTS, VBLKS
Forth field
Color burst phase Composite video signal Horizontal scanning line Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval
BSTE, VBLKS
EQPE
BSTS
VBLKE
BSTE VBLKS
Notes indicates HSYNC positions equalizing pulse intervals. arrows marks indicate phase color subcarrier. +135°, -135°)
MB90092
SAMPLE CIRCUIT
This standard example circuit synthesize character input video signal input internal generation video signal from outside. Note that composition different according system parts used.
Composite Video amplifer clamp circuit Video amplifer clamp circuit
MB90092
Composite VOUT Buffer circuit YOUT COUT Buffer circuit
Sync separation circuit
EXHSYN
Control microcontroller SCLK ADR0
ADR20
AVCC1 AVCC2
READ
(16M ROM)
AVSS
(Approx. MHz)
NTSC 14.31818 17.734475
MB90092
ORDERING INFORMATION
Part number MB90092PF Package 80-pin, plastic (QFP-80P-M06) Remarks
MB90092
PACKAGE DIMENSION
80-pin plastic (FPT-80P-M06) Note Pins width pins thickness include plating thickness.
23.90±0.40(.941±.016) 20.00±0.20(.787±.008)
0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) INDEX Details part
0.25(.010) +0.30 3.05 -0.20 +.012 .120 -.008 (Mounting height)
0.80(.031)
0~8°
0.37±0.05 (.015±.002)
0.20(.008)
0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.30 -0.25
+0.10 +.004
.012 -.010 (Stand off)
2001 FUJITSU LIMITED F80010S-c-4-4
Dimensions (inches).
MB90092
FUJITSU LIMITED
further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, Jose, 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. Fri.: (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, Lorong Chuan, Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. products described this document designed, manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated accompanying fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), requiring extremely high reliability (i.e., submersible repeater artificial satellite). Please note that Fujitsu will liable against and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Control Japan, prior authorization Japanese government should required export those products from Japan.
F0108 FUJITSU LIMITED Printed Japan

ASSP Screen Display Control CMOS ON-Screen Display Controlle

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