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Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
This product description provides overview major functions Agere Systems Inc. Ambassador T8110 device. T8110 newest addition Ambassador Series computer telephony integrated circuits. This device contains capabilities previous members Ambassador family also extends them providing flexible interface switching packet payloads between local H.100/ H.110 buses. This part intended work with coprocessor providing header, framing, checksum generation, since T8110 operates purely payloads, multiple protocols supported simultaneously such ATM, A-Bis. Support non-PCI devices provided through minibridge, reducing system-integration costs. Figure below shows typical application which provides connectivity framers, over Ethernet, H.100 Bus.
H.100 CLOCKS STREAMS STREAMS TRUNKS FRAMERS BRIDGE AGERE T8110 COPROCESSOR ETHERNET MAC/PHY 10/100
LOCAL
MEMORY
PCI-PCI BRIDGE
HOST
5-8921a
Figure Basic Application T8110 Switch CT-IP Payload Processor
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Table Contents
Contents
Page
Introduction Main Architectural Features Interface Operating Control Status Registers. Clock Architecture Frame Group General-Purpose Stream Rate Control Minibridge Error Reporting Interrupt Control Connection Control-Standard Virtual Channel. Ambassador Selection Guide
Figures
Page
Figure Basic Application T8110 Switch CT-IP Payload Processor Figure T8110 Block Diagram. Figure Main Clock Paths Figure NETREF Paths. Figure Clock Register Transfer During Fallback. Figure Frame Group Figure Minibridge Functional Diagram.11 Figure H.1x0 Clock Error Management Figure Standard Connection.13 Figure Virtual Channel Switching (H.1x0 Side) Figure Upstream Data Management Figure Downstream Data Management.17
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Main Architectural Features
main features T8110 following:
Eight independent general-purpose lines Eight independently programmed framing signals Four local clocks T1/E1 rate adaptation clock fallback modes Stratum 4/4E AT&T 62411 MTIE compliant swap friendly evaluation boards, CompactPCI* swap Single supply with tolerant inputs compatible outputs PBGA package
Combined master/slave interface with burst
Full H.100/H.110 support data lines, clock modes) 4,096-connection unified switch local lines Mbits/s, Mbits/s, Mbits/s, Mbits/s) Packet payload engine supporting virtual channels Interrupt controller with external inputs Minibridge with programmable chip selects
LOCAL CLOCKS
H.1x0 CLOCKS
PARALLEL-TO-SERIAL CONVERSION (OUTPUT) SERIAL-TO-PARALLEL CONVERSION (INPUT)
FRAME GROUPS
CLOCKING TIMING CONTROL FRAME GROUPS TIMING ADDITIONAL H.1x0 EVEN CONNECTION MEMORY INTERNAL CLOCKS H.1x0 CONNECTION MEMORY LOCAL HIGH CONNECTION MEMORY LOCAL CONNECTION MEMORY
VIRTUAL CHANNEL CONTROLLER
DATA MEMORY CONTROLLER
H.1x0 STREAMS (BIDIRECTIONAL)
ERROR SIGNALS
CLOCK INTERRUPT ERRORS ERROR CONTROL SYSTEM ERRORS
DATA MEMORY DATA MEMORY
LOCAL STREAMS (BIDIRECTIONAL)
GENERALPURPOSE GENERALI/O PURPOSE REGISTER ACCESS CONTROL CONNECTION MEMORY CONTROLLER
BRIDGE SIGNALS MINIBRIDGE
MASTER/SLAVE CORE WITH BURST
(LOCAL)
5-8920a
Figure T8110 Block Diagram
CompactPCI registered trademark Industrial Computer Manufacturers Group.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Interface
interface arranged provide mixture accesses. Initialization register programming typically under coprocessor control, T8110 will operate slave when being programmed coprocessor, host PCI-PCI bridge. Diagnostics error handling also defined slave operations. However, when processing packets either taking data from H.1x0 passing external memory, when retrieving data from memory sending H.1x0 bus, T8110 operates master, arbitrating taking control burst transactions. This ensures that bandwidth required T8110 local owner kept minimum. Packet transactions limited H.1x0 bus. Local time slots routed from bus, well. Address Type Configuration Space Operating Control Status Clocks Rate Control Frame Group General-Purpose Interrupt Control Minibridge Control Reserved Virtual Channel Memory Data Memory Reserved Connection Memory Reserved Minibridge Operating Space Reserved Range (Hex) 0x00000-0x000FF 0x00100-0x001FF 0x00200-0x002FF 0x00300-0x003FF 0x00400-0x004FF 0x00500-0x005FF 0x00600-0x006FF 0x00700-0x007FF 0x00800-0x0FFFF 0x10000-0x1FFFF 0x20000-0x2FFFF 0x30000-0x3FFFF 0x40000-0x4FFFF 0x50000-0x6FFFF 0x70000-0x7FFFF 0x80000-0xFFFFF Total Space Allocated (bytes) 128K 512K
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Operating Control Status Registers
operating control status registers perform following functions:
Reset management: Soft reset Enable/disable reset backend Enable/disable external reset Resource enable (separate enables for): H-Bus clocks H-Bus data Local clocks (LSCs, frame group signals) Local buses Minibridge Clock register initialization control: Power default clock register allowing user program this becomes operating when specific command issued. sets fully redundant. Clock fallback control (provides several options managing fallback): Rotating secondary Fixed secondary (There choices resetting clocks: command frame sync command only. Command refers clearing fallback condition.) Forced operation Clock error reporting: Reports clocks available. Frame watchdogs also report under flow (short frame) well overflow (long frame). Data memory control: modes available controlling data memory mixing traditional switching n-by-64K streams with wireless based packets. Connection reporting Data memory connection overflow count, virtual channel overflow warnings, bonded time-slot offset warnings active-page status reported.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Clock Architecture
clocking T8110 based other Ambassador series products, though there some notable enhancements. main clock paths shown Figure APLL1 heart clocking section. input source selected modified that delivers source APLL1. APLL1 locks this reference generates signal state machine that, turn, provides internal clocks. These clocks aligned external frame well, that regenerated framing signals phase locked frame reference well frequency locked clock reference. changes have been made places: DPLL1 associated with APLL1 support circuitry APLL2. First, additional multiplexer (MUX) been placed front DPLL1 with connections from dividers (main resource). This allows 1.544 signal brought local references NETREFs division down kHz, then spun either 2.048 4.096 rate conversion. jitter induced this process short-term maximum value 0.036 bypass also been created main divider (through source selection MUX) that both resource main dividers utilized directly APLL1. APLL2 sees greatest modifications from predecessors. oscillator based 6.176 12.352 crystal drives APLL2 49.4 MHz. This used drive DPLL, which phase aligned with either several internal sources, external source. This provides phase aligned rate conversion back 1.544 MHz. essence, take smooth (jitter free) from receive path framer, through DPLL2, generate aligned transmit clock transmit side framer. Maximum jitter will 0.022 when APLL2 running MHz.
WATCHDOGS
/CT_FRAME_A /CT_FRAME_B /FR_COMP LREF[4:7] PROGRAMMABLE INVERSION LREF[0:7] CT_NETREF1 CT_NETREF2 CT_C8A CT_C8B
SLIDER CONTROLS FRAME WATCHDOG DPLL1 SOURCE RATE DPLL1 SYNC SAMPLED FRAME
PHASE ALIGNMENT
2.048 4.096 8.192
INTERNAL CLOCK GENERATION
16.364 FRAME 32.768 (INTERNAL) FRAME MEMORIES
CLOCK SELECT RESOURCE DIVIDE-BY-N DIVIDE REGISTER MAIN DIVIDE-BY-N DIVIDE REGISTER
APLL 65.536
65.536 APLL BYPASS
WATCHDOGS
MVIP* CLOCKS) H-MVIP CLOCKS) SC-BUS CLOCKS)
SCSA CLOCKS)
FAIL SAFE CLOCK SOURCE SELECT FRAME WATCHDOG MULT
LOCK STATUS TCLK_OUT APLL 49.408 APLL BYPASS APLL RATE SELECT OSC2
PROG. INVERSION OSC1
DPLL2
DPLL2 SOURCE RATE PRI_REF_OUT PRI_REF_IN
XTAL1
XTAL1 OSC1
XTAL2 XTAL2 OSC2
5-9432c
MVIP trademark Natural MicroSystems Corporation.
Figure Main Clock Paths
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Clock Architecture (continued)
independent NETREF paths have been created supporting CT_NETREF1 CT_NETREF2, based original architecture. complicated MUXing NETREF1 NETREF2 found earlier Ambassador series devices been eliminated. Both NETREF paths treated independent resources, though options remain deriving NETREF from another should user desire. Refer Figure below. clock registers arranged somewhat differently T8110 than previous Ambassador devices. First, most features have been given independent registers. example, main clock select, which occupied part byte T8100, T8100A, T8102, T8105, accessible through register. addition, registers arranged driver-friendly manner simplify command parsing. general, programmers will find this structure easier developing applications. technical reference describes clock functions more detail. Clock fallback triggered more watchdogs (clock monitors). clock register actually complete sets registers. copy acts primary other copy acts secondary set. watchdog event causes fallback, secondary register will assume control main clock path. sets dubbed control registers used control read write access sets.
NR1_SEL_OUT
NR1_DIV_IN
PROGRAMMABLE INVERSION
PROGRAMMABLE INVERSION CT_NETREF2 NETREF1 DIVIDE-BY-N NETREF1 (FROM XTAL2) SOURCE SELECT CT_NETREF1 SELECT DIVIDE REGISTER
(FROM XTAL1)
LREF[0:7]
SOURCE SELECT
NETREF2 CT_NETREF1
SELECT NETREF2 DIVIDE-BY-N CT_NETREF2 DIVIDE REGISTER
PROGRAMMABLE INVERSION PROGRAMMABLE INVERSION NR2_SEL_OUT NR2_DIV_IN
5-9433a
Figure NETREF Paths
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Clock Architecture (continued)
fixed secondary mode, primary will reassume control when fallback cleared. Thus, primary reprogrammed while secondary control. switch from secondary back primary issued immediate event command, timed event synchronized internal frame. rotating secondary mode, primary will reassume control when fallback cleared. Thus original secondary become primary, original primary become secondary. When fallback cleared, fallback mechanism rearmed. Figure illustrates these ideas graphically. Fallback also disabled forced command.
FALLBACK EVENT
PRIMARY REGISTER
SECONDARY REGISTER FALLBACK CLEARED
FIXED SECONDARY SCENARIO
FALLBACK EVENT
FALLBACK CLEARED
REGISTER
REGISTER
FALLBACK CLEARED
FALLBACK EVENT
ROTATING SECONDARY SCENARIO
5-8917a
Figure Clock Register Transfer During Fallback
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Frame Group
frame group T8110 derived from original T8100. Rather than have groups sequential pulses, however, T8110 provides eight independently programmed signals. frame group signals have starting value that programmable 30.5 increments (equal time). This improvement from T8100A, T8102, T8105 which have programmable resolution Frame group signals repeat once every either high-going pulse low-going pulse, pulse width bit, bits, byte, bytes wide. times MHz, MHz, MHz. Frame group signal swapped favor programmable 16-bit asynchronous counter. This counter clocked internal frame sync external signal from frame signal When frame sync source, minimum count maximum count 8.192 frame signal pins used part frame group, they used external I/O. Figure below.
REGISTER WRITE
REGISTER READ I/O0 FRAME GENERATOR ENABLE FRAME SIGNAL REGISTER
REGISTER WRITE
REGISTER READ I/O7 FRAME COUNTER
FRAME GENERATOR
ENABLE
FRAME SIGNAL REGISTER
5-8916a
Figure Frame Group
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
General-Purpose
General-purpose (GPIO) T8110 nearly identical those found T8100A, T8102, T8105. previous designs, physical registers required: enable, direction (read/ write). Unlike earlier devices, though, bits accessible times (there multifunction requirements GP7). addition operating eight independent I/Os, following features available GPIO signals:
clock master. used H.110 clock master indicator. Coupled with clock master enable register, will automatically indicate clock master then used drive external clock FETs required H.110 specification. Forwarded PCI_RST# status. forwarded version PCI_RST#. External interrupts. GPIO signals used externally sourced inputs into interrupt controller logic. Diagnostics. GPIO signals used observe predefined internal test points.
Stream Rate Control
There total available streams T8110. These divided between H.1x0 streams) local streams. streams bidirectional with rates 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s. H.1x0 streams divided into blocks odd-numbered streams even-numbered streams, following convention earlier Ambassador devices. local streams arranged (0-15) high (16-31). stream rates both H.1x0 local programmed groups four. Thus, there total independently controlled groups. local stream groups offer additional rate choice 16.384 Mbits/s. this chosen, then resources assigned each local pair (even-odd, e.g., local local used multiplexed pair 8.192 signals single pin, yielding 16.384 throughput single stream. pair must used outputs, e.g., local inputs.
Minibridge
purpose minibridge provide means accessing non-PCI devices T8110. Examples this framers, HDLC controllers, DSPs. Since these devices already pass data from Ambassador family members Local serial streams, this bridging ability provides natural migration existing architectures PCI-based platforms. non-PCI side provides eight programmable chips select lines, address lines, data lines, read strobe write strobe plus programmable wait-states. chip selects strobes inverted. non-PCI memory space block that further subdivided using programmable chip selects. registers required each chip select. Each eight chip selects responds fixed portion space. data transferred based chip select strobe timing. Independent programmable wait-states available both read write timing. Wait-states placed three positions each strobe: prior assertion leading edge (set up), prior assertion trailing edge (width), prior deassertion chip selects (hold). Chip selects strobes have programmable inversions. Address setup hold times relative strobe signals also programmable.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Minibridge (continued)
structure minibridge shown Figure below.
PCI_AD[15:0] (ADDRESS PHASE)
ADDR HOLD
MB_A[15:0]
HOLD ADDRESS POSTED WRITES DELAYED READ REQUESTS
[15:13]
ADDRESS DECODER
MINIBRIDGE CONTROL REGS 0x00700-780 CHIP SELECT STROBE GENERATOR
MB_CS7 MB_CS6 MB_CS5 MB_CS4 MB_CS3 MB_CS2 MB_CS1 MB_CS0
PCI_AD[31:16] (ADDRESS PHASE) PCI_CBE#
MINIBRIDGE ACCESS REQUEST DETECT
CONTROL STROBE GENERATOR
MB_RD MB_WR
HOLD DATA POSTED WRITES PCI_AD[31:16] (DATA PHASE) UNUSED DATA HOLD MB_D[15:0] DATA HOLD HOLD DATA DELAYED READ COMPLETIONS
2223
PCI_AD[15:0] (DATA PHASE)
Figure Minibridge Functional Diagram
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Error Reporting Interrupt Control
T8110 offers interrupt controller managing both internal external events. Internally, clock errors routed CLKERR output both clock system errors prioritized reporting SYSERR output sent interface INTA# line. functional diagram error control section each H.1x0 clock line shown below Figure
CLOCK ERROR SYSTEM ERROR FALLBACK CLKERR1
CLOCK RESET WATCHDOG ENABLE WATCHDOG RESET CLKERR1
CLKERR2
CLKERR2 CLEAR CLKERR ENABLE SYSERR ENABLE FALLBACK ENABLE
5-8914a
Figure H.1x0 Clock Error Management From this point, clock errors routed directly clock error interrupt controller that tied system error pin. Clock fallback discussed Section Clock Architecture. interrupt controller combines clock errors, system errors, external inputs from I/O, weights them sends them SYSERR optionally INTA# bus. This arrangement permits direct interrupt management (via SYSERR pin) implementation PCI-based interrupt management. T8110 contains registers controlling, masking, prioritizing interrupts. available modes tiered flat. Flat refers equal priority equivalent function except that interrupt vector available. Tiered refers three-level priority scheme. clock errors equally weighted highest tier, followed system errors equally weighted middle tier, followed external errors equally weighted lowest tier. vector available each interrupt, nested interrupts available programming option (higher tier interrupting lower tier).
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Connection Control-Standard Virtual Channel
heart T8110 novel robust connection control arrangement. Enough data storage provided following operations: Connection Capacity Mode Mode Mode Mode Mode Mode 4,096 simplex, single buffered 2,048 simplex, double buffered 2,048 simplex, single buffered, 1,024 simplex, double buffered 2,048 simplex, single buffered 1,024 simplex, double buffered standard switching Virtual Channels
Standard switching utilizes associative memory constructs similar contents-addressable memory (CAM) architecture found other Ambassador series devices. T8110 provides entries streams time slots connection memory, total 8,192 equal streams time-slots/stream. This divided into four pages 2,048 entries that parallel. Pages associated with major stream groups: H.1x0 streams, H.1x0 even streams, local lower streams, local upper streams. given connection requires entries, describing from other describing Each these halves points assigned (programmed) location data memory. Thus, half connection controls transfer data into data memory location, other half controls transfer data data memory location. This illustrated below Figure
H.1x0 EVEN, H.1x0 ODD, LOCAL LOW, LOCAL HIGH
CONNECTION MEMORY
DATA MEMORY DEEP EACH
DEEP EACH
MEMORY ACCESS CHANNEL CONTROL
H.1x0 STREAMS, EVEN H.1x0 STREAMS, LOCAL STREAMS, LOCAL STREAMS, HIGH
5-8913a
Figure Standard Connection
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Connection Control-Standard Virtual Channel (continued)
standard modes achieved operating data memory pages either single page deep, alternating-page arrangement. This latter mode useful maintaining virtual frames across real frame boundaries. virtual channel operation relies several items: virtual channel configuration memory, virtual channel controller, descriptor controller. first items required data storage switching from streams. last item used conjunction with mastering creating efficient transfer mechanism from T8110 across local bus. virtual channel operation, connection memory longer references data memory access controller directly. Instead, connection memory references virtual channel memory, which turn references data memory. side, similar indirect access mechanism takes place. descriptor controller accesses table external memory that turn points specific buffer also external memory. data virtual channel buffer T8110 transferred from) external buffer means virtual channel controller, descriptor controller interface. virtual channels have following features:
channels treated circular buffers both data memory buffers residing external memory, well. starting address channel buffer occupy location T8110 data memory. external buffer likewise occupy appropriate memory space. size (depth) channel buffer variable, from minimum dwords bytes) maximum dwords (256 bytes). Externally, range from bytes Kbytes. result, internal external buffers have same size.) maximum channels permitted each page data memory channel count maximum, buffer depth minimum). Bonded H.1x0 channels permitted, constrained consecutive time-ordered time slots (i.e., scatter-gather DMA). Subrate packing1 permitted though simultaneously with bonded H.1x0 channels.
user provides descriptors each virtual channel data memory descriptors provided external buffers, well. External buffer descriptors reside different portion external memory from actual buffers. rest information required making n-by-64K packet switching carried connection memory entry. Figure shows virtual channel switching H.1x0 side.
Subrate unpacking also achieved when using data modes along with method described T8100A/02/05 data sheets.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Connection Control-Standard Virtual Channel (continued)
side, transfers from host memory semiautonomous. interface operating master mode these transfers; thus, controls access from bus. external buffer viewed shared resource with another device (microprocessor, Ethernet multi access controller [MAC], etc.) protocol external buffer requires pointers: under control T8110 other available external device. this way, external buffer treated dual-port buffer, data operations operate asynchronously.
CONNECTION MEMORY
H.1x0 EVEN, H.1x0 ODD, LOCAL LOW, LOCAL HIGH
DATA MEMORY MEMORY ACCESS CHANNEL CONTROL DEEP EACH
DEEP EACH
CHANNEL MEMORY DEEP
H.1x0 STREAMS, EVEN H.1x0 STREAMS, LOCAL STREAMS, LOCAL STREAMS, HIGH
5-8912a
Figure Virtual Channel Switching (H.1x0 Side) descriptor table created external memory managing external buffers one-to-one correspondence with internal virtual channels T8110. alleviate some confusion this type system will create, term upstream defined passing data external buffer. Similarly, downstream used denote data retrieved from external buffer.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Connection Control-Standard Virtual Channel (continued)
upstream operation, virtual channels from data memory transferred order availability (i.e., when they're full) into outbound (write) FIFO. T8110 fetches descriptor associated virtual channel, then uploads data. finishes updating external buffer's descriptor. T8110 thus controls write pointer external buffer (via descriptor table). microprocessor intelligent peripheral) will control read pointer, also through descriptor table. This illustrated below Figure
H.1x0
DATA MEMORY
T8110
n-BY-64K DATA
VIRTUAL CHANNEL ACCESS POINTER CONTROLS
BUFFERED n-BY-64K DATA
WRITE FIFO
UPSTREAM DATA PACKET
CONTROL INFO
CONTROL HANDSHAKE
VIRTUAL CHANNEL DESCRIPTOR
DESC CONTROL
CHANNEL CONTROLLER
ADDRESS FIFO
MASTER
EXTERNAL ADDRESSES
STATUS OTHER SECTIONS READ FIFO
INCOMING BUFFER STATUS
ADDRESSING ACCESS CONTROL PCI-SPACE MEMORY BUFFER WRITE POINTER PCI-SPACE MEMORY BUFFER DESCRIPTOR DATA PACKET UPSTREAM DATA PACKET ADDRESSING ACCESS CONTROL BUFFER STATUS
READ POINTER (NOT CONTROLLED T8110)
5-8911
Figure Upstream Data Management
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Connection Control-Standard Virtual Channel (continued)
downstream operation, empty virtual channel buffers will cause T8110 seek additional data from corresponding external buffer. T8110 will fetch descriptor info, then retrieve data, finish updating descriptor. retrieved data comes through read data FIFO transferred into virtual channel buffer within T8110. this case, T8110 controls read pointer buffer through descriptor table, microprocessor peripheral controls write pointer. Refer Figure below.
H.1x0 T8110 INCOMING BUFFER STATUS n-BY-64K DATA VIRTUAL CHANNEL ACCESS POINTER CONTROLS VIRTUAL CHANNEL DESCRIPTOR DESC CONTROL BUFFERED UNPACKED DATA READ FIFO DOWNSTREAM DATA PACKET CONTROL HANDSHAKE MASTER
DATA MEMORY
STATUS
CONTROL INFO
CHANNEL CONTROLLER
ADDRESS FIFO
EXTERNAL ADDRESSES
ADDRESSING ACCESS CONTROL PCI-SPACE MEMORY BUFFER DATA PACKET WRITE POINTER (NOT CONTROLLED T8110) DOWNSTREAM DATA PACKET ADDRESSING ACCESS CONTROL PCI-SPACE MEMORY BUFFER DESCRIPTOR BUFFER STATUS
READ POINTER
5-8910
Figure Downstream Data Management both upstream downstream cases, T8110 access both pointer values monitor read overflows (reading past write pointer) write overflows (overwriting unread data), take appropriate action. peripheral controller which controlling pointer used T8110 assumed following similar protocol (status read, data transfer, status write) maintain consistent operation. T8110 requires multiple accesses external memory space (two status, data) order perform these operations. Under maximum buffering conditions (512 virtual channels comprised 8-byte buffers), estimated that T8110 require much bandwidth (this includes overhead). Thus, maximum number buffers used, sparsely populated local recommended. When external buffers larger, i.e., bytes each buffers), then bandwidth requirement only about general, fewer, deeper virtual channels make T8110 more efficient from bandwidth perspective. bandwidth requirements tenths percent small number very deep channels.
Agere Systems Inc.
Ambassador T8110 PCI-Based H.100/H.110 Switch Packet Payload Engine
Ambassador Selection Guide
Ambassador Products
Features Number Connections: Local Local Local H-bus Number Local Data Local Data Rates Supported Subrate Switching Intel/Motorola Microprocessor Interface 32-bit Interface Minibridge H-bus/L-bus Packet Switching StarFabric Interface Package Type Power Supply Voltage T8100A 1024 16I/16O Mbits/s 4-bit SQFP PBGA T8102 16I/16O Mbits/s 4-bit SQFP PBGA T8105 1024 16I/16O Mbits/s 4-bit SQFP PBGA T8110 T8150
4096
4096
Mbits/s Mbits/s 4-bit 4-bit PBGA PBGA
T8102, local-to-local connections achieved through L-H-L switching.
Below subset Agere products that could complement Ambassador family your application. Product Family Analog Line Card Solutions Description Complete integrated circuit line card solution. Products included protection, switches, SLIC, codec, ringing. Portfolio backplane interface devices that interconnect UTOPIA Level Acell bus. Product family targeted enterprise phone market, well suited small office gateways consumer phones. Website www.agere.com/alc
CelXpresAInterconnect
www.agere.com/A
Phone-On-A-ChipVoIP Solutions
www.agere.com/phone_chip
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Tower, Century Boulevard Pudong, Shanghai 200121 Tel. (86) 50471212, (86) 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 3507670 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Ambassador registered trademark Phone-On-A-Chip CelXpres trademarks Agere Systems Inc.
Copyright 2001 Agere Systems Inc. Rights Reserved Printed U.S.A.
July 2001 OT01-285CTI

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