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VSC9186 VSC9186 Killington Quad STS-48/STM-16 STS-192/STM-64 Line


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VSC9186
VSC9186 Killington Quad STS-48/STM-16 STS-192/STM-64 Line Interface
2.5V 1.8V Core Power Supplies 0.18µ CMOS Technology 720-pin CCGA /1.0mm Column Pitch Maximum Power Consumption
SPLITTER/COMBINER MODE (DWDM): Four independently-timed 2.5Gb/s SONET/SDH signals received, terminated, monitored line level. They pointer processed local time domain, passed through STS-1 level crossconnect, multiplexed STS-192/STM-64 signal. STS-192/STM-64 received opposite direction pointer processed local clock. signal crossconnected STS-1 level then demultiplexed four STS-48/STM-16 signals. Full section line termination performed five SONET interfaces. Overhead transparency supported through external interface maximum customer flexibility. Killington devices used East/West ring configuration forming logical 40Gb/s crossconnect. bidirectional interfaces allow loopback four STS-48/STM-16 STS-192/ STM-64 interfaces simultaneously.
Bidirectional Quad STS-48/STM-16 STS-192/ STM-64 Section Line Termination Device with Pointer Processing Time Slot Interchange Accommodates 300ppm Difference Between Incoming Local System Clock Performs Pointer Processing Quad Independent STS-48/ STM-16 Single STS-192/STM-64 Pointer Processing Concatenation Levels Including STS-192c, STS-48c, STS-12c, STS-3c, STS-1 Three ports featuring Serial 622Mb/s Timestream Backplane Interfaces with Integrated Other Line Interfaces Switch Section/Line Drop/Insertion with External Interfaces Channels Supports Section/Line Overhead Transparency Protection Interface Allows Full STS-1/STM-0 Hairpinning Drop/Continue Both Tributary Ring Traffic Integrated Bidirectional STS-1 Level Crossconnects Embedded Hardware UPSR Compliant with SONET Requirements Stated ANSI T1.105, Bellcore GR-253-CORE ITU-T G.707 Provides JTAG Controller Conforming IEEE 1149.1 Standard Bidirectional Path Monitoring
Four independently-timed 2.5Gb/s signals single 10Gb/s SONET/SDH signal received, terminated, monitored line level. incoming STS-1 signals sent through STS-1 switch that allows ring loopback hairpinning tributaries from either line interface backplane interface. parity supported both interfaces backplane integrity monitoring. backplane receive circuitry built-in data recovery realignment working protection LVDS inputs. These signals then crossconnected again STS-1 level through transmitted either four STS-48/STM-16 STS-192/STM-64 interface.
PB-VSC9186-001
VSC9186
VSC9186 Killington Quad STS-48/STM-16 STS-192/STM-64 Line Interface
GENERAL DESCRIPTION: VSC9186 bidirectional quad STS-48/STM-16 OC-192/STM-64 framer pointer processor. addition full path overhead monitoring, section line termination available line inputs outputs. bidirectional protection interface allows both line tributary traffic looped back simultaneously through companion device. UPSR implemented entirely hardware driven STE/LTE logic, pointer interpreter path overhead monitor. VSC9186 supports transparency off-chip using XILINX Virtex (XC2V1000-4FG256C). verified reference design available with purchase. VSC9186 used SONET/SDH applications such Time Slot Interchange (TSI) switches, digital crossconnects, add/drop multiplexers, DWDM terminal multiplexer applications.
VSC9186 BLOCK DIAGRAM:
Interface RefSync OC-192 4xOC-48
Interpreter Pre-Buffer
External Switch Control
768x288
Data Clock(s) Quad OC-48
RSLOP-192 RSLOP-48
Generator
Elastic Store
High Speed Interface
Data Clock Clock
Path Overhead Processor OC-192 Data Clock Clock Quad OC-48 External Switch Control TSLOP-48 TSLOP-192
Generator
768x288
OC-192
Interpreter Elastic Store Pre-Buffer
High Speed Interface
Data Clock
SouthRx
NorthRx
SouthTx
NorthTx
RefClk BACKPLANE/OC-192 LINE INTERFACE
OC-48 OC-192 LINE INTERFACE
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