Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226B DATA SHEET PRODU
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EtherMapTM-3 Device
Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226B DATA SHEET PRODUCT PREVIEW FEATURES
Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface Supports single 1000 Mbit/s Ethernet port, using parallel GMII interface (lead shared with SMII interfaces) Supports Ethernet Management interface control configuration externally connected PHYs. Supports IEEE 802.3 Half Duplex mode 10/100 Mbit/s Full Duplex mode 10/100/1000 Mbit/s Ethernet ports Supports IEEE 802.3 Management Statistics (RMON) Supports Ethernet frame encapsulation/decapsulation protocols: ITU-T G.7041, Generic Framing Procedure (GFP) ITU-T X.86/X.85, Link Access Procedure (LAPS) ITU-T Q.922, Link Access Procedure Frame Mode (LAPF) RFC1662/2878, Bridging Control Protocol (BCP) Performs mapping/demapping encapsulated Ethernet frames into/from order (VT1.5 SPE/VC-12) high order (STS-1 SPE/VC-3) virtual concatenated payloads Performs mapping/demapping encapsulated Ethernet frames into/from single contiguous concatenated (STS-3cSPE/VC-4) payload single Low/High order (VT1.5/VC12/STS-1/VC-3) payload Supports optional on-chip LCAS processing (per ITU-T G.7042) high order virtual concatenated payloads Glueless memory interface external 64/128/256 Mbit SDRAMs Supports 84/63 VT/TU Order Pointer processing Supports High Order processing STS-1/VC-3/STS-3c/VC-4 Byte-wide parallel Drop Telecom interfaces Supports per-port Ethernet side SONET/SDH system side loopback system level diagnostics 16-bit wide microprocessor interface, selectable between Motorola Intel Boundary scan (IEEE 1149.1 standard) 3.3V +1.8V power supplies, tolerant leads 400-lead plastic ball grid array package (PBGA, Device Driver
EtherMapTM-3 highly integrated device that provides mapping 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport payloads. device supports connection eight 10/100 Mbit/s Ethernet ports, using SMII interfaces, single 1000 Mbit/s Ethernet port, using GMII interface. Ethernet frames encapsulated using either LAPS, LAPF PPP/BCP protocol. encapsulated Ethernet frames then mapped into either virtually concatenated high order payloads, such VT1.5 SPE/VC-12/STS-1 SPE/VC-3, into contiguously concatenated payloads such STS-3c SPE/VC-4. high order SONET/SDH generation processing/termination performed. byte-wide parallel interface Telecom format provides SONET/SDH interface support either Drop timing modes. addition support full-rate Ethernet transfer, over-subscribed Ethernet transfers also supported using back pressure mechanisms (half full duplex flow control) order prevents frame loss. External SDRAM used buffering Ethernet frames support bandwidth oversubscription flow control operation well used receive SONET/SDH container alignment differential delay compensation high order virtually concatenated payloads. both high order virtual concatenated payloads, optional onchip standards based LCAS processing provided allow hitless dynamic bandwidth adjustments. powerful hardware RTOS independent EtherMap device driver provides full access features device through APIs. utilizes matched get/set functions easily ported.
APPLICATIONS
SONET/SDH add/drop terminal multiplexers Multi-service access platforms (MSAP) Compact Access platforms DSLAMS Wireless Backhaul Electronics (RNC/BSC)
TELECOM SIDE
+1.8V +3.3V
HO/LO RING Ports
HO/LO Ports
Controls
CLOCKS (SONET/SDH Ref, System, Sec.)
ETHERNET LINE SIDE
EtherMap-3
DROP
Ethernet into STS-3/STM-1 SONET/SDH Mapper
10/100 Mbit/s SMII (Port 1000 Mbit/s GMII
TXC-04226B
10/100 Mbit/s SMII (Port
U.S. and/or foreign patents issued pending Copyright 2003 TranSwitch Corporation EtherMap trademark TranSwitch Corporation PHAST, TEMx28, TranSwitch registered trademarks TranSwitch Corporation
Microprocessor SDRAM Interface Interface
Boundary Scan
Ethernet Management Interface
Document Number: PRODUCT PREVIEW TXC-04226B-MB, October 2003
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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EtherMap-3 TXC-04226B
DATA SHEET
TABLE CONTENTS
Section Page
List Figures List Tables Features Mappings Encapsulation Protocols Ethernet Ports 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block SDRAM Interface Telecom Timing Alarm Indication Port Interface Port Interface Microprocessor Interface JTAG Interface Block Diagram Block Diagram Description Data Processing/Flow 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block Mapper Block Demapper Block Ethernet Ports Microprocessor Interface SDRAM Memory Interface Parallel Telecom Interface High Order (Path Overhead Byte) Port Interface High Order Alarm Indication Port Interface Alarms Performance Monitoring Blocks JTAG Interface Power-Up Sequencing Application Example Lead Diagram Lead Descriptions Absolute Maximum Ratings Environmental Limitations (Referenced VSS) Thermal Characteristics Power Requirements Input, Output Input/Output Parameters Timing Characteristics Operation SONET/SDH Processing General Transmit High Order Path Termination (VC-3/VC-4/STS-1/STS-3C Generator) General F3/Z3, K3/Z4, N1/Z5 Receive High Order Path Termination (VC-3/VC-4/STS-1/STS-3C Monitor) General F3/Z3, K3/Z4, N1/Z5 High Order Port Interface High Order Alarm Indication Port Interface AU-4 AU-3 Pointer Generation Drop Timing Mode Timing Mode Timing Mode TU-3 Pointer Generation TU-3 Pointer Tracking VC-3/STS-1/TUG-3 Timeslot Interchange
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EtherMap-3 TXC-04226B
TABLE CONTENTS (cont.)
Section Page
TU/VT Pointer Tracking TU/VT Pointer Generation Order Timeslot Interchange Transmit Order Path Termination (Low Order Generator) General BIP-2 Signal Label REI/RDI K4/Z7 N2/Z6 Receive Order Path Termination (Low Order Monitor) General BIP-2 Signal Label REI/RDI/RFI K4/Z7 N2/Z6 Order High Order Path Monitor Alarm Registers Order Port Interface Order Alarm Indication Port Interface Virtual Concatenation LCAS Order Virtual Concatenation without LCAS Order Virtual Concatenation with LCAS High Order Virtual Concatenation without LCAS High Order Virtual Concatenation with LCAS Configuration General Transmit Virtual Concatenation (Ethernet SONET/SDH) Transmit side VCAT add/remove non-lcas Special Configuration Transmit LCAS Receive Virtual Concatenation Receive VCAT add/remove non-lcas Differential Delay Compensation Maximum Differential Delay Allowed Maximum Differential Delay Detected Ethernet Line Interfaces Ethernet Blocks Ethernet Half Duplex Carrier Sense Collision Detection Alternate Truncation Excessive Collisions Half-Duplex Flow Control Flow Control Operation Encapsulation/Decapsulation Host Insertion/Extraction Management/Control Frames Linear Frame Mode Operation Transmit Side Linear Extension Header Transmit Side Configuration Tables Receive Side Linear Extension Header Receive Side Configuration Tables LAPS LAPF (with Support) SDRAM Controller SDRAM Memory Interface Latency BANK/ROW Activation Commands Reset Configuration SDRAM Controller Configuration Changes/Initialization
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TABLE CONTENTS (cont.)
Section Page
Microprocessor Access SDRAM Reset Operation General External Lead Controlled Hardware Reset Microprocessor Controlled Hardware Reset Microprocessor Controlled Soft Reset Microprocessor Controlled Global Performance Counter Reset Telecom Operation General Drop Interface Drop Parity Selection Interface Timing Modes Parity Selection Delay Force VC-3 VC-4 High Impedance Force TUG-3 High Impedance Force TUG-2 High Impedance Force TU-11/TU-12 High Impedance Loop Backs Loopback Telecom Loopbacks Boundary Scan Introduction Boundary Scan Operation Boundary Scan Reset Boundary Scan Chain Memory Information General Device Registers Table through General Configuration Status Device Ethernet Registers Tables through Status Information Tables through Configuration Tables through Management Interface (used MAC0 only) Ethernet Registers Tables through Configuration, Alarms Interrupts Ethernet MACs Encapsulation Registers Tables through Configuration, Status Alarms Encapsulation Block Decapsulation Registers Tables through Configuration, Status Alarms Decapsulation Block SDRAM Control Registers Table SDRAM Control SDRAM Interface Configuration Table Microprocessor Access SDRAM (Indirect Access) Virtual Concatenation Registers Tables through Configuration, Status Alarms Transmit (Ethernet SONET) Virtual Concatenation Block Virtual Concatenation Registers Tables through Configuration, Status Alarm Receive (SONET Ethernet) Virtual Concatenation Block Ethernet SONET Handling Registers Tables through Configuration Status Ethernet Frame Format Block (Output Ethernet MAC) Table through Ethernet Buffering Flow Control Transmit (Ethernet SONET) Receive (SONET Ethernet) Paths Mapper Block Registers Tables through Configuration, Status Interrupt handling Transmit Mapper Block Tables through Configuration Transmit Mapper Block DeMapper Block Registers Tables through Configuration, Status Alarms Receive Demapper Block Tables through Configuration, Status Alarms Order Monitor Tables through Configuration, Status Alarms Order Alarm Indication (RING) Port Table Configuration Order Alarm Indication (RING) Port Tables through Configuration Status general Order Interrupt Controller Table Configuration High Order Alarm Indication (RING) Port
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EtherMap-3 TXC-04226B
TABLE CONTENTS (cont.)
Section Page
Tables through Configuration, Status Alarms High Order Alarm Indication (RING) Port Tables through Configuration, Status Alarms High Order Monitor Tables through Configuration, Status Alarms Tracker Tables Configuration Cross Connect Tables through Configuration, Status Alarms Generator Tables through Configuration High Order (VC-3 VC-4) Generator Tables through Configuration, Status Alarms Retimer Tables through Configuration, Status Alarms AU-3/4 Retimer Tables through Configuration Status General High Order Interrupt Controller Tables through Configuration, Status Alarms Combus Interface Tables through Configuration, Status Alarms Combus Interface Tables through Configuration Status General Combus Interface Interrupt Controller Tables through Configuration Status General VTMAPPER Interrupt Controller Alarms, Performance Fault Monitoring Terminology System Alarm (Raw, Unlatched Alarm) Alarm Event Latched Alarm Secondary Alarm Inhibition Trail Signal Failure (TSF) Server Signal Failure (SSF) Interrupt Mask Performance Fault Monitoring Performance Monitoring (PM) Fault Monitoring (FM) 1-Second Clock Performance Counters Unlatched Alarms Inhibition Secondary Unlatched Alarm Generation Latched Alarms Latched Alarm Bits Interrupt Generation (Lalarm_name/L1alarm_name) Latched Alarm Masking Bits (Malarm_name) Secondary Latched Alarm Inhibition Latched Alarm Bits PM/FM (L2ALARM_name), Performance Monitoring Bits; Palarm_name) Fault Monitoring Bits; Falarm_name) Positive Edge Events Negative Edge Events Positive Negative Edge Events Overall Alarm Generation PM/FM Process Diagram Performance Counters Scheme Counters with Roll-Over/Saturation Option Scheme Performance Counters with 1-second Shadow Register Option Alarm Feature Combinations System Alarm, Interrupt, PM/FM Hierarchy Alarm Interrupt Tree Register Tree Mapper/Demapper Performance Monitoring Mapper/Demapper Interrupt Tree Mapper/Demapper PM/FM Tree Block Mapper/Demapper Consequent Actions Block Package Information Ordering Information Related Products Standards Documentation Sources List Data Sheet Changes
Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
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LIST FIGURES
Figure
Page
Functional Block Diagram EtherMap-3 Order Virtual Concatenation Structure SONET High Order Virtual Concatenation Structure SONET Typical Application using EtherMap-3 PHAST-3N Devices EtherMap-3 TXC-04226B Lead Diagram Drop Timing (Only APAR, Output) Drop Timing (Only APAR, Output) Drop Timing (all Signals Outputs) Drop Timing (all Signals Outputs) Timing (Timing Signals Inputs) Timing (Timing Signals Inputs) Timing (Timing Signals Outputs) GMII Ethernet Interface GMII Ethernet Interface Tx/Rx SMII Ethernet Interface (SYNC Output) Tx/Rx SMII Ethernet Interface (SYNC Input) Ethernet Management Interface SDRAM Interface Single Word Read SDRAM Interface Single Word Write SDRAM Interface Burst Read SDRAM Interface Burst Write VC-3 Byte Interface VC-3 Byte Interface Order Byte Interface Order Byte Interface VC-3 Alarm Indication Port Interface VC-3 Alarm Indication Port Interface Order Alarm Indication Port Interface Order Alarm Indication Port Interface Asynchronous Microprocessor Interface: Intel-type Write Cycle Timing Asynchronous Microprocessor Interface: Intel-type Read Cycle Timing Asynchronous Microprocessor Interface: Motorola 68360-type Write Cycle Timing Asynchronous Microprocessor Interface: Motorola 68360-type Read Cycle Timing Synchronous Microprocessor Interface: Motorola MPC860-type Read Cycle Timing Synchronous Microprocessor Interface: Motorola MPC860-type Write Cycle Timing Boundary Scan Timing Functional Block Diagram Mapper/Demapper Functional Model Mapper/Demapper Mapper/Demapper Bypass Modes VT1.5-Xv-SPE Structure VC-11-Xv Structure Multiplexing Structure Supported EtherMap-3 Multiplexing Structure Supported EtherMap-3 Multiplexing Structure Supported EtherMap-3 SONET Multiplexing Structure Supported EtherMap-3 STS-1-Xv-SPE Structure VC-3-Xv Structure Multiplexing Structure Supported EtherMap-3 SONET Multiplexing Structure Supported EtherMap-3 EtherMap-3 Switch Interconnection Using GMII Interface Format Frame with Ethernet Frame Payload Format LAPS Frame with Ethernet Frame Payload
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EtherMap-3 TXC-04226B
LIST FIGURES (cont.)
Figure
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Format LAPF Bridged Frame with Ethernet Frame Payload Format Frame with Ethernet Frame Payload Loopback Telecom Loopbacks Boundary Scan Schematic Latched Alarm (L1Alarm_name) Transitions Positive Edge Event PM/FM Signal Generation Negative Edge Event PM/FM Signal Generation Positive/Negative Edge Event PM/FM Signal Generation Alarm, Interrupt PM/FM Generation Process Alarm, Interrupt PM/FM Generation Process (Inhibition Function) Alarm Interrupt Hierarchy Alarm Interrupt Tree Part Alarm Interrupt Tree Part Part Alarm Interrupt Tree Part Part Alarm Interrupt Tree Part Parts Alarm Interrupt Tree Parts Parts Alarm Interrupt Tree Parts Parts Alarm Interrupt Tree Parts Part Alarm Interrupt Tree Part Register Tree Parts Register Tree Parts (continued) Mapper/Demapper Interrupt Tree Part Mapper/Demapper Interrupt Tree Part Parts Mapper/Demapper Interrupt Tree Parts Part Mapper/Demapper Interrupt Tree Part Mapper/Demapper RX_VC3_POH_MONITOR PM/FM Trees Mapper/Demapper MONITOR PM/FM Trees Mapper/Demapper COMBUS PM/FM Trees Mapper/Demapper RX_TU3_PTR PM/FM Trees Mapper/Demapper TX_TU3_PTR PM/FM Trees Mapper/Demapper COMBUS PM/FM Trees Mapper/Demapper LODMP_POHMONITOR PM/FM Trees Mapper/Demapper LODMP_Ptr PM/FM Trees EtherMap-3 TXC-04226B Package Diagram
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LIST TABLES
Table
Page
TU-3 Pointer Tracker/Retimer Modes TU-3 Pointer Generator Modes Configuration rMAXDELVCG_x Order Configuration rMAXDELVCG_x High Order Allowed Range High/Low Watermark Registers Scheduling Matrix Scheduling Matrix Mapped EtherMap-3 Register Memory Overview General Device Configuration (RW) General Device Status (RO) Registers (RO) Combined Receive Transmit Counters Receive Counters Transmit Counters Interface Status Registers Carry Carry Mask Registers Configuration Registers Station Address Registers Registers Half Duplex Registers Maximum Frame Registers Test Registers Mgmt Configuration Registers Mgmt Command Registers Mgmt Address Registers Mgmt Control Registers Mgmt Status Registers Mgmt Indicators Registers Block General Configuration (RW) Block Alarms (RO) Block Alarm Interrupt Masks (RW) Block Latched Alarms (RR) Block Interrupts (RO) Encapsulation Block General Configuration (RW) Encapsulation Block LAPS Configuration (RW) Encapsulation Block LAPF Configuration (RW) Encapsulation Block Configuration (RW) Encapsulation Block Configuration (RW) Encapsulation Block Control Frame Buffers (RW) Encapsulation Block Status (RW) Encapsulation Block Status Registers (RO) Encapsulation Block Performance Counters Encapsulation Block Alarms (RO) Encapsulation Block Alarm Interrupt Masks (RW) Encapsulation Block Interrupts (RO) Encapsulation Block Latched Alarms (RR) Decapsulation Block General Configuration (RW) Decapsulation Block LAPS Configuration (RW) Decapsulation Block LAPF Configuration (RW) Decapsulation Block Control Buffer Status (RW)
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EtherMap-3 TXC-04226B
LIST TABLES (cont.)
Table
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Decapsulation Block Link Status (RO) Decapsulation Block Configuration (RW) Decapsulation Block Configuration (RW) Decapsulation Block Buffers (RO) Decapsulation Block Alarms (RO) Decapsulation Block Alarm Interrupt Masks (RW) Decapsulation Block Latched Alarms (RR) Decapsulation Block Interrupts (RO) Decapsulation Block Performance Counters Decapsulation Block Status (RR) SDRAM Control General Configuration (RW) SDRAM Access Control Registers (RW) SDRAM Access Results Registers (RO) Virtual Concatenation Block General Configuration (RW) Virtual Concatenation Block LCAS Alarms (RO) Virtual Concatenation Block LCAS Alarm Interrupt Masks (RW) Virtual Concatenation Block LCAS Latched Alarms (RR) Virtual Concatenation Block LCAS Interrupts (RO) Virtual Concatenation Block Order Tributary Configuration (RW) Virtual Concatenation Block High Order Tributary Configuration (RW) Virtual Concatenation Block LCAS Configuration (RW) Address Offsets Virtual Concatenation Block Status (RO) Virtual Concatenation Block General Configuration Registers (RW) Virtual Concatenation Block Alarms (RO) Virtual Concatenation Block Alarm Interrupt Masks (RW) Virtual Concatenation Block Latched Alarms (RR) Virtual Concatenation Block Interrupts (RO) Virtual Concatenation Block Order Tributary Configuration (RW) Virtual Concatenation Block High Order Tributary Configuration (RW) Virtual Concatenation Block Status (RO) Virtual Concatenation Block Frame Counter Status (RO) Virtual Concatenation Block Differential Delay Status (RO) Ethernet Frame Format Block General Configuration (RW) Ethernet Frame Format Block Alarms (RO) Ethernet Frame Format Block Alarm Interrupt Masks (RW) Ethernet Frame Format Block Latched Alarms (RR) Ethernet Frame Format Block Interrupts (RO) SONET Ethernet General Configuration Watermarks (RW) SONET Ethernet SDRAM Alarms (RO) SONET Ethernet SDRAM Alarm Interrupt Masks (RW) SONET Ethernet SDRAM Latched Alarms (RR) SONET Ethernet SDRAM Interrupts (RO) SONET Ethernet SDRAM Performance Counters (RR) SONET Ethernet SDRAM FIFO Status (RO) Ethernet SONET Flow Control Configuration (RW) SDRAM Controller Alarm (RO) SDRAM Controller Direction) (RW) SDRAM Controller Directions) (RR) Ethernet SONET, SDRAM Output Interrupts (RO) Ethernet SONET, SDRAM Output Performance Counters
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LIST TABLES (cont.)
Table
Page
Mapper Block Reset (RW) Mapper Block Interrupt Configuration (RO) Mapper Block Interrupt Mask (RW) Mapper Demapper Block Status (RO) Mapper Block Timing Configuration (RW) Mapper Block TUG-3/VC-3 Configuration (RW) Mapper Block TUG-2 Configuration (RW) Mapper Block Pointer Configuration (RW) Mapper Block General Configuration (RW) Mapper Block TUG-2 Configuration (RW) Mapper Block Configuration (RW) Mapper Block Cross Connect Configuration (RW) Mapper Block Configuration (RW) Mapper Block Byte Values (RW) Mapper Block Bypass Control (RW) Demapper Block General Configuration (RW) Demapper Block Bypass Control (RW) Demapper Block TUG-2 Configuration (RW) Demapper Block Performance Counters (RO) Demapper Block Alarm Control (RW) Demapper Block Interrupts (RO) Demapper Block Alarms (RO) Demapper Block Latched Alarms (R/COW-1) Demapper Block Alarm Masks (RW) LODMP_Ptr_DefectCorrelations_LP (R/COW-0) LODMP_Ptr_DefectCorrelations_PM (RO) LODMP_Ptr_DefectCorrelations_FM (RO) Demapper Block Byte Monitors (RO) Monitor Bypass Control (RW) Monitor Trace Message Handling Monitor Byte Monitors (RO) Monitor Accepted Values (RO) Monitor Expected Values (RW) Monitor General Configuration (RW) Monitor Channel Configuration (RW) Monitor Channel Status (RO) Monitor Channel Report (RO) Monitor Channel Defects (RO) Monitor Defect Correlations (RO) Monitor Latched Defects (R/COW-1) Monitor Defect Correlations Latched PMFM (R/COW-0) Monitor Defect Correlations Monitor (RO) Monitor Defect Correlations Monitor (RO) Monitor Defect Correlations Mask (R/W) Monitor Defect Correlations Configuration (RW) Monitor Defect Correlations Summary (RO) Monitor Defect Correlations Summary Mask (RW) Monitor Defect Correlations Group Summary (RO) Monitor Performance Monitor Second Latch (RO) Monitor Performance Counters (RW) Monitor Performance Counter Shadow Registers (RO)
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EtherMap-3 TXC-04226B
LIST TABLES (cont.)
Table
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Ring Port General Configuration (RW) Ring Port Event Latch (COW-1) Ring Port Performance Counters (RW) Ring Port Performance Counter Shadow Registers (RO) Ring Port Defects Ring Port Interrupt Mask (RW) Ring Port Event Interrupt (RO) Ring Port Defect Interrupt (RO) Ring Port Configuration (RW) Interrupt Controller Interrupts (RO) Interrupt Controller Interrupt Masks (RW) Interrupt Controller Summary (RO) Ring Port Configuration (RW) Ring Port Configuration (RW) Ring Port Counter Configuration (RW) Ring Port Event Latch (COW-1) Ring Port Performance Counters (RW) Ring Port Performance Counter Shadow Registers (RO) Ring Port Defects Ring Port Interrupt Mask (RW) Ring Port General Interrupt (RO) Ring Port Defect Interrupt (RO) Monitor Received-64 Byte Trace Message (RO) Monitor Received 16-Byte Trace Message (RO) Monitor Accepted Bytes (RO) Monitor Expected Bytes (RW) Monitor Expected Bytes (RW) Monitor Received Bytes (RO) Monitor Accepted Bytes (RO) Monitor Configuration (RW) Monitor Loopback Control (RW) Monitor Channel Configuration (RW) Monitor Channel Status (RO) Monitor Channel Defects (RO) Monitor Message Status (RO) Monitor Defects (RO) Monitor Latched Defects (R/COW-1) Monitor Defect Masks (RW) Monitor Defects Latched PMFM (R/COW-0) Monitor Defects (RO) Monitor Defects (RO) Monitor Defect Configuration (RW) Monitor Defect Summary (RO) Monitor Defect Summary Mask (RW) Monitor Defect Group Summary (RO) Monitor Event (RO) Monitor Latched Event (R/COW-1) Monitor Event Mask (RW) Monitor Interrupt (RO) Monitor Performance Counters (RW) Monitor Performance Counters Second Latch (RO)
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LIST TABLES (cont.)
Table
Page
Monitor Performance Counter Shadow Registers (RO) Monitor Performance Counter Configuration (RW) Monitor Counter Reset (WO) Monitor PMFM Configuration (RW) Tracker General Configuration (RW) Tracker Channel Configuration (RW) Tracker Defects (RO) Tracker Defects Latched Interrupt (R/COW-1) Tracker Defects Latched PMFM (R/COW-0) Tracker Defects (RO) Tracker Defects (RO) Tracker Defect Masks (RW) Tracker Defect Summary (RO) Tracker Defect Summary Mask (RW) Tracker Defect Group Summary (RO) Tracker Performance Counters (RW) Tracker Performance Counter Shadow Registers (RO) Transmit VC-3/STS-1/TUG-3 Time Slot Interchange (RW) Receive VC-3/STS-1/TUG-3 Time Slot Interchange (RW) Generator General Configuration (RW) Generator Channel Configuration (RW) Generator Defects (RO) Generator Defects Latched Interrupt (R/COW-1) Generator Defects Latched PMFM (R/COW-0) Generator Defects (RO) Generator Defects (RO) Generator Defect Mask (RW) Generator Defect Summary (RO) Generator Defect Summary Mask (RW) Generator Defect Group Summary (RO) Generator Performance Counters (RW) Generator Performance Counter Shadow Registers (RO) Generator Channel Control (RW) Generator Configuration (RW) Generator Message Bytes (RW) Generator Insertion Values (RW) Generator Port Monitors (RO) Retimer General Configuration (RW) Retimer Channel Configuration (RW) Retimer Defects (RO) Retimer Defects Latched Interrupt (R/COW-1) Retimer Defect Masks (RW) Retimer Defect Group Summary (RO) Retimer Sequencer Configuration (RW) Retimer Sequencer Data (RW) AU-3/4 Retimer General Configuration (RW) AU-3/4 Retimer Channel Configuration (RW) AU-3/4 Retimer Defects (RO) AU-3/4 Retimer Defects Latched Interrupt (R/COW-1) AU-3/4 Retimer Defect Masks (RW) AU-3/4 Retimer Defect Group Summary (RO)
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EtherMap-3 TXC-04226B
LIST TABLES (cont.)
Table
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AU-3/4 Retimer Leak Reset Value (RW) AU-3/4 Retimer Performance Counters (RO) Interrupt Controller Interrupts (RO) Interrupt Controller Interrupt Masks (RW) Interrupt Controller Interrupt Group Summary (RO) Combus Interface General Configuration (RW) Combus Interface Channel Configuration (RW) Combus Interface Channel Status (RO) Combus Interface Defects (RO) Combus Interface Defects Latched Interrupt (R/COW-1) Combus Interface Defects Latched PMFM (R/COW-0) Combus Interface Defects (RO) Combus Interface Defects (RO) Combus Interface Defect Masks (RW) Combus Interface Defect Group Summary (RO) Combus Interface Channel Defects (RO) Combus Interface Channel Defects Latched Interrupt (R/COW-1) Combus Interface Channel Defects Latched PMFM (R/COW-0) Combus Interface Channel Defects (RO) Combus Interface Channel Defects (RO) Combus Interface Channel Defect Masks (RW) Combus Interface Channel Defect Summary (RO) Combus Interface Channel Defect Summary Masks (RW) Combus Interface Channel Defect Group Summary (RO) Combus Interface General Configuration (RW) Combus Interface AUG1 Configuration (RW) Combus Interface AU-3 Configuration (RW) Combus Interface TUG-2 Configuration (RW) Combus Interface TU11/TU12 Configuration (RW) Combus Interface Defects (RO) Combus Interface Defects Latched Interrupt (R/COW-1) Combus Interface Defect Masks (RW) Combus Interface Defects Latched PMFM (R/COW-0) Combus Interface Defects (RO) Combus Interface Defects (RO) Combus Interface Defect Group Summary (RO) Combus Interface Channel Defects (RO) Combus Interface Channel Defects Latched Interrupt (R/COW-1) Combus Interface Channel Defect Masks (RW) Combus Interface Channel Defects Latched PMFM (R/COW-0) Combus Interface Channel Defects (RO) Combus Interface Channel Defects (RO) Combus Interface Channel Defect Summary (RO) Combus Interface Channel Defect Summary Masks (RW) Combus Interface Channel Defect Group Summary (RO) Combus Interface Defect Configuration (RW) Combus Interrupt Controller Interrupts (RO) Combus Interrupt Controller Interrupt Masks (RW) Combus Interrupt Controller Interrupt Group Summary (RO) Mapper Interrupt Controller Interrupts (RO) Mapper Interrupt Controller Interrupt Masks (RW)
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LIST TABLES (cont.)
Table
Page
Mapper Interrupt Controller Interrupt Group Summary (RO) Reserved Registers Latched Alarm (L1Alarm_name) Transition Selection Latched Alarm (L2Alarm_name) Transition Selection
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EtherMap-3 TXC-04226B
FEATURES
EtherMap-3 supports following features: MAPPINGS EtherMap-3 maps Ethernet traffic 10/100 Mb/s SMII ports (1)1000 Mb/s GMII port onto SONET/SDH Performs Virtual Concatenation SONET/SDH, compensating differential delay Implements Link Capacity Adjustment Scheme (LCAS) allow size virtual concatenation groups changed dynamically with hitless switching. Supports both High Order Order Virtual Concatenation STM-1/AU-4/VC-4/C-4 STS-3/STS-1-SPE/VT-1.5, STS-3/STS-1-SPE, STS-3c/STS-3c-SPE supported virtual concatenation mappings mixed according [G.707] multiplexing structure total payload rate equivalent STS-3/STM-1 signal. Supports Mbit/s Mbit/s traffic ports). 10/100 Mb/s operation ports), virtually concatenate VC-12s VT1.5SPEs. Mb/s operation, single VC-4 single STS-3c used, virtually concatenate VC-12s VC-3s virtually concatenate VT1.5-SPEs STS-1-SPEs 1000 Mb/s either single VC-4, virtually concatenate VC-3s either single STS-3c-SPE, virtually concatenate STS-1-SPEs ENCAPSULATION PROTOCOLS EtherMap-3 supports four encapsulation protocols Ethernet MAC: LAPS (Link Access Procedure SDH) LAPF (Link Access Procedure Framed Mode service) (Generic Framing Procedure) (with support) ETHERNET PORTS EtherMap-3 provides following Ethernet Port features: Eight independent SMII (Serial Medial Independent Interfaces) 10/100 Mbit/s Ethernet Global reference clock Global Synchronization signal Lead selects Switch connection external client Single GMII (Gigabit MII) 1000 Mbit/s Ethernet Lead shared with SMII ports Selection GMII SMII selected through lead
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Ethernet Management Interface Switch Selection
10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK Compliant IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac Full Duplex Operation 10/100/1000 Mbit/s Half Duplex Operation 10/100 Mbit/s control layer provides support control frames including PAUSE frames Provides support statistics gathering based RMON Group RMON Group RMON Group RMON Group RMON Ethernet
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SDRAM INTERFACE Glueless interface external Mbits, Mbits, Mbits SDRAM devices Data, Address, Chip Select, Clock, Clock Enable, Address Strobe, Column Address Strobe, Write Enable Strobe, Data Mask, Bank Address leads Buffers TX/RX data transfers Clock frequency Programmable Refresh Period latency supported Refresh operation transparent user timing selected SDRAM must below TELECOM TIMING single Telecom interface provided interfacing SONET/SDH line through TranSwitch's TOH/POH Terminator devices such PHAST-3N PHAST-12E/POP-12 chip set. Timing adding tributaries derived from either Drop bus. EtherMap-3 provides following timing modes bus: Drop timing timing derived from Drop timing input signals Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs. C1J1, SPE, Optional clock optionally disabled. timing (two modes) timing derived from timing input signals Drop bus: C1J1, SPE, Optional Data, Clock, Parity signal leads inputs bus: C1J1, Clock, Optional signal leads inputs; Data, Parity Indication signal leads outputs timing derived from external reference clock Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs ALARM INDICATION PORT INTERFACE High Order Alarm Indication Port support ring applications Order Alarm Indication Port support ring applications
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EtherMap-3 TXC-04226B
PORT INTERFACE High Order Port access bytes Order Port access bytes MICROPROCESSOR INTERFACE 16-bit Address Data Motorola Intel style split supported Interrupt request lead Interrupt mask bits controlling generation hardware interrupt requests
JTAG INTERFACE IEEE 1149.1 compliant provided board level testing.
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BLOCK DIAGRAM
PARALLEL TELECOM INTERFACE
Telecom DROP Telecom
Telecom Perspective
High order port order port High order Alarm indication Port order Alarm indication Port
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High order port order port High order Alarm indication Port order Alarm indication Port
Mapper Block SONET/SDH (VT1.5/VC-12/ VC-3/VC-4)
Demapper Block SONET/SDH (VT1.5/VC-12/ VC-3/VC-4)
Transmit SONET/SDH Virtual Concatenation LCAS Processing Block
Transmit SONET/SDH Side LAPS, LAPF, Encapsulation Block
Receive SONET/SDH Virtual Concatenation LCAS Processing Block
Performance Statistics Counters Block
Alarm Processing Block
SDRAM Controller Block
SDRAM Interface Block
Transmit Ethernet Side LAPS, LAPF, Decapsulation Block
Clock Generator Block
10/100/1000 Mbit/s Ethernet Media Access Controllers (MACs); Half Full Duplex operation; RMON statistics counters; Ethernet Line Side loopbacks 10/100 Mbit/s Ethernet SMII i/fs; 1000 Mbit/s Ethernet GMII (shared)
JTAG Block
Ethernet Client Perspective ETHERNET PORTS
Figure Functional Block Diagram EtherMap-3
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Clocks
Address
MicroProcessor Interface
Data
Receive Ethernet Side Frame Format Block
Transmit Ethernet Side Frame Reinterleave Logic Block
Operation Control Block
External SDRAM Memory
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EtherMap-3 TXC-04226B
BLOCK DIAGRAM following sections describe functional block diagram EtherMap-3 shown Figure above: DATA PROCESSING/FLOW general, EtherMap-3 provides functionality mapping demapping Ethernet frames from SONET/SDH virtual concatenated tributary structures both LCAS/non-LCAS mode. figures below represent virtual tributary structures that supported EtherMap-3 device.
VT1.5-Xv payload capacity 500µs VT1.5 500µs VT1.5 VT1.5-Xv 500µs
Figure Order Virtual Concatenation Structure SONET
figure below shows STS-1-Xv structure. This structure provides contiguous payload area STS-1 with payload capacity X*48384 kbit/s shown. payload capacity (i.e., encapsulated Ethernet frames) mapped into individual STS-1 SPEs which form STS-1-Xv SPE. Each STS-1 POH. Just like VT1.5-SPE case above, STS-1-SPEs travel through SONET network independently reassembled their destination recover Ethernet data. While these cases only show SONET examples, same principle applies payloads concatenating VC-3s VC-12s.
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figure below shows VT1.5-Xv structure. VT1.5-Xv provides payload area VT1.5 payload capacity shown. Ethernet payload mapped into individual VT1.5 SPEs which form VT1.5-Xv SPE. Each VT1.5 sent throughout SONET network individually then reassembled destination.
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Xx84
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STS-1-Xv payload capacity
STS-1-Xv fixed stuff 125µs
125µs STS-1 125µs STS-1
Figure High Order Virtual Concatenation Structure SONET
SONET/SDH side, EtherMap-3 supports STM-1/STS-3/STS-3c like structure using single TranSwitch defined Telecom operating 19.44 MHz. Ethernet Line side, EtherMap-3 supports EIGHT 10/100 Mbit/s Ethernet ports 1000 Mbit/s (Gigabit) Ethernet port. eight 10/100 Mbit/s Ethernet ports each support industry standard SMII interface. single Gigabit Ethernet port supports industry standard GMII interface lead shared with SMII interfaces. transmit direction (Ethernet-to-SONET/SDH), EtherMap-3 terminates 10/100/1000 Mbit/s Ethernet traffic. Ethernet frames from configured port(s) extracted buffered external SDRAM memory. external SDRAM primarily used implementing flow control when Ethernet line side bandwidth greater than allocated bandwidth SONET/SDH side (i.e., over-subscription situation). Based system configuration, Ethernet frames from each Ethernet ports encapsulated using supported link layer protocols: GFP, LAPS, LAPF independently. encapsulated
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EtherMap-3 TXC-04226B
Ethernet frames then byte interleaved over preselected SONET/SDH containers transported using virtual concatenation. EtherMap-3 provides complete High order path overhead generation SONET/SDH containers. bandwidth SONET/SDH containers using virtual concatenation, allowed increase decrease hitless fashion through integrated link capacity adjustment scheme (LCAS). SONET/SDH containers carrying Ethernet frames then transmitted upstream SONET/SDH Overhead Terminator device such TranSwitch's PHAST-3N, using parallel telecom bus. receive direction (SONET/SDH-to-Ethernet), EtherMap-3 terminates parallel telecom with SONET/SDH containers carrying encapsulated (GFP LAPS, LAPF, PPP) Ethernet frames. EtherMap-3 provides complete High order path overhead processing SONET/SDH tributaries. SONET/SDH containers then extracted buffered using external SDRAM memory. This memory primarily used providing alignment differential delay compensation select SONET/SDH containers which form part virtual concatenation group. Once alignment delay compensation been achieved, Ethernet frames byte reinterleaved from SONET/SDH containers form their original frame structure port basis. Ethernet frames then extracted from encapsulations (GFP, LAPS, LAPF PPP) used transmit side passed onto Ethernet port transmission external client(s). 10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK interface 10/100 Mbit/s Ethernet ports 1000 Mbit/s Ethernet port supported integrated Ethernet block. This block supports eight 10/100 Mbit/s ports single 1000 Mbit/s port. 10/100/1000 Mbit/s Ethernet block IEEE 802.3, 802.3x, 802.3z 802.3ac compliant supports Full Duplex/Half Duplex 10/100 Mbit/s Ethernet only Full Duplex 1000 Mbit/s Ethernet (MAC implements IEEE 802.3 Control layer PAUSE operation flow control) mode operation. main features which supported this block follows: Connection external 10/100/1000 Mbit/s Ethernet PHYs 10/100/1000 Mbit/s Ethernet Switch devices either SMII interfaces single GMII interface Line side loopbacks diagnostic capability Verify frame integrity (FCS Length checks) Errored frames configured passed discarded Egress Ethernet frame encapsulation, such padding achieve minimum length generation Programmable IPG/IFG Minimum frame size bytes; Maximum frame size 1600 bytes Transparent IEEE 802.3-1998 VLAN (Virtual LAN) byte Supports IEEE 802.3 mandatory Control Management Registers Over Subscription support Device Configuration Flow Control Option support IEEE 802.3-1998 Flow Control each Ethernet port Programmable watermarks FIFO full conditions Full Duplex mode, automatic generation Pause frames based FIFO fill levels. Half Duplex mode, automatic back pressure flow control based FIFO fill levels. Control disable acting received PAUSE frames, that enables transparent transmission Ethernet PAUSE frame Reconciliation Frames. Control Statistics IEEE 802.3z-1998) that includes among others: Detection device, initialization, Device Standard Control Status Registers grouped function: Receive Transmit Control Registers, Receive Transmit Status Registers, RMON registers (for Network Management), Flow Control Registers, Management Registers, Ethernet Interface Control Status Registers PRODUCT PREVIEW TXC-04226B-MB, October 2003
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Performance counters ensure roll-over compliance with standards Provides statistic counters support RMON implementations (minimum support Ethernet Statistics Group, Ethernet History Group, Alarm Group, Event Group). MAPPER BLOCK This block provides mapping multiplexing order High order tributaries (carrying Ethernet framed data) into STS-3/STS-3c/STM-1 structures transmitted side telecom bus. range SONET/SDH rates format mappings supported indicated below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s order VC/VT tributaries formatted into STS-3 STM-1 structure. pointer value carried bytes transmitted with fixed value VT1.5 TU-12. microprocessor writes signal label, value message 16-byte message. device provides either single-bit extended using K4/Z7 bytes. Local alarms, microprocessor, generate remote payload, server, connectivity defect indications. Remote Error Indication (REI) inserted from BIP-2 errors detected receive side, BIP-2 parity generated byte. Control bits provided generating unequipped status, generating TU/VT AIS, inserting BIP-2 errors byte. Control bits also provided that enable microprocessor insert overhead byte test values, including byte. list VT/TU Overhead byte generation functions listed below: Byte Byte Microprocessor written message Forced ZERO option (Z7) Byte Signal label insertion Insertion (from receive side) Insertion Host Processor control BIP-2 calculation Insertion Insertion (from receive side) Enable bits alarms Host Processor control Single extended (bit byte bits K4/Z7 byte) Generate least superframes Mask Alarm Bits from sending Microprocessor control Control spare bits byte bits single Bits through (Z7) byte
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EtherMap-3 TXC-04226B
(Z6) Byte: Tandem connection support Unequipped Channel Generation Supervisory Equipped Generation TU/VT Generation order VT/TU Pointer generation Fixed TU-12 Asynchronous Format Fixed VT1.5 Asynchronous Format High order VC-3/STS-1 Overhead byte generation Insertion bytes into STS-1s VC-3s that being mapped with asynchronous line signals byte 16-byte message insertion ETSI Applications 64-byte message insertion ANSI Applications byte ability generate sequence lower order tributaries should provided when higher order virtual concatenation mode byte Signal Label Insertion byte BIP-8 Calculation Insertion Mask byte Single-bit (ETSI) extended generation (ANSI) (path FEBE) insertion insertion N1/Z5 byte: tandem connection support Transmit Path Generation STS-1/AU-3/TUG-3 Overrides Unequipped generation Transmit Unequipped Generation STS-1/AU-3/TUG-3 Supervisory Unequipped generation option High order TU-3 (VC-3)/STS-1 Pointer generation: Drop timing mode pointer bytes follow drop C1J1 pulses Timing Mode pointer bytes follow C1J1 pulses Timing Mode pointer bytes fixed High order VC-4/STS-3c Overhead byte generation generated PHAST-3N EtherMap-3 High order VC-4/STS-3 Pointer generation pointer generation handled external Overhead Terminator device such PHAST-3N POP-12
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DEMAPPER BLOCK Demapper Block provides demapping demultiplexing order High order tributaries from STS-3/STS-3c/STM-1 structures received Drop side telecom bus. range formats that supported Mapper Block also supported Demapper Block shown below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s
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EtherMap-3 device provides processing SONET/SDH overhead bytes follows: Microprocessor Access VT/TU overhead bytes, V1/V2 pointer bytes, byte each channel available microprocessor read cycle, well V5/K4 Bytes. Byte Multiframe Detectors pulse (C1J1V1) reference input Determines Location V1/V2 Pointer Bytes Pointer Tracking V1/V2 Pointer Bytes ETSI/ITU/ANSI State Machine Wrong Size Bits Detection Positive/Negative Justification 8-bit Counters order tributaries, this Demapper block performs pointer processing based location bytes. pointer bytes monitored loss pointer Alarm Indication Signal (AIS). pointer tracking process based ETSI/ITU-T standards, which also meets ANSI requirements. Pointer increments decrements also counted, size bits monitored correct value. This block also processes monitors various alarms found four overhead bytes. These operations including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection bit/block error counter, error counting, detector, single-bit extended Remote Defect Indications (RDI). Demapper performs 16-byte trail trace comparison channels selected. N2/Z6 byte processing supported. Below bullet list High order VC-3/STS-1 Overhead byte processing that performed Demapper block: received bytes applicable alarm indications made accessible micro-processor. byte trace mismatch detection 16-byte trail trace alignment (MFAS pattern) comparison ETSI Applications 64-byte message alignment (Multiframe Alignment MFAS pattern CR/LF alignment) byte ability detect generate pulse from byte sequence lower order tributaries supported. byte
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ETHERNET PORTS EtherMap-3 provides eight independent Full Duplex/Half Duplex Serial Media Independent Interfaces (SMII) support 10/100 Mbit/s Ethernet traffic single Full Duplex GMII port support 1000 Mbit/s Ethernet traffic. Please note, SMII interfaces signal-shared with GMII interface they cannot used together. power-up, GMII/SMII lead (see "Lead Descriptions" page selects between SMII GMII interfaces. SMII ports allow EtherMap-3 connected external 10/100 Mbit/s Ethernet client (PHY/Switch). configuration choice (PHY/Switch) made power-up/initialization through PHY/MAC signal lead (see "Lead Descriptions" page 31). SMII interface comprised signals port Data Data), global synchronization signal global reference clock. eight 10/100 Mbit/s Ethernet signals combination). Gigabit Media Independent Interface (GMII) used allow mapper connect external 1000 Mbit/s Ethernet client (PHY/Switch). EtherMap-3 device supports SINGLE GMII interface. Please note, GMII interface signal-shared with SMII interfaces configuration choice made powerup/initialization. GMII interface comprised independent 8-bit data paths, transmit enable signal, receive data valid signal. Status outputs report when coding violations detected. Network status inputs provided reporting errored frames frame received error. signals synchronous clock. single Ethernet Management interface provided EtherMap-3 connect external Ethernet order configure control operation. This interface used both eight 10/100 Mbit/s ports single 1000 Mbit/s port. comprised output Management Data clock signal bidirectional Management Data signal that allows serial data clocked external device. data transfers synchronous clock signal provides support PHYs. MICROPROCESSOR INTERFACE EtherMap-3's microprocessor interface provides support either standard Motorola, Intel split address/data interface which allows access EtherMap-3's memory register locations through 16-bit data bus. There 16-bit address bus. most significant location's address. device will correspond microprocessor address bus. mode operation configurable external package signal leads. interrupt request lead provided allow maskable interrupt bits generate interrupts external microprocessor, thus reducing required Host bandwidth. SDRAM MEMORY INTERFACE This interface used allow mapper connect external SDRAM memory device. external SDRAM memory device used buffering Ethernet traffic both directions provides "glueless" interface Mbits, Mbits Mbits external SDRAM memory devices. PRODUCT PREVIEW TXC-04226B-MB, October 2003
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Signal label mismatch Unequipped detection generation detection byte Single-bit (ETSI) extended detection (ANSI) (path FEBE) calculation with 16-bit Block error count access host processor access N1/Z5 byte: supported Demapper provides complete TU-3 pointer tracking state machines including applicable alarm indications. Other higher order processing done external device such PHAST-3N POP-12 device; high order pointer processing must done external device such PHAST-3N POP-12.
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Virtually concatenated realigned differential delay accommodated SDRAM during reconstruction process received frame. PARALLEL TELECOM INTERFACE Telecom interface enables EtherMap-3 connect upstream SONET/SDH Line Overhead Terminator such TranSwitch's PHAST-3N OC-3/STM-1 applications. OC-12/STM-4 applications, EtherMap-3 would connect TranSwitch's POP-12/PHAST-12E chip set. Telecom interface collectively comprised single Drop (RX) single (TX) bus.
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EtherMap-3 supports single telecom architecture which consists single Drop single bus. This same architecture supported other TranSwitch Mappers (e.g., TL3M) SONET/SDH Overhead Terminators (e.g., PHAST-3N, PHAST-12E, POP-12) products. Telecom operates 19.44 rate. telecom interface consists byte wide data, 19.44 (STM-1/STS-3) clock, indication, C1J1(V1) pulses, even parity indication, active indicator. EtherMap-3 supports either Drop timing modes. ABUST (see "Lead Descriptions" page lead used provide this selection. This approach prevents contention upon power device reset. Drop timing mode: this mode, timing derived from Drop timing input signals. When Drop timing mode selected, interface output leads byte-wide data, parity indicator, add-to-bus indicator. clock, C1J1V1 signals, which derived from Drop bus, output disabled. selection performed package lead. Note following restrictions apply when using Drop timing mode: SONET (STS-3 STS-1-SPEs) mode, high order virtual concatenation supported. SONET (STS-3 STS-1 SPEs VT1.5s) mode, selection order tributaries (VT1.5s) virtual concatenation group restricted same STS-1 SPE. Note that this means that virtual concatenation group this mode limited maximum VT1.5s. (STM-1 AU-3 VC-3 TUG-2s TU-12s VC-12s) mode, selection order tributaries (VC-12s) virtual concatenation group restricted same VC-3. Note that this means that virtual concatenation group this mode limited maximum VC-12s. timing mode(s): these modes, interface timing independent Drop interface timing above restrictions apply. Using control bit, interface timing signals configured follows: timing mode Byte Clock, 19.44 (input); indicator (input); C1J1V1 indicator (input); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, external timing source must ensure three pointers pulses) when operating STS-3/AU-3 mode, synchronized fixed relative each other (i.e., there must pointer movements relative each other). same principle applies when operating STM-1 STS-3c mode; pointer adjustments allowed Bus. TranSwitch PHAST-3N overhead terminator device provide external timing required this mode.
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timing mode interface signals follows: Byte Clock, 19.44 (output), derived from input clock lead; indicator (output); C1J1V1 indicator (output); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, EtherMap-3 sources timing signals.
Drop parity configured checked over data only over signals, check even parity. Drop clock monitored stuck high stuck conditions. parity generated even generated over data only over signals. indicator goes active indicate when VT/TU/VC/SPE data being added Telecom Bus. When data being added telecom bus, data parity Tristated. HIGH ORDER (PATH OVERHEAD BYTE) PORT INTERFACE byte interface provides alternative access SONET/SDH Order High Order tributary bytes external processing. There interfaces. interface VT1.5/VC-12 second interface STS-1/VC-3 STS-3c/VC-4 POH. Individual fields except TTI, Signal label BIP-2/BIP-8 fields inserted into from transmit byte interface. bytes provided their respective receive byte interface external processing. HIGH ORDER ALARM INDICATION PORT INTERFACE Alarm Indication Port provided transport remote information signal from mate monitor generator. remote information includes REI, various extended indications. There separate Alarm Indication Ports; VT1.5/VC-12 STS-1/VC-3 STS-3c/VC-4 ALARMS PERFORMANCE MONITORING BLOCKS This block maintains updates statistics/performance counters GFP, LAPS, LAPF, (for Ethernet ports) accessible host. following types statistics/performance counters provided this block: Flag error counters Payload size violation counters error counters Control Field mismatch counters Total number payload frames/octets transmitted counters Total number payload frames/octets received counters
Mapper/Demapper statistics/performance counters (for tributaries) grouped within part Mapper/Demapper block.
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JTAG INTERFACE This interface provides five signal Boundary Scan capability that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external Input/Output leads from board component test. addition lead provided place output buffers high impedance state systems that support IEEE 1149.1 standard.
POWER-UP SEQUENCING
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During power-up, Supply Voltage VDD33 (3.3V) must lead VDD18 (1.8V), VDDP18 (1.8V) VDDPA18 (1.8V) supplies. addition, Core Supply Voltage (VDD18) needs brought after Supply Voltage, brought together with VDDP18 VDDPA18 supplies. After power Supply Voltage must below Core Supply Voltage more than 0.5V time, including power down. maximum interval that VDD18, VDDP18 VDDPA18, must powered after VDD33 depends slew rate power ramp-up customer's application.
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APPLICATION EXAMPLE
EtherMap-3 used broad array telecommunications applications, such SONET/SDH add/drop terminal multiplexers Multi-service access platforms (MSAP) Compact Access platforms DSLAMS Wireless Backhaul Electronics (RNC/BSC)
Multi-service Ethernet Aggregation with OC-3/STM-1 Uplink
SDRAM Drop
10/100 Mbit/s SMII interfaces 10/100 Mbit/s SMII interfaces
OC-3/STM-1
PHAST-3N
EtherMap-3 TXC-04226B
Ethernet Switch Ports)
TEMx28
28xDS1 21xE1
EtherMap-3 TXC-04226B
1000 Mbit/s GMII interface
Gigabit Ethernet
1000 Mbit/s Line
SDRAM
Figure Typical Application using EtherMap-3 PHAST-3N Devices
Figure shows Multiservice STM-1/STS-3 application using EtherMap-3. TEMx28 device provides access 28xDS1 channels STS-3/STM-1 signal. EtherMap-3 devices used Gigabit Ethernet into STS-1-SPE/VC-3 container 10/100 Mbit/s Ethernet Traffic into VT1.5-SPE/VC-12. demonstrated this application, very small number TranSwitch components enables board developed which used simultaneously support mixture 10/100/1000 Mbit/s Ethernet Traffic T1/E1 Traffic. adding TranSwitch's TL3M device Telecom Bus, also supported.
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LEAD DIAGRAM
BOTTOM VIEW
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Notes: This bottom view. leads solder balls. Figure package information. This view rotated relative bottom view Figure Power supply leads shown solid black circles, ground leads cross-hatched circles.
Figure EtherMap-3 TXC-04226B Lead Diagram
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EtherMap-3 TXC-04226B
LEAD DESCRIPTIONS
POWER SUPPLY, GROUND, CONNECT LEADS Symbol VDD33 Lead E12, E14, G16, J16, M16, P16, T12, E10, E11, E13, E15, F16, H16, K16, L16, N16, R16, T10, T11, T13, A20, B19, C18, D17, E16, F10, F11, F12, F13, F14, F15, G10, G11, G12, G13, G14, G15, H10, H11, H12, H13, H14, H15, J10, J11, J12, J13, J14, J15, K10, K11, K12, K13, K14, K15, L10, L11, L12, L13, L14, L15, M10, M11, M12, M13, M14, M15, N10, N11, N12, N13, N14, N15, P10, P11, P12, P13, P14, P15, R10, R11, R12, R13, R14, R15, T16, U17, V18, W19, A10, A11, A19, B11, B15, B18, B20, C14, C17, C19, D13, D16, D18, U18, V17, V19, W10, W14, W18, W20, Y10, Y15, I/O/P* Name/Function VDD33: +3.3 volt power supply, (See "Power-Up Sequencing" page 28). VDD18: +1.8 volt power supply, (See "Power-Up Sequencing" page 28).
VDD18
Ground: (zero) Volts reference.
VDDP18 VDDPA18 VSSP18 VSSPA18
VDDP18: +1.8 volt digital power supply PLL, (See "Power-Up Sequencing" page 28). VDDPA18: +1.8 volt analog power supply PLL, (See "Power-Up Sequencing" page 28). VSSP18: digital ground PLL. VSSPA18: analog ground PLL. Connect: These leads connected, even another connect lead, must left floating. Connection lead impair performance cause damage device. leads that currently unused assigned functions future version device, affecting usability applications which have left them floating.
Note: Input; Output; OD=Open Drain Output; Power; Tristate:
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DROP SIDE ORDER TRIBUTARY TELECOM INTERFACE Symbol DD(7-0) Lead D10, C10, A12, I/O/P Type Name/Function
LVTTL-5 Drop Data Byte wide data corresponding STM-1/STS-3c/STS-3 signal from Drop bus. first received (dropped) corresponds LVTTL-5 Drop Clock: This clock operates 19.44 STM1/STS-3c/STS-3 operation used clock data other signals into EtherMap-3. Drop byte wide data, parity bit, indication, C1J1(V1) signals clocked into EtherMap-3 core negative transitions this clock. This clock also used timing used derive like named byte wide data, add, TU/VT indications, parity bits. Drop timing mode selected, this clock must already present during initial configuration device. LVTTL-5 Drop Indicator/Multiframe Pulse: active high timing signal that carries frame information. high during bytes STM1/STS-3c/STS-3 payload. Three pulses present STS-3 operation pulse present STM-1/STS-3c operation. pulse optional C1J1 signal. When pulse provided, EtherMap-3 core provides detectors determine location V1/V2 bytes place using pulse. When pulses provided, there will three pulses STS-3 operation pulse STM-1/STS-3c operation. DC1J1V1 signal works conjunction with DSPE signal. pulse identifies location byte STM-1/STS-c/STS-3 signals, when DSPE signal low. pulses identify starting location bytes STM-1/STS-3c/STS-3 signal when DSPE high. pulses occur every four frames (after frame where byte 00H) following pulse(s). LVTTL-5 Drop Indicator: signal that active high during each byte STM-1/STS-3c/STS-3 payload bytes, during Transport Overhead byte times. LVTTL-5 Drop Parity Bit: Parity input signal that represents parity calculation each data byte, SPE, C1J1V1 signal from bus. Even parity detected, option checking parity over DD(7-0) only over drop signals provided. parity error reported otherwise effect operation EtherMap-3 core.
DCLK
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DC1J1V1
DSPE
DPAR
SIDE ORDER TRIBUTARY TELECOM INTERFACE Symbol AD(7-0) Lead I/O/P O(T) Type Name/Function
LVCMOS Data Byte Byte wide data that corresponds selected TU/VT/VC.
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EtherMap-3 TXC-04226B
Symbol ACLK
Lead
I/O/P
Type
Name/Function
AC1J1V1
LVTTL-5/ Indicator/Multiframe Pulse: When LVCMOS timing selected cTBADD=0, this signal input must provided timing. When timing selected cTBADD=1, this signal output device timing. Composite active high input timing signal that carries STM-1, STS-3c, STS-3 starting frame byte location information. This timing signal functions conjunction with ASPE signal. (J0) pulse identifies location first (J0) byte SONET/SDH frame when ASPE low. pulse identifies starting location byte VC-4 signal STS-3c-SPE three pulses identify starting location three bytes STS-1-SPE signals when ASPE high. more pulses present asynchronous VT/TU mappings determine starting location byte. When drop timing selected, option (ABTE low) provided outputting this signal, otherwise this lead disabled. LVTTL-5/ Indicator: When timing selected LVCMOS cTBADD=0, this signal input must provided timing. When timing selected cTBADD=1, this signal output device timing. This signal active high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead times. When drop timing selected, option (ABTE low) provided outputting this signal, otherwise this lead disabled.
ASPE
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LVTTL-5/ Clock: This clock operates 19.44 MHz. When LVCMOS timing selected cTBADD=0, clock this input must provided timing. this case AC1J1V1 ASPE clocked negative transitions this clock while AD(7-0), APAR, clocked positive transitions this clock. This above case default value cTBADD. When timing selected cTBADD=1, clock output this lead. AC1J1V1, ASPE, AD(7-0), APAR, clocked positive transitions this clock. that case, RTCLK DCLK clock inputs must active. When drop timing selected, option (ABTE low) provided outputting this clock along with other signals, which derived from DCLK, otherwise this lead disabled. slave timing mode selected, this input clock must already present during initial configuration device. master timing mode selected, this output clock must pulled high with weak pull-up (like ohm). After hard reset, first microprocessor access must cTBADD register this moment, EtherMap-3 will able drive clock.
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DATA SHEET
Symbol APAR
Lead
I/O/P O(T)
Type
Name/Function
LVCMOS Parity Bit: even parity output signal which calculated over byte wide data. This 3-state lead only active when there data being added bus. control provided that allows even parity calculated. LVCMOS Data Present Indicator: This active signal present when output data valid. identifies location TU/VT/VC time slots being added bus. When VC-4/STS-3c mode, when HighZ_AU3 bits timeslots, entire VC-4/STS-3c will indicated active. Additionally master mode, pointer bytes that output will indicated active.
PRODUCT PREVIEW
ETHERNET GMII/ 8xSMII INTERFACES control lead GMII/SMII selects when low, group eight SMII Ethernet interfaces, when high, selects single GMII interface. GMII interface described section below, also leads shared with SMII interface leads. Each SMII interface comprised Serial Data Transmit Output (SMII_DOn) Serial Data Receive Input (SMII_DIn); where 1-8. SMII data interface serial streaming standard Mbit/s (Fast Ethernet) interface (Media Independent Interface). Symbol GTX_CLK Lead I/O/P Type Name/Function
LVCMOS Gigabit Ethernet Transmit Clock Output: GTX_CLK used drive TXD(7-0), TX_EN, TX_ER signals; runs MHz. LVTTL-5 Transmit Clock: This input clock, required only GMII mode, only these cases: When control lead PHY/MAC low. When Loopback (see page 189) selected. LVTTL-5/ GMII Transmit Enable/Global SMII SYNC: When LVCMOS GMII/SMII control lead high, this lead used output control signal indicate valid data being presented GMII TXD(7-0) leads. When GMII/SMII control lead SYNC_DIR control lead high, this lead used output global SYNC signal (i.e., common eight SMII interfaces). When GMII/SMII control lead SYNC_DIR control lead low, this lead used input global SYNC signal (i.e., common eight SMII interfaces).
TX_CLK
TX_EN /(SMII_ GSYNC)
TX_ER
LVCMOS Transmit Error: This output signal asserted indicate that coding violation received input data stream.
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DATA SHEET
EtherMap-3 TXC-04226B
Symbol
Lead
I/O/P
Type
Name/Function
TXD(7-0) U12, Y14, V13, /(SMII_ U13, W15, Y16, DO(8-1) V14,
LVCMOS Transmit Data Out: Data output transmitted group eight data signals, PHY. When GMII/SMII control lead low, these leads operate eight SMII interface Data signals SMII_DOn correspond (i.e., TXD7 corresponds SMIIDO8). LVTTL-5 Receive Data Data received passed group eight data signals DTE. When GMII/SMII control lead low, these leads operate eight SMII interface Data signals SMII_DIn correspond (i.e., RXD7 corresponds SMIIDI8). LVTTL-5 Receive Data Valid: This signal asserted indicate that valid data (octets) being presented RXD(7-0) inputs. LVTTL-5 Receive Data Error: This signal asserted indicate frame received error. LVTTL Receive Clock: clock recovered from incoming data stream, passed onto DTE. RX_CLK runs either Mbit/s Ethernet Mbit/s operation. When GMII/SMII control lead low, operates SMII_GCLK. Note: duty cycle should 60%.
RX_DV
RX_ER RX_CLK /(SMII_ GCLK)
MDIO
LVTTL-5/ Management Data I/O: Data input/output IEEE LVCMOS 802.3u compliant Management Status interface. LVCMOS Management Data Interface Clock: management data (MDIO) clocked into EtherMap-3 rising edge this clock. frequency this clock derived from microprocessor clock input (MICCLK) divided factor (Max 12.5 MHz, Mgmt Clock Select Table page 212).
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RXD(7-0) /(SMII_ DI(8-1)
Y11, U10, V10,
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DATA SHEET
SDRAM INTERFACE following table shows standard wide Data, SDRAM interface. There thirteen address bits, that include bank Selection needed; input mask bits (byte-wise); write enable, RAS/CAS, clock clock enable. Symbol DATA(31-0) Lead N18, R20, P18, T20, R18, U20, T18, V20, T17, U19, R17, T19, P17, R19, N17, P19, E17, D19, F17, E19, G17, F19, H17, G19, H18, F20, G18, E20, F18, D20, E18, K18, K19, N20, J20, K20, L19, L18, L17, M18, M17, P20, N19, M20, I/O/P I/O(T) Type Name/Function
LVTTL/ SDRAM Controller External Data I/O: bits wide data LV3CMOS bus; byte wise tristateable. least significant bit.
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ADDR(12-0)
LV3CMOS Address Bus: bits wide. least significant bit.
BA(1-0)
LV3CMOS Bank Select: These signals used select Banks standard SDRAM.
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EtherMap-3 TXC-04226B
Symbol
Lead
I/O/P
Type
Name/Function
LV3CMOS Address Strobe: control external SDRAM. This signal along with define command being given external SDRAM. Function
NOP: operation
READ: Used initialize SDRAM burst read. WRITE: Used initialize SDRAM burst write. PRECHARGE: Deactivate open bank banks. AUTO REFRESH: This command performed every 2480 SYSCLK period, ensure that SDRAM rows refreshed. This default setting changed SDRARP register address 0x1d604. LOAD MODE REGISTER: This command issued configuration step, configure internal mode register SDRAM. last command before SDRAM ready read/write accesses.
LV3CMOS Column Address Strobe: control external SDRAM. signal along with define command being given external SDRAM. Refer table lead description. LV3CMOS Write Enable: control external SDRAM. This signal along with define command being given external SDRAM. Refer table lead description. LV3CMOS Chip Select: control external SDRAM. Used select deselect external SDRAM. LV3CMOS Mask Bits: This control output used mask standard wide SDRAM memory interface. used tristate SDRAM data during READ cycle mask SDRAM data during WRITE cycle.
MASK
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ACTIVE: Used activate particular bank. BA(1-0) selects bank, ADDR(12-0) selects row.
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DATA SHEET
Symbol
Lead
I/O/P
Type
Name/Function
LV3CMOS Interface Clock: control external SDRAM. SDRAM interface signals sampled/output rising edge this clock, which runs MHz. LV3CMOS Interface Clock Enable: control external SDRAM. High intended activate clock, intended deactivate clock.
CLKE
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RECEIVE VC-3 PATH OVERHEAD (VC-3POH) BYTE INTERFACE Symbol RPCLK Lead I/O/P Type Name/Function
LVCMOS Receive VC-3POH Interface Clock: receive VC-3POH address (RPADD), address latch enable (RPALE), data (RPDAT), data latch enable (RPDLE) signals clocked falling edges this clock (2.43 MHz). LVCMOS Receive VC-3POH Interface Address Latch Enable: positive (RPCLK) clock cycle-wide pulse that indicates valid address (eight consecutive bits) present RPADD. LVCMOS Receive VC-3POH Interface Address: states present this lead during address latch enable time indicate output VC-3POH byte SDH/SONET format. Eight consecutive bits make valid address. LVCMOS Receive VC-3POH Interface Data Latch Enable: positive (RPCLK) clock cycle-wide pulse that indicates valid data present RPDAT. LVCMOS Receive VC-3POH Interface Data: states present this lead over eight consecutive bits, during data latch enable time constitute output byte data selected address.
RPALE
RPADD
RPDLE
RPDAT
TRANSMIT VC-3 PATH OVERHEAD (VC-3POH) BYTE INTERFACE Symbol TPCLK Lead I/O/P Type Name/Function
LVCMOS Transmit VC-3POH Interface Clock: transmit address (TPADD), address latch enable (TPALE), data latch enable (RPDLE) signals clocked falling edge TPCLK (2.43 MHz). Data (TPDAT), clocked rising edge this clock. LVCMOS Transmit VC-3POH Interface Address Latch Enable: positive (TPCLK) clock cycle-wide pulse that indicates valid address (eight consecutive bits) present TPADD. LVCMOS Transmit VC-3POH Interface Address: states present this lead during address latch enable time indicate output byte SDH/SONET format. Eight consecutive bits make valid address.
TPALE
TPADD
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EtherMap-3 TXC-04226B
Symbol TPDLE
Lead
I/O/P
Type
Name/Function
LVCMOS Transmit VC-3POH Interface Data Latch Enable: positive (TPCLK) clock cycle-wide pulse that indicates valid data present TPDAT. LVTTL-5 Transmit VC-3POH Interface Data: states present this lead over eight consecutive bits, during data latch enable time, constitute input byte data selected address.
TPDAT
Symbol RPCLK1
Lead
I/O/P
Type
Name/Function
LVCMOS Receive LOPOH Interface Clock: receive LOPOH address (RPADD1), address latch enable (RPALE1), data (RPDAT1), data latch enable (RPDLE1) signals clocked falling edges this clock (19.44 MHz). LVCMOS Receive LOPOH Interface Address Latch Enable: positive (RPCLK1) clock cycle-wide pulse that indicates valid address (twelve consecutive bits) present RPADD1. LVCMOS Receive LOPOH Interface Address: states present this lead during address latch enable time indicate output LOPOH byte SDH/SONET format. Twelve consecutive bits make valid address. LVCMOS Receive LOPOH Interface Data Latch Enable: positive (RPCLK1) clock cycle-wide pulse that indicates valid data present RPDAT1. LVCMOS Receive LOPOH Interface Data: states present this lead over eight consecutive bits, during data latch enable time constitute output byte data selected address.
RPALE1
RPADD1
RPDLE1
RPDAT1
TRANSMIT LOWER ORDER PATH OVERHEAD (LOPOH) BYTE INTERFACE Symbol TPCLK1 Lead I/O/P Type Name/Function
LVCMOS Transmit LOPOH Interface Clock: transmit LOPOH address (TPADD1), address latch enable (TPALE1), data latch enable (RPDLE1) signals clocked falling edge TPCLK1 (19.44 MHz). Data (TPDAT1), clocked rising edge this clock. LVCMOS Transmit LOPOH Interface Address Latch Enable: positive (TPCLK1) clock cycle-wide pulse that indicates valid address (twelve consecutive bits) present TPADD1. LVCMOS Transmit LOPOH Interface Address: states present this lead during address latch enable time indicate output LOPOH byte SDH/SONET format. Twelve consecutive bits make valid address. LVCMOS Transmit LOPOH Interface Data Latch Enable: positive (TPCLK1) clock cycle-wide pulse that indicates valid data present TPDAT1.
PRODUCT PREVIEW TXC-04226B-MB, October 2003
TPALE1
TPADD1
TPDLE1
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RECEIVE LOWER ORDER PATH OVERHEAD (LOPOH) BYTE INTERFACE
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DATA SHEET
Symbol TPDAT1
Lead
I/O/P
Type LVTTL-5
Name/Function Transmit LOPOH Interface Data: states present this lead over eight consecutive bits, during data latch enable time, constitute input byte data selected address.
RECEIVE (VC-3) HIGH ORDER ALARM INDICATION PORT Symbol Lead I/O/P Type Name/Function
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RAIPF
LVCMOS Receive Alarm Indication Port Frame Pulse: active high (RAIPC) clock cycle-wide frame pulse that identifies data stream. LVCMOS Receive Alarm Indication Port Clock: 19.44 output clock used clocking frame pulse (RAIPF) serial data (RAIPD) into mate device. LVCMOS Receive Alarm Indication Port Data: serial frame that contains count alarm states high order SPE/VCs.
RAIPC
RAIPD
TRANSMIT (VC-3) High Order ALARM INDICATION PORT Symbol TAIPF Lead I/O/P Type Name/Function
LVTTL-5 Transmit Alarm Indication Port Frame Pulse: active high (TAIPC) clock cycle-wide frame pulse that identifies data stream. Connected RAIPF mate device. LVTTL-5 Transmit Alarm Indication Port Clock: 19.44 output clock used clocking frame pulse (TAIPF1) serial data (TAIPD1). Connected RAIPC mate device. LVTTL-5 Transmit Alarm Indication Port Data: serial frame that contains count, alarm states, Tandem Connection monitoring alarm states individual TU-3 VC-3 Paths. Connected RAIPD mate device.
TAIPC
TAIPD
RECEIVE ORDER ALARM INDICATION PORT Symbol RAIPF1 Lead I/O/P Type Name/Function
LVCMOS Receive Alarm Indication Port Frame Pulse: active high (RAIPC) clock cycle-wide frame pulse that identifies data stream. LVCMOS Receive Alarm Indication Port Clock: 19.44 output clock used clocking frame pulse (RAIPF1) serial data (RAIPD1) into mate device. LVCMOS Receive Alarm Indication Port Data: serial frame that contains count alarm states VT/TUs.
RAIPC1
RAIPD1
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EtherMap-3 TXC-04226B
TRANSMIT ORDER ALARM INDICATION PORT Symbol TAIPF1 Lead I/O/P Type LVTTL-5 Name/Function Transmit Alarm Indication Port Frame Pulse: active high (TAIPC) clock cycle-wide frame pulse that identifies data stream. Connected RAIPF1 mate device. Transmit Alarm Indication Port Clock: 19.44 output clock used clocking frame pulse (TAIPF1) serial data (TAIPD1). Connected RAIPC1 mate device.
TAIPC1
LVTTL-5
CONTROLS Symbol GMII/SMII Lead I/O/P Type Name/Function
LVTTL-5p GMII/SMII Interface Select: selects SMII Ethernet interfaces place single GMII. This lead internal pull-up resistor. LVTTL-5p High Impedance Select: forces output leads, except boundary scan data output TDO, high impedance state testing purposes. This lead internal pull-up resistor. LVTTL-5p Reset: active signal used resetting internal cores performance counters within EtherMap-3 preset values. reset must applied only after power applied stable, clocks also stable. reset must present minimum This lead internal pull-up resistor. After de-assertion this lead, microsecond wait period must observed, where microprocessor access made. LVTTL-5p Timing Signals Enabled: active signal enables ACLK, ASPE, AC1J1V1 outputs when drop timing selected. This lead internal pull resistor. high this lead causes those signals tristated. LVTTL-5p Timing Selection: selects timing mode. When timing selected, ACLK, ASPE, AC1J1V1, programmed inputs used source AD(7-0), APAR, signal, they generated internally provided output signals. high selects drop timing. signals direction derived from drop bus. This lead internal pull resistor.
HIGHZ
RESET
ABTE
ABUST
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TAIPD1
LVTTL-5 Transmit Alarm Indication Port Data: serial frame that contains count, alarm states, Tandem Connection monitoring alarm states individual VT/TU Paths. Connected RAIPD1 mate device.
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DATA SHEET
Symbol PHY/MAC
Lead
I/O/P
Type
Name/Function
PRODUCT PREVIEW
LVTTL-5p PHY/MAC Interface Select: SMII mode, selects MAC-to-MAC interconnection type Ethernet side, while high selects MAC-to-PHY interconnection. GMII mode, high, selects RX_CLK source GTX_CLK low, selects TX_CLK source GTX_CLK. Note: GMII mode, loopback enabled, TX_CLK always required source GTX_CLK, independent PHY/MAC state. This lead internal pull-up resistor. SMII mode, whatever value this input, RX_CLK used reference clock. LVTTL-5p Global SYNC Direction Select: SMII mode when low, SMII_GSYNC signal input. SMII mode when high, SMII_GSYNC signal output. GMII mode, this lead must kept high. This lead internal pull-up resistor.
SYNC_DIR
CLOCK INTERFACES Symbol RTCLK Lead I/O/P Type Name/Function
LVTTL-5d Reference Mapper/Demapper clock: This clock 19.44 clock, (40% max. duty cycle) used Mapper/Demapper blocks. When Master Mode (cTBADD lead ABUST low) this input should maximum, since that mode this clock source ACLK. This clock required operating modes. This clock does have have relationship ACLK. LVTTL-5 System Reference Clock: input clock, with max. duty cycle minimum accuracy ppm. This clock internally doubled used system clock other functions except Mapper/Demapper block. LVTTL-5d Second Performance Measurement Clock: This clock input used second shadow counters, PM/FM alarm registers. This input either below: (+/- ppm) clock, pulse, with minimum 51.44 high time.
SYSCLK
ONESEC
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EtherMap-3 TXC-04226B
HOST PROCESSOR INTERFACE Symbol MICCLK Lead I/O/P Type Name/Function
LVTTL-5 Microprocessor Clock: This clock should come from microprocessor being interfaced this device. Intel Motorola 68360 modes, recommended that this lead connected microprocessor clock. Motorola MPC860 mode, this clock must synchronous microprocessor clock.
D(15-0)
I/O(T)
LVTTL-5/ Data Bus: Bidirectional data lines used transferring data LVCMOS between EtherMap-3 host processor. most significant bit.
LVTTL-5p Select: enables data transfers between host processor EtherMap-3 read/write cycle. This lead internal pull-up resistor. LVTTL-5 Write Enable (Intel Mode)/Data Strobe (Motorola Mode)/Transfer Start (Motorola Mode): active signal. Intel Mode: Asserted initiate write cycle. Motorola 68360 Mode: This data strobe signal which indicates that host processor ready accept data during read cycle valid data during write cycle. Motorola MPC860 Mode: Indicates start cycle when becomes asserted. LVTTL-5 Read (Intel Mode) Read/Write (Both Motorola Modes): active signal that asserted initiate Read cycle Intel Mode. either Motorola Modes, high this lead initiates Read, initiates Write.
DS/TS
(RD/WR)
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A(15-0)
LVTTL-5 Address Bus: These leads active high address line inputs that used host processor accessing EtherMap-3 read/write cycle. most significant location's address. device will correspond microprocessor address bus.
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DATA SHEET
Symbol READY/ DTACK/TA
Lead
I/O/P
Type
Name/Function
PRODUCT PREVIEW
LVCMOS Ready (Intel Mode)/Data Transfer Acknowledge (Motorola Mode)/Transfer Acknowledge (Motorola Mode): Intel Mode: high indicates that transfer to/from memory accomplished. high (active) state kept MICCLK cycles. Motorola 68360 Mode: This lead active low, indicates either that data valid during Read operation, indicates data acceptance during Write operation. (active) state kept MICCLK cycles. Motorola MPC860 Mode: This lead active low, indicates either that data valid during Read operation, indicates data acceptance during Write operation. (active) state synchronous MICCLK MICCLK cycle wide. Note: This output open-drain buffer which requires external pull-up resistor. LVCMOS Interrupt: Intel Mode: high this output lead signals interrupt request host processor. Both Motorola Modes: this output lead signals interrupt request host processor. LVTTL-5 Intel/Motorola: Selector lead selecting Intel/Motorola interface:
INT/IRQ
MOTO(1-0)
MOTO1
MOTO0 Interface
Intel Processor Interface. Motorola 68360 Processor Interface. Motorola MPC860 Processor Interface. use.
BOUNDARY SCAN (IEEE STANDARD 1149.1) Symbol Lead I/O/P Type Name/Function
LVTTL-5 Test Boundary Scan Clock: This signal used shift data into rising edge falling edge. maximum clock frequency MHz. LVTTL-5p Test Boundary Scan Data Input: Serial test instructions data clocked into this lead rising edge TCK. This lead internal pull-up resistor. LVCMOS Test Boundary Scan Data Output: Serial data test instructions data clocked this lead falling edge TCK. When inactive, this lead goes high impedance state.
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DATA SHEET
EtherMap-3 TXC-04226B
Symbol
Lead
I/O/P
Type
Name/Function
LVTTL-5p Test Boundary Scan Mode Select: This input lead sampled rising edge TCK. used place Test Access Port controller into various states, defined IEEE 1149.1. internal pull-up holds this lead high during normal operation. This lead internal pull-up resistor. LVTTL-5p Test Boundary Scan Reset: active signal that asynchronously resets Test Access Port controller. reset must present minimum Specific control this lead required order ensure normal operation device. This lead should held whenever boundary scan operations being performed. This lead internal pull-up resistor.
TEST Symbol SCAN_EN Lead I/O/P Type Name/Function
LVTTL-5d Scan Enable: This lead used TranSwitch Testing purposes only. This lead internal pull-down should held low. LVTTL-5d Memory Bist: This lead used TranSwitch Testing purposes only. This lead internal pull-down should held low. LVTTL-5d Bypass: This lead used TranSwitch Testing purposes only. This lead internal pull-down should held low. LVCMOS Output: This lead used TranSwitch Testing purposes only. This lead should left open (floating). LVTTL-5d Scan Mode: This lead used TranSwitch Testing purposes only. This lead internal pull-down should held low.
MBIST_MODE
PLL_BYPASS
PLLOUT SCAN_MODE
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DATA SHEET
ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS (REFERENCED VSS)
Parameter Supply voltage (3.3V) Core Supply voltage (1.8V) input voltage LVTTL input voltage LVTTL-5 input voltage Symbol VDD33 VDD18 -0.5 +150
-0.3 -0.3
Unit
Conditions Note Note Note
PRODUCT PREVIEW
Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification
Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note
Level
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883E, Method 3015.7. Device core only. input signals leads accept signals except SMII/GMII SDRAM memory interface signals which accept only 3.3V signals.
THERMAL CHARACTERISTICS Parameter Thermal resistance: junction ambient 14.7 Unit
oC/W
Test Conditions Test performed with package assembled JEDEC standard Multilayer test board with ft/min linear airflow.
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DATA SHEET
EtherMap-3 TXC-04226B
POWER REQUIREMENTS
GMII MODE (traffic running single port) Parameter VDD33 IDD33 VDD18 IDD18 Power Dissipation, PDDTOTAL Power Dissipation, PDDTOTAL5 3.15 84.5 1.71 1660 1743 3.30 89.6 1.80 1880 1974 3.45 97.5 1.89 2103 2208 Unit Note Note Note Note Test Conditions
SMII MODE (traffic running single port) Parameter VDD33 IDD33 VDD18 IDD18 Power Dissipation, PDDTOTAL Power Dissipation, PDDTOTAL5 3.15 60.0 1.71 1379 1448 3.30 63.5 1.80 1547 1619 3.45 70.7 1.89 1764 1852 Unit Note Note Note Note Test Conditions
SMII MODE (traffic running eight ports) Parameter VDD33 IDD33 VDD18 IDD18 Power Dissipation, PDDTOTAL Power Dissipation, PDDTOTAL5 3.15 84.0 1.71 1416 1487 3.30 90.6 1.80 1649 1732 3.45 97.0 1.89 1852 1944 Unit Note Note Note Note Test Conditions
Notes: IDD33 IDD18, figure reported represents absolute minimum maximum across following variations: VDD18 3.15 VDD33 3.45 (temperature) total power, maximum consumption occurs when both VDD33 VDD18 their maximum test value. minimum consumption occurs when both VDD33 VDD18 their minimum test value. Very small effect temperature power consumption been observed. figure Typical power measured VDD33 VDD18 values power have been rounded nearest higher 0.01 PDDTOTAL5 represent PDDTOTAL value reported above, line plus cover process temperature variations that exist. Measurement taken with traffic injected Gbps, with flow control enabled. Packet size bytes. Measurement taken with traffic injected Mbps, with flow control enabled. Packet size 1514 bytes.
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DATA SHEET
INPUT, OUTPUT INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS LVTTL-5 VOLT TOLERANT) Parameter Input leakage current Unit Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 VDD33 3.45,
PRODUCT PREVIEW
Input capacitance
INPUT PARAMETERS LVTTL-5p VOLT TOLERANT, with PULL-UP RESISTOR) Parameter Input leakage current Input capacitance Unit Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 VDD33 =3.45; Input volts
INPUT PARAMETERS LVTTL-5d VOLT TOLERANT, with PULL-DOWN RESISTOR) Parameter Input leakage current Input capacitance Unit Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 VDD33 3.45; Input 3.45 volts
INPUT PARAMETERS LVTTL (3.3 VOLT TOLERANT) Parameter Input leakage current Input capacitance Unit Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 VDD33 3.45,
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EtherMap-3 TXC-04226B
OUTPUT PARAMETERS LVCMOS 24mA (Open Drain) Parameter Output capacitance tRISE tFALL Leakage tristate 1.17 0.87 2.25 1.77 Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
Note: Open Drain requires external pull-up resistor VDD33.
OUTPUT PARAMETERS LVCMOS 12mA Parameter Output capacitance tRISE tFALL Leakage tristate 1.43 1.22 2.71 2.45 Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
OUTPUT PARAMETERS LVCMOS Parameter Output capacitance tRISE tFALL Leakage tristate 1.78 1.65 3.38 3.22 Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
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OUTPUT PARAMETERS LVCMOS Parameter Output capacitance 2.97 2.95 5.54 5.66 tRISE tFALL Leakage tristate Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
PRODUCT PREVIEW
OUTPUT PARAMETERS LV3CMOS 16mA pull-ups more than 3.3V with these outputs) Parameter Output capacitance tRISE tFALL Leakage tristate 1.28 1.04 2.87 2.65 Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
OUTPUT PARAMETERS LV3CMOS pull-ups more than 3.3V with these outputs) Parameter Output capacitance tRISE tFALL Leakage tristate 1.78 1.65 3.41 3.38 Unit CLOAD CLOAD input VDD33 3.15; VDD33 3.15; Test Conditions
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DATA SHEET
EtherMap-3 TXC-04226B
INPUT/OUTPUT PARAMETERS LVTTL-5 INPUT LVCMOS OUTPUT 12mA VOLT TOLERANT Input) Parameter Input leakage current Input capacitance tRISE tFALL 1.44 1.23 2.72 2.45 Unit CLOAD CLOAD VDD33 3.15; Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 input VDD33 3.15;
INPUT/OUTPUT PARAMETERS LVTTL-5 INPUT LVCMOS OUTPUT VOLT TOLERANT Input) Parameter Input leakage current Input capacitance tRISE tFALL 1.79 1.67 3.40 3.24 Unit CLOAD CLOAD VDD33 3.15; VDD33 3.15; Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 input
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INPUT/OUTPUT PARAMETERS LVTTL INPUT LV3CMOS OUTPUT 16mA (3.3V VOLT TOLERANT Input) Parameter Input leakage current Input capacitance 1.76 1.60 2.85 2.64 tRISE tFALL Unit CLOAD CLOAD VDD33 3.15; VDD33 3.15; Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 input
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INPUT/OUTPUT PARAMETERS LVTTL INPUT LV3CMOS OUTPUT (3.3V VOLT TOLERANT Input) Parameter Input leakage current Input capacitance tRISE tFALL 1.80 1.78 3.39 3.36 Unit CLOAD CLOAD VDD33 3.15; VDD33 3.15; Test Conditions 3.15 VDD33 3.45 3.15 VDD33 3.45 input
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EtherMap-3 TXC-04226B
TIMING CHARACTERISTICS
This section presents detailed timing characteristics EtherMap-3 Figures through with values timing parameters tabulated below each waveform diagram. outputs measured with maximum load capacitance unless otherwise stated. Timing parameters measured voltage levels (VOH +VOL)/2 output signals (VIH VIL)/2 input signals.
Figure Drop Timing (Only APAR, Output)
DCLK (Input)
tSU(1)
DD(7-0) DPAR (Inputs) DSPE (Input)
DATA
DATA
DATA
FIXED STUFF
FIXED STUFF
H1(1) TUG-3
H1(2) TUG-3
tSU(2)
tH(1)
tH(2) tSU(3) tD(1) tH(3)
DATA
DC1J1V1 (Input) AD(7-0)/ APAR (Outputs) (Output)
tD(3)
FIXED STUFF
tD(2)
tD(4)
tD(5)
Load Notes: STM-1 mode with TUG-3 mapping shown. STS-3 mode used there would three pulses that would asynchronous with respect each other. However timing (i.e., setup hold, propagation delays) change.
parameter table next page.
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tCYC
tPWH
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Parameter DCLK clock period DCLK duty cycle tPWH/tCYC DD(7-0)/DPAR setup time DCLK DD(7-0)/DPAR hold time after DCLK DSPE setup time DCLK DSPE hold time after DCLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(3) tD(4) tD(5)
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DC1J1V1 setup time DCLK DC1J1V1 hold time after DCLK AD(7-0)/APAR stable from DCLK AD(7-0)/APAR tristated from DCLK AD(7-0)/APAR turn from DCLK AD(7-0)/APAR valid from DCLK delay after DCLK
Note:
inputs DD(7-0)/DPAR, DC1J1V1 DSPE sampled falling edge DCLK according setting configuration Active Edge (see Table 279, page 339).
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EtherMap-3 TXC-04226B
Figure Drop Timing (Only APAR, Output)
tCYC tPWH
DCLK (Input)
tSU(1)
DD(7-0) DPAR (Inputs) DSPE (Input)
DATA
DATA
DATA
FIXED STUFF
FIXED STUFF
H1(1) TUG-3
H1(2) TUG-3
tSU(2)
tH(1)
tH(2) tSU(3) tD(1) tH(3)
DATA
DC1J1V1 (Input) AD(7-0)/ APAR (Outputs) (Output)
tD(3)
FIXED STUFF
tD(2)
tD(4)
tD(5)
Load Notes: STM-1 mode with TUG-3 mapping shown. STS-3 mode used there would three pulses that would asynchronous with respect each other. However timing (i.e., setup hold, propagation delays) change.
parameter table next page.
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Parameter DCLK clock period DCLK duty cycle tPWH/tCYC DD(7-0)/DPAR setup time DCLK DD(7-0)/DPAR hold time after DCLK DSPE setup time DCLK DSPE hold time after DCLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(3) tD(4) tD(5)
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DC1J1V1 setup time DCLK DC1J1V1 hold time after DCLK AD(7-0)/APAR stable from DCLK AD(7-0)/APAR tristated from DCLK AD(7-0)/APAR turn from DCLK AD(7-0)/APAR valid from DCLK delay after DCLK
Note:
inputs DD(7-0)/DPAR, DC1J1V1 DSPE sampled rising edge DCLK according setting configuration Active Edge (see Table 279, page 339).
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EtherMap-3 TXC-04226B
Figure Drop Timing (all Signals Outputs)
tCYC DCLK (Input) DD(7-0) DPAR (Input) DSPE (Input) DC1J1V1 (Input) ACLK (Output) tD(2) AC1J1V1 (Output) ASPE (Output) AD(7-0) APAR (Output) (Output)
C1(1) STS-1 STS-1 STS-1
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(2)
tH(2)
Occurs every four frames when provided place byte STS-1 STS-1 STS-1 STS-1
tSU(3)
C1(1)
tH(3)
tD(1)
tD(3) tD(4) tD(6)
Selected
tD(5)
Load
Notes: single shown illustration purposes. STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e., setup hold, propagation delays) change.
Parameter DCLK clock period DCLK duty cycle tPWH/tCYC DD(7-0)/DPAR setup time before DCLK DD(7-0)/DPAR hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK ACLK delay from DCLK AC1J1V1 delay from ACLK ASPE delay from ACLK AD(7-0)/APAR turn from ACLK delay from ACLK AD(7-0)/APAR valid delay from ACLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(3) tD(4) tD(5) tD(6)
Note: inputs DD(7-0)/DPAR, DC1J1V1 DSPE sampled falling edge DCLK according setting configuration Active Edge (see Table 279, page 339).
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Figure Drop Timing (all Signals Outputs)
tCYC DCLK (Input) DD(7-0) DPAR (Input) DSPE (Input)
tSU(3)
C1(1)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(2)
tH(2)
Occurs every four frames when provided place byte STS-1 STS-1 STS-1 STS-1
tH(3)
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DC1J1V1 (Input) ACLK (Output)
tD(1)
tD(2) AC1J1V1 (Output) ASPE (Output) AD(7-0) APAR (Output) (Output)
C1(1) STS-1 STS-1 STS-1
tD(3) tD(4) tD(6)
Selected
tD(5)
Load
Notes: single shown illustration purposes. STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e., setup hold, propagation delays) change.
Parameter DCLK clock period DCLK duty cycle tPWH/tCYC DD(7-0)/DPAR setup time before DCLK DD(7-0)/DPAR hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK ACLK delay from DCLK AC1J1V1 delay from ACLK ASPE delay from ACLK AD(7-0)/APAR turn from ACLK delay from ACLK AD(7-0)/APAR valid delay from ACLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(3) tD(4) tD(5) tD(6)
Note: inputs DD(7-0)/DPAR, DC1J1V1 DSPE sampled rising edge DCLK according setting configuration Active Edge (see Table 279, page 339).
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EtherMap-3 TXC-04226B
Figure Timing (Timing Signals Inputs)
tCYC ACLK (Input) ASPE (Input)
tSU(1) tH(1)
C1(1) STS-1 STS-1 STS-1
tPWH tSU(2)
tH(2)
Occurs every four frames
tD(2) AD(7-0) APAR (Output) (Output) tD(4) tD(1)
tD(3)
Byte from STS-1
Load Notes: single shown illustration purposes. delay clock cycle shown (selected register 0x184c8). STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e., setup hold, propagation delays) change.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK AD(7-0)/APAR valid delay from ACLK AD(7-0)/APAR tristate delay from ACLK indicator delayed from ACLK AD(7-0)/APAR tristate driven delay from ACLK
Note:
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(1) tD(4)
inputs AC1J1V1 ASPE sampled falling edge ACLK according setting configuration Active Edge (see Table 279, page 339).
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AC1J1V1
(Input)
STS-1
STS-1
STS-1
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Figure Timing (Timing Signals Inputs)
tCYC ACLK (Input) ASPE (Input)
tSU(1) tH(1)
C1(1) STS-1 STS-1 STS-1
tPWH tSU(2)
tH(2)
Occurs every four frames
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AC1J1V1
(Input)
STS-1
STS-1
STS-1
tD(2) AD(7-0) APAR (Output) (Output) tD(4) tD(1)
tD(3)
Byte from STS-1
Load Notes: single shown illustration purposes. delay clock cycle shown (selected register 0x184c8). STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e., setup hold, propagation delays) change.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK AD(7-0)/APAR valid delay from ACLK AD(7-0)/APAR tristate delay from ACLK indicator delayed from ACLK AD(7-0)/APAR tristate driven delay from ACLK
Note:
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(1) tD(4)
inputs AC1J1V1 ASPE sampled rising edge ACLK according setting configuration Active Edge (see Table 279, page 339).
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Figure Timing (Timing Signals Outputs)
tCYC ACLK (Output) ASPE (Output)
AC1J1V1
tPWH
tD(6) tD(5)
Occurs every four frames
STS-1
STS-1
STS-1
STS-1
STS-1
STS-1
tD(2) AD(7-0) APAR (Output) (Output) tD(4) tD(1)
tD(3)
Byte corresponding toSTS-1
Load Notes: single shown illustration purposes. delay clock cycle shown (refer register 0x184c8). STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e., setup hold, propagation delays) change.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1out valid delay from ACLK ASPE valid delay from ACLK AD(7-0)/APAR valid delay from ACLK AD(7-0)/APAR tristate delay from ACLK indicator delayed from ACLK AD(7-0)/APAR tristate driven delay from ACLK
Note:
Symbol tCYC
51.44
Unit
tD(5) tD(6) tD(2) tD(3) tD(1) tD(4)
ACLK derived from RTCLK input (lead should SONET/SDH minimum clock better.
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(Output)
C1(1)
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Figure GMII Ethernet Interface
tPWH
tCYC GTX_CLK (Output)
TX_EN (Output)
tD(1)
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TXD(7-0)
(Output)
tD(2) TX_ER (Output)
tD(3)
Load
Parameter GTX_CLK clock period GTX_CLK duty cycle, tPWH/tCYC TX_EN valid delay from GTX_CLK TXD(7-0) valid delay from GTX_CLK TX_ER valid delay from GTX_CLK
Symbol tCYC
Unit
tD(1) tD(2) tD(3)
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EtherMap-3 TXC-04226B
Figure GMII Ethernet Interface
tCYC RX_CLK (Input) tS(1) RX_DV (Input) tS(2)
RXD(7-0)
tPWH
tH(1)
(Input)
tH(2) RX_ER (Input) tS(3)
tH(3)
Load
Parameter RX_CLK clock period RX_CLK duty cycle, tPWH/tCYC RX_DV setup time before RX_CLK RX_DV hold time after RX_CLK RXD(7-0) setup time before RX_CLK RXD(7-0) hold time after RX_CLK (see Note RX_ER setup time before RX_CLK RX_ER hold time after RX_CLK
Note:
Symbol tCYC
Unit
tS(1) tH(1) tS(2) tH(2) tS(3) tH(3) 0.25
Does comply with IEEE 802.3 timing requirement compensated through board layout.
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Figure Tx/Rx SMII Ethernet Interface (SYNC Output)
tCYC SMII_GCLK (Input) tPWH
SMII_GSYNC (Output) tD(1)
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SMII_DOn
(Output)
TXD6
TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
TXD3
TXD4 TXD5
TXD6 TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
tD(2) SMII_DIn (Input)
RXD6 RXD7
RX_DV RXD0
RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
RX_DV RXD0
RXD1 RXD2
n=1-8
Load
Parameter SMII_GCLK clock period SMII_GCLK duty cycle, tPWH/tCYC SMII_GSYNC valid delay from SMII_GCLK SMII_DOn valid delay from SMII_GCLK SMII_DIn setup time before SMII_GCLK SMII_DIn hold time after SMII_GCLK
Symbol tCYC
Unit
tD(1) tD(2)
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EtherMap-3 TXC-04226B
Figure Tx/Rx SMII Ethernet Interface (SYNC Input)
tCYC SMII_GCLK (Input) SMII_GSYNC (Input)
SMII_DOn
tPWH
(Output)
TXD6
TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
TXD3
TXD4 TXD5
TXD6 TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
tD(2) SMII_DIn (Input)
RXD6 RXD7
RX_DV RXD0
RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
RX_DV RXD0
RXD1 RXD2
n=1-8
Load
Parameter SMII_GCLK clock period SMII_GCLK duty cycle, tPWH/tCYC SMII_GSYNC setup time before SMII_GCLK SMII_GSYNC hold time after SMII_GCLK SMII_DOn valid delay from SMII_GCLK SMII_DIn setup time before SMII_GCLK SMII_DIn hold time after SMII_GCLK
Symbol tCYC
Unit
tD(2)
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Figure Ethernet Management Interface
tCYC (Output)
WRITE OPERATION MDIO
tPWH
(Output)
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READ OPERATION MDIO
(Input)
Load
Parameter clock period pulse width MDIO valid delay from MDIO setup time before MDIO hold time after
Symbol tCYC tPWH
Unit
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EtherMap-3 TXC-04226B
Figure SDRAM Interface Single Word Read
tCYC
tPWH tD(1)
ACTIVE READ*
tD(2)
tD(3)
tD(4)
tD(5)
MASK
tD(7)
BK(1-0) ADDR(12-0)
tD(8)
DATA(31-0)
Latency
Note*: read commands enable auto precharge feature with ADDR(10)=1
Load
Parameter clock period duty cycle, tPWH/tCYC CLKE valid delay from valid delay from valid delay from valid delay from valid delay from BA(1-0) valid delay from ADDR(12-0) valid delay from DATA(31-0) setup time DATA(31-0) hold time from
Symbol tCYC
Unit
tD(1) tD(2) tD(3) tD(4) tD(5) tD(7) tD(8)
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Figure SDRAM Interface Single Word Write
tCYC
tPWH tD(1)
ACTIVE WRITE* ACTIVE WRITE*
tD(2)
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tD(3)
tD(4)
tD(5)
tD(6)
MASK
tD(7)
BK(1-0) ADDR(12-0)
tD(8)
tD(9)
DATA(31-0)
tD(10)
tD(12)
Note*: write commands enable auto precharge feature with ADDR(10)=1
Load Parameter
clock period duty cycle, tPWH/tCYC CLKE valid delay from valid delay from valid delay from valid delay from valid delay from MASK valid delay from BA(1-0) valid delay from ADDR(12-0) valid delay from DATA(31-0) tristate driven from DATA(31-0) valid delay from DATA(31-0) valid hold from DATA(31-0) driven tristate from tD(1) tD(2) tD(3) tD(4) tD(5) tD(6) tD(7) tD(8) tD(9) tD(10) tD(12)
Symbol
tCYC
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