Mbit (two Mbit, x16, FlexibleROMTM) Supply, Multiple Memory Product
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M27W1282
Mbit (two Mbit, x16, FlexibleROMTM) Supply, Multiple Memory Product
FEATURES SUMMARY TIME PROGRAMMABLE
Figure Package
Mbit FlexibleROMMEMORIES STACKED SINGLE PACKAGE SUPPLY VOLTAGE 3.6V Read 11.4 12.6V Program
ACCESS TIME 100, 120ns 3.6V PROGRAMMING TIME Word typical Multiple Word Programming Option (16s typical Chip Program)
SO44
SUITABLE ON-BOARD PROGRAMMING PROGRAM CONTROLLER Embedded Word Program algorithms ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code 8888h
September 2003
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M27W1282
TABLE CONTENTS FEATURES SUMMARY Figure Packages Figure Logic Diagram Table Signal Names Figure Connections SIGNAL DESCRIPTIONS Address Inputs (A0-A21) Data Inputs/Outputs (DQ0-DQ7). Data Inputs/Outputs (DQ8-DQ15). Chip Enable (E). Output Enable (G). Supply Voltage. Address/Voltage Supply (A22/VPP) Ground. OPERATIONS. Read. Write. Output Disable. Standby. Automatic Standby. Electronic Signature. Table Operations
COMMAND INTERFACE Read/Reset Command. Auto Select Command. Word Program Command. Multiple Word Program Command Setup Phase. Program Phase. Verify Phase. Exit Phase. Figure Latch Procedure Waveforms Table Latch Procedure Characteristics Figure Programming Flowchart Table Standard Commands. Table Multiple Word Program Command Table Program Times Figure Multiple Word Program Flowchart 64Mbit Bottom
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STATUS REGISTER Data Polling (DQ7). Toggle (DQ6). Error (DQ5). Status (DQ4) Multiple Word Program (DQ0) Multiple Word Program (DQ0) Table Status Register Bits Figure Data Polling Flowchart Figure Data Toggle Flowchart MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS Table Operating Measurement Conditions Figure Measurement Waveform Figure Measurement Load Circuit Table Device Capacitance. Table Characteristics. Figure Read Waveforms Table Read Characteristics Figure Chip Enable Controlled, Write Waveforms Table Chip Enable Controlled, Write Characteristics PACKAGE MECHANICAL SO44 lead Plastic Small Outline, mils body width, Package Outline SO44 lead Plastic Small Outline, mils body width, Package Mechanical Data PART NUMBERING Table Ordering Information Scheme REVISION HISTORY. Table Document Revision History
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SUMMARY DESCRIPTION M27W1282 Mbit (8Mb x16) non-volatile, Time Programmable (OTP), FlexibleROMMemory. Read operations performed using single voltage (2.7 3.6V) supply. Program operations require additional (11.4 12.6V) power supply. power-up memory defaults Read mode where read same EPROM. Mask-ROM compatibility obtained using dual function Address/Voltage Supply (A22/ VPP). Read mode A22/VPP works address pin; Program mode also works voltage supply pin. beginning program operation, specific procedure (see Figure must performed internally memorize value that will used during program operation. Program commands written Command Interface memory. on-chip Program Controller (PC) simplifies process programming memory taking care special operations that required update memory contents. device composed 64Mbit memories assembled side side single package. Recommended operating conditions allow both memories active same time. Addres
selects memory enabled. other memory Standby mode. Read mode works address pin: selects die; selectrs Bottom die. beginning program operation, specific procedure (see Figure must performed internally memorize value that will used during program operation. M27W1282 features innovative command, Multiple Word Program, used program large streams data. greatly reduces total programming time when large number Words written memory time. Using this command entire memory programmed compared using standard Word Program. program operation detected error conditions identified. command required control memory consistent with JEDEC standards. Chip Enable Output Enable signals control operation memory. They allow simple connection most microprocessors, often without additional logic. memory offered SO44 package supplied with bits '1'.
Figure Logic Diagram
Table Signal NameA0-A21 Address Inputs Address Input/Supply Voltage Program Data Inputs/Outputs Chip Enable Output Enable Supply Voltage read Ground
A22/VPP
A22/VPP DQ0-DQ15
A0-A21
DQ0-DQ15
M27W1282
AI08220
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M27W1282
Figure Connection
DQ10 DQ11
M27W1282
A22/VPP DQ15 DQ14 DQ13 DQ12
AI08221
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SIGNAL DESCRIPTIONS Figure Logic Diagram, Table Signal Names, brief overview signals connected this device. Address Inputs (A0-A21). Address Inputs select cells memory array access during Read operations. During Write operations they control commands sent Command Interface Program Controller. Address/Voltage Supply (A22/V A22/VPP signal functions. During read operations A22/VPP signal works address input, which used select (A22 VIH) Bottom (A22 VIL) die. During program operations also works voltage supply pin. beginning program operation, specific procedure (see Figure must performed internally memorize value that will used during program operation. When range (see Table Characteristic, relevant values) program operations enabled. During such operations must stable range. Program operation allowed when below range. Data Inputs/Outputs (DQ0-DQ7). Data Inputs/Outputs output data stored selected address during Read operation. During
Write operations they represent command sent Command Interface Program Controller. When reading Status Register they report status ongoing algorithm. Data Inputs/Outputs (DQ8-DQ15). Data Inputs/Outputs output data stored selected address during Read operation. During Write operations Command Interface does these bits. When reading Status Register these bits should ignored. Chip Enable (E). Chip Enable, activates memory, allowing Read operations performed. also controls Write operations, when range. Output Enable (G). Output Enable, controls Read operations memory. also allows Write operations, when range. Supply Voltage. Supply Voltage supplies power Read operations. 0.1µF capacitor should connected between Supply Voltage Ground decouple current surges from power supply. track widths must sufficient carry currents required during program operations, ICC3. Ground. Ground reference voltage measurements.
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M27W1282
OPERATIONS There standard operations that control device. These Read, Write, Output Disable, Standby, Automatic Standby Electronic Signature. Table Operations, summary. Typically glitches less than Chip Enable Write Enable ignored memory affect operations. Read. Read operations read from memory cells, specific registers Command Interface. valid Read operation involves setting desired address Address Inputs applying signal, VIL, Chip Enable Output Enable. Data Inputs/Outputs will output value, Figure Read Waveforms, Table Read Characteristics, details when output becomes valid. Write. Write operations write Command Interface. Write enabled only when VHH. valid Write operation begins setting desired address Address Inputs. Address Inputs latched Command Interface falling edge Chip Enable. Data Inputs/Outputs latched Command Interface rising edge Chip Enable. Output Enable must remain High, VIH, during whole Write operation. Figure Write Waveforms, Table Write Characteristics, details timing requirements. Table OperationOperation Read Write Output Disable Standby Read Manufacturer Code Read Device Code
Note:
Output Disable. Data Inputs/Outputs high impedance state when Output Enable High, VIH. Standby. When Chip Enable High, VIH, memory enters Standby mode Data Inputs/Outputs pins placed high-impedance state. reduce Supply Current Standby Supply Current, ICC2, Chip Enable should held within 0.2V. Standby current level Table Characteristics. During program operation memory will continue Program Supply Current, ICC3, Program operation until operation completes. Automatic Standby. CMOS levels (VCC 0.2V) used drive inactive 150ns more memory enters Automatic Standby where internal Supply Current reduced Standby Supply Current, ICC2. Data Inputs/Outputs will still output data Read operation progress. Electronic Signature. memory codes, manufacturer code device code, that read identify memory. These codes read applying signals listed Table Operations, once Auto Select Command executed. exit Electronic Signature mode, Read/Reset command must issued.
A22/VPP(2) VIL/VIH(3) VHH(4)
Address Inputs A0-A21 Cell Address Command Address VIL, VIL, Others VIH, VIL, Others
Data Inputs/Outputs DQ15-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 8888h
VIH. When reading Status Register during program operation A22/VPP must kept VHH. enables Bottom die, enables during read array operation. after latching VIH.
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COMMAND INTERFACE Write operations memory interpreted Command Interface. Commands consist more sequential Write operations. Failure observe valid sequence Write operations will result memory returning Read mode. long command sequences imposed maximize data security. Refer Tables summary commands. Read/Reset Command. Read/Reset command returns memory Read mode where behaves like EPROM, unless otherwise stated. also resets errors Status Register. Either three Write operations used issue Read/Reset command. must during Read/Reset command. either command will ignored. command issued, between Write cycles before start program operation, return device read mode. Once program operation started Read/Reset command longer accepted. Auto Select Command. Auto Select command used read Manufacturer Code Device Code. must during Auto Select command. either command will ignored. Three consecutive Write operations required issue Auto Select command. Once Auto Select command issued memory remains Auto Select mode until Read/Reset command issued, other commands ignored. From Auto Select mode Manufacturer Code read using Read operation with VIL. other address bits either VIH. Device Code read using Read operation with VIL. other address bits either VIH. Word Program Command. Word Program command used program Word memory array. must during Word Program. either command will ignored, data will remain unchanged device will revert Read/Reset mode. command requires four Write operations, final write operation latches address data internal state machine starts During program operation memory will ignore commands. possible issue command abort pause operation. Typical program times given Table Read
erations during program operation will output Status Register Data Inputs/Outputs. section Status Register more details. After program operation completed memory will return Read mode, unless error occurred. When error occurs memory will continue output Status Register. Read/Reset command must issued reset error condition return Read mode. Note that Program command cannot change back '1'. Multiple Word Program Command Multiple Word Program command used program large streams data. greatly reduces total programming time when large number Words written memory once. must during Multiple Word Program. either command will ignored, data will remain unchanged device will revert Read mode. four phases: Setup Phase initiate command, Program Phase program data memory, Verify Phase check that data been correctly programmed reprogram necessary Exit Phase. Setup Phase. Multiple Word Program command requires three Write operations initiate command (refer Table Multiple Word Program Command Figure Multiple Word Program Flowchart). Status Register must read order check that started (see Table Figure Program Phase. Program Phase requires Write operations, where number Words, execute programming phase (refer Table Multiple Word Program Figure Multiple Word Program Flowchart). Before Write operation Program Phase, Status Register must read order check that ready accept operation (see Table Figure Program Phase executed three different sub-phases: first Write operation Program Phase (the command) latches Start Address first Word programmed. Each subsequent Write operation latches next Word programmed automatically increments internal Address Bus. necessary provide address location programmed only Continue Address, (A17 equal
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Start Address), that indicates that Program Phase continue. `don't care'. Finally, after Words have been programmed, Write operation (the (n+1)th) with Final Address, (A17 higher address different from Start Address), ends Program Phase. memory enter Verify Phase. Verify Phase. Verify Phase similar Program Phase that Words must resent memory them checked against programmed data. Before Write Operation Verify Phase, Status Register must read order check that ready next operation reprogram location failed (see Table Figure Three successive steps required execute Verify Phase command: first Write operation Verify Phase latches Start Address Word verified. Each subsequent Write operation latches next Word verified automatically increments internal Address Bus. Program Phase, necessary provide address location programmed only Continue Address, (A17 equal Start Address). Finally, after Words have been verified, Write cycle with Final Address, (A17 higher address different from Start Address) ends Verify Phase. Exit Phase. After Verify Phase ends, Status Register must read check command successfully completed (see Table Figure Verify Phase successful, memory returns Read mode stops toggling. fails reprogram given location, Verify Phase terminates, continues toggling error Status Register. error failure also set. When operation fails Read/Reset command must issued return device Read mode. During Multiple Word Program operation memory will ignore commands. possible issue command abort pause operation. Typical program times given Table Read operations during program operation will output Status Register Data Inputs/Outputs. section Status Register more details. Note that Multiple Word Program command cannot change back '1'.
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Figure Latch Procedure WaveformtA9HA9L latched rising edge tA22VA9TL VALID
A0-A8; A10-A21
AI08257
Note: VIH; DQ0-DQ15 Don't care; 10.5 0.25V; 3.6V; VIH.
Table Latch Procedure CharacteristicSymbol tA22VA9TL tA9HA9L Parameter valid Third Level High Unit
Figure Programming Flowchart
Start
Latch procedure with
Program Command execution 64Mbit
Latch procedure with
Program Command execution 64Mbit Bottom
READ (verify pattern) 128Mbit
AI08208
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M27W1282
Table Standard CommandLength Write Operations Data Data Data Data Command
Read/Reset Auto Select Word Program
Note: Don't Care, Program Address, Program Data. values table hexadecimal. Command Interface only uses A0-A10 DQ0-DQ7 verify commands; A11-A21, DQ8-DQ15 Don't Care.
Table Multiple Word Program Command
Phase Length Write Operations Data Data Data Data Data Data Final Data
Set-Up Program Verify
Note: Read must done between each Write cycle where data programmed verified, Read Status Register check that memory ready accept next data. Start Address. Continue Address. Final Address. Don't Care, number Words programmed.
Table Program TimeParameter Program (Word) Chip Program (Multiple Word) Chip Program (Word Word)
Note: 25°C, 12V.
Unit
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Figure Multiple Word Program Flowchart 64Mbit Bottom
Setup Phase
Start Write Address 555h Read Status Register Verify Phase
Write Address 2AAh
Write Address 555h
Write Data1 Start Addres
Read Status Register Setup time exceeded? EXIT (setup failed) Program Phase Write Data1 Start Address toggling?
Read Status Register Write Data Continue Address
Read Status Register
Read Status Register
Write Data Continue Addres
Write Data Continue Addres
Read Status Register
Read Status Register
Exit Phase
Write Data Continue Addres
Write Final Address Read Status Register
Read Status Register
Read Status Register toggling? Write Final Address
Fail error
Fail, error
Write Address
Exit (read mode)
AI05954b
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STATUS REGISTER Read operations from address always read Status Register during Program operations. bits Status Register summarized Table Status Register Bits. Data Polling (DQ7). Data Polling used identify whether Program Controller successfully completed operation. Data Polling output when Status Register read. During Word Program operation Data Polling outputs complement being programmed DQ7. After successful completion Word Program operation memory returns Read mode Read operations from address just programmed output DQ7, complement. Figure Data Polling Flowchart, gives example Data Polling Bit. Valid Address address being programmed. Toggle (DQ6). Toggle used identify whether Program Controller successfully completed operation. Toggle output when Status Register read. During Program operations Toggle changes from '0', etc., with successive Read operations address. After successful completion operation memory returns Read mode.
Figure Data Toggle Flowchart, gives example Data Toggle Bit. Error (DQ5). Error used identify errors detected Program Controller. Error when Program operation fails write correct data memory. Error Read/Reset command must issued before other commands issued. Error output when Status Register read. Note that Program command cannot change back attempting will `1'. Read operation that address will show still `0'. Status (DQ4). Status used identify Program operation failed error. falls below during Program operation, operation aborts `1'. remains throughout Program operation, operation completes `0'. Multiple Word Program (DQ0). Multiple Word Program used indicate whether Program Controller active inactive during Multiple Word Program. When Program Controller written Word ready accept next Word, `0'. Status Register reserved.
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Table Status Register BitCommand P.C. Status Programming Multiple Word Program Waiting data Program fail Programming Word Program Program error Toggle
Toggle Toggle Toggle Toggle
Note: Unspecified data bits should ignored. during Program algorithm execution; during Program algorithm execution.
Figure Data Polling Flowchart
Figure Data Toggle Flowchart
START READ
START
READ VALID ADDRESS
READ
DATA
TOGGLE
READ VALID ADDRESS
READ TWICE
DATA FAIL
TOGGLE
PASS
FAIL PASS
AI01370B
AI03598
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M27W1282
MAXIMUM RATING Stressing device above rating listed "Absolute Maximum Ratings" table cause permanent damage device. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. These stress ratings only operation device Table Absolute Maximum RatingSymbol TBIAS TSTG Temperature Under Bias Storage Temperature Input Output Voltage (1,2) Read Supply Voltage Program Supply Voltage Parameter -0.6 -0.6 -0.6 +0.6 13.5 Unit
these other conditions above those indicated Operating sections this specification implied. Refer also STMicroelectronics SURE Program other relevant quality documents.
Note: Minimum voltage undershoot less than 20ns during transitions. Maximum voltage overshoot less than 20ns during transitions. Maximum voltage overshoot 14.0V less than 20ns during transitions. must remain more than total 80hrs.
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PARAMETERS This section summarizes operating measurement conditions, characteristics device. parameters characteristics Tables that follow, derived from tests performed under Measurement
Conditions summarized Table Operating Measurement Conditions. Designers should check that operating conditions their circuit match operating conditions when relying quoted parameters.
Table Operating Measurement ConditionM27W1282 Parameter Read Supply Voltage Program Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages 11.4 100, 12.6 Unit
Figure Measurement Waveform
Figure Measurement Load Circuit
1.3V
1N914
1.5V
AI05546
3.3k DEVICE UNDER TEST
30pF includes capacitance
AI05447
Table Device Capacitance
Symbol COUT CA22/Vpp Parameter Input Capacitance Output Capacitance A22/VPP Capacitance Test Condition VOUT VA22/Vpp Unit
Note: Sampled only, 100% tested.
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Table CharacteristicSymbol ICC1 ICC2 ICC3 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Supply Current (Program) Input Voltage Input High Voltage Output Voltage Output High Voltage Program Voltage Current (Program) Active 1.8mA -100µ -0.4 11.4 12.6 Test Condition VOUT VIL, VIH, IOUT 0mA, 6MHz ±0.2V active -0.5 0.7VCC +0.3 0.45 Unit
Note: must applied simultaneously before removed simultaneously after VPP. Average Value.
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Figure Read Waveform
A0-A22 tAVQV tELQV tGLQV DQ0-DQ15
VALID tAXQX
tEHQZ
tGHQZ VALID
AI08263
Table Read CharacteristicM27W1282 Symbol Parameter Test Condition Unit
3.6V 3.6V
tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z
VIL,
Address Transition Output Transition
Note: must applied after with Chip Enable VIH. Sampled only, 100% tested.
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Figure Chip Enable Controlled, Write Waveform
A0-A21
VALID tELAX tAVEL tEHGL
tGHEL tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH
tVCHEL A22/VPP tVPHEL
AI08233
Table Chip Enable Controlled, Write CharacteristicSymbol tELEH tDVEH tEHDX tEHEL tAVEL tELAX tGHEL tEHGL tVCHEL tVPHEL(2) tOEH tVCS tVCS tCPH Parameter Chip Enable Chip Enable High Input Valid Chip Enable High Chip Enable High Input Transition Chip Enable High Chip Enable Address Valid Chip Enable Chip Enable Address Transition Output Enable High Chip Enable Chip Enable High Output Enable High Chip Enable High Chip Enable M27W1282 Unit
Note: 25°C; 11.4 12.6V. 3.6V. must applied after with Chip Enable VIH. Sampled only, 100% tested. required Auto Select Read/Reset command sequences.
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M27W1282
PACKAGE MECHANICAL Figure SO44 lead Plastic Small Outline, mils body width, Package Outline
SO-F
Note: Drawing scale.
Table SO44 lead Plastic Small Outline, mils body width, Package Mechanical Data
millimeters Symbol 16.03 12.60 1.27 0.79 1.73 15.77 12.47 28.50 0.10 2.69 2.56 0.35 0.18 28.37 2.79 0.50 0.28 28.63 0.10 16.28 12.73 0.631 0.496 0.050 0.031 0.068 0.621 0.491 1.122 3.00 0.004 0.106 0.101 0.014 0.007 1.117 0.110 0.020 0.011 1.127 0.004 0.641 0.501 0.118 inche
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PART NUMBERING Table Ordering Information Scheme
Example: Device Type FlexibleROMMemory Operating Voltage 3.6V Device Function Mbit (x16) Device Function dice Speed Package SO44, 500mils body width Temperature Range Option Tape Reel Packing
M27W128
Devices shipped from factory with bits '1'. list available options (Speed, Package, etc.) further information aspect this device, please contact Sales Office nearest you.
REVISION HISTORY Table Document Revision History
Date 29-Apr-2003 17-Sep-2003 Version First Issue From Preliminary Data Datasheet Revision Detail
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M27W1282
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics FlexibleROM pending trademark STMicroelectronics Group other names property their respective owners 2003 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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