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PLASMA DISPLAY PANEL SCAN DRIVER Outputs Plasma Display Driver 17


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STV7697A
PLASMA DISPLAY PANEL SCAN DRIVER
Outputs Plasma Display Driver 170V Absolute Maximum Rating Supply Logic -200/850 Peak Output Current 1000 Source Sink Output Diode 64-Bit Shift Register MHz) Blank Control Complementary Output Control Technology Pin-PQFP Package Dice.
DESCRIPTION STV7697A scan driver Plasma Display Panel (PDP) implemented ST's proprietary technology. Using 64-bit cascadable shift register, drives high current high voltage outputs. serially connecting several STV7697A, vertical pixel definition performed. STV7697A supplied with separated 160V power output supply logic supply. command inputs CMOS compatible. STV769 package pin-PQFP.
PQFP100 2.80 (Full Plastic Quad Flat Pack) ORDER CODE: STV7697A
ORDER CODE: STV7697A/WAF (1): Unsawn Tested Wafer
Version
August 2003
This preliminary information product development undergoing evaluation. Details subject change without notice.
1/17
Table Contents
CONNECTIONS pinout PQFP pinout)
ASSIGNMENT PQFP100 package Power outputs
PADS DIMENSIONS µm)/ PADS POSITIONS BLOCK DIAGRAM CIRCUIT DESCRIPTION ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS TIMINGS REQUIREMENTS
TIMINGS CHARACTERISTICS INPUT/OUTPUT SCHEMATICS TESTED WAFER DISCLAIMER PACKAGE MECHANICAL DATA Revision History
2/17
VSSSUB VSSP VSSLOG VSSSUB VSSLOG OUT31 VSSLOG OUT32 OUT34 OUT33
VSSLOG
VSSSUB
SSSUB
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSLOG
pinout
PQFP pinout)
OUT31 VSSLOG OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 (0,0) OUT47 OUT48 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64
OUT32
OUT33
OUT34
OUT30
OUT29
OUT28
OUT27
OUT26
CONNECTIONS
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
Bare
PQFP100
OUT13
OUT12
STV7697A
STV7697A
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
VSSP VSSP VSSLOG SIN(SOUT) SOUT(SIN)
VSSP
SSLOG
SIN(SOUT)
SOUT(SIN)
VSSP
VSSP
STV7697A
3/17
STV7697A
ASSIGNMENT
PQFP100 package
Number 33-37-44-48-81-84-97-100 34-35-36-45-46-47-82-83-98-99 38-43 39-40-42-94 88-95-96 Symbol VSSP VSSSUB VSSLOG SOUT (SIN) (SOUT) Type Supply Supply Ground Ground Ground Output Output Input Input Input Input Input Input Function High voltage supply power outputs logic supply Ground power outputs Substrate ground Logic ground Power output Shift register data output (forward) Polarity selection Output blanking command Selection shift direction Shift register data input (forward) Latch data outputs Clock data shift register
Power outputs
Output Output Output
Output
4/17
STV7697A
PADS DIMENSIONS µm)/ PADS POSITIONS
reference centre (x=0, y=0) SIDE from left right
Name VSSP VSSP VSSLOG SOUT VSSP VSSP Centre:X 2468.5 2313.5 2188.5 2063.5 1620.0 1430.0 -781.0 -612.5 -335.5 379.5 548.0 1082.0 1853.0 2021.5 2156.5 2291.5 2454.5 Centre:Y 4135.0 4135.0 4135.0 4134.5 4135.0 4135.0 4135.0 4135.0 4144.5 4135.0 4135.0 4135.0 4135.0 4140.0 4140.0 4140.0 4129.5 Size:x 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 SIze: 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0
BOTTOM SIDE from left right
Name OUT34 OUT33 VSSP VSSP VSSP VSSSUB VSSLOG VSSLOG VSSLOG VSSSUB VSSP VSSP VSSP OUT32 OUT31 Centre:X 2468.0 2318.0 2182.0 2047.0 1912.0 1777.0 1642.0 -683.0 -382.5 419.5 618.5 951.0 1308.0 1438.5 1797.5 1932.5 2067.5 2193.0 2318.0 2468.5 Centre:Y 4087.5 4089.5 4089.5 4093.0 4093.0 4093.0 4089.5 4088.0 4088.0 4087.5 4087.5 -4087.5 -4087.5 -4087.5 -4093.5 -4093.5 -4093.5 -4093.5 -4093.5 -4093.5 Size:x 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 SIze: 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0
5/17
STV7697A
RIGHT SIDE from bottom
Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 Centre:X 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 Centre:Y 3697.0 3484.0 3238.5 2992.5 2743.0 2506.5 2264.0 2018.0 1774.5 1529.0 1285.5 1040.0 796.5 551.0 307.5 62.0 -181.5 -427.0 -670.5 -916.0 -1159.5 -1405.0 -1648.5 -1894.0 -2137.5 -2383.5 -2627.0 -2872.5 -3116.0 -3363.0 Size:x 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 SIze: 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0
LEFT SIDE from bottom
Name OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64 Centre:X -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 Centre:Y -3363.0 -3116.0 -2872.5 -2627.0 -2383.5 -2137.5 -1894.0 -1648.5 -1405.0 -1159.5 -916.0 -670.5 -427.0 -181.5 62.0 307.5 551.0 796.5 1040.0 1285.5 1529.0 1774.5 2018.0 2264.0 2506.5 2743.0 2949.5 3228.5 3487.0 3763.0 Size:x 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 SIze: 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0
6/17
STV7697A
BLOCK DIAGRAM
64-BIT SHIFT REGISTER
SOUT (SIN) VSSSUB Pins 38-43 VSSLOG Pins 39-40-42-94 Pins 41-90 VSSP Pins 34-35-36-45-46 47-82-83-98-99 Pins 33-37-44-48 81-84-97-100
(SOUT)
Q1Q2
LATCH
Q63Q64
STV7697A
VSSP OUT1
VSSP OUT64
7/17
STV7697A
CIRCUIT DESCRIPTION
level power output inverted when polarity command (POL) pulled high. Sustain current must sunk power output when power supply applied. VSSLOG VSSSUB must connected close possible logical reference ground application. Table Shift Register Truth Table
Input Rise Rise Input/Output Shift Register Function Output Forward Shift Steady Reverse Shift Steady
STV7697A contains logic power circuits necessary drive rows Plasma Display Panel P.). state displayed line loaded into shift register. Data shifted each high transition (CLK) shift clock. After shifts first available serial output. This output used cascade several drivers perform vertical resolution. forward reverse (F/R) input used select direction shift register, data input/output status according selected direction. SIN, CLK, inputs Smith trigger inputs. used application, F/R, BLK, logical inputs internally pulled level "1". maximum frequency shift clock MHz. data memorized into latch stage when strobe input (STB) pulled high. Blanking input (BLK) forces power outputs high level when pulled high with polarity input (POL) high level forced level with level. Table Power Output Truth Table
Driver Output
Comments Forced High Forced Copy Data Copy Data Copy Inverted Data Copy Inverted Data Data Latched Inverted Data Latched
Note 1:Qn parallel output shift register 64). takes value serial input (SIN) after shift clock periods.
8/17
STV7697A
ABSOLUTE MAXIMUM RATINGS
Symbol VPP_waf VOUT VPOUT IPOUT IDOUT Toper Tjmax Tstg Logic Supply Range Driver Supply Range Driver supply range package Logic Input Voltage Range Logic Output Voltage Range Driver Output Voltage Range Driver Output Current Diode Output Current Operating Temperature Junction Temperature Storage Temperature Parameter Value -0.3, -0.3, +170 -0.3, +150 -0.3, +0.3 -0.3, -0.3, -250/+850 ±1000 -20, +125 -50,+150 Unit
susceptibility Human Body Model:100pF, 1.5k. pins withstand ±2.2kV except power outputs: 1.7kV positive voltage discharge.
THERMAL DATA
Symbol Rth(j-a) Poper Tjoper Parameter Junction-ambient Thermal Resistance Operating Power Dissipation (Tamb 25°C) Operating Junction Temperature +125 °C/W Value Unit
Note 2:For PQFP100 packaging. Note 3:Through power output. Note 4:Through power output with VSSP (see test diagram). Note 5:These parameters measured during ST's internal qualification which includes temperature characterization standard batches corners batches process. These parameters tested parts.
9/17
STV7697A
ELECTRICAL CHARACTERISTICS
(VCC VSSP VSSLOG VSSSUB Tamb 25°C, fCLK MHz, unless otherwise specified)
Symbol SUPPLY ICCH ICCL VPP_waf IPPH OUTPUT OUT1-OUT64 VPOUTH IPOUTH-peak VPOUTL IPOUTL-peak VDOUTH1 VDOUTL1 VDOUTH2 VDOUTL2 SOUT/SIN Logic Output High Level Logic Output Level Power Output High Level (voltage drop versus VPP, VPP=90V) Power Output Peak Current Power Output Level Power Output Peak Current Output Diode High Level Output Diode Level Output Diode High Level Output Diode Level IPOUTH IPOUTH =130V IPOUTL VPOUTL IDOUTH +400 IDOUTL IDOUTH +1000 IDOUTL 1000 -200 -1.5 Logic Supply Voltage Logic Supply Current (all inputs high) Logic Supply Current Power Output Supply Voltage Power Output Supply Voltage (Die package) Power Output Supply Current (steady outputs) fCLK MHz, =1010 Parameter Test Conditions Min. Typ. Max. Unit
INPUT (CLK, F/R, STB, POL, BLK, SIN/SOUT) Input High Level Input Level High Level Input Current Level Input Current CLK, SIN/SOUT, STB, F/R, BLK, 0.2VCC
Note 6:Peak current: pulse mode 200ns pulse width, VCC=5 Note 7:Compatible with power dissipation (see Figure 2.Test Configuration). Note 8:The typical value increases when more than output activated. Note 9:These parameters measured during ST's internal qualification which includes temperature characterization standard batches corners batches process. These parameters tested parts.
10/17
STV7697A
TIMINGS REQUIREMENTS
Symbol tCLK tWHCLK tWHCLK tSDAT tHDAT tSFR tDSTB tSTB tBLK tPOL Data Clock Period Duration clock (CLK) pulse high level Duration clock (CLK) pulse level Set-up Time data input before clock high transition Hold Time data input after clock high transition Forward/reverse (F/R) Set-up Time before high transition Minimum Delay latch after clock high transition Strobe Pulse Duration Blank (BLK) Pulse Duration Polarity (POL) Pulse Duration Parameter Min. Typ. Max. Unit
(VCC Tamb +85°C, input signals leading edge trailing edge (tR,
TIMINGS CHARACTERISTICS
(VCC VSSP VSSLOG VSSSUB Tamb 25°C, fCLK MHz, VILMax. Vcc, VIHMin. VCC, 15pF, unless otherwise specified)
Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay logic data output change high transition after transition Delay logic data output change high transition after transition Delay power output change high transition after transition Delay power output change high transition after transition Delay power output change high transition after transition Delay power output change high transition after transition Delay power output change high transition after transition Delay power output change high transition after transition Power Output Rise Time (10) Power Output Fall Time (10) Parameter Min. Typ. Max. Unit
Note 10:One output among loading capacitor COUT 200pF, other outputs level.
11/17
STV7697A
Figure Characteristics Waveform
tCLK tWLCLK tWHCLK tSDAT tHDAT tPLH1 tRDAT tSFR tPHL2 OUTn tPLH2 tBLK tPLH3 tPHL3 OUTn tPOL tROUT tFOUT tPHL4 tPLH4 tSTB tDSTB tFDAT SOUT
OUTn
12/17
STV7697A
Figure Test Configuration
VPP=VSSP VPP=VSSP
VDOUTH
IDOUTH
VDOUTL VSSP VSSP
IDOUTL
Output sinking current positive value, sourcing current negative value
13/17
STV7697A
INPUT/OUTPUT SCHEMATICS
Figure SIN, SOUT Input
(Pins
Figure F/R, BLK, POL,
(Pins
SIN, SOUT (Pins
F/R, BLK, (Pins
VSSLOG (Pins
VSSLOG (Pins
VSSSUB (Pins VSSLOG (Pins
VSSSUB (Pins
Figure CLK,
(Pins
Figure Power Output
(Pins 100)
CLK, (Pins
OUTi (Pins
VSSSUB (Pins
VSSLOG (Pins
VSSP (Pins
TESTED WAFER DISCLAIMER
wafers tested guaranteed comply with datasheet limits point wafer sawing period ninety (90) days from delivery date. remind that customer's responsibility test qualify their application which used. Microelectronics ready support customer when qualifying product.
14/17
STV7697A
PACKAGE MECHANICAL DATA
0,10 .004 inch SEATING PLANE
PINS THIN PLASTIC QUAD FLAT PACK (PQFP100)
Millimetres Dimensions Min. 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 (Min.), (Max.) 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.38 0.23 23.45 20.10 Typ. Max. 3.40 0.010 0.100 0.0087 0.005 0.903 0.783 Min.
Inches Typ. Max. 0.134
0.110
0.120 0.015 0.009
0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063
0.923 0.791
0.687 0.555
0.037
15/17
STV7697A
Revision History
Table Summary Modifications
Version
Date January 2003 January 2003
Description Changed "TQFP" "PQFP" pages Global change fCLK from tCLK Min. from Global change fCLK from tCLK Min. from
16/17
STV7697A
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo trademark STMicroelectronics. 2003 STMicroelectronics Rights Reserved Purchase Components STMicroelectronics, conveys license under Philips Patent. Rights these components system, granted provided that system conforms Standard Specifications defined Philips. STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States http://www.st.com
17/17

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