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revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2329 Series, H8S/2328 Series
Hardware Manual
Specifications Common Series
ADE-602-171C Rev. 3/20/2003 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8S/2329 Series H8S/2328 Series series high-performance microcontrollers with 32-bit H8S/2000 core, on-chip supporting functions required system configuration. H8S/2000 execute basic instructions state, provided with sixteen 16-bit general registers with 32-bit internal configuration, concise optimized instruction set. handle 16-Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. address space divided into eight areas. data width access states selected each these areas, various kinds memory connected fast easily. Single-power-supply flash memory (F-ZTATTM) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. On-chip supporting functions include 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. addition, on-chip controller (DMAC) data transfer controller (DTC) provided, enabling high-speed data transfer without intervention. H8S/2329 Series H8S/2328 Series enables easy implementation compact, highperformance systems capable processing large volumes data. Refer H8S/2600 Series, H8S/2000 Series Programming Manual detailed description instruction programming-related information.
Rev. 4.0, 03/03 page xliv
Rev. 4.0, 03/03 page xliv
List Main Revisions Additions This Version
Item Overview Table Overview Page Revisions (See Manual Details) Package Memory H8S/2326C F-ZTAT lineup added, note amended
Product Code H8S/2329, H8S/2329B* H8S/2329E* H8S/2328, H8S/2328B* H8S/2327 H8S/2326
H8S/2326C*
kbytes kbytes kbytes kbytes kbytes kbytes
kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320
Notes: H8S/2329B F-ZTAT low-cost version H8S/2329 F-ZTAT. Refer item H8S/2329 F-ZTAT. on-chip debug function used with E10-A emulator (E10-A compatible version). However, some function modules functions unavailable when on-chip debug function use. Refer figures 1-8, Arrangement. H8S/2328B F-ZTAT low-cost version H8S/2328 F-ZTAT. Refer item H8S/2328 F-ZTAT. planning
Operating modes Eight operating modes (H8S/2328 F-ZTAT, H8S/2326 F-ZTAT) Mode deleted from table
Rev. 4.0, 03/03 page xliv
Item Overview Table Overview
Page
Revisions (See Manual Details) Four operating modes (ROMless, mask versions, H8S/2329F-ZTAT H8S/2326C F-ZTAT) Item Operating Mode deleted from table, notes amended
Operating Mode Mode Description
External Data On-Chip Initial Value Maximum Value
Advanced On-chip disabled Disabled bits bits expansion mode On-chip disabled Disabled bits bits expansion mode On-chip enabled Enabled bits bits expansion mode Single-chip mode Enabled Notes: User boot mode H8S/2326C F-ZTAT. table 19.73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. Boot mode H8S/2329 F-ZTAT, H8S/2326C F-ZTAT. table 19.9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user boot modes. table 19.9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user program modes. table 19.73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user program modes. table 19.73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. ROMless versions only modes
Product lineup Table notes amended
Condition Operating power supply voltage Operating frequency Model
HD64F2328B*
Condition
HD6432327 HD64F2326
HD64F2326C*
HD6412324S HD6432323 HD6412322R HD6412321 HD6412320
This low-cost version. specifications, refer items H8S/2328 F-ZTAT. planning Item Other features newly added
Rev. 4.0, 03/03 page xliv
Item Block Diagram Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Internal Block Diagram
Page
Revisions (See Manual Details) Figure amended (Before) (After) WDTOVF (FEW, EMLE) WDTOVF (FEW, EMLE, VCL)
Note amended Note: EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. 72nd name note amended (Before) (After) WDTOVF (FWE, EMLE) WDTOVF (FWE, EMLE, VCL)
1.3.1 Arrangement Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Arrangement (TFP-120: View)
Note amended Note: EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. 80th name note amended (Before) (After) WDTOVF (FWE, EMLE) WDTOVF (FWE, EMLE, VCL)
Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Arrangement (FP-128B: View)
Note amended Note: EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. 1.3.2 Functions Each Operating Mode Table Functions Each Operating Mode 72nd name TFP-120, 80th name FP128B amended (Before) (After) (Before) (After) WDTOVF (FWE, EMLE) WDTOVF (FWE, EMLE, VCL) FWE, EMLE FWE, EMLE,
Note amended Note: EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only.
1.3.3 Functions Table Functions
Added table
Type Power Symbol TFP-120 FP-128B 100, Input Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply
Input
Internal stepdown
VCL*
Output external capacitor should connected between this (0V). connect VCC.
Rev. 4.0, 03/03 page xliv
Item 1.3.3 Functions Table Functions
Page
Revisions (See Manual Details) Operating mode control Table relation between settings pins operating mode amended
H8S/2328 F-ZTAT, H8S/2326 F-ZTAT: Operating Mode
Mask ROMless versions, H8S/2329 F-ZTAT, H8S/2326C F-ZTAT: Operating Mode Mode Mode Mode Mode Mode Mode Mode
Notes: Applies H8S/2326C F-ZTAT only. Applies H8S/2329 F-ZTAT H8S/2326C F-ZTAT only. ROMless versions only modes
Note added Note: Applies H8S/2326C F-ZTAT only.
2.6.3 Table Instructions Classified Function Table Instructions Classified Function 2.7.1 Addressing Mode Memory Indirect
MOVFPE MOVTPE functions amended (Before) (After) Cannot used H8S/2357 Series. Cannot used H8S/2329 H8S/2328 Series.
Description amended upper bits absolute address assume address range (H'000000 H'0000FF). advanced mode, memory operand long word operand, first byte which assumed (H'00).
3.1.1 Operating Mode Selection (H8S/2328 F-ZTAT, H8S/2326 FZTAT) Table Operating Mode Selection (H8S/2328 F-ZTAT, H8S/2326 F-ZTAT)
Item Operating Mode deleted from table.
Rev. 4.0, 03/03 page viii xliv
Item 3.1.2 Operating Mode Selection (Mask ROMless Versions, H8S/2329 F-ZTAT, H8S/2326C F-ZTAT)
Page
Revisions (See Manual Details) Title description amended ROMless mask versions have four operating modes (modes H8S/2329 F-ZTAT operating modes (modes H8S/2326C F-ZTAT seven operating modes (modes
3.1.2 Operating Mode Selection (Mask ROMless Versions, H8S/2329 F-ZTAT, H8S/2326C F-ZTAT) Table Operating Mode Selection (Mask ROMless Versions, H8S/2329 FZTAT, H8S/2326C F-ZTAT)
Item Operating Mode deleted from table notes amended
Operating Mode
Notes:*1 User boot mode H8S/2326C F-ZTAT. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. Boot mode H8S/2329 F-ZTAT, H8S/2326C FZTAT. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user boot modes. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. Description amended from 10th line ROMless mask versions only used modes This means that mode pins must select these modes. However, note that only mode ROMless version. H8S/2329 F-ZTAT only used modes This means that mode pins must select these modes. H8S/2326C F-ZTAT only used modes This means that mode pins must select these modes.
Rev. 4.0, 03/03 page xliv
Item 3.2.3 System Control Register (SYSCR2) (F-ZTAT Version Only)
Page
Revisions (See Manual Details) Description note amended Note: H8S/2329 F-ZTAT H8S/2326C F-ZTAT. 3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2 case H8S/2329 FZTAT, H8S/2328 F-ZTAT, H8S/2326 F-ZTAT: FCCS, FPCS, FECS, FKEY, FMATS, FTDAR case H8S/2326C F-ZTAT). details, section ROM.
FLSHE Description H8S/2329F-ZTAT, H8S/2328F-ZTAT, H8S/2326F-ZTAT
Flash control registers selected addresses H'FFFFC8 H'FFFFCB (Initial value)
H8S/2326C F-ZTAT Flash control registers selected addresses H'FFFFC4 H'FFFFCF Flash control registers selected addresses H'FFFFC8 H'FFFFCB Flash control registers selected addresses H'FFFFC4 H'FFFFCF H8S/2329F-ZTAT, H8S/2328F-ZTAT, H8S/2326F-ZTAT
H8S/2326C F-ZTAT
0-Reserved: H8S/2329F-ZTAT H8S/2326C FZTAT, this reserved should only written with 3.3.1 Mode (H8S/2326C FZTAT Only) Title amended description replaced This flash memory user boot mode. section ROM, details. This same advanced single chip mode, except when erasing reprogramming flash memory. Title amended Title amended
3.3.2 Mode (H8S/2329F-ZTAT H8S/2326C F-ZTAT Only) 3.3.3 Mode (H8S/2329F-ZTAT H8S/2326C F-ZTAT Only)
Rev. 4.0, 03/03 page xliv
Item Functions Each Operating Mode Table Functions Each Mode
Page
Revisions (See Manual Details) Table notes amended
Port Mode
Port Port Port Port Port Port
Memory Each Operating Mode Figure 3-5(a) H8S/2326C F-ZTAT Address Each Operating Mode Figure 3-5(b) H8S/2326C F-ZTAT Address Each Operating Mode 4.1.3 Exception Vector Table
Valid only H8S/2329 F-ZTAT H8S/2326C FZTAT. Valid only H8S/2326C F-ZTAT.
Newly added
Newly added
Description line amended, note added this case, clearing BCRL enables 256-kbyte (128 kbytes/384 kbytes/512 kbytes)* area comprising addresses H'000000 H'03FFFF H'01FFFF/H'05FFFF/H'07FFFF) used. Note: amount on-chip differs depending product.
6.2.5 Control Register (BCRL)
table note amended 5-External Address Enable (EAE)
Description H8S/2329, H8S/2328, H8S/2326, H8S/2326C On-chip
Note: Addresses H'010000 H'05FFFF H8S/2329. Addresses H'010000 H'07FFFF H8S/2326 H8S/2326C.
Rev. 4.0, 03/03 page xliv
Item 8.3.7 Block Transfer Mode
Page
Revisions (See Manual Details) Description amended block transfer mode, operation transfers block area. Either transfer source transfer destination designated block area.
13.2.3 Reset Control/Status Register (RSTCSR)
Description amended 7-Watchdog Timer Overflow Flag (WOVF) [Clearing Condition] amended (Before) TCSR (After) RSTCSR
5-Reserved: This should written with 13.3.4 Timing Watchdog Timer Overflow Flag (WOVF) Setting Note added Note: WDTOVF function cannot used FZTAT versions. Description 11th line amended (Before) TCSR (After) 15.2.2 Serial Status Register (SSR) RSTCSR
13.5.5 Internal Reset Watchdog Timer Mode
table amended Signal Status (ERS)
Description Indicates data received normally with error signal [Clearing conditions] (Initial value)
Upon reset, standby mode module stop mode When written after reading Indicates error signal sent showing detection parity error receiving side [Setting condition] When level error signal sampled
TEND Description Indicates transfer progress [Clearing conditions] When written TDRE after reading TDRE When DMAC* activated interrupt writes data Indicates transfer complete [Setting conditions] (Initial value)
Upon reset, standby mode module stop mode
Rev. 4.0, 03/03 page xliv
Item 15.2.4 Serial Control Register (SCR)
Page
Revisions (See Manual Details) table amended Bits 0-Clock Enable (CKE1, CKE0)
SCMR SMIF
18.1 Overview
Description amended H8S/2329 H8S/2324S have kbytes on-chip highspeed static RAM, H8S/2326C kbytes, H8S/2328, H8S/2327, H8S/2326, H8S/2323, H8S/2322R have kbytes, H8S/2321 H8S/2320 have kbytes.
19.2.2 Control Register (BCRL)
5-External Address Enable (EAE)
Description H8S/2329, H8S/2328, H8S/2326, H8S/2326C On-chip
Note: Addresses H'010000 H'05FFFF H8S/2329. Addresses H'010000 H'07FFFF H8S/2326 H8S/2326C. 19.3 Operation Table 19-2 Operating Modes (H8S/2328 F-ZTAT, H8S/2326 F-ZTAT) Item Mode deleted from table
Rev. 4.0, 03/03 page xiii xliv
Item 19.3 Operation Table 19-3 Operating Modes (H8S/2329 F-ZTAT, H8S/2326C F-ZTAT, Mask Version)
Page
Revisions (See Manual Details) Item Mode deleted from table notes amended
Mode On-Chip
Enabled (256 kbytes)*1*2 Enabled kbytes) Enabled (256 kbytes) *1*2 Enabled kbytes)
Notes: amount on-chip differs depending product. Refer section 3.5, Memory Each Operation Mode, details. User boot mode H8S/2326C F-ZTAT. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. Boot mode H8S/2329 F-ZTAT, H8S/2326C FZTAT. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user boot modes. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329C F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. 19.5.5 System Control Register (SYSCR2) tale amended
Initial value
Description amended Bits 1-Reserved: These bits cannot modified always read 0-Reserved: This should written with
19.7.2 Program-Verify Mode Figure 19-14 Program/ProgramVerify Flowchart
(Preliminary) deleted from figure title
Rev. 4.0, 03/03 page xliv
Item 19.7.4 Erase-Verify Mode Figure 19-15 Erase/Erase-Verify Flowchart 19.16.2 Program-Verify Mode Figure 19-41 Program/ProgramVerify Flowchart 19.16.4 Erase-Verify Mode Figure 19-42 Erase/Erase-Verify Flowchart 19.21 Flash Memory Programming Erasing Precautions Figure 19-56 Power On/Off Timing (Boot Mode) Figure 19-57 Power On/Off Timing (User Program Mode)
Page
Revisions (See Manual Details) (Preliminary) deleted from figure title
(Preliminary) deleted from figure title
(Preliminary) deleted from figure title
Figure amended (Before)Wait time: 10µs (After) Wait time: 100µs
cleared
Figure amended
cleared
Figure 19-58 Mode Transition Timing
Figure amended
cleared
19.25.2 Program-Verify Mode Figure 19-71 Program/ProgramVerify Flowchart 19.25.4 Erase-Verify Mode Figure 19-72 Erase/Erase-Verify Flowchart 19.30 Flash Memory Programming Erasing Precautions Figure 19-86 Power On/Off Timing (Boot Mode) Figure 19-87 Power On/Off Timing (User Program Mode)
(Preliminary) deleted from figure title
Figure amended (Before) Wait time: 10µs (After) Wait time: 100µs
cleared
Figure amended
cleared
Figure 19-88 Mode Transition Timing
Figure amended
cleared
Rev. 4.0, 03/03 page xliv
Item
Page
Revisions (See Manual Details) Newly added
19.31 Overview Flash Memory (H8S/2326C F-ZTAT) 19.38.3 Procedure Program Storable Area Programming Data 20.3.2 External Clock Input Table 20-4 External Clock Input Conditions 21.1 Overview Table 21-1 Operating Modes
Condition amended (Before) (After) Table amended
Operating Mode High speed mode Mediumspeed mode High speed Registers Function High speed Modules Registers Function
Medium Function speed
High/ Function medium speed
22.1.4 Conversion Characteristics Table 22-10 Conversion Characteristics 22.2 Electrical Characteristics F-ZTAT (H8S/2329F-ZTAT, H8S/2328F-ZTAT, H8S/2328B FZTAT, H8S/2326F-ZTAT) 22.2.1 Absolute Maximum Ratings Table 22-12 Absolute Maximum Ratings
1036
Quantization error conditions amended
Condition Item Quantization error -0.5 Condition -0.5 Unit
1038
Title amended
Table notes amended (Before) Input voltage (FWE)*2 (After) Input voltage (FWE*2, EMLE*3)
Notes:*2 applies H8S/2328 F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT. EMLE applies H8S/2329 F-ZTAT, H8S/2329B F-ZTAT, H8S/2329E F-ZTAT.
Rev. 4.0, 03/03 page xliv
Item 22.2.2 Characteristics Table 22-13 Characteristics
Page 1039, 1040
Revisions (See Manual Details) Table amended note added
Item Input high voltage Input voltage Input leakage current
4-5, 56*;, NMI, MD0,, FWE* EMLE* 4-5, 56*;, MD0, FWE* EMLE* 56*;, NMI,
MD0, FWE* EMLE*
Note EMLE applies H8S/2329F-ZTAT H8S/2329B F-ZTAT, H8S/2329E F-ZTAT. 22.2.4 Conversion Characteristics Table 22-20 Conversion Characteristics 22.3 Electrical Characteristics H8S/2326C F-ZTAT Planning) 22.3.7 Usage Note (internal voltage step down H8S/2326C F-ZTAT) Instruction Table Instruction Instruction Codes Table Instruction Codes 1052 1064 1048 Quantization error conditions amended
Condition Item Quantization error -0.5 Unit
Newly added
1069, 1088 1097, 1102, 1103
Note deleted from S
Note deleted from S
Number State Required 1116, Instruction Execution 1120, 1121 Table Number State Required Instruction Execution State during Instruction Execution Table Instruction Execution Cycles 1129, 1130, 1134,
Note deleted from S
Note deleted
Rev. 4.0, 03/03 page xvii xliv
Item List Registers (Address Order)
Page 1144
Revisions (See Manual Details) Table amended
Data Register Address H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 H'FEDB Name ABWCR ASTCR WCRH WCRL BCRH BCRL ABW7 AST7 ICIS1 BRLE RFSHE ABW6 AST6 ICIS0 ABW5 AST5 ABW4 AST4 ABW3 AST3 ABW2 AST2 ABW1 AST1 ABW0 AST0 Module Name controller Width bits
BRSTRM BRSTS1 BRSTS0 MXC1 CMIE
RMTS2 RMTS1 RMTS0 MXC0 CKS2 WDBE WAITE RLW1 CKS1 RLW0 CKS0
BREQOE RCDM RMODE
DRAMCR RTCNT
RTCOR RAMER RAMS RAM2 RAM1 RAM0 Flash memory bits
1145
Table amended
Data Register Address H'FF06 Name FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Module Name Short address mode FAE1 FAE0 DTA1 DTA0 Full address mode Width
DMABCRH FAE1
1148
Table amended
Data Register Address H'FF98 H'FF99 Name ADCSR ADCR TRGS1 ADIE TRGS0 ADST SCAN CKS1 Module Name converter Width bits
1149 1151
Item Flash memory (H8S/2326C F-ZTAT) newly added table Notes added Note: Applies H8S/2326C F-ZTAT.
Rev. 4.0, 03/03 page xviii xliv
Item
Page
Revisions (See Manual Details) Table amended
Module DMAC0 Register Memory address register address register Transfer count register Memory address register address register Transfer count register DMAC1*7 Memory address register address register Transfer count register Memory address register address register Transfer count register Both DMAC channels*7 write enable register terminal control register control register control register control register control register band control register Module stop control register
List Registers Module) 1153
1159
Added item Flash memory
Module Flash memory Register Flash memory control register Flash memory control register Erase block register Erase block register Flash code control status register Abbreviation
FLMCR1* FLMCR2* EBR1* EBR2*
Initial Value Address*
H'00/H'80 H'FFC8 H'00 H'FFC9 H'00* H'FFCA
H'00* H'80 H'00 H'00 H'00 H'00 H'00 H'00
H'FFCB H'FFC4*13 H'FFC5*13
FCCS* Flash program code select register FPCS* Flash erase code select register FECS*
Flash code register Flash select register Flash transfer destination address register emulation register System control register
FKEY* FMATS* FTDAR*
H'FFC6*13 H'00/H'AA* H'FFC8*13 H'FFC9*13 H'FFCA*13 H'FEDB H'FF42
RAMER*24 SYSCR2*
Rev. 4.0, 03/03 page xliv
Item
Page
Revisions (See Manual Details) Notes amended Notes: FLMCR1, FLMCR2, EBR1, EBR2 8-bit registers. Only byte access used these registers, with access requiring states. (Applies H8S/2329F-ZTAT, H8S/2328FZTAT, H8S/2326F-ZTAT.) Value bits Applies H8S/2326C F-ZTAT only. accessed when on-chip flash memory valid. user mode user program mode, initial value when wake H'00. initial value depends mode. Value bits Valid only F-ZTAT
List Registers Module) 1162
Functions
1194
Figure note amended BCRL H'FED5 Control Register
External Addresses H'010000 H'03FFFF Enable H8S/2329, H8S/2328, H8S/2326, H8S/2326C, addresses H'010000 H'03FFFF*2 on-chip H8S/2327, addresses H'010000 H'01FFFF on-chip ROM, addresses H'020000 H'03FFFF reserved area*1 H8S/2323, addresses H'010000 H'03FFFF reserved area*1
Note H'010000 H'03FFFF H8S/2328, H'010000 H'05FFFF H8S/2329, H'010000 H'07FFFF H8S/2326 H8S/2326C. 1198 Added Emulation Register (Valid only F-ZTAT) 1220 Figure amended
System Clock Select SCK2 SCK1 SCK0
Rev. 4.0, 03/03 page xliv
Item Functions
Page 1208, 1209
Revisions (See Manual Details) Figure amended DMACR0A DMACR1B H'FF02 H'FF05 (Not supported H8S/2321): DMAC DMACRB Full address mode, DMACR Short address mode
Data Transfer Factor
Block Transfer Mode
Activated channel transmission data-empty interrupt Activated channel reception data-full interrupt Activated channel transmission data-empty interrupt Activated channel reception data-full interrupt
1222
Figure amended SYSCR2 H'FF42(Valid only F-ZTAT versions):
FLSHE Initial value Read/Write (R/W)
H8S/2329 H8S/2326C only this R/W, should only written with Flash Memory Control Register Enable H8S/2329F-ZTAT, H8S/2328F-ZTAT, H8S/2326F-ZTAT Flash control registers selected addresses H'FFFFC8 H'FFFFCB H8S/2326C F-ZTAT Flash control registers selected addresses H'FFFFC4 H'FFFFCF H8S/2329F-ZTAT, H8S/2328F-ZTAT, H8S/2326F-ZTAT Flash control registers selected addresses H'FFFFC8 H'FFFFCB H8S/2326C F-ZTAT Flash control registers selected addresses H'FFFFC4 H'FFFFCF
1245
Figure amended SCR0 H'FF7A Smart Card Interface
1254
Figure amended SCR1 H'FF82 Smart Card Interface
Rev. 4.0, 03/03 page xliv
Item Functions
Page 1263
Revisions (See Manual Details) Figure amended SCR2 H'FF8A Smart Card Interface
1277
Figure amended TCSR H'FFBC H'FFBC
Initial value Read/Write*1 R/(W)*2 WT/IT CKS2 CKS1 CKS0
Timer Mode Select Interval timer mode: Sends interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates WDTOVF signal*1 when TCNT overflows*2
Notes: WDTOVF function available F-ZTAT versions. details case where TCNT overflows watchdog timer mode, section 13.2.3, Reset Control/Status Register (RSTCSR). Overflow Flag [Clearing condition] When written after reading [Setting condition] When TCNT overflows from H'FF H'00 interval timer mode
Notes: method writing TCSR different from that general registers prevent accidental overwriting. details, section 13.2.4, Notes Register Access. only written with flag clearing.
1278
Figure amended RSTCSR H'FFBE H'FFBF (Before) This cannot modified This should written with (After) [Clearing condition] (Before) When written WOVF after reading WOVF (After) When written WOVF after reading RSTCSR when WOVF
1286
Figure newly added H'FFC4 FCCS: FLASH (Valid only H8S/2326C F-ZTAT)
1287
Figures newly added H'FFC5 FPCS: FLASH (Valid only H8S/2326C F-ZTAT) H'FFC6 FECS: FLASH (Valid only H8S/2326C F-ZTAT)
1288
Figures newly added H'FFC8 FKEY: FLASH (Valid only H8S/2326C F-ZTAT) H'FFC9 FMATS: FLASH (Valid only H8S/2326C FZTAT)
Rev. 4.0, 03/03 page xxii xliv
Item Functions
Page 1289
Revisions (See Manual Details) Figure newly added H'FFCA FTDAR: FLASH (Valid only H8S/2326C FZTAT)
Appendix Product Lineup
1356
HD64F2328B, HD64F2326C lineup added note amended
Product Type H8S/2328 Mask version F-ZTAT Model HD6432328 HD64F2328 Marking HD6432328TE HD6432328F HD64F2328VTE Package (Hitachi Package Code) 120-pin TQFP (TFP-120) 128-pin (FP-128B) 120-pin TQFP (TFP-120)
HD64F2328VF 128-pin (FP-128B) HD64F2328B* HD64F2328BVTE 120-pin TQFP (TFP-120) HD64F2328BVF H8S/2327 H8S/2326 Mask version F-ZTAT HD6432327 HD64F2326 HD64F2326C HD6432327TE HD6432327F HD64F2326VTE HD64F2326VF
H8S/2326C* F-ZTAT
128-pin (FP-128B) 120-pin TQFP (TFP-120) 128-pin (FP-128B) 120-pin TQFP (TFP-120) 128-pin (FP-128B) 120-pin TQFP (TFP-120) 128-pin (FP-128B)
HD64F2326CVTE HD64F2326CVF
Note: planning
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Contents
Section Overview
Overview Block Diagram. Description 1.3.1 Arrangement. 1.3.2 Functions Each Operating Mode. 1.3.3 Functions.
Section
Overview 2.1.1 Features 2.1.2 Differences between H8S/2600 H8S/2000 CPU. 2.1.3 Differences from H8/300 2.1.4 Differences from H8/300H Operating Modes Address Space Register Configuration. 2.4.1 Overview 2.4.2 General Registers 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats 2.5.1 General Register Data Formats. 2.5.2 Memory Data Formats. Instruction Set. 2.6.1 Overview 2.6.2 Instructions Addressing Modes. 2.6.3 Table Instructions Classified Function 2.6.4 Basic Instruction Formats. Addressing Modes Effective Address Calculation. 2.7.1 Addressing Mode 2.7.2 Effective Address Calculation Processing States 2.8.1 Overview 2.8.2 Reset State 2.8.3 Exception-Handling State. 2.8.4 Program Execution State 2.8.5 Bus-Released State 2.8.6 Power-Down State.
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Basic Timing 2.9.1 Overview 2.9.2 On-Chip Memory (ROM, RAM). 2.9.3 On-Chip Supporting Module Access Timing 2.9.4 External Address Space Access Timing 2.10 Usage Note 2.10.1 Instruction
Section Operating Modes
Overview 3.1.1 Operating Mode Selection (H8S/2328 F-ZTAT, H8S/2326 F-ZTAT). 3.1.2 Operating Mode Selection (Mask ROMless Versions, H8S/2329 F-ZTAT, H8S/2326C F-ZTAT) 3.1.3 Register Configuration Register Descriptions. 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR). 3.2.3 System Control Register (SYSCR2) (F-ZTAT Version Only) Operating Mode Descriptions. 3.3.1 Mode (H8S/2326C F-ZTAT Only). 3.3.2 Mode (H8S/2329 F-ZTAT H8S/2326C F-ZTAT Only) 3.3.3 Mode (H8S/2329 F-ZTAT H8S/2326C F-ZTAT Only) 3.3.4 Mode (Expanded Mode with On-Chip Disabled). 3.3.5 Mode (Expanded Mode with On-Chip Disabled). 3.3.6 Mode (Expanded Mode with On-Chip Enabled) 3.3.7 Mode (Single-Chip Mode) 3.3.8 Modes (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only) 3.3.9 Mode (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only). 3.3.10 Mode (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only). 3.3.11 Modes (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only) 3.3.12 Mode (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only). 3.3.13 Mode (H8S/2328 F-ZTAT H8S/2326 F-ZTAT Only). Functions Each Operating Mode. Memory Each Operating Mode.
Section Exception Handling
Overview 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table. Reset 4.2.1 Overview 4.2.2 Reset Sequence.
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4.2.3 Interrupts after Reset 4.2.4 State On-Chip Supporting Modules after Reset Release Traces Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack.
Section Interrupt Controller
Overview 5.1.1 Features 5.1.2 Block Diagram 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR). 5.2.2 Interrupt Priority Registers (IPRA IPRK) 5.2.3 Enable Register (IER). 5.2.4 Sense Control Registers (ISCRH, ISCRL). 5.2.5 Status Register (ISR) Interrupt Sources 5.3.1 External Interrupts. 5.3.2 Internal Interrupts 5.3.3 Interrupt Exception Vector Table. Interrupt Operation 5.4.1 Interrupt Control Modes Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Control Mode 5.4.4 Interrupt Exception Handling Sequence 5.4.5 Interrupt Response Times. Usage Notes. 5.5.1 Contention between Interrupt Generation Disabling. 5.5.2 Instructions that Disable Interrupts. 5.5.3 Times when Interrupts Disabled 5.5.4 Interrupts during Execution EEPMOV Instruction DMAC Activation Interrupt. 5.6.1 Overview 5.6.2 Block Diagram 5.6.3 Operation.
Section Controller
Overview 6.1.1 Features
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6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions. 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR) 6.2.3 Wait Control Registers (WCRH, WCRL) 6.2.4 Control Register (BCRH) 6.2.5 Control Register (BCRL) 6.2.6 Memory Control Register (MCR) 6.2.7 DRAM Control Register (DRAMCR) 6.2.8 Refresh Timer Counter (RTCNT) 6.2.9 Refresh Time Constant Register (RTCOR) Overview Control. 6.3.1 Area Partitioning 6.3.2 Specifications 6.3.3 Memory Interfaces. 6.3.4 Advanced Mode 6.3.5 Chip Select Signals. Basic Interface. 6.4.1 Overview 6.4.2 Data Size Data Alignment 6.4.3 Valid Strobes 6.4.4 Basic Timing 6.4.5 Wait Control. DRAM Interface (Not supported H8S/2321). 6.5.1 Overview 6.5.2 Setting DRAM Space 6.5.3 Address Multiplexing 6.5.4 Data 6.5.5 Pins Used DRAM Interface 6.5.6 Basic Timing 6.5.7 Precharge State Control. 6.5.8 Wait Control. 6.5.9 Byte Access Control 6.5.10 Burst Operation 6.5.11 Refresh Control DMAC Single Address Mode DRAM Interface (Not supported H8S/2321). 6.6.1 When 6.6.2 When Burst Interface 6.7.1 Overview 6.7.2 Basic Timing
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6.7.3 Wait Control. Idle Cycle 6.8.1 Operation. 6.8.2 States Idle Cycle. Write Data Buffer Function 6.10 Release 6.10.1 Overview 6.10.2 Operation. 6.10.3 States External Released State 6.10.4 Transition Timing. 6.10.5 Usage Note 6.11 Arbitration 6.11.1 Overview 6.11.2 Operation. 6.11.3 Transfer Timing. 6.11.4 External Release Usage Note 6.12 Resets Controller.
Section Controller (Not Supported H8S/2321).
Overview 7.1.1 Features 7.1.2 Block Diagram 7.1.3 Overview Functions 7.1.4 Configuration 7.1.5 Register Configuration Register Descriptions (Short Address Mode) 7.2.1 Memory Address Registers (MAR) 7.2.2 Address Register (IOAR) 7.2.3 Execute Transfer Count Register (ETCR) 7.2.4 Control Register (DMACR) 7.2.5 Band Control Register (DMABCR) Register Descriptions (Full Address Mode). 7.3.1 Memory Address Register (MAR) 7.3.2 Address Register (IOAR) 7.3.3 Execute Transfer Count Register (ETCR) 7.3.4 Control Register (DMACR) 7.3.5 Band Control Register (DMABCR) Register Descriptions 7.4.1 Write Enable Register (DMAWER). 7.4.2 Terminal Control Register (DMATCR) 7.4.3 Module Stop Control Register (MSTPCR) Operation. 7.5.1 Transfer Modes
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Sequential Mode. Idle Mode Repeat Mode Single Address Mode Normal Mode Block Transfer Mode DMAC Activation Sources. Basic DMAC Cycles DMAC Cycles (Dual Address Mode) DMAC Cycles (Single Address Mode) Write Data Buffer Function. DMAC Multi-Channel Operation. Relation Between DMAC External Requests, Refresh Cycles, 7.5.15 Interrupts DMAC 7.5.16 Forced Termination DMAC Operation 7.5.17 Clearing Full Address Mode. Interrupts Usage Notes.
7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14
Section Data Transfer Controller
Overview 8.1.1 Features 8.1.2 Block Diagram 8.1.3 Register Configuration Register Descriptions. 8.2.1 Mode Register (MRA). 8.2.2 Mode Register (MRB) 8.2.3 Source Address Register (SAR) 8.2.4 Destination Address Register (DAR) 8.2.5 Transfer Count Register (CRA) 8.2.6 Transfer Count Register (CRB) 8.2.7 Enable Registers (DTCER) 8.2.8 Vector Register (DTVECR) 8.2.9 Module Stop Control Register (MSTPCR) Operation. 8.3.1 Overview 8.3.2 Activation Sources. 8.3.3 Vector Table. 8.3.4 Location Register Information Address Space. 8.3.5 Normal Mode 8.3.6 Repeat Mode 8.3.7 Block Transfer Mode
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8.3.8 Chain Transfer. 8.3.9 Operation Timing 8.3.10 Number Execution States 8.3.11 Procedures Using 8.3.12 Examples DTC. Interrupts Usage Notes.
Section Ports
Overview Port 9.2.1 Overview 9.2.2 Register Configuration 9.2.3 Functions. Port 9.3.1 Overview 9.3.2 Register Configuration 9.3.3 Functions. Port 9.4.1 Overview 9.4.2 Register Configuration 9.4.3 Functions. Port 9.5.1 Overview 9.5.2 Register Configuration 9.5.3 Functions. Port 9.6.1 Overview 9.6.2 Register Configuration 9.6.3 Functions. Port 9.7.1 Overview 9.7.2 Register Configuration 9.7.3 Functions. Port 9.8.1 Overview 9.8.2 Register Configuration 9.8.3 Functions. 9.8.4 Input Pull-Up Function Port 9.9.1 Overview 9.9.2 Register Configuration 9.9.3 Functions.
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9.9.4 Input Pull-Up Function 9.10 Port 9.10.1 Overview 9.10.2 Register Configuration 9.10.3 Functions. 9.10.4 Input Pull-Up Function 9.11 Port 9.11.1 Overview 9.11.2 Register Configuration 9.11.3 Functions. 9.11.4 Input Pull-Up Function 9.12 Port 9.12.1 Overview 9.12.2 Register Configuration 9.12.3 Functions. 9.12.4 Input Pull-Up Function 9.13 Port 9.13.1 Overview 9.13.2 Register Configuration 9.13.3 Functions. 9.14 Port 9.14.1 Overview 9.14.2 Register Configuration 9.14.3 Functions.
Section 16-Bit Timer Pulse Unit (TPU) 10.1 Overview 10.1.1 Features 10.1.2 Block Diagram 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Timer Control Registers (TCR). 10.2.2 Timer Mode Registers (TMDR) 10.2.3 Timer Control Registers (TIOR) 10.2.4 Timer Interrupt Enable Registers (TIER) 10.2.5 Timer Status Registers (TSR). 10.2.6 Timer Counters (TCNT). 10.2.7 Timer General Registers (TGR) 10.2.8 Timer Start Register (TSTR) 10.2.9 Timer Synchro Register (TSYR) 10.2.10 Module Stop Control Register (MSTPCR) 10.3 Interface Master
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10.4
10.5
10.6
10.7
10.3.1 16-Bit Registers. 10.3.2 8-Bit Registers. Operation. 10.4.1 Overview 10.4.2 Basic Functions 10.4.3 Synchronous Operation 10.4.4 Buffer Operation. 10.4.5 Cascaded Operation. 10.4.6 Modes 10.4.7 Phase Counting Mode. Interrupts 10.5.1 Interrupt Sources Priorities 10.5.2 DTC/DMAC* Activation 10.5.3 Converter Activation Operation Timing 10.6.1 Input/Output Timing. 10.6.2 Interrupt Signal Timing Usage Notes.
Section Programmable Pulse Generator (PPG)
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Configuration 11.1.4 Registers 11.2 Register Descriptions. 11.2.1 Next Data Enable Registers (NDERH, NDERL) 11.2.2 Output Data Registers (PODRH, PODRL). 11.2.3 Next Data Registers (NDRH, NDRL) 11.2.4 Notes Access 11.2.5 Output Control Register (PCR) 11.2.6 Output Mode Register (PMR) 11.2.7 Port Data Direction Register (P1DDR) 11.2.8 Port Data Direction Register (P2DDR) 11.2.9 Module Stop Control Register (MSTPCR) 11.3 Operation. 11.3.1 Overview 11.3.2 Output Timing 11.3.3 Normal Pulse Output 11.3.4 Non-Overlapping Pulse Output 11.3.5 Inverted Pulse Output 11.3.6 Pulse Output Triggered Input Capture. 11.4 Usage Notes.
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11.4.1 Operation Pulse Output Pins 11.4.2 Note Non-Overlapping Output
Section 8-Bit Timers
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counters (TCNT0, TCNT1). 12.2.2 Time Constant Registers (TCORA0, TCORA1) 12.2.3 Time Constant Registers (TCORB0, TCORB1) 12.2.4 Time Control Registers (TCR0, TCR1). 12.2.5 Timer Control/Status Registers (TCSR0, TCSR1) 12.2.6 Module Stop Control Register (MSTPCR) 12.3 Operation. 12.3.1 TCNT Incrementation Timing. 12.3.2 Compare Match Timing. 12.3.3 Timing TCNT External Reset 12.3.4 Timing Overflow Flag (OVF) Setting 12.3.5 Operation with Cascaded Connection. 12.4 Interrupts 12.4.1 Interrupt Sources Activation 12.4.2 Converter Activation 12.5 Sample Application 12.6 Usage Notes. 12.6.1 Contention between TCNT Write Clear 12.6.2 Contention between TCNT Write Increment. 12.6.3 Contention between TCOR Write Compare Match 12.6.4 Contention between Compare Matches 12.6.5 Switching Internal Clocks TCNT Operation 12.6.6 Interrupts Module Stop Mode.
Section Watchdog Timer
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Timer Counter (TCNT) 13.2.2 Timer Control/Status Register (TCSR)
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13.2.3 Reset Control/Status Register (RSTCSR). 13.2.4 Notes Register Access 13.3 Operation. 13.3.1 Operation Watchdog Timer Mode. 13.3.2 Operation Interval Timer Mode. 13.3.3 Timing Overflow Flag (OVF) Setting 13.3.4 Timing Watchdog Timer Overflow Flag (WOVF) Setting 13.4 Interrupts 13.5 Usage Notes. 13.5.1 Contention between Timer Counter (TCNT) Write Increment. 13.5.2 Changing Value CKS2 CKS0 13.5.3 Switching between Watchdog Timer Mode Interval Timer Mode. 13.5.4 System Reset WDTOVF Signal. 13.5.5 Internal Reset Watchdog Timer Mode
Section Serial Communication Interface (SCI)
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Receive Shift Register (RSR) 14.2.2 Receive Data Register (RDR). 14.2.3 Transmit Shift Register (TSR). 14.2.4 Transmit Data Register (TDR) 14.2.5 Serial Mode Register (SMR) 14.2.6 Serial Control Register (SCR) 14.2.7 Serial Status Register (SSR) 14.2.8 Rate Register (BRR). 14.2.9 Smart Card Mode Register (SCMR). 14.2.10 Module Stop Control Register (MSTPCR) 14.3 Operation. 14.3.1 Overview 14.3.2 Operation Asynchronous Mode. 14.3.3 Multiprocessor Communication Function 14.3.4 Operation Synchronous Mode 14.4 Interrupts 14.5 Usage Notes.
Section Smart Card Interface
15.1 Overview 15.1.1 Features
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15.1.2 Block Diagram 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Smart Card Mode Register (SCMR). 15.2.2 Serial Status Register (SSR) 15.2.3 Serial Mode Register (SMR) 15.2.4 Serial Control Register (SCR) 15.3 Operation. 15.3.1 Overview 15.3.2 Connections. 15.3.3 Data Format. 15.3.4 Register Settings. 15.3.5 Clock 15.3.6 Data Transfer Operations 15.3.7 Operation Mode. 15.3.8 Operation Block Transfer Mode. 15.4 Usage Notes.
Section Converter Analog Input Channel Version)
16.1 Overview 16.1.1 Features 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Registers (ADDRA ADDRD) 16.2.2 Control/Status Register (ADCSR) 16.2.3 Control Register (ADCR) 16.2.4 Module Stop Control Register (MSTPCR) 16.3 Interface Master 16.4 Operation. 16.4.1 Single Mode (SCAN 16.4.2 Scan Mode (SCAN 16.4.3 Input Sampling Conversion Time 16.4.4 External Trigger Input Timing 16.5 Interrupts 16.6 Usage Notes.
Section Converter 17.1 Overview 17.1.1 Features 17.1.2 Block Diagram
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17.1.3 Configuration 17.1.4 Register Configuration 17.2 Register Descriptions. 17.2.1 Data Registers (DADR0, DADR1). 17.2.2 Control Registers (DACR01). 17.2.3 Module Stop Control Register (MSTPCR) 17.3 Operation.
Section 18.1 Overview 18.1.1 Block Diagram 18.1.2 Register Configuration 18.2 Register Descriptions. 18.2.1 System Control Register (SYSCR). 18.3 Operation. 18.4 Usage Note Section 19.1 Overview 19.1.1 Block Diagram 19.1.2 Register Configuration 19.2 Register Descriptions. 19.2.1 Mode Control Register (MDCR). 19.2.2 Control Register (BCRL) 19.3 Operation. 19.4 Overview Flash Memory (H8S/2329 F-ZTAT). 19.4.1 Features 19.4.2 Overview 19.4.3 Flash Memory Operating Modes 19.4.4 On-Board Programming Modes 19.4.5 Flash Memory Emulation 19.4.6 Differences between Boot Mode User Program Mode 19.4.7 Block Configuration 19.4.8 Configuration 19.4.9 Register Configuration 19.5 Register Descriptions. 19.5.1 Flash Memory Control Register (FLMCR1) 19.5.2 Flash Memory Control Register (FLMCR2) 19.5.3 Erase Block Register (EBR1). 19.5.4 Erase Block Registers (EBR2) 19.5.5 System Control Register (SYSCR2). 19.5.6 Emulation Register (RAMER). 19.6 On-Board Programming Modes
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19.7
19.8
19.9
19.10 19.11
19.12 19.13
19.14
19.6.1 Boot Mode. 19.6.2 User Program Mode Programming/Erasing Flash Memory. 19.7.1 Program Mode. 19.7.2 Program-Verify Mode 19.7.3 Erase Mode. 19.7.4 Erase-Verify Mode Flash Memory Protection 19.8.1 Hardware Protection. 19.8.2 Software Protection 19.8.3 Error Protection. Flash Memory Emulation 19.9.1 Emulation 19.9.2 Overlap Interrupt Handling when Programming/Erasing Flash Memory Flash Memory PROM Mode 19.11.1 PROM Mode Setting. 19.11.2 Socket Adapters Memory 19.11.3 PROM Mode Operation 19.11.4 Memory Read Mode. 19.11.5 Auto-Program Mode 19.11.6 Auto-Erase Mode 19.11.7 Status Read Mode 19.11.8 Status Polling 19.11.9 PROM Mode Transition Time 19.11.10Notes Memory Programming Flash Memory Programming Erasing Precautions. Overview Flash Memory (H8S/2328 F-ZTAT). 19.13.1 Features 19.13.2 Overview 19.13.3 Flash Memory Operating Modes 19.13.4 On-Board Programming Modes 19.13.5 Flash Memory Emulation 19.13.6 Differences between Boot Mode User Program Mode 19.13.7 Block Configuration 19.13.8 Configuration 19.13.9 Register Configuration Register Descriptions. 19.14.1 Flash Memory Control Register (FLMCR1) 19.14.2 Flash Memory Control Register (FLMCR2) 19.14.3 Erase Block Register (EBR1). 19.14.4 Erase Block Registers (EBR2) 19.14.5 System Control Register (SYSCR2).
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19.14.6 Emulation Register (RAMER). 19.15 On-Board Programming Modes 19.15.1 Boot Mode. 19.15.2 User Program Mode 19.16 Programming/Erasing Flash Memory. 19.16.1 Program Mode. 19.16.2 Program-Verify Mode 19.16.3 Erase Mode. 19.16.4 Erase-Verify Mode 19.17 Flash Memory Protection 19.17.1 Hardware Protection. 19.17.2 Software Protection 19.17.3 Error Protection. 19.18 Flash Memory Emulation 19.18.1 Emulation 19.18.2 Overlap 19.19 Interrupt Handling when Programming/Erasing Flash Memory 19.20 Flash Memory PROM Mode 19.20.1 PROM Mode Setting. 19.20.2 Socket Adapters Memory 19.20.3 PROM Mode Operation 19.20.4 Memory Read Mode. 19.20.5 Auto-Program Mode 19.20.6 Auto-Erase Mode 19.20.7 Status Read Mode 19.20.8 Status Polling 19.20.9 PROM Mode Transition Time 19.20.10Notes Memory Programming 19.21 Flash Memory Programming Erasing Precautions. 19.22 Overview Flash Memory (H8S/2326 F-ZTAT). 19.22.1 Features 19.22.2 Overview 19.22.3 Flash Memory Operating Modes 19.22.4 On-Board Programming Modes 19.22.5 Flash Memory Emulation 19.22.6 Differences between Boot Mode User Program Mode 19.22.7 Block Configuration 19.22.8 Configuration 19.22.9 Register Configuration 19.23 Register Descriptions. 19.23.1 Flash Memory Control Register (FLMCR1) 19.23.2 Flash Memory Control Register (FLMCR2) 19.23.3 Erase Block Register (EBR1).
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19.24
19.25
19.26
19.27
19.28 19.29
19.30 19.31
19.23.4 Erase Block Registers (EBR2) 19.23.5 System Control Register (SYSCR2). 19.23.6 Emulation Register (RAMER). On-Board Programming Modes 19.24.1 Boot Mode. 19.24.2 User Program Mode Programming/Erasing Flash Memory. 19.25.1 Program Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 19.25.2 Program-Verify Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 19.25.3 Erase Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 19.25.4 Erase-Verify Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). Flash Memory Protection 19.26.1 Hardware Protection. 19.26.2 Software Protection 19.26.3 Error Protection. Flash Memory Emulation 19.27.1 Emulation 19.27.2 Overlap Interrupt Handling when Programming/Erasing Flash Memory Flash Memory PROM Mode 19.29.1 PROM Mode Setting. 19.29.2 Socket Adapters Memory 19.29.3 PROM Mode Operation 19.29.4 Memory Read Mode. 19.29.5 Auto-Program Mode 19.29.6 Auto-Erase Mode 19.29.7 Status Read Mode 19.29.8 Status Polling 19.29.9 PROM Mode Transition Time 19.29.10Notes Memory Programming Flash Memory Programming Erasing Precautions. Overview Flash Memory (H8S/2326C F-ZTAT) 19.31.1 Features 19.31.2 Overview 19.31.3 Operating Mode Flash Memory 19.31.4 Mode Comparison 19.31.5 Flash Configuration 19.31.6 Block Division. 19.31.7 Programming/Erasing Interface.
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19.32
19.33
19.34
19.35 19.36 19.37
19.38
19.31.8 Configuration 19.31.9 Register Configuration Register Description Flash Memory. 19.32.1 Programming/Erasing Interface Register. 19.32.2 Programming/Erasing Interface Parameter. 19.32.3 System Control Register (SYSCR2). 19.32.4 Emulation Register (RAMER). On-Board Programming Mode 19.33.1 Boot Mode. 19.33.2 User Program Mode 19.33.3 User Boot Mode Protection 19.34.1 Hardware Protection. 19.34.2 Software Protection 19.34.3 Error Protection. Flash Memory Emulation Switching between User User Boot MAT. 19.36.1 Usage Notes. PROM Mode 19.37.1 Arrangement Socket Adapter 19.37.2 PROM Mode Operation 19.37.3 Memory-Read Mode 19.37.4 Auto-Program Mode. 19.37.5 Auto-Erase Mode 19.37.6 Status-Read Mode 19.37.7 Status Polling. 19.37.8 Time Taken Transition PROM Mode 19.37.9 Notes Using PROM Mode. Further Information 19.38.1 Serial Communication Interface Specification Boot Mode. 19.38.2 Characteristics Timing PROM Mode. 19.38.3 Procedure Program Storable Area Programming Data.
Section Clock Pulse Generator. 20.1 Overview 20.1.1 Block Diagram 20.1.2 Register Configuration 20.2 Register Descriptions. 20.2.1 System Clock Control Register (SCKCR) 20.3 Oscillator 20.3.1 Connecting Crystal Resonator 20.3.2 External Clock Input. 20.4 Duty Adjustment Circuit.
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20.5 Medium-Speed Clock Divider 20.6 Master Clock Selection Circuit.
Section Power-Down Modes
21.1 Overview 21.1.1 Register Configuration 21.2 Register Descriptions. 21.2.1 Standby Control Register (SBYCR) 21.2.2 System Clock Control Register (SCKCR) 21.2.3 Module Stop Control Register (MSTPCR) 21.3 Medium-Speed Mode 21.4 Sleep Mode. 21.5 Module Stop Mode. 21.5.1 Module Stop Mode. 21.5.2 Usage Notes.1000 21.6 Software Standby Mode .1001 21.6.1 Software Standby Mode .1001 21.6.2 Clearing Software Standby Mode.1001 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.1002 21.6.4 Software Standby Mode Application Example.1002 21.6.5 Usage Notes.1003 21.7 Hardware Standby Mode .1004 21.7.1 Hardware Standby Mode.1004 21.7.2 Hardware Standby Mode Timing .1004 21.8 Clock Output Disabling Function .1005
Section Electrical Characteristics .1007
22.1 Electrical Characteristics Mask Version (H8S/2328, H8S/2327, H8S/2323) ROMless Version (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320).1007 22.1.1 Absolute Maximum Ratings .1007 22.1.2 Characteristics.1008 22.1.3 Characteristics.1012 22.1.4 Conversion Characteristics .1036 22.1.5 Conversion Characteristics .1037 22.2 Electrical Characteristics F-ZTAT (H8S/2329 F-ZTAT, H8S/2329B F-ZTAT, H8S/2329E F-ZTAT, H8S/2328 F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) .1038 22.2.1 Absolute Maximum Ratings .1038 22.2.2 Characteristics.1039 22.2.3 Characteristics.1042 22.2.4 Conversion Characteristics .1048 22.2.5 Conversion Characteristics .1049 22.2.6 Flash Memory Characteristics .1050 22.3 Electrical Characteristics H8S/2326C F-ZTAT Planning).1052
Rev. 4.0, 03/03 page xlii xliv
22.3.1 Absolute Maximum Ratings .1052 22.3.2 Characteristics.1053 22.3.3 Characteristics.1056 22.3.4 Conversion Characteristics .1062 22.3.5 Conversion Characteristics .1063 22.3.6 Flash Memory Characteristics .1063 22.3.7 Usage Note (internal voltage step down H8S/2326C F-ZTAT).1064 22.4 Usage Note .1064
Appendix Instruction .1065
Instruction List.1065 Instruction Codes.1089 Operation Code .1104 Number States Required Instruction Execution.1108 States during Instruction Execution.1122 Condition Code Modification.1136
Appendix Internal Registers .1142
List Registers (Address Order).1142 List Registers Module) .1152 Functions .1163
Appendix Port Block Diagrams .1309
C.10 C.11 C.12 C.13 Port .1309 Port .1312 Port .1316 Port .1319 Port .1320 Port .1324 Port .1330 Port .1333 Port .1334 Port .1335 Port E.1336 Port F.1337 Port .1345
Appendix States.1349
Port States Each Mode .1349
Appendix Product Lineup.1356 Appendix Package Dimensions.1357
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Rev. 4.0, 03/03 page xliv xliv
Section Overview
Overview
H8S/2329 Series H8S/2328 Series series microcomputers (MCUs: microcomputer units), built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with supporting functions on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip supporting functions required system configuration include controller (DMAC)*1 data transfer controller (DTC) masters, memory, 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. high-functionality controller also provided, enabling fast easy connection DRAM other kinds memory. Single-power-supply flash memory (F-ZTATTM*2) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching thus speeded processing speed increased. features H8S/2329 Series H8S/2328 Series shown table 1-1. Notes: DMAC supported H8S/2321. F-ZTAT trademark Hitachi, Ltd.
Rev. 4.0, 03/03, page 1358
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: operation) 16-bit register-register divide: operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating mode Advanced mode: 16-Mbyte address space
controller
Address space divided into areas, with specifications settable independently each area Chip select output possible each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable Maximum 8-Mbyte DRAM* directly connectable interval timer possible) External release function
controller* (DMAC)
Choice short address mode full address mode channels short address mode channels full address mode Transfer possible repeat mode, block transfer mode, etc. Single address mode transfer possible activated internal interrupt
Data transfer controller (DTC)
activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated
Rev. 4.0, 03/03, page 1358
Item 16-bit timer-pulse unit (TPU)
Specification 6-channel 16-bit timer Pulse processing capability pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting possible 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channel High-speed conversion: minimum conversion time operation) Single scan mode selectable Sample-and-hold circuit conversion activated external trigger timer trigger
Programmable pulse generator (PPG)
8-bit timer, channels
Watchdog timer (WDT) Serial communication interface (SCI), channels converter
converter ports
Resolution: bits Output: channels input/output pins, input pins
Rev. 4.0, 03/03, page 1358
Item Memory
Specification Flash memory, mask High-speed static kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
Product Code H8S/2329, H8S/2329B H8S/2329E H8S/2328, H8S/2328B* H8S/2327 H8S/2326
H8S/2326C*
H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320
Notes: H8S/2329B F-ZTAT low-cost version H8S/2329 F-ZTAT. Refer item H8S/2329 F-ZTAT. on-chip debug function used with E10-A emulator (E10-A compatible version). However, some function modules functions unavailable when on-chip debug function use. Refer figures 1-8, Arrangement. H8S/2328B F-ZTAT low-cost version H8S/2328 F-ZTAT. Refer item H8S/2328 F-ZTAT. planning Interrupt controller Power-down state external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Variable clock division ratio
Rev. 4.0, 03/03, page 1358
Item Operating modes
Specification Eight operating modes (H8S/2328 F-ZTAT, H8S/2326 F-ZTAT) External Data On-Chip Initial Value Maximum Value
Operating Mode Mode Description Advanced User program mode Advanced Boot mode Advanced On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode
Disabled bits bits Enabled bits Enabled Enabled bits bits
bits bits bits bits bits
Rev. 4.0, 03/03, page 1358
Item Operating modes
Specification Four operating modes (ROMless, mask versions, H8S/2329 F-ZTAT H8S/2326C F-ZTAT) Operating Mode Mode Description
External Data On-Chip Initial Value Maximum Value
Advanced On-chip disabled Disabled bits bits expansion mode On-chip disabled Disabled bits bits expansion mode On-chip enabled Enabled bits bits expansion mode Single-chip mode Enabled Notes: User boot mode H8S/2326C F-ZTAT. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. Boot mode H8S/2329 F-ZTAT, H8S/2326C F-ZTAT. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329 F-ZTAT user boot modes. table 19-9 section 19.6, On-Board Programming Modes, information H8S/2329 F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user program modes. table 19-73 section 19.33, On-Board Programming Modes, information H8S/2326C F-ZTAT user boot modes. ROMless versions only modes Clock pulse generator Built-in duty correction circuit
Rev. 4.0, 03/03, page 1358
Item Product lineup
Specification Condition Operating power supply voltage Operating frequency Model HD64F2329
HD64F2329B* HD64F2329E*
Condition
HD6432328 HD64F2328
HD64F2328B*
HD6432327 HD64F2326
HD64F2326C*
HD6412324S HD6432323 HD6412322R HD6412321 HD6412320
Products current lineup Notes: Low-cost version. specifications refer H8S/2329 FZTAT item. on-chip debug function used with E10-A emulator (E10-A compatible version). However, some function modules functions unavailable when on-chip debug function use. Refer figures 1-8, Arrangement. This low-cost version. specifications, refer items H8S/2328 F-ZTAT. planning
Rev. 4.0, 03/03, page 1358
Item Other features
Specification Differences between H8S/2326 F-ZTAT H8S/2326C F-ZTAT On-chip H8S/2326 F-ZTAT: kbytes (H'FFDC00 H'FFFBFF) H8S/2326C F-ZTAT: kbytes (H'FFBC00 H'FFFBFF) On-chip flash memory H8S/2326 F-ZTAT H8S/2326C F-ZTAT both have kbytes on-chip flash memory. However, method controlling flash memory different LSIs. When on-chip flash memory enabled, registers (parameters) used control different. details, section about H8S/2326 F-ZTAT H8S/2326C F-ZTAT section ROM. Address address maps H8S/2326 F-ZTAT H8S/2326C F-ZTAT differ places. details, section 3.5, Memory Each Operating Mode.
Note: supported H8S/2321.
Rev. 4.0, 03/03, page 1358
Block Diagram
Port
Port
Internal data
H8S/2000
Internal address
STBY WDTOVF (FWE, EMLE, VCL)*1
Clock pulse generator
EXTAL XTAL
Port
/A23 IRQ7 /A22 IRQ6 /A21 IRQ5 /A20 IRQ4 /A19 /A18 /A17 /A16
Interrupt controller LCAS WAIT BREQO BACK BREQ IRQ3 IRQ2 IRQ1 IRQ0 TEND1 DREQ1 TEND0 DREQ0
Port
Peripheral address Peripheral data
ROM*2
Port
DMAC
/A15 /A14 /A13 /A12 /A10
controller
Port
Port
8-bit timer /SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 ADTRG/IRQ7/WAIT/BREQO /SCK2/IRQ6 /RxD2/IRQ5 /TxD2/IRQ4
converter
Port
Port
converter
Port
Port
Port
Port
Vref AVCC AVSS
PO15 TIOCB2 TCLKD PO14 TIOCA2 PO13 TIOCB1 TCLKC PO12 TIOCA1 PO11 TIOCD0 TCLKB PO10 TIOCC0 TCLKA TIOCB0 DACK1 TIOCA0 DACK0
Notes: applies H8S/2328 F-ZTAT H8S/2326 F-ZTAT only. EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. WDTOVF function available F-ZTAT versions. supported ROMless versions.
Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Internal Block Diagram
TIOCB5 TMO1 TIOCA5 TMO0 TIOCB4 TMCI1 TIOCA4 TMRI1 TIOCD3 TMCI0 TIOCC3 TMRI0 TIOCB3 TIOCA3
Rev. 4.0, 03/03, page 1358
Port
Port
Internal data
H8S/2000
Internal address
STBY WDTOVF
Clock pulse generator
EXTAL XTAL
Port
/A23 IRQ7 /A22 IRQ6 /A21 IRQ5 /A20 IRQ4 /A19 /A18 /A17 /A16
controller
Interrupt controller WAIT BREQO BACK BREQ IRQ3 IRQ2 IRQ1 IRQ0
Port
Peripheral address Peripheral data
/A15 /A14 /A13 /A12 /A10
Port
Port
Port
8-bit timer /SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 ADTRG/IRQ7/WAIT/BREQO /SCK2/IRQ6 /RxD2/IRQ5 /TxD2/IRQ4
converter
Port
Port
converter
Port
Port
Port
Port
Vref AVCC AVSS
PO15 TIOCB2 TCLKD PO14 TIOCA2 PO13 TIOCB1 TCLKC PO12 TIOCA1 PO11 TIOCD0 TCLKB PO10 TIOCC0 TCLKA TIOCB0 TIOCA0
Figure H8S/2321 Internal Block Diagram
Rev. 4.0, 03/03, page 1358
TIOCB5 TMO1 TIOCA5 TMO0 TIOCB4 TMCI1 TIOCA4 TMRI1 TIOCD3 TMCI0 TIOCC3 TMRI0 TIOCB3 TIOCA3
1.3.1
Description
Arrangement
WDTOVF (FWE, EMLE, VCL)*
RxD2/IRQ5 TxD2/IRQ4 BREQ BACK LCAS/WAIT BREQO EXTAL XTAL
Note: applies H8S/2328 F-ZTAT H8S/2326 F-ZTAT only. EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. WDTOVF function available F-ZTAT versions.
Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Arrangement (TFP-120: View)
/A17 IRQ4 IRQ5 IRQ6 IRQ7 CS7/ IRQ3 CS6/ IRQ2
/SCK2 IRQ6 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /DA0 /AN6 /DA1 /AN7 AVSS /PO15 /TIOCB2 /TCLKD /PO14 /TIOCA2 /PO13 /TIOCB1 /TCLKC /PO12 /TIOCA1 /PO11 /TIOCD0 /TCLKB /PO10 /TIOCC0 /TCLKA /PO9 /TIOCB0 DACK1 /PO8 /TIOCA0 DACK0
TIOCA3 TIOCB3 TIOCC3 TMRI0 TIOCD3 TMCI0 TIOCA4 TMRI1 TIOCB4 TMCI1 TIOCA5 TMO0 TIOCB5 TMO1 TEND1 DREQ1 TEND0
STBY
DREQ0 /SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 /D15 /D14 /D13 /D12 /D11 /D10 IRQ0 IRQ1
Rev. 4.0, 03/03, page 1358
ADTRG/IRQ7/WAIT/BREQO /SCK2 /IRQ6 /RxD2/IRQ5 /TxD2/IRQ4 BREQ BACK LCAS/WAIT BREQO EXTAL XTAL
Note: applies H8S/2328 F-ZTAT H8S/2326 F-ZTAT only. EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C F-ZTAT only. WDTOVF function available F-ZTAT versions.
Figure Mask Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Arrangement (FP-128B: View)
Rev. 4.0, 03/03, page 1358
VSSNC /A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 IRQ4 /A21 IRQ5 /A22 IRQ6 /A23 IRQ7 CS7/ IRQ3 CS6/ IRQ2 IRQ1 IRQ0
AVCC Vref AVSS PO15 TIOCB2 TCLKD PO14 TIOCA2 PO13 TIOCB1 TCLKC PO12 TIOCA1 PO11 TIOCD0 TCLKB PO10 TIOCC0 TCLKA TIOCB0 DACK1 TIOCA0 DACK0
WDTOVF (FWE, EMLE, VCL)* /PO0 /TIOCA3 /PO1 /TIOCB3 /PO2 /TIOCC3 /TMRI0 /PO3 /TIOCD3 /TMCI0 /PO4 /TIOCA4 /TMRI1 /PO5 /TIOCB4 /TMCI1 /PO6 /TIOCA5 /TMO0 /PO7 /TIOCB5 /TMO1 TEND1 DREQ1 TEND0 DREQ0
SCK1 SCK0 RxD1 RxD0 TxD1 TxD0
STBY
Figure H8S/2321 Arrangement (TFP-120: View)
/A17 IRQ4 IRQ5 IRQ6 IRQ7 CS7/ IRQ3 CS6/ IRQ2
/SCK2 IRQ6 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /DA0 /AN6 /DA1 /AN7 AVSS /PO15 /TIOCB2 /TCLKD /PO14 /TIOCA2 /PO13 /TIOCB1 /TCLKC /PO12 /TIOCA1 /PO11 /TIOCD0 /TCLKB /PO10 /TIOCC0 /TCLKA /PO9 /TIOCB0 /PO8 /TIOCA0
TIOCA3 TIOCB3 TIOCC3 TMRI0 TIOCD3 TMCI0 TIOCA4 TMRI1 TIOCB4 TMCI1 TIOCA5 TMO0 TIOCB5 TMO1
RxD2/IRQ5 TxD2/IRQ4 BREQ BACK WAIT BREQO EXTAL XTAL
WDTOVF
STBY
/SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 /D15 /D14 /D13 /D12 /D11 /D10 IRQ0 IRQ1
Rev. 4.0, 03/03, page 1358
AVCC Vref AVSS PO15 TIOCB2 TCLKD PO14 TIOCA2 PO13 TIOCB1 TCLKC PO12 TIOCA1 PO11 TIOCD0 TCLKB PO10 TIOCC0 TCLKA TIOCB0 TIOCA0
Rev. 4.0, 03/03, page 1358
STBY
ADTRG/IRQ7/WAIT/BREQO /SCK2 /IRQ6 /RxD2/IRQ5 /TxD2/IRQ4 BREQ BACK WAIT BREQO EXTAL XTAL
Figure H8S/2321 Arrangement (FP-128B: View)
VSSNC /A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 IRQ4 /A21 IRQ5 /A22 IRQ6 /A23 IRQ7 CS7/ IRQ3 CS6/ IRQ2 IRQ1 IRQ0
SCK1 SCK0 RxD1 RxD0 TxD1 TxD0
WDTOVF
/PO0 /TIOCA3 /PO1 /TIOCB3 /PO2 /TIOCC3 /TMRI0 /PO3 /TIOCD3 /TMCI0 /PO4 /TIOCA4 /TMRI1 /PO5 /TIOCB4 /TMCI1 /PO6 /TIOCA5 /TMO0 /PO7 /TIOCB5 /TMO1
E10-A compatible version
RxD2/IRQ5 TxD2/IRQ4 BREQ BACK LCAS/WAIT BREQO EXTAL XTAL EMLE* TIOCA3 TIOCB3 TIOCC3 TMRI0 TIOCD3 TMCI0 TIOCA4 TMRI1 TIOCB4 TMCI1 TIOCA5 TMO0 TIOCB5 TMO1 TEND1/ DREQ1/ TEND0 CS5/
STBY
Note: E10-A emulator used, TDO, TDI, TDK, TMS, TRST pins used exclusively H-UDI functions function modules associated with these pins available. channel available. Also, watchdog timer continues operate during break states and, settings specify that internal reset performed, reset generated overflow occurs. Refer E10-A Emulator User's Manual E10-A emulator connection examples.
Figure HD64F2329E Arrangement (TFP-120: View)
/A17 IRQ4 IRQ5 IRQ6 IRQ7 CS7/ IRQ3 CS6/ IRQ2
/SCK2 IRQ6 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /DA0 /AN6 /DA1 /AN7 AVSS /PO15 /TIOCB2 /TCLKD /PO14 /TIOCA2 /PO13 /TIOCB1 /TCLKC /PO12 /TIOCA1 /PO11 /TIOCD0 /TCLKB /PO10 /TIOCC0 /TCLKA /PO9 /TIOCB0 DACK1 /PO8 /TIOCA0 DACK0
DREQ0 CS4/ /SCK1 /SCK0/ TRST* /RxD1 /RxD0 /TxD1 /TxD0 /D15 /D14 /D13 /D12 /D11 /D10 IRQ0 IRQ1
Rev. 4.0, 03/03, page 1358
E10-A compatible version
ADTRG/IRQ7/WAIT/BREQO SCK2 /IRQ6 RxD2/IRQ5 TxD2/IRQ4 BREQ BACK LCAS/WAIT BREQO EXTAL XTAL
Note: E10-A emulator used, TDO, TDI, TDK, TMS, TRST pins used exclusively H-UDI functions function modules associated with these pins available. channel available. Also, watchdog timer continues operate during break states and, settings specify that internal reset performed, reset generated overflow occurs. Refer E10-A Emulator User's Manual E10-A emulator connection examples.
Figure HD64F2329E Arrangement (FP-128B: View)
Rev. 4.0, 03/03, page 1358
IRQ4 IRQ5 IRQ6 IRQ7 CS7/ IRQ3 CS6/ IRQ2 IRQ1 IRQ0
AVCC Vref /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6 /DA0 /AN7 /DA1 AVSS /PO15 /TIOCB2 /TCLKD /PO14 /TIOCA2 /PO13 /TIOCB1 /TCLKC /PO12 /TIOCA1 /PO11 /TIOCD0 /TCLKB /PO10 /TIOCC0 /TCLKA /PO9 /TIOCB0 DACK1 /PO8 /TIOCA0 DACK0
EMLE* TIOCA3 TIOCB3 TIOCC3 TMRI0 TIOCD3 TMCI0 TIOCA4 TMRI1 TIOCB4 TMCI1 TIOCA5 TMO0 TIOCB5 TMO1 TEND1/TDO DREQ1/TDI TEND0 CS5/TCK DREQ0 CS4/TMS
STBY
/SCK1 /SCK0/ TRST* /RxD1 /RxD0 /TxD1 /TxD0 /D15 /D14 /D13 /D12 /D11 /D10
1.3.2
Functions Each Operating Mode Functions Each Operating Mode
Name Flash Memory Programmer Mode
Table
TFP-120
FP-128B
Mode
Mode
Mode PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6
Mode PA4/IRQ4 PA5/IRQ5 PA6/IRQ6
PA5/A21/IRQ5 PA6/A22/IRQ6
PA5/A21/IRQ5 PA6/A22/IRQ6
Rev. 4.0, 03/03, page 1358
Name Flash Memory Programmer Mode I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
TFP-120
FP-128B
Mode
Mode
Mode PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 P65/IRQ1 P64/IRQ0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 P30/TxD0 P31/TxD1 P32/RxD0
Mode PA7/IRQ7 P67/IRQ3 P66/IRQ2 P65/IRQ1 P64/IRQ0 P30/TxD0 P31/TxD1 P32/RxD0
PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 P65/IRQ1 P64/IRQ0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 P30/TxD0 P31/TxD1 P32/RxD0
PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 P65/IRQ1 P64/IRQ0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 P30/TxD0 P31/TxD1 P32/RxD0
Rev. 4.0, 03/03, page 1358
Name Flash Memory Programmer Mode
TFP-120
FP-128B
Mode
Mode
Mode P33/RxD1 P34/SCK0 P35/SCK1
Mode P33/RxD1 P34/SCK0 P35/SCK1
P33/RxD1 P34/SCK0 P35/SCK1 P60/DREQ0*
P61/TEND0*
P33/RxD1 P34/SCK0 P35/SCK1 P60/DREQ0*
P61/TEND0*
P60/DREQ0*
P61/TEND0*
P60/DREQ0*
P61/TEND0*
P62/DREQ1*
P63/TEND1*
P62/DREQ1*
P63/TEND1*
P62/DREQ1*
P62/DREQ1*
P63/TEND1*
P63/TEND1*
P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0
P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0
P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0
P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0
P25/PO5/ P25/PO5/ P25/PO5/ P25/PO5/ TIOCB4/TMCI1 TIOCB4/TMCI1 TIOCB4/TMCI1 TIOCB4/TMCI1 P24/PO4/ P24/PO4/ P24/PO4/ P24/PO4/ TIOCA4/TMRI1 TIOCA4/TMRI1 TIOCA4/TMRI1 TIOCA4/TMRI1 P23/PO3/ P23/PO3/ P23/PO3/ P23/PO3/ TIOCD3/TMCI0 TIOCD3/TMCI0 TIOCD3/TMCI0 TIOCD3/TMCI0 P22/PO2/ P22/PO2/ P22/PO2/ P22/PO2/ TIOCC3/TMRI0 TIOCC3/TMRI0 TIOCC3/TMRI0 TIOCC3/TMRI0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE, EMLE, VCL)* STBY P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE, EMLE, VCL)* STBY P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE, EMLE, VCL)* STBY P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE, EMLE, VCL)* STBY FWE, EMLE,
Rev. 4.0, 03/03, page 1358
Name Flash Memory Programmer Mode XTAL EXTAL
TFP-120
FP-128B
Mode XTAL EXTAL PF7/ PF6/AS
Mode XTAL EXTAL PF7/ PF6/AS
Mode XTAL EXTAL PF7/ PF6/AS PF3/LWR
Mode XTAL EXTAL PF7/
PF3/LWR PF2/LCAS WAIT/BREQO PF1/BACK PF0/BREQ
PF3/LWR
PF2/LCAS WAIT/BREQO PF1/BACK PF0/BREQ
PF2/LCAS WAIT/BREQO PF1/BACK PF0/BREQ
P50/TxD2/IRQ4 P50/TxD2/IRQ4 P50/TxD2/IRQ4 P50/TxD2/IRQ4 P51/RxD2/IRQ5 P51/RxD2/IRQ5 P51/RxD2/IRQ5 P51/RxD2/IRQ5 P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5
Rev. 4.0, 03/03, page 1358
Name Flash Memory Programmer Mode
TFP-120
FP-128B
Mode
Mode
Mode P46/AN6/DA0 P47/AN7/DA1 AVSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1* P10/PO8/ TIOCA0/ DACK0*
PG0/CAS
Mode P46/AN6/DA0 P47/AN7/DA1 AVSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1* P10/PO8/ TIOCA0/ DACK0*
P46/AN6/DA0 P47/AN7/ AVSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1* P10/PO8/ TIOCA0/ DACK0*
PG0/CAS
P46/AN6/DA0 P47/AN7/DA1 AVSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1* P10/PO8/ TIOCA0/ DACK0*
PG0/CAS
PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0
PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0
PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0
Rev. 4.0, 03/03, page 1358
Name Flash Memory Programmer Mode
TFP-120
FP-128B
Mode
VSSNC*
Mode
VSSNC*
Mode
VSSNC*
Mode
VSSNC*
Notes: Only modes provided ROMless version. DREQ0, TEND0, DREQ1, TEND1 functions supported H8S/2321. applies H8S/2328 F-ZTAT H8S/2326 F-ZTAT only. EMLE applies H8S/2329 F-ZTAT only. applies H8S/2326C FZTAT only. WDTOVF function available F-ZTAT versions. LCAS function supported H8S/2321. DACK1 function supported H8S/2321. DACK0 functions supported H8S/2321. VSSNC connected released.
Rev. 4.0, 03/03, page 1358
1.3.3
Functions Functions
Table
Type Power
Symbol
TFP-120
FP-128B 100, Input
Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply
Input
Internal stepdown Clock
VCL*
Output external capacitor should connected between this (0V). connect VCC. Input Connects crystal resonator. section Clock Pulse Generator typical connection diagrams crystal resonator external clock input. Connects crystal resonator. EXTAL also input external clock. section Clock Pulse Generator typical connection diagrams crystal resonator external clock input.
XTAL
EXTAL
Input
Output System clock: Supplies system clock external device.
Rev. 4.0, 03/03, page 1358
Type Symbol TFP-120 FP-128B Input Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while chip operating. H8S/2328 F-ZTAT, H8S/2326 F-ZTAT: Operating Mode Mode Mode Mode Mode Mode Mode Mode Mode
Operating mode control
Rev. 4.0, 03/03, page 1358
Type Symbol TFP-120 FP-128B Input Name Function Mask ROMless versions, H8S/2329 F-ZTAT, H8S/2326C F-ZTAT: Operating Mode Mode Mode Mode Mode Mode Mode Mode
Operating mode control
Notes: Applies H8S/2326C F-ZTAT only. Applies H8S/2329 F-ZTAT H8S/2326C F-ZTAT only. ROMless versions only modes System control STBY Input Input Reset input: When this driven low, chip reset. Standby: When this driven low, transition made hardware standby mode. request: Used external master issue request chip.
BREQ
Input
BREQO
Output request output: external request signal used when internal master accesses external space external busreleased state. Output request acknowledge: Indicates that been released external master.
BACK
Rev. 4.0, 03/03, page 1358
Type System control Symbol
FWE*
TFP-120
FP-128B Input Input Input
Name Function Flash write enable: Enables/ disables flash memory programming. Emulator enable: connection power supply Nonmaskable interrupt: Requests nonmaskable interrupt. When this used, should fixed high. Interrupt request These pins request maskable interrupt.
EMLE*
Interrupts
IRQ7 IRQ0
Input 101,
Address
Output Address bus: These pins output address.
Data
Data bus: These pins constitute bidirectional data bus.
control
Output Chip select: Signals selecting areas 127, 128, Output Address strobe: When this low, indicates that address output address enabled. Output Read: When this low, indicates that external address space read. Output High write/write enable: strobe signal that writes external space indicates that upper half (D15 data enabled. 2-CAS type DRAM write enable signal. Output write: strobe signal that writes external space indicates that lower half data enabled.
Rev. 4.0, 03/03, page 1358
Type control Symbol
CAS*
TFP-120
FP-128B
Name Function
Output Upper column address strobe/ column address strobe: 2CAS type DRAM upper column address strobe signal. Output Lower column address strobe: 2-CAS type DRAM lower column address strobe signal. Input Wait: Requests insertion wait state cycle when accessing external 3-state access space. request These pins request DMAC activation.
LCAS*
WAIT
controller (DMAC)
DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0
Input
Output transfer These pins indicate DMAC data transfer. Output transfer acknowledge These DMAC single address transfer acknowledge pins. Clock input These pins input external clock. Input capture/output compare match TGR0A TGR0D input capture input output compare output, output pins. Input capture/output compare match TGR1A TGR1B input capture input output compare output, output pins. Input capture/output compare match TGR2A TGR2B input capture input output compare output, output pins. Input capture/output compare match TGR3A TGR3D input capture input output compare output, output pins.
111,
121,
16-bit timer pulse unit (TPU)
TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1
105, 107, 115, 117, Input 109, 119,
108,
118,
TIOCA2, TIOCB2
106,
116,
TIOCA3, TIOCB3, TIOCC3, TIOCD3
Rev. 4.0, 03/03, page 1358
Type 16-bit timer pulse unit (TPU) Symbol TIOCA4, TIOCB4 TFP-120 FP-128B Name Function Input capture/output compare match TGR4A TGR4B input capture input output compare output, output pins. Input capture/output compare match TGR5A TGR5B input capture input output compare output, output pins.
TIOCA5, TIOCB5
Programmable PO15 pulse generator (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Watchdog timer (WDT) Serial communication interface (SCI)/ smart card interface
112,
122,
Output Pulse output Pulse output pins. Output Compare match output: compare match output pins. Input Counter external clock input: Input pins external clock input counter. Counter external reset input: counter reset input pins.
Input
WDTOVF*
Output Watchdog timer overflow: counter overflow signal output watchdog timer mode. Output Transmit data (channel Data output pins. Input Receive data (channel Data input pins. Serial clock (channel Clock pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion.
TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0
101,
converter
ADTRG
Input Input
converter
DA1,
102,
112,
Output Analog output: converter analog output pins.
Rev. 4.0, 03/03, page 1358
Type converter converter Symbol AVCC TFP-120 FP-128B Input Name Function This power supply converter converter. When converter converter used, this should connected system power supply This ground converter converter. This should connected system power supply This reference voltage input converter converter. When converter converter used, this should connected system power supply Port 8-bit port. Input output designated each means port data direction register (P1DDR). Port 8-bit port. Input output designated each means port data direction register (P2DDR). Port 6-bit port. Input output designated each means port data direction register (P3DDR). Port 8-bit input port. Port 4-bit port. Input output designated each means port data direction register (P5DDR).
AVSS
Input
Vref
Input
ports
Input
102, 101,
Rev. 4.0, 03/03, page 1358
Type ports Symbol TFP-120 FP-128B Name Function Port 8-bit port. Input output designated each means port data direction register (P6DDR). Port 8-bit port. Input output designated each means port data direction register (PADDR). Port 8-bit port. Input output designated each means port data direction register (PBDDR). Port 8-bit port. Input output designated each means port data direction register (PCDDR). Port 8-bit port. Input output designated each means port data direction register (PDDDR). Port 8-bit port. Input output designated each means port data direction register (PEDDR). Port 8-bit port. Input output designated each means port data direction register (PFDDR). Port 5-bit port. Input output designated each means port data direction register (PGDDR).
Notes:
Applies H8S/2326C F-ZTAT only. Applies H8S/2328 F-ZTAT H8S/2326 F-ZTAT only. Applies H8S/2329 F-ZTAT only. supported H8S/2321. available F-ZTAT versions. Cannot used port ROMless versions.
Rev. 4.0, 03/03, page 1358
Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally)
Rev. 4.0, 03/03, page 1358
High-speed operation frequently-used instructions execute states Maximum clock rate 8-bit register-register multiply 8-bit register-register divide 16-bit register-register multiply 16-bit register-register divide operating mode Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences between H8S/2600 H8S/2000 8/16/32-bit register-register add/subtract
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number exection states MULXU MULXS instructions.
Internal Operation Instruction MULXU MULXS Mnemonic MULXU.B MULXU.W MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, functions, power-down state, etc., depending product.
Rev. 4.0, 03/03, page 1358
2.1.3
Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit control register, have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Rev. 4.0, 03/03, page 1358
Operating Modes
H8S/2329 H8S/2328 Series advanced operating mode. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum 16-Mbyte program area maximum Gbytes program data areas combined). mode selected mode pins microcontroller. Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Rev. 4.0, 03/03, page 1358
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2-1). details exception vector table, section Exception Handling.
H'00000000
Reserved Power-on reset exception vector
H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Rev. 4.0, 03/03, page 1358
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-2. When invalid, pushed onto stack. details, section Exception Handling.
Reserved bits)
EXR*1 Reserved*1 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Advanced Mode
Rev. 4.0, 03/03, page 1358
Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'00000000
Program area
H'00FFFFFF
Data area
Cannot used H8S/2329 H8S/2328 Series
H'FFFFFFFF Advanced Mode
Figure Memory
Rev. 4.0, 03/03, page 1358
2.4.1
Register Configuration
Overview
internal registers shown figure 2-4. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR:
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask bit*
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: H8S/2329 H8S/2328 Series, this cannot used interrupt mask.
Figure Registers
Rev. 4.0, 03/03, page 1358
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Rev. 4.0, 03/03, page 1358
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: These bits reserved. They always read Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details, refer section Interrupt Controller. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags.
Rev. 4.0, 03/03, page 1358
7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exception-handling sequence. details, refer section Interrupt Controller. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. With H8S/2329 H8S/2328 Series, this cannot used interrupt mask bit. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, Instruction List. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized.
Rev. 4.0, 03/03, page 1358
stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure shows data formats general registers.
Data Type Register Number Data Format
1-bit data
care
1-bit data
care
4-bit data
Upper
Lower
care
4-bit data
care
Upper
Lower
Byte data
care
care
Byte data
Figure General Register Data Formats
Rev. 4.0, 03/03, page 1358
Data Type
Register Number
Data Format
Word data
Word data
Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats (cont)
Rev. 4.0, 03/03, page 1358
2.5.2
Memory Data Formats
Figure shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure Memory Data Formats When used address register access stack, operand size should word size longword size.
Rev. 4.0, 03/03, page 1358
2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2-1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE, MOVTPE*
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
Logic operations Shift manipulation Branch System control Block data transfer
AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR, EEPMOV
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Total: Notes: B-byte size; W-word size; L-longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used H8S/2329 H8S/2328 Series. Only register ER0, ER1, ER4, should used when using instruction.
Rev. 4.0, 03/03, page 1358
2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2600 use. Table Combinations Instructions Addressing Modes
Addressing Modes
ERn/@ERn+ @(d:16,ERn) @(d:32,ERn)
Data transfer
POP, PUSH LDM, SMOVFPE, MOVTPE*1
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS TAS*2
Logic operations Shift
AND,
manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer Legend Byte Word Longword
@@aa:8
Function
Instruction
@ERn
@(d:16,PC)
@(d:8,PC)
@aa:16
@aa:24
@aa:32
@aa:8
Notes: Cannot used H8S/2329 H8S/2328 Series. Only register ER0, ER1, ER4, should used when using instruction.
Rev. 4.0, 03/03, page 1358
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Rev. 4.0, 03/03, page 1358
Table
Type Data transfer
Instructions Classified Function
Instruction Size*
Function (EAs) (Ead) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2329 H8S/2328 Series. Cannot used H8S/2329 H8S/2328 Series. @SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
B/W/L
MOVFPE MOVTPE
PUSH
S
Rev. 4.0, 03/03, page 1358
Type Arithmetic operations
Instruction
Size*
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8bit remainder bits bits 16-bit quotient 16-bit remainder.
B/W/L
ADDX SUBX
B/W/L
ADDS SUBS
MULXU
MULXS
DIVXU
Rev. 4.0, 03/03, page 1358
Type Arithmetic operations
Instruction DIVXS
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8bit remainder bits bits 16-bit quotient 16-bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @Erd)* Tests memory contents, sets most significant (bit
B/W/L
B/W/L
EXTU
EXTS
Rev. 4.0, 03/03, page 1358
Type Logic operations
Instruction
Size*
Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR
B/W/L
SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
Rev. 4.0, 03/03, page 1358
Type Bitmanipulation instructions
Instruction BSET
Size*
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Rev. 4.0, 03/03, page 1358
Type Bitmanipulation instructions
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Rev. 4.0, 03/03, page 1358
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine.
Rev. 4.0, 03/03, page 1358
Type
Instruction
Size*
Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
System control TRAPA instructions SLEEP
ANDC
XORC
Rev. 4.0, 03/03, page 1358
Type Block data transfer instruction
Instruction EEPMOV.B
Size*
Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
Notes: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
Rev. 4.0, 03/03, page 1358
2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, MOV.B @(d:16, Rn), etc.
Figure Instruction Formats (Examples) Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions.
Rev. 4.0, 03/03, page 1358
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2-4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Rev. 4.0, 03/03, page 1358
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Advanced Mode bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Rev. 4.0, 03/03, page 1358
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch
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