H8S/2676 F-ZTAT HD64F2676 H8S/2676 HD6432676 H8S/2
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HD6412670 Hardware Manual
ADE-602-242A Rev. 04/05/02 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Rev. 2.0, 04/02, page xliv
General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Rev. 2.0, 04/02, page xliv
Configuration This Manual
This manual comprises following items: General Precautions Handling Product Configuration This Manual Preface Contents Overview Description Functional Modules System-Control Modules On-Chip Peripheral Modules configuration functional description each module differs according module. However, generic style includes following items: Feature Input/Output iii) Register Description Operation Usage Note When designing application system that includes this LSI, take notes into account. Each section includes notes relation descriptions given, usage notes given, required, final part each section. List Registers Electrical Characteristics Appendix Main Revisions Additions this Edition (only revised versions) list revisions summary points that have been revised added earlier versions. This does include revised contents. details, actual locations this manual. Index
Rev. 2.0, 04/02, page xliv
Preface
H8S/2678 Series H8S/2678R Series microcomputers (MCU) made H8S/2600 employing Hitachi's original architecture their cores, peripheral functions required configure system. H8S/2600 internal 32-bit configuration, sixteen 16-bit general registers, simple optimized instruction high-speed operation. H8S/2600 handle 16-Mbyte linear address space. This equipped with direct memory access controller (DMAC EXDMAC) data transfer controller (DTC) masters, memory, 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer (TMR), watchdog timer (WDT), serial communication interface (SCI IrDA), 10-bit converter, 8-bit converter, ports on-chip peripheral modules required system configuration high functionality controller also provided, enabling fast easy connection DRAM, SDRAM, other kinds memory. single-power flash memory (F-ZTAT version masked version available this LSI's ROM. F-ZTAT version provides flexibility reprogrammed time cope with situations from early stages mass production full-scale mass production. This particularly applicable application devices with specifications that will most probably change. This manual describes this LSI's hardware. Note: F-ZTAT
trademark Hitachi, Ltd.
Target Users: This manual written users will using this design application systems. Target users expected understand fundamentals electrical circuits, logical circuits, microcomputers. Objective: This manual written explain hardware functions electrical characteristics this target users. Refer H8S/2600 Series, H8S/2000 Series Programming Manual detailed description instruction set.
Notes reading this manual: order understand overall functions chip Read manual according contents. This manual roughly categorized into parts CPU, system control functions, peripheral functions electrical characteristics.
Rev. 2.0, 04/02, page xliv
order understand details CPU's functions Read H8S/2600 Series, H8S/2000 Series Programming Manual. order understand details register when name known Read index that final part manual find page number entry register. addresses, bits, initial values registers summarized section List Registers. Examples: Register name: following notation used cases when same similar function, e.g. 16-bit timer pulse unit serial communication, implemented more than channel: XXX_N (XXX register name channel number) left right. Binary B'xxxx, hexadecimal H'xxxx, decimal xxxx. overbar added low-active signal: xxxx
order: Number notation: Signal notation: Related Manuals:
latest versions related manuals available from site. Please ensure have latest versions documents require.
H8S/2678 Series H8S/2678R Series manuals:
Manual Title H8S/2678 Series,H8S/2678R Series Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual This manual ADE-602-083
User's manuals development tools:
Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-247 ADE-702-282 ADE-702-231 ADE-702-201
Rev. 2.0, 04/02, page xliv
Contents
Section Overview.
Features Block Diagram Description.5 1.3.1 Arrangement 1.3.2 Arrangement Each Operating Mode 1.3.3 Functions
Section CPU.
Features 2.1.1 Differences between H8S/2600 H8S/2000 2.1.2 Differences from H8/300 CPU.22 2.1.3 Differences from H8/300H CPU.23 Operating Modes 2.2.1 Normal Mode.23 2.2.2 Advanced Mode Address Space Registers.29 2.4.1 General Registers 2.4.2 Program Counter (PC) 2.4.3 Extended Register (EXR).31 2.4.4 Condition-Code Register (CCR) 2.4.5 Multiply-Accumulate Register (MAC) 2.4.6 Initial Values Internal Registers.33 Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction 2.6.1 Table Instructions Classified Function 2.6.2 Basic Instruction Formats Addressing Modes Effective Address Calculation 2.7.1 Register Direct-Rn.49 2.7.2 Register Indirect-@ERn 2.7.3 Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn).49 2.7.4 Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn 2.7.5 Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32.50 2.7.6 Immediate-#xx:8, #xx:16, #xx:32 2.7.7 Program-Counter Relative-@(d:8, @(d:16, PC).51
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2.7.8 Memory Indirect-@@aa:8 2.7.9 Effective Address Calculation Processing States. Usage Note. 2.9.1 Usage Notes Bit-wise Operation Instructions
Section Operating Modes
Operating Mode Selection Register Descriptions 3.2.1 Mode Control Register (MDCR) 3.2.2 System Control Register (SYSCR) Operating Mode Descriptions 3.3.1 Mode 3.3.2 Mode 3.3.3 Mode 3.3.4 Mode 3.3.5 Mode 3.3.6 Mode 3.3.7 Mode 3.3.8 Mode 3.3.9 Mode 3.3.10 Mode 3.3.11 Mode 3.3.12 Mode 3.3.13 Mode 3.3.14 Functions Memory Each Operating Mode
Section Exception Handling
Exception Handling Types Priority Exception Sources Exception Vector Table Reset 4.3.1 Reset exception handling 4.3.2 Interrupts after Reset. 4.3.3 On-Chip Peripheral Functions after Reset Release Traces. Interrupts. Trap Instruction. Stack Status after Exception Handling. Usage Note.
Section Interrupt Controller.85
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Features Input/Output Pins Register Descriptions 5.3.1 Interrupt Control Register (INTCR).87 5.3.2 Interrupt Priority Registers (IPRA IPRK) 5.3.3 Enable Register (IER) 5.3.4 Sense Control Registers (ISCRH, ISCRL).92 5.3.5 Status Register (ISR).97 5.3.6 Select Register (ITSR) 5.3.7 Software Standby Release Enable Register (SSIER) .100 Interrupt Sources .100 5.4.1 External Interrupts .100 5.4.2 Internal Interrupts.101 Interrupt Exception Handling Vector Table.102 Interrupt Control Modes Interrupt Operation .107 5.6.1 Interrupt Control Mode .107 5.6.2 Interrupt Control Mode .109 5.6.3 Interrupt Exception Handling Sequence .110 5.6.4 Interrupt Response Times .112 5.6.5 DMAC Activation Interrupt .113 Usage Notes .116 5.7.1 Contention between Interrupt Generation Disabling.116 5.7.2 Instructions that Disable Interrupts .117 5.7.3 Times when Interrupts Disabled .117 5.7.4 Interrupts during Execution EEPMOV Instruction.117 5.7.5 Change Select Register (ITSR) Setting .117 5.7.6 Note Status Register (ISR) .118
Section Controller (BSC).
Features .119 Input/Output Pins .121 Register Descriptions .123 6.3.1 Width Control Register (ABWCR).124 6.3.2 Access State Control Register (ASTCR) .124 6.3.3 Wait Control Registers (WTCRAH, WTCRAL, WTCRBH, WTCRBL).125 6.3.4 Read Strobe Timing Control Register (RDNCR).130 6.3.5 Assertion Period Control Registers (CSACRH, CSACRL).131 6.3.6 Area Burst Interface Control Register (BROMCRH) Area Burst Interface Control Register (BROMCRL).133 6.3.7 Control Register (BCR) .134 6.3.8 DRAM Control Register (DRAMCR) .136
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6.3.9 DRAM Access Control Register (DRACCR). 6.3.10 Refresh Control Register (REFCR) 6.3.11 Refresh Timer Counter (RTCNT). 6.3.12 Refresh Time Constant Register (RTCOR) Control 6.4.1 Area Division. 6.4.2 Specifications. 6.4.3 Memory Interfaces. 6.4.4 Chip Select Signals Basic Interface 6.5.1 Data Size Data Alignment. 6.5.2 Valid Strobes. 6.5.3 Basic Operation Timing. 6.5.4 Wait Control 6.5.5 Read Strobe (RD) Timing. 6.5.6 Extension Chip Select (CS) Assertion Period. DRAM Interface 6.6.1 Setting DRAM Space. 6.6.2 Address Multiplexing 6.6.3 Data Bus. 6.6.4 Pins Used DRAM Interface. 6.6.5 Basic Timing. 6.6.6 Column Address Output Cycle Control 6.6.7 Address Output State Control. 6.6.8 Precharge State Control 6.6.9 Wait Control 6.6.10 Byte Access Control 6.6.11 Burst Operation. 6.6.12 Refresh Control. 6.6.13 DMAC EXDMAC Single Address Transfer Mode DRAM Interface. Synchronous DRAM Interface. 6.7.1 Setting Continuous Synchronous DRAM Space. 6.7.2 Address Multiplexing 6.7.3 Data Bus. 6.7.4 Pins Used Synchronous DRAM Interface. 6.7.5 Synchronous DRAM Clock 6.7.6 Basic Operation Timing. 6.7.7 Latency Control. 6.7.8 Address Output State Control. 6.7.9 Precharge State Count. 6.7.10 Cycle Control Write Cycle 6.7.11 Byte Access Control
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6.10 6.11
6.12
6.13 6.14
Burst Operation.210 Refresh Control.214 Mode Register Setting Synchronous DRAM.219 DMAC EXDMAC Single Address Transfer Mode Synchronous DRAM Interface.221 Burst Interface. 6.8.1 Basic Timing.226 6.8.2 Wait Control.228 6.8.3 Write Access .228 Idle Cycle .229 6.9.1 Operation .229 6.9.2 States Idle Cycle .245 Write Data Buffer Function .245 Release .246 6.11.1 Operation .246 6.11.2 States External Released State.248 6.11.3 Transition Timing .249 Arbitration.251 6.12.1 Operation .251 6.12.2 Transfer Timing .251 Controller Operation Reset .253 Usage Notes .253 6.14.1 External Release Function All-Module-Clocks-Stopped Mode.253 6.14.2 External Release Function Software Standby .253 6.14.3 External Release Function Refreshing/Auto Refreshing.253 6.14.4 BREQO Output Timing .254 6.14.5 Notes Usage Synchronous DRAM .254
6.7.12 6.7.13 6.7.14 6.7.15
Section Controller (DMAC)
Features .255 Input/Output Pins .257 Register Descriptions .257 7.3.1 Memory Address Registers (MARA MARB) .258 7.3.2 Address Registers (IOARA IOARB) .259 7.3.3 Execute Transfer Count Registers (ETCRA ETCRB).259 7.3.4 Control Registers (DMACRA DMACRB) .261 7.3.5 Band Control Registers (DMABCRH DMABCRL).268 7.3.6 Write Enable Register (DMAWER) .279 7.3.7 Terminal Control Register (DMATCR).281 Activation Sources .282 7.4.1 Activation Internal Interrupt Request.282 7.4.2 Activation External Request .283
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7.4.3 Activation Auto-Request Operation 7.5.1 Transfer Modes 7.5.2 Sequential Mode 7.5.3 Idle Mode. 7.5.4 Repeat Mode 7.5.5 Single Address Mode. 7.5.6 Normal Mode. 7.5.7 Block Transfer Mode 7.5.8 Basic Cycles. 7.5.9 Cycles (Dual Address Mode) 7.5.10 Cycles (Single Address Mode) 7.5.11 Write Data Buffer Function 7.5.12 Multi-Channel Operation 7.5.13 Relation between DMAC External Requests, Refresh Cycles, EXDMAC 7.5.14 DMAC Interrupts 7.5.15 Forced Termination DMAC Operation. 7.5.16 Clearing Full Address Mode. Interrupt Sources. Usage Notes 7.7.1 DMAC Register Access during Operation. 7.7.2 Module Stop. 7.7.3 Write Data Buffer Function 7.7.4 TEND Output. 7.7.5 Activation Falling Edge DREQ 7.7.6 Activation Source Acceptance. 7.7.7 Internal Interrupt after Transfer. 7.7.8 Channel Re-Setting
Section EXDMA Controller .331
Features. Input/Output Pins Register Descriptions 8.3.1 EXDMA Source Address Register (EDSAR). 8.3.2 EXDMA Destination Address Register (EDDAR) 8.3.3 EXDMA Transfer Count Register (EDTCR). 8.3.4 EXDMA Mode Control Register (EDMDR) 8.3.5 EXDMA Address Control Register (EDACR) Operation 8.4.1 Transfer Modes 8.4.2 Address Modes
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8.4.3 Transfer Requests .350 8.4.4 Modes .350 8.4.5 Transfer Modes .352 8.4.6 Repeat Area Function .354 8.4.7 Registers during Transfer Operation.356 8.4.8 Channel Priority Order.360 8.4.9 EXDMAC Cycles (Dual Address Mode).363 8.4.10 EXDMAC Cycles (Single Address Mode) .368 8.4.11 Examples Operation Timing Each Mode.373 8.4.12 Ending Transfer .386 8.4.13 Relationship between EXDMAC Other Masters .387 Interrupt Sources .387 Usage Notes .390 8.6.1 EXDMAC Register Access during Operation .390 8.6.2 Module Stop State.390 8.6.3 EDREQ Falling Edge Activation.390 8.6.4 Activation Source Acceptance .390 8.6.5 Enabling Interrupt Requests when EDMDR .391 8.6.6 ETEND Refresh Cycle.391
Section Data Transfer Controller (DTC)
Features .393 Register Descriptions .394 9.2.1 Mode Register (MRA) .395 9.2.2 Mode Register (MRB).396 9.2.3 Source Address Register (SAR).396 9.2.4 Destination Address Register (DAR) .396 9.2.5 Transfer Count Register (CRA) .396 9.2.6 Transfer Count Register (CRB).397 9.2.7 Enable Registers (DTCERA DTCERG) .397 9.2.8 Vector Register (DTVECR) .397 Activation Sources .398 Location Register Information Vector Table .399 Operation.402 9.5.1 Normal Mode.404 9.5.2 Repeat Mode .405 9.5.3 Block Transfer Mode .406 9.5.4 Chain Transfer .407 9.5.5 Interrupt Sources.408 9.5.6 Operation Timing.409 9.5.7 Number Execution States.410 Procedures Using DTC.411
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9.6.1 Activation Interrupt. 9.6.2 Activation Software Examples 9.7.1 Normal Mode. 9.7.2 Chain Transfer 9.7.3 Chain Transfer when Counter 9.7.4 Software Activation Usage Notes 9.8.1 Module Stop Mode Setting 9.8.2 On-Chip 9.8.3 DTCE Setting.
Section Ports.417
10.1 Port 10.1.1 Port Data Direction Register (P1DDR). 10.1.2 Port Data Register (P1DR). 10.1.3 Port Register (PORT1). 10.1.4 Functions 10.2 Port 10.2.1 Port Data Direction Register (P2DDR). 10.2.2 Port Data Register (P2DR). 10.2.3 Port Register (PORT2). 10.2.4 Functions 10.3 Port 10.3.1 Port Data Direction Register (P3DDR). 10.3.2 Port Data Register (P3DR). 10.3.3 Port Register (PORT3). 10.3.4 Port Open Drain Control Register (P3ODR) 10.3.5 Port Function Control Register (PFCR2) 10.3.6 Functions 10.4 Port 10.4.1 Port Register (PORT4). 10.4.2 Functions 10.5 Port 10.5.1 Port Data Direction Register (P5DDR). 10.5.2 Port Data Register (P5DR). 10.5.3 Port Register (PORT5). 10.5.4 Functions 10.6 Port 10.6.1 Port Data Direction Register (P6DDR). 10.6.2 Port Data Register (P6DR). 10.6.3 Port Register (PORT6).
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10.6.4 Functions .454 10.7 Port 7.457 10.7.1 Port Data Direction Register (P7DDR).458 10.7.2 Port Data Register (P7DR).458 10.7.3 Port Register (PORT7).459 10.7.4 Functions .459 10.8 Port 8.462 10.8.1 Port Data Direction Register (P8DDR).462 10.8.2 Port Data Register (P8DR).463 10.8.3 Port Register (PORT8).464 10.8.4 Functions .464 10.9 Port .467 10.9.1 Port Data Direction Register (PADDR) .468 10.9.2 Port Data Register (PADR) .469 10.9.3 Port Register (PORTA) .469 10.9.4 Port Pull-Up Control Register (PAPCR) .470 10.9.5 Port Open Drain Control Register (PAODR).470 10.9.6 Port Function Control Register (PFCR1) .470 10.9.7 Functions .472 10.9.8 Port Input Pull-Up States.472 10.10 Port .473 10.10.1 Port Data Direction Register (PBDDR).473 10.10.2 Port Data Register (PBDR) .474 10.10.3 Port Register (PORTB) .474 10.10.4 Port Pull-Up Control Register (PBPCR).475 10.10.5 Functions .475 10.10.6 Port Input Pull-Up States .475 10.11 Port .476 10.11.1 Port Data Direction Register (PCDDR).476 10.11.2 Port Data Register (PCDR) .477 10.11.3 Port Register (PORTC) .477 10.11.4 Port Pull-Up Control Register (PCPCR).477 10.11.5 Functions .478 10.11.6 Port Input Pull-Up States .478 10.12 Port .479 10.12.1 Port Data Direction Register (PDDDR) .479 10.12.2 Port Data Register (PDDR) .480 10.12.3 Port Register (PORTD) .480 10.12.4 Port Pull-up Control Register (PDPCR).481 10.12.5 Functions .481 10.12.6 Port Input Pull-Up States.481 10.13 Port .482
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10.13.1 Port Data Direction Register (PEDDR) 10.13.2 Port Data Register (PEDR). 10.13.3 Port Register (PORTE). 10.13.4 Port Pull-up Control Register (PEPCR) 10.13.5 Functions 10.13.6 Port Input Pull-Up States 10.14 Port 10.14.1 Port Data Direction Register (PFDDR) 10.14.2 Port Data Register (PFDR) 10.14.3 Port Register (PORTF) 10.14.4 Functions 10.15 Port 10.15.1 Port Data Direction Register (PGDDR) 10.15.2 Port Data Register (PGDR). 10.15.3 Port Register (PORTG) 10.15.4 Port Function Control Register (PFCR0) 10.15.5 Functions 10.16 Port 10.16.1 Port Data Direction Register (PHDDR) 10.16.2 Port Data Register (PHDR). 10.16.3 Port Register (PORTH) 10.16.4 Functions
Section 16-Bit Timer Pulse Unit (TPU) .501
11.1 Features. 11.2 Input/Output Pins 11.3 Register Descriptions 11.3.1 Timer Control Register (TCR). 11.3.2 Timer Mode Register (TMDR) 11.3.3 Timer Control Register (TIOR) 11.3.4 Timer Interrupt Enable Register (TIER) 11.3.5 Timer Status Register (TSR). 11.3.6 Timer Counter (TCNT). 11.3.7 Timer General Register (TGR) 11.3.8 Timer Start Register (TSTR). 11.3.9 Timer Synchronous Register (TSYR). 11.4 Operation 11.4.1 Basic Functions. 11.4.2 Synchronous Operation. 11.4.3 Buffer Operation 11.4.4 Cascaded Operation 11.4.5 Modes
Rev. 2.0, 04/02, page xliv
11.5 11.6 11.7 11.8 11.9
11.4.6 Phase Counting Mode .556 Interrupt Sources .562 Activation.564 DMAC Activation.564 Converter Activation .564 Operation Timing.565 11.9.1 Input/Output Timing .565 11.9.2 Interrupt Signal Timing.568 11.10 Usage Notes .571 11.10.1 Module Stop Mode Setting .571 11.10.2 Input Clock Restrictions.571 11.10.3 Caution Cycle Setting .572 11.10.4 Contention between TCNT Write Clear Operations .572 11.10.5 Contention between TCNT Write Increment Operations.573 11.10.6 Contention between Write Compare Match .574 11.10.7 Contention between Buffer Register Write Compare Match .574 11.10.8 Contention between Read Input Capture.575 11.10.9 Contention between Write Input Capture.576 11.10.10 Contention between Buffer Register Write Input Capture .576 11.10.11 Contention between Overflow/Underflow Counter Clearing.577 11.10.12 Contention between TCNT Write Overflow/Underflow.578 11.10.13 Multiplexing Pins .578 11.10.14 Interrupts Module Stop Mode .578
Section Programmable Pulse Generator (PPG)
12.1 Features .579 12.2 Input/Output Pins .581 12.3 Register Descriptions .581 12.3.1 Next Data Enable Registers (NDERH, NDERL).582 12.3.2 Output Data Registers (PODRH, PODRL).583 12.3.3 Next Data Registers (NDRH, NDRL) .584 12.3.4 Output Control Register (PCR).586 12.3.5 Output Mode Register (PMR).587 12.4 Operation.589 12.4.1 Output Timing.590 12.4.2 Sample Setup Procedure Normal Pulse Output .591 12.4.3 Example Normal Pulse Output (Example Five-Phase Pulse Output).592 12.4.4 Non-Overlapping Pulse Output.593 12.4.5 Sample Setup Procedure Non-Overlapping Pulse Output .594 12.4.6 Example Non-Overlapping Pulse Output (Example Four-Phase Complementary Non-Overlapping Output).595 12.4.7 Inverted Pulse Output .596
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12.4.8 Pulse Output Triggered Input Capture 12.5 Usage Notes 12.5.1 Module Stop Mode Setting 12.5.2 Operation Pulse Output Pins.
Section 8-Bit Timers (TMR) .599
13.1 Features. 13.2 Input/Output Pins 13.3 Register Descriptions 13.3.1 Timer Counter (TCNT). 13.3.2 Time Constant Register (TCORA). 13.3.3 Time Constant Register (TCORB) 13.3.4 Timer Control Register (TCR). 13.3.5 Timer Control/Status Register (TCSR). 13.4 Operation 13.4.1 Pulse Output. 13.5 Operation Timing. 13.5.1 TCNT Incrementation Timing 13.5.2 Timing CMFA CMFB Setting when Compare-Match Occurs 13.5.3 Timing Timer Output when Compare-Match Occurs. 13.5.4 Timing Compare Match Clear 13.5.5 Timing TCNT External Reset. 13.5.6 Timing Overflow Flag (OVF) Setting 13.6 Operation with Cascaded Connection. 13.6.1 16-Bit Counter Mode 13.6.2 Compare Match Count Mode. 13.7 Interrupts. 13.7.1 Interrupt Sources Activation 13.7.2 Converter Activation. 13.8 Usage Notes 13.8.1 Contention between TCNT Write Clear. 13.8.2 Contention between TCNT Write Increment 13.8.3 Contention between TCOR Write Compare Match 13.8.4 Contention between Compare Matches 13.8.5 Switching Internal Clocks TCNT Operation. 13.8.6 Mode Setting with Cascaded Connection 13.8.7 Interrupts Module Stop Mode.
Section Watchdog Timer .621
14.1 Features. 14.2 Input/Output Pin. 14.3 Register Descriptions
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14.3.1 Timer Counter (TCNT).623 14.3.2 Timer Control/Status Register (TCSR) .623 14.3.3 Reset Control/Status Register (RSTCSR) .625 14.4 Operation.626 14.4.1 Watchdog Timer Mode .626 14.4.2 Interval Timer Mode .627 14.5 Interrupt Source .628 14.6 Usage Notes .628 14.6.1 Notes Register Access.628 14.6.2 Contention between Timer Counter (TCNT) Write Increment .629 14.6.3 Changing Value CKS2 CKS0.630 14.6.4 Switching between Watchdog Timer Mode Interval Timer Mode.630 14.6.5 Internal Reset Watchdog Timer Mode.630 14.6.6 System Reset WDTOVF Signal.631
Section Serial Communication Interface (SCI, IrDA)
15.1 Features .633 15.2 Input/Output Pins .635 15.3 Register Descriptions .636 15.3.1 Receive Shift Register (RSR).637 15.3.2 Receive Data Register (RDR) .637 15.3.3 Transmit Data Register (TDR).637 15.3.4 Transmit Shift Register (TSR) .638 15.3.5 Serial Mode Register (SMR).638 15.3.6 Serial Control Register (SCR).641 15.3.7 Serial Status Register (SSR).644 15.3.8 Smart Card Mode Register (SCMR) .648 15.3.9 Rate Register (BRR) .649 15.3.10 IrDA Control Register (IrCR) .658 15.3.11 Serial Extension Mode Register (SEMR) .659 15.4 Operation Asynchronous Mode .661 15.4.1 Data Transfer Format.661 15.4.2 Receive Data Sampling Timing Reception Margin Asynchronous Mode 15.4.3 Clock.664 15.4.4 Initialization (Asynchronous Mode) .665 15.4.5 Data Transmission (Asynchronous Mode).666 15.4.6 Serial Data Reception (Asynchronous Mode).668 15.5 Multiprocessor Communication Function.672 15.5.1 Multiprocessor Serial Data Transmission .674 15.5.2 Multiprocessor Serial Data Reception .676 15.6 Operation Clocked Synchronous Mode .679 15.6.1 Clock.679
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15.7
15.8 15.9
15.10
Initialization (Clocked Synchronous Mode) Serial Data Transmission (Clocked Synchronous Mode) Serial Data Reception (Clocked Synchronous Mode). Simultaneous Serial Data Transmission Reception (Clocked Synchronous Mode) Operation Smart Card Interface Mode. 15.7.1 Connection Example. 15.7.2 Data Format (Except Block Transfer Mode). 15.7.3 Block Transfer Mode 15.7.4 Receive Data Sampling Timing Reception Margin. 15.7.5 Initialization 15.7.6 Data Transmission (Except Block Transfer Mode) 15.7.7 Serial Data Reception (Except Block Transfer Mode) 15.7.8 Clock Output Control. IrDA Operation Interrupt Sources. 15.9.1 Interrupts Normal Serial Communication Interface Mode 15.9.2 Interrupts Smart Card Interface Mode Usage Notes 15.10.1 Module Stop Mode Setting 15.10.2 Break Detection Processing 15.10.3 Mark State Break Sending 15.10.4 Receive Error Flags Transmit Operations (Clocked Synchronous Mode Only) 15.10.5 Relation between Writes TDRE Flag 15.10.6 Restrictions DMAC DTC. 15.10.7 Operation Case Mode Transition.
15.6.2 15.6.3 15.6.4 15.6.5
Section Converter .709
16.1 Features. 16.2 Input/Output Pins 16.3 Register Descriptions 16.3.1 Data Registers (ADDRA ADDRH) 16.3.2 Control/Status Register (ADCSR) 16.3.3 Control Register (ADCR) 16.4 Operation 16.4.1 Single Mode. 16.4.2 Scan Mode 16.4.3 Input Sampling Conversion Time 16.4.4 External Trigger Input Timing. 16.5 Interrupt Source 16.6 Conversion Accuracy Definitions
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16.7 Usage Notes .726 16.7.1 Module Stop Mode Setting .726 16.7.2 Permissible Signal Source Impedance .726 16.7.3 Influences Absolute Precision.727 16.7.4 Setting Range Analog Power Supply Other Pins .727 16.7.5 Notes Board Design .728 16.7.6 Notes Noise Countermeasures .728
Section Converter.
17.1 Features .731 17.2 Input/Output Pins .732 17.3 Register Descriptions .733 17.3.1 Data Registers (DADR0 DADR3) .733 17.3.2 Control Registers (DACR01, DACR23) .733 17.4 Operation.737 17.5 Usage Notes .738 17.5.1 Setting Module Stop Mode.738 17.5.2 Output Hold Function Software Standby Mode.738
Section Section Flash Memory (F-ZTAT Version)
19.1 19.2 19.3 19.4 19.5 Features .741 Mode Transitions .742 Block Configuration.746 Input/Output Pins .749 Register Descriptions .749 19.5.1 Flash Memory Control Register (FLMCR1).749 19.5.2 Flash Memory Control Register (FLMCR2).751 19.5.3 Erase Block Register (EBR1).751 19.5.4 Erase Block Register (EBR2).752 19.5.5 Emulation Register (RAMER).754 On-Board Programming Modes.756 19.6.1 Boot Mode .756 19.6.2 User Program Mode.759 Flash Memory Emulation RAM.760 Flash Memory Programming/Erasing .762 19.8.1 Program/Program-Verify .762 19.8.2 Erase/Erase-Verify .764 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.764 Program/Erase Protection .766 19.9.1 Hardware Protection .766
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19.6
19.7 19.8
19.9
19.10 19.11 19.12 19.13
19.9.2 Software Protection. 19.9.3 Error Protection. Programmer Mode Power-Down States Flash Memory. Usage Notes Note Switching from F-ZTAT Version Masked Version
Section Masked .775 Section Clock Pulse Generator .777
21.1 Register Descriptions 21.1.1 System Clock Control Register (SCKCR) 21.1.2 Control Register (PLLCR) 21.2 Oscillator. 21.2.1 Connecting Crystal Resonator. 21.2.2 External Clock Input. 21.3 Circuit 21.4 Frequency Divider 21.5 Usage Notes 21.5.1 Notes Clock Pulse Generator 21.5.2 Notes Resonator 21.5.3 Notes Board Design
Section Power-Down Modes .785
22.1 Register Descriptions 22.1.1 Standby Control Register (SBYCR) 22.1.2 Module Stop Control Registers (MSTPCRH, MSTPCRL). 22.2 Operation 22.2.1 Clock Division Mode. 22.2.2 Sleep Mode 22.2.3 Software Standby Mode. 22.2.4 Hardware Standby Mode 22.2.5 Module Stop Mode 22.2.6 All-Module-Clocks-Stop Mode 22.3 Clock Output Control. 22.4 Usage Notes 22.4.1 Port Status. 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period. 22.4.3 EXDMAC/DMAC/DTC Module Stop 22.4.4 On-Chip Peripheral Module Interrupts 22.4.5 Writing MSTPCR
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Section List Registers
23.1 Register Addresses functional module, order corresponding section numbers).800 23.2 Register Bits.811 23.3 Register States Each Operating Mode.824
Section Electrical Characteristics
24.1 24.2 24.3 24.4 24.5 24.6 24.7 Absolute Maximum Ratings .835 Characteristics .836 Characteristics .840 Conversion Characteristics.876 Conversion Characteristics.876 Flash Memory Characteristics.877 Usage Note.879
Appendix
Port States Each State.881 Product Lineup.890 Package Dimensions .891
Main Revisions Additions this Edition Index
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Figures
Section Overview Figure H8S/2678 Series Internal Block Diagram Figure H8S/2678R Series Internal Block Diagram.4 Figure H8S/2678 Series Arrangement.5 Figure H8S/2678R Series Arrangement Section Figure Exception Vector Table (Normal Mode) Figure Stack Structure Normal Mode Figure Exception Vector Table (Advanced Mode) Figure Stack Structure Advanced Mode Figure Memory Map.28 Figure Registers Figure Usage General Registers Figure Stack Figure General Register Data Formats Figure General Register Data Formats Figure 2.10 Memory Data Formats.36 Figure 2.11 Instruction Formats (Examples) Figure 2.12 Branch Address Specification Memory Indirect Mode Figure 2.13 State Transitions Section Operating Modes Figure H8S/2676 Memory Figure H8S/2676 Memory Figure H8S/2676 Memory Figure H8S/2676 Memory Figure H8S/2675 Memory Figure H8S/2675 Memory Figure H8S/2673 Memory Figure H8S/2673 Memory Figure H8S/2670 Memory Map.73 Figure H8S/2674R Memory Section Exception Handling Figure Reset Sequence (Advanced Mode with On-chip Enabled).78 Figure Reset Sequence (Advanced Mode with On-chip Disabled).79 Figure Stack Status after Exception Handling Figure Operation when Value Odd.83 Section Interrupt Controller Figure Block Diagram Interrupt Controller Figure Block Diagram Interrupts IRQ15 IRQ0 .101 Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode 0.108
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Flowchart Procedure Interrupt Acceptance Interrupt Control Mode Interrupt Exception Handling DTC, DMAC, Interrupt Controller Contention between Interrupt Generation Disabling Controller (BSC) Block Diagram Controller. Read Strobe Negation Timing (Example 3-State Access Space) Address Assertion Period Extension (Example 3-State Access Space RDNn Figure Signal Assertion Timing (2-State Column Address Output Cycle, Full Access). Figure Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for Latency Figure Area Divisions. Figure Signal Output Timing Figure Access Sizes Data Alignment Control (8-Bit Access Space) Figure Access Sizes Data Alignment Control (16-bit Access Space) Figure 6.10 Timing 8-Bit, 2-State Access Space Figure 6.11 Timing 8-Bit, 3-State Access Space Figure 6.12 Timing 16-Bit, 2-State Access Space (Even Address Byte Access). Figure 6.13 Timing 16-Bit, 2-State Access Space (Odd Address Byte Access) Figure 6.14 Timing 16-Bit, 2-State Access Space (Word Access) Figure 6.15 Timing 16-Bit, 3-State Access Space (Even Address Byte Access). Figure 6.16 Timing 16-Bit, 3-State Access Space (Odd Address Byte Access) Figure 6.17 Timing 16-Bit, 3-State Access Space (Word Access) Figure 6.18 Example Wait State Insertion Timing Figure 6.19 Example Read Strobe Timing Figure 6.20 Example Timing when Chip Select Assertion Period Extended Figure 6.21 DRAM Basic Access Timing (RAST CAST Figure 6.22 Example Access Timing with 3-State Column Address Output Cycle (RAST Figure 6.23 Example Access Timing when Signal Goes from Beginning State (CAST Figure 6.24 Example Timing with Address Output Maintenance State (RAST CAST Figure 6.25 Example Timing with Two-State Precharge Cycle (RAST CAST Figure 6.26 Example Wait State Insertion Timing (2-State Column Address Output) Figure 6.27 Example Wait State Insertion Timing (3-State Column Address Output) Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST CAST Figure 6.29 Example 2-CAS DRAM Connection Figure 6.30 Operation Timing Fast Page Mode (RAST CAST Figure 6.31 Operation Timing Fast Page Mode (RAST CAST Figure 6.32 Example Operation Timing Down Mode (RAST CAST
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Figure Figure Figure Figure Section Figure Figure Figure
Figure 6.33 Figure 6.34 Figure 6.35 Figure 6.36 Figure 6.37 Figure 6.38 Figure 6.39 Figure 6.40 Figure 6.41 Figure 6.42 Figure 6.43 Figure 6.44 Figure 6.45 Figure 6.46 Figure 6.47 Figure 6.48 Figure 6.49 Figure 6.50 Figure 6.51 Figure 6.52 Figure 6.53 Figure 6.54 Figure 6.55 Figure 6.56 Figure 6.57 Figure 6.58 Figure 6.59 Figure 6.60 Figure 6.61 Figure 6.62 Figure 6.63 Figure 6.64
Example Operation Timing Mode (RAST CAST 0).187 RTCNT Operation .188 Compare Match Timing .188 Refresh Timing .189 Refresh Timing (RCW1 RCW0 RLW1 RLW0 0).189 Example Refresh Timing (CBRM .190 Self-Refresh Timing .191 Example Timing when Precharge Time after Self-Refreshing Extended States.192 Example DACK/EDACK Output Timing when EDDS (RAST CAST .193 Example DACK/EDACK Output Timing when EDDS (RAST CAST .194 Relationship between SDRAM (when frequency multiplication factor .199 Basic Access Timing Synchronous DRAM (CAS Latency .200 Latency Control Timing (SDWCD Latency .202 Example Access Timing when Address Output Hold State State (RCD1 RCD0 SDWCD Latency .204 Example Timing with Two-State Precharge Cycle (TPC1 TPC0 SDWCD Latency 2).206 Example Write Access Timing when Latency Control Cycle Disabled (SDWCD .207 DQMU DQML Control Timing (Upper Byte Write Access: SDWCD Latency 2).208 DQMU DQML Control Timing (Lower Byte Read Access: Latency .209 Example DQMU DQML Byte Control .210 Operation Timing Burst Access SDWCD Latency .212 Example Operation Timing Down Mode Latency 2).213 Auto Refresh Timing.215 Auto Refresh Timing (TPC TPC0 RCW1 RCW0 .216 Auto Refresh Timing (TPC TPC0 RLW1 RLW0 .217 Self-Refresh Timing (TPC1 TPC0 RCW1 RCW0 RLW1 RLW0 .218 Example Timing when Precharge Time after Self-Refreshing Extended States (TPCS2 TPCS0 H'2, TPC1 TPC0 Latency .219 Synchronous DRAM Mode Setting Timing .220 Example DACK/EDACK Output Timing when EDDS .222 Example DACK/EDACK Output Timing when EDDS .224 Example Timing when Read Data Extended States (DDS EDDS RDXC1 RDXC0 Latency 2).225 Example Burst Access Timing (ASTn 2-State Burst Cycle).227 Example Burst Access Timing (ASTn 1-State Burst Cycle).228
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Example Idle Cycle Operation (Consecutive Reads Different Areas) Example Idle Cycle Operation (Write after Read) Example Idle Cycle Operation (Read after Write) Relationship between Chip Select (CS) Read (RD). Example DRAM Full Access after External Read (CAST Example Idle Cycle Operation Down Mode (Consecutive Reads Different Areas) (IDLC RAST CAST Figure 6.71 Example Idle Cycle Operation Down Mode (Write after Read) (IDLC RAST CAST Figure 6.72 Example Synchronous DRAM Full Access after External Read (CAS Latency Figure 6.73 Example Idle Cycle Operation Down Mode (Read Different Area) (IDLC Latency Figure 6.74 Example Idle Cycle Operation Down Mode (Read Different Area) (IDLC Latency Figure 6.75 Example Idle Cycle Operation Down Mode (Write after Read) (IDLC Latency Figure 6.76 Example Idle Cycle Operation after DRAM Access (Consecutive Reads Different Areas) (IDLC RAST CAST Figure 6.77 Example Idle Cycle Operation after DRAM Access (Write after Read) (IDLC RAST CAST Figure 6.78 Example Idle Cycle Operation after DRAM Write Access (IDLC ICIS1 RAST CAST Figure 6.79 Example Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC Latency Figure 6.80 Example Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC ICIS1 SDWCD Latency Figure 6.81 Example Timing Idle Cycle Insertion Case Consecutive Read Write Accesses DRAM Space Down Mode Figure 6.82 Example Timing Idle Cycle Insertion Case Consecutive Read Write Accesses Continuous Synchronous DRAM Space Down Mode (SDWCD Latency Figure 6.83 Example Timing when Write Data Buffer Function Used Figure 6.84 Released State Transition Timing Figure 6.85 Release State Transition Timing when Synchronous DRAM Interface Section Controller (DMAC) Figure Block Diagram DMAC Figure Areas Register Re-Setting (Channel Figure Operation Sequential Mode. Figure Example Sequential Mode Setting Procedure Figure Operation Idle Mode
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Figure 6.65 Figure 6.66 Figure 6.67 Figure 6.68 Figure 6.69 Figure 6.70
Figure Example Idle Mode Setting Procedure.290 Figure Operation Repeat mode .292 Figure Example Repeat Mode Setting Procedure.293 Figure Operation Single Address Mode (When Sequential Mode Specified).295 Figure 7.10 Example Single Address Mode Setting Procedure (When Sequential Mode Specified).296 Figure 7.11 Operation Normal Mode.298 Figure 7.12 Example Normal Mode Setting Procedure.299 Figure 7.13 Operation Block Transfer Mode (BLKDIR .301 Figure 7.14 Operation Block Transfer Mode (BLKDIR .302 Figure 7.15 Operation Flow Block Transfer Mode.303 Figure 7.16 Example Block Transfer Mode Setting Procedure .304 Figure 7.17 Example Transfer Timing .305 Figure 7.18 Example Short Address Mode Transfer .306 Figure 7.19 Example Full Address Mode Transfer (Cycle Steal).307 Figure 7.20 Example Full Address Mode Transfer (Burst Mode).308 Figure 7.21 Example Full Address Mode Transfer (Block Transfer Mode).309 Figure 7.22 Example DREQ Falling Edge Activated Normal Mode Transfer.310 Figure 7.23 Example DREQ Falling Edge Activated Block Transfer Mode Transfer .311 Figure 7.24 Example DREQ Level Activated Normal Mode Transfer.312 Figure 7.25 Example DREQ Level Activated Block Transfer Mode Transfer .313 Figure 7.26 Example Single Address Mode Transfer (Byte Read) .314 Figure 7.27 Example Single Address Mode (Word Read) Transfer.314 Figure 7.28 Example Single Address Mode Transfer (Byte Write) .315 Figure 7.29 Example Single Address Mode Transfer (Word Write) .316 Figure 7.30 Example DREQ Falling Edge Activated Single Address Mode Transfer.317 Figure 7.31 Example DREQ Level Activated Single Address Mode Transfer.318 Figure 7.32 Example Dual Address Transfer Using Write Data Buffer Function.319 Figure 7.33 Example Single Address Transfer Using Write Data Buffer Function .320 Figure 7.34 Example Multi-Channel Transfer.321 Figure 7.35 Example Procedure Continuing Transfer Channel Interrupted Interrupt.322 Figure 7.36 Example Procedure Forcibly Terminating DMAC Operation .323 Figure 7.37 Example Procedure Clearing Full Address Mode .324 Figure 7.38 Block Diagram Transfer End/Transfer Break Interrupt .325 Figure 7.39 DMAC Register Update Timing.326 Figure 7.40 Contention between DMAC Register Update Read.326 Figure 7.41 Example Which Level Output TEND .328 Section EXDMA Controller Figure Block Diagram EXDMAC .332 Figure Example Timing Dual Address Mode.347 Figure Data Flow Single Address Mode.348 Figure Example Timing Single Address Mode .349
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Figure Example Timing Cycle Steal Mode Figure Examples Timing Burst Mode Figure Examples Timing Normal Transfer Mode Figure Example Timing Block Transfer Mode Figure Example Repeat Area Function Operation. Figure 8.10 Example Repeat Area Function Operation Block Transfer Mode Figure 8.11 EDTCR Update Operations Normal Transfer Mode Block Transfer Mode Figure 8.12 Procedure Changing Register Settings Operating Channel Figure 8.13 Example Channel Priority Timing Figure 8.14 Examples Channel Priority Timing. Figure 8.15 Example Normal Transfer Mode (Cycle Steal Mode) Transfer Figure 8.16 Example Normal Transfer Mode (Burst Mode) Transfer. Figure 8.17 Example Block Transfer Mode (Cycle Steal Mode) Transfer. Figure 8.18 Example Normal Mode Transfer Activated EDREQ Falling Edge Figure 8.19 Example Block Transfer Mode Transfer Activated EDREQ Falling Edge Figure 8.20 Example Normal Mode Transfer Activated EDREQ Level Figure 8.21 Example Block Transfer Mode Transfer Activated EDREQ Level. Figure 8.22 Example Single Address Mode (Byte Read) Transfer Figure 8.23 Example Single Address Mode (Word Read) Transfer. Figure 8.24 Example Single Address Mode (Byte Write) Transfer Figure 8.25 Example Single Address Mode (Word Write) Transfer. Figure 8.26 Example Single Address Mode Transfer Activated EDREQ Falling Edge Figure 8.27 Example Single Address Mode Transfer Activated EDREQ Level Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode Contention/Dual Address Mode) Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode). Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/BGUP Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode Contention/Dual Address Mode/Low Level Sensing)
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Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing).378 Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode Contention/Single Address Mode/Falling Edge Sensing).378 Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing .379 Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode Contention/Dual Address Mode/Low Level Sensing/BGUP .380 Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode Contention/Single Address Mode/Falling Edge Sensing/BGUP 0).381 Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP 0).382 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP .383 Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP 1).384 Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing).385 Figure 8.45 Transfer Interrupt Logic.388 Figure 8.46 Example Procedure Restarting Transfer Channel which Transfer Interrupt Occurred .389 Section Data Transfer Controller (DTC) Figure Block Diagram .394 Figure Block Diagram Activation Source Control .399 Figure Correspondence between Vector Address Register Information .400 Figure Flowchart Operation.403 Figure Memory Mapping Normal Mode .405 Figure Memory Mapping Repeat Mode .406 Figure Memory Mapping Block Transfer Mode.407 Figure Operation Chain Transfer.408 Figure Operation Timing (Example Normal Mode Repeat Mode).409 Figure 9.10 Operation Timing (Example Block Transfer Mode, with Block Size .409 Figure 9.11 Operation Timing (Example Chain Transfer) .409 Figure 9.12 Chain Transfer when Counter .414 Section 16-Bit Timer Pulse Unit (TPU) Figure 11.1 Block Diagram TPU.504 Figure 11.2 Example Counter Operation Setting Procedure .539 Figure 11.3 Free-Running Counter Operation .540 Figure 11.4 Periodic Counter Operation .541 Figure 11.5 Example Setting Procedure Waveform Output Compare Match.541 Figure 11.6 Example Output/1 Output Operation .542 Figure 11.7 Example Toggle Output Operation .542
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Figure 11.8 Example Setting Procedure Input Capture Operation. Figure 11.9 Example Input Capture Operation. Figure 11.10 Example Synchronous Operation Setting Procedure Figure 11.11 Example Synchronous Operation. Figure 11.12 Compare Match Buffer Operation. Figure 11.13 Input Capture Buffer Operation. Figure 11.14 Example Buffer Operation Setting Procedure. Figure 11.15 Example Buffer Operation (1). Figure 11.16 Example Buffer Operation (2). Figure 11.17 Cascaded Operation Setting Procedure Figure 11.18 Example Cascaded Operation (1). Figure 11.19 Example Cascaded Operation (2). Figure 11.20 Example Mode Setting Procedure Figure 11.21 Example Mode Operation Figure 11.22 Example Mode Operation Figure 11.23 Example Mode Operation Figure 11.24 Example Phase Counting Mode Setting Procedure. Figure 11.25 Example Phase Counting Mode Operation Figure 11.26 Example Phase Counting Mode Operation Figure 11.27 Example Phase Counting Mode Operation Figure 11.28 Example Phase Counting Mode Operation Figure 11.29 Phase Counting Mode Application Example. Figure 11.30 Count Timing Internal Clock Operation. Figure 11.31 Count Timing External Clock Operation. Figure 11.32 Output Compare Output Timing Figure 11.33 Input Capture Input Signal Timing. Figure 11.34 Counter Clear Timing (Compare Match) Figure 11.35 Counter Clear Timing (Input Capture) Figure 11.36 Buffer Operation Timing (Compare Match). Figure 11.37 Buffer Operation Timing (Input Capture) Figure 11.38 Interrupt Timing (Compare Match) Figure 11.39 Interrupt Timing (Input Capture) Figure 11.40 TCIV Interrupt Setting Timing. Figure 11.41 TCIU Interrupt Setting Timing. Figure 11.42 Timing Status Flag Clearing Figure 11.43 Timing Status Flag Clearing DTC/DMAC Activation Figure 11.44 Phase Difference, Overlap, Pulse Width Phase Counting Mode Figure 11.45 Contention between TCNT Write Clear Operations. Figure 11.46 Contention between TCNT Write Increment Operations Figure 11.47 Contention between Write Compare Match. Figure 11.48 Contention between Buffer Register Write Compare Match Figure 11.49 Contention between Read Input Capture Figure 11.50 Contention between Write Input Capture
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Figure 11.51 Contention between Buffer Register Write Input Capture.577 Figure 11.52 Contention between Overflow Counter Clearing.577 Figure 11.53 Contention between TCNT Write Overflow.578 Section Programmable Pulse Generator (PPG) Figure 12.1 Block Diagram .580 Figure 12.2 Overview Diagram PPG.589 Figure 12.3 Timing Transfer Output Contents (Example) .590 Figure 12.4 Setup Procedure Normal Pulse Output (Example).591 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) .592 Figure 12.6 Non-Overlapping Pulse Output .593 Figure 12.7 Non-Overlapping Operation Write Timing .594 Figure 12.8 Setup Procedure Non-Overlapping Pulse Output (Example).594 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary).595 Figure 12.10 Inverted Pulse Output (Example) .596 Figure 12.11 Pulse Output Triggered Input Capture (Example) .597 Section 8-Bit Timers (TMR) Figure 13.1 Block Diagram 8-Bit Timer Module .600 Figure 13.2 Example Pulse Output.608 Figure 13.3 Count Timing Internal Clock Input.608 Figure 13.4 Count Timing External Clock Input.609 Figure 13.5 Timing Setting .609 Figure 13.6 Timing Timer Output .610 Figure 13.7 Timing Compare Match Clear.610 Figure 13.8 Timing Clearance External Reset.611 Figure 13.9 Timing Setting.611 Figure 13.10 Contention between TCNT Write Clear .614 Figure 13.11 Contention between TCNT Write Increment.615 Figure 13.12 Contention between TCOR Write Compare Match .616 Section Watchdog Timer Figure 14.1 Block Diagram .622 Figure 14.2 Operation Watchdog Timer Mode.627 Figure 14.3 Operation Interval Timer Mode.628 Figure 14.4 Writing TCNT, TCSR, RSTCSR.629 Figure 14.5 Contention between TCNT Write Increment.630 Figure 14.6 Circuit System Reset WDTOVF Signal (Example) .631 Section Serial Communication Interface (SCI, IrDA) Figure 15.1 Block Diagram .635 Figure 15.2 Data Format Asynchronous Communication (Example with 8-Bit Data, Parity, Stop Bits) .661 Figure 15.3 Receive Data Sampling Timing Asynchronous Mode .663 Figure 15.4 Relation between Output Clock Transfer Data Phase (Asynchronous Mode) .664 Figure 15.5 Sample Initialization Flowchart .665
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Figure 15.6 Example Operation Transmission Asynchronous Mode (Example with 8-Bit Data, Parity, Stop Bit). Figure 15.7 Sample Serial Transmission Flowchart Figure 15.8 Example Operation Reception (Example with 8-Bit Data, Parity, Stop Bit). Figure 15.9 Sample Serial Reception Data Flowchart Figure 15.9 Sample Serial Reception Data Flowchart Figure 15.10 Example Communication Using Multiprocessor Format (Transmission Data H'AA Receiving Station Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Figure 15.12 Example Operation Reception (Example with 8-Bit Data, Multiprocessor Bit, Stop Bit) Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1). Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2). Figure 15.14 Data Format Clocked Synchronous Communication (For LSB-First) Figure 15.15 Sample Initialization Flowchart Figure 15.16 Sample Transmission Operation Clocked Synchronous Mode Figure 15.17 Sample Serial Transmission Flowchart Figure 15.18 Example Operation Reception Figure 15.19 Sample Serial Reception Flowchart Figure 15.20 Sample Flowchart Simultaneous Serial Transmit Receive Operations Figure 15.21 Schematic Diagram Smart Card Interface Connections. Figure 15.22 Normal Smart Card Interface Data Format Figure 15.23 Direct Convention (SDIR SINV Figure 15.24 Inverse Convention (SDIR SINV Figure 15.25 Receive Data Sampling Timing Smart Card Mode (Using Clock Times Rate). Figure 15.26 Retransfer Operation Transmit Mode. Figure 15.27 TEND Flag Generation Timing Transmission Operation Figure 15.28 Example Transmission Processing Flow. Figure 15.29 Retransfer Operation Receive Mode Figure 15.30 Example Reception Processing Flow Figure 15.31 Timing Fixing Clock Output Level. Figure 15.32 Clock Halt Restart Procedure Figure 15.33 Block Diagram IrDA. Figure 15.34 IrDA Transmit/Receive Operations. Figure 15.35 Example Synchronous Transmission Using DTC. Figure 15.36 Sample Flowchart Mode Transition during Transmission. Figure 15.37 Port States during Mode Transition (Internal Clock, Asynchronous Transmission) Figure 15.38 Port States during Mode Transition (Internal Clock, Synchronous Transmission). Figure 15.39 Sample Flowchart Mode Transition during Reception
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Section Converter Figure 16.1 Block Diagram Converter .710 Figure 16.2 Conversion Timing .722 Figure 16.3 External Trigger Input Timing .724 Figure 16.4 Conversion Accuracy Definitions.725 Figure 16.5 Conversion Accuracy Definitions.726 Figure 16.6 Example Analog Input Circuit .727 Figure 16.7 Example Analog Input Protection Circuit .729 Figure 16.8 Analog Input Equivalent Circuit .729 Section Converter Figure 17.1 Block Diagram Converter .732 Figure 17.2 Example Converter Operation.738 Section Flash Memory (F-ZTAT Version) Figure 19.1 Block Diagram Flash Memory .742 Figure 19.2 Flash Memory State Transitions.743 Figure 19.3 Boot Mode.744 Figure 19.4 User Program Mode .745 Figure 19.5 384-Kbyte Flash Memory Block Configuration (Modes 7).747 Figure 19.6 256-Kbyte Flash Memory Block Configuration (Modes 11).748 Figure 19.7 Programming/Erasing Flowchart Example User Program Mode .759 Figure 19.8 Flowchart Flash Memory Emulation .760 Figure 19.9 Example Overlap Operation.761 Figure 19.10 Program/Program-Verify Flowchart.763 Figure 19.11 Erase/Erase-Verify Flowchart .765 Figure 19.12 Power-On/Off Timing (H8S/2678 Series).770 Figure 19.13 Power-On/Off Timing (H8S/2678R Series) .771 Figure 19.14 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) .772 Section Masked Figure 20.1 Block Diagram 256-Kbyte Masked (HD6432676) .775 Figure 20.2 Block Diagram 128-Kbyte Masked (HD6432675) .775 Figure 20.3 Block Diagram 64-Kbyte Masked (HD643673) .776 Section Clock Pulse Generator Figure 21.1 Block Diagram Clock Pulse Generator .777 Figure 21.2 Connection Crystal Resonator (Example) .780 Figure 21.3 Crystal Resonator Equivalent Circuit .780 Figure 21.4 External Clock Input (Examples) .781 Figure 21.5 External Clock Input Timing.782 Figure 21.6 Note Board Design Oscillation Circuit .784 Figure 21.7 Recommended External Circuitry Circuit.784 Section Power-Down Modes Figure 22.1 Mode Transitions.787 Figure 22.2 Software Standby Mode Application Example .794
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Figure 22.3 Hardware Standby Mode Timing Section Electrical Characteristics Figure 24.1 Output Load Circuit. Figure 24.2 System Clock Timing Figure 24.3 SDRAM Timing* Figure 24.4 Oscillation Stabilization Timing Figure 24.4 Oscillation Stabilization Timing Figure 24.5 Reset Input Timing. Figure 24.6 Interrupt Input Timing. Figure 24.7 Basic Timing: Two-State Access Figure 24.8 Basic Timing: Three-State Access Figure 24.9 Basic Timing: Three-State Access, Wait Figure 24.10 Basic Timing: Two-State Access Assertion Period Extended) Figure 24.11 Basic Timing: Three-State Access Assertion Period Extended) Figure 24.12 Burst Access Timing: One-State Burst Access. Figure 24.13 Burst Access Timing: Two-State Burst Access. Figure 24.14 DRAM Access Timing: Two-State Access Figure 24.15 DRAM Access Timing: Two-State Access, Wait. Figure 24.16 DRAM Access Timing: Two-State Burst Access. Figure 24.17 DRAM Access Timing: Three-State Access (RAST Figure 24.18 DRAM Access Timing: Three-State Access, Wait. Figure 24.19 DRAM Access Timing: Three-State Burst Access. Figure 24.20 CAS-Before-RAS Refresh Timing Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST Figure 24.24 External Release Timing Figure 24.25 External Request Output Timing. Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency Figure 24.27 Synchronous DRAM Self-Refresh Timing Figure 24.28 Read Data: Two-State Expansion (CAS Latency Figure 24.29 DMAC EXDMAC Single Address Transfer Timing: Two-State Access. Figure 24.30 DMAC EXDMAC Single Address Transfer Timing: Three-State Access. Figure 24.31 DMAC EXDMAC TEND/ETEND Output Timing. Figure 24.32 DMAC EXDMAC DREQ/EDREQ Input Timing. Figure 24.33 EXDMAC EDRAK Output Timing Figure 24.34 Port Input/Output Timing. Figure 24.35 Output Timing. Figure 24.36 Input/Output Timing Figure 24.37 Clock Input Timing. Figure 24.38 8-Bit Timer Output Timing Figure 24.39 8-Bit Timer Clock Input Timing Figure 24.40 8-Bit Timer Reset Input Timing
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Figure 24.41 Output Timing .875 Figure 24.42 Clock Input Timing.875 Figure 24.43 Input/Output Timing: Synchronous Mode .875 Figure 24.44 Converter External Trigger Input Timing.875 Appendix Figure Package Dimensions (FP-144H).891 Figure Package Dimensions (FP-144G).892
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Tables
Section Table Table Section Table Table Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Section Table Table Section Table Table Table Table Section Table Table Table Table Table Section Table Table Table Table Table Table Overview Arrangement Each Operating Mode.7 Functions Instruction Classification Operation Notation Data Transfer Instructions Arithmetic Operations Instructions Arithmetic Operations Instructions Logic Operations Instructions.42 Shift Instructions Manipulation Instructions Manipulation Instructions Branch Instructions.45 System Control Instructions Block Data Transfer Instructions.47 Addressing Modes Absolute Address Access Ranges.50 Operating Modes Operating Mode Selection Functions Each Operating Mode.64 Exception Handling Exception Types Priority Exception Handling Vector Table Status after Trace Exception Handling Status after Trap Instruction Exception Handling.81 Interrupt Controller Configuration Interrupt Sources, Vector Addresses, Interrupt Priorities .103 Interrupt Control Modes .107 Interrupt Response Times .112 Number States Interrupt Handling Routine Execution Statuses.113 Controller (BSC) Configuration .121 Specifications Each Area (Basic Interface) .153 Data Buses Used Valid Strobes .158 Relation between Settings Bits RMTS2 RMTS0 DRAM Space .171 Relation between Settings Bits MXC2 MXC0 Address Multiplexing .172 DRAM Interface Pins .173
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Table
Relation between Settings Bits RMTS2 RMTS0 Synchronous DRAM Space. Table Relation between Settings Bits MXC2 MXC0 Address Multiplexing Table Synchronous DRAM Interface Pins Table 6.10 Setting Latency Table 6.11 Idle Cycles Mixed Accesses Normal Space DRAM Continuous Synchronous DRAM Space Table 6.12 States Idle Cycle. Table 6.13 States Released State. Section Controller (DMAC) Table Configuration Table DMAC Activation Sources. Table DMAC Transfer Modes. Table Register Functions Sequential Mode. Table Register Functions Idle Mode Table Register Functions Repeat Mode. Table Register Functions Single Address Mode Table Register Functions Normal Mode Table 7.10 Register Functions Block Transfer Mode. Table 7.11 DMAC Channel Priority Order Table 7.12 Interrupt Sources Priority Order Section EXDMA Controller Table Configuration Table EXDMAC Transfer Modes Table EXDMAC Channel Priority Order Table Interrupt Sources Priority Order Section Data Transfer Controller (DTC) Table Interrupt Sources, Vector Addresses, Corresponding DTCEs Table Chain Transfer Conditions. Table Register Function Normal Mode Table Register Function Repeat Mode Table Register Function Block Transfer Mode Table Execution Status Table Number States Required Each Execution Status Section Ports Table 10.1 Port Functions. Table 10.2 Input Pull-Up States (Port Table 10.3 Input Pull-Up States (Port Table 10.4 Input Pull-Up States (Port Table 10.5 Input Pull-Up States (Port Table 10.6 Input Pull-Up States (Port Section 16-Bit Timer Pulse Unit (TPU) Table 11.1 Functions.
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Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 Table 11.7 Table 11.8 Table 11.9 Table 11.10 Table 11.11 Table 11.12 Table 11.13 Table 11.14 Table 11.15 Table 11.16 Table 11.17 Table 11.18 Table 11.19 Table 11.20 Table 11.21 Table 11.22 Table 11.23 Table 11.24 Table 11.25 Table 11.26 Table 11.27 Table 11.28 Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Section Table 12.1 Section Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5
Configuration .505 CCLR2 CCLR0 (Channels .509 CCLR2 CCLR0 (Channels .509 TPSC2 TPSC0 (Channel .510 TPSC2 TPSC0 (Channel .510 TPSC2 TPSC0 (Channel .511 TPSC2 TPSC0 (Channel .511 TPSC2 TPSC0 (Channel .512 TPSC2 TPSC0 (Channel .512 .514 TIORH_0.516 TIORL_0 .517 TIOR_1.518 TIOR_2.519 TIORH_3.520 TIORL_3 .521 TIOR_4.522 TIOR_5.523 TIORH_0.524 TIORL_0 .525 TIOR_1.526 TIOR_2.527 TIORH_3.528 TIORL_3 .529 TIOR_4.530 TIOR_5.531 Register Combinations Buffer Operation .546 Cascaded Combinations .549 Output Registers Output Pins .552 Clock Input Pins Phase Counting Mode.556 Up/Down-Count Conditions Phase Counting Mode .557 Up/Down-Count Conditions Phase Counting Mode .558 Up/Down-Count Conditions Phase Counting Mode .559 Up/Down-Count Conditions Phase Counting Mode .560 Interrupts .563 Programmable Pulse Generator (PPG) Configuration .581 8-Bit Timers (TMR) Configuration .601 Clock Input TCNT Count Condition .604 8-Bit Timer Interrupt Sources.613 Timer Output Priorities.616 Switching Internal Clock TCNT Operation.618
Rev. 2.0, 04/02, page xliv
Section Watchdog Timer Table 14.1 configuration Table 14.2 Interrupt Source. Section Serial Communication Interface (SCI, IrDA) Table 15.1 Configuration Table 15.2 Relationships between Setting Rate Table 15.3 Settings Various Rates (Asynchronous Mode) (1). Table 15.3 Settings Various Rates (Asynchronous Mode) (2). Table 15.3 Settings Various Rates (Asynchronous Mode) (3). Table 15.3 Settings Various Rates (Asynchronous Mode) (4). Table 15.4 Maximum Rate Each Frequency (Asynchronous Mode) Table 15.5 Maximum Rate with External Clock Input (Asynchronous Mode) Table 15.6 Settings Various Rates (Clocked Synchronous Mode) Table 15.7 Maximum Rate with External Clock Input (Clocked Synchronous Mode) Table 15.8 Examples Rate Various Settings (Smart Card Interface Mode) (when 372). Table 15.9 Maximum Rate Various Frequencies (Smart Card Interface Mode) (when 372). Table 15.10 Serial Transfer Formats (Asynchronous Mode) Table 15.11 Status Flags Receive Data Handling. Table 15.12 Settings Bits IrCKS2 IrCKS0. Table 15.13 Interrupt Sources Table 15.14 Interrupt Sources Section Converter Table 16.1 Converter Pins Table 16.2 Analog Input Channels Corresponding ADDR Registers. Table 16.3 Conversion Time (Single Mode) Table 16.4 Conversion Time (Scan Mode). Table 16.5 Converter Interrupt Source Table 16.6 Analog Specifications Section Converter Table 17.1 Configuration Table 17.2 Control Conversion Table 17.3 Control Conversion Section Flash Memory (F-ZTAT Version) Table 19.1 Differences between Boot Mode User Program Mode Table 19.2 Configuration Table 19.3 Erase Blocks Table 19.4 Setting On-Board Programming Modes Table 19.5 Boot Mode Operation Table 19.6 System Clock Frequencies which Automatic Adjustment Rate Possible Table 19.7 Flash Memory Operating States
Rev. 2.0, 04/02, page xlii xliv
Section Table 21.1 Table 21.2 Table 21.3 Section Table 22.1 Table 22.2 Table 22.3 Section Table 24.1 Table 24.2 Table 24.3 Table 24.4 Table 24.5 Table 24.6 Table 24.7 Table 24.8 Table 24.9 Table 24.10 Table 24.11 Table 24.12 Table 24.13
Clock Pulse Generator Damping Resistance Value.780 Crystal Resonator Characteristics.780 External Clock Input Conditions .782 Power-Down Modes Operating Modes .786 Oscillation Stabilization Time Settings .793 State Each Processing State.796 Electrical Characteristics Absolute Maximum Ratings .835 Characteristics.836 Characteristics.838 Permissible Output Currents.839 Clock Timing.841 Control Signal Timing .844 Timing .846 Timing .847 DMAC EXDMAC Timing .868 Timing On-Chip Peripheral Modules.872 Conversion Characteristics .876 Conversion Characteristics .876 Flash Memory Characteristics .877
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Rev. 2.0, 04/02, page xliv xliv
Section Overview
Features
High-speed H8S/2600 central processing unit with internal 16-bit architecture Upward-compatible with H8/300 H8/300H CPUs object level Sixteen 16-bit general registers basic instructions Various peripheral functions controller (DMAC) EXDMA controller (EXDMAC) Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous clocked synchronous serial communication interface (SCI) 10-bit converter 8-bit converter Clock pulse generator On-chip memory
Type Flash memory Version Masked version Model HD64F2676 HD6432676 HD6432675 HD6432673 ROMless version HD6412674R HD6412670 kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes Remarks
General ports pins: Input-only pins: Supports various power-down states Compact package
Rev. 2.0, 04/02, page
Product H8S/2678 Series H8S/2678R Series
Package QFP-144 LQFP-144
(Code) FP-144G FP-144H
Mounting Height 3.05 (Max.) 1.70 (Max.)
Body Size 22.0 22.0 22.0 22.0
Pitch
Rev. 2.0, 04/02, page
Block Diagram
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8
PLLVcc PLLVss
Port
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Port
H8S/2600
controller
FWE*2 PF6/ PF5/ PF4/ PF3/ PF0/
Clock pulse generator
Internal data
Internal address
EXTAL XTAL
/A23 /A22 /A21 /A20 /A19 /A18 /A17 /A16 /A15 /A14 /A13 /A12 /A10
PF2/ PF1/
EXDMAC
PG6/ PG5/ PG4/ PG3/ PG2/ PG1/ PG0/ P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/ P61/TMRI1/ P60/TMRI0/ P85/ P84/ P83/ P82/ P81/ P80/
Port
Port
Port
ROM*1 (Flash memory mask ROM)
DMAC
Peripheral address
Interrupt controller
Port
Peripheral data
Port
Port
channels
Port
channels
channels
P35/SCK1/( P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P57/AN15/DA3/ P56/AN14/DA2/ P55/AN13/ P54/AN12/ P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/
Port
10-bit converter
Port
Port
Port
Port
8-bit converter
Port
Port
Vref AVcc AVss
P10/ TIOCA0 TIOCB0 PO10 TIOCC0 TCLKA PO11 TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2/ PO15 TIOCB2 TCLKD/
/PO0 TIOCA3/( /PO1 TIOCB3/( /PO2 TIOCC3 /PO3 TIOCD3 /PO4 TIOCA4 /PO5 TIOCB4 /PO6 TIOCA5 /PO7 TIOCB5
Notes:
supported ROMless version. used only F-ZTAT version. other versions, this pin.
Figure H8S/2678 Series Internal Block Diagram
Rev. 2.0, 04/02, page
PH3/ PH2/
PH1/ PH0/
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8
PLLVcc PLLVss
Port
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Port
H8S/2600
Clock pulse generator
Internal address
Internal data
DCTL EXTAL XTAL
PA7/A23 PA6/A22 PA5/A21 PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/( )/(CKE) P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P57/AN15/DA3/ P56/AN14/DA2/ P55/AN13/ P54/AN12/ P53/ P52/SCK2/ P51/RxD2/ P50/TxD2/
PF7/ PF6/ PF5/ PF4/ PF3/ /DQML /DQMU PF0/
controller
DMAC ROM* (Flash memory)
PF2/ PF1/
Peripheral address
Interrupt controller
Peripheral data
Port
PG3/ PG2/
PG6/ PG5/ PG4/ PG1/ PG0/
Port
EXDMAC
Port Port
P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/ P61/TMRI1/ P60/TMRI0/ P85/ P84/ P83/ P82/ P81/ P80/
channels
Port
channels
channels
8-bit converter
Port
10-bit converter
Port
Port
Port
Port
Port
Port
Port
Port
Vref AVcc AVss
P10/ TIOCA0 TIOCB0 PO10 TIOCC0 TCLKA PO11 /TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2/ PO15 TIOCB2 TCLKD/
TIOCA3/( TIOCB3/( TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Note: supported ROMless version.
Figure H8S/2678R Series Internal Block Diagram
Rev. 2.0, 04/02, page
PH3/
PH1/
)/CKE PH2/ /SDRAM PH0/
1.3.1
Description
Arrangement
PLLVss PF6/ PF5/ PF4/ PF3/ PF2/ PF1/ PF0/ P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/ PD0/ PD1/ PD2/ PD3/ PD4/ PD5/ PD6/
P51/RxD2/ P50/TxD2/ PH1/ PH0/ PG3/ PG2/ PG1/ PG0/
PLLVcc
XTAL EXTAL
PF7/
P52/SCK2/ P53/ PH2/ PH3/ PG4/ PG5/ PG6/
P83/ P84/ P85/
Notes: used only F-ZTAT version. other versions, this pin. should unconnected.
Figure H8S/2678 Series Arrangement
P70/ P71/ P72/
PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 NC*2
P40/ P41/ P42/ P43/ Vref AVcc P44/ P45/ P46/AN6/ P47/AN7/ P54/AN12/ P55/AN13/ P56/AN14/DA2/ P57/AN15/DA3/ AVss NC*2 P35/SCK1/( P34/ SCK0 P33/ RxD1 P32/RxD0/IrRxD P31/ TxD1 P30/TxD0/IrTxD P80/ P81/ P82/
FP-144G (Top view)
PD7/ PE0/ PE1/ PE2/ PE3/ PE4/ PE5/ PE6/ PE7/ FWE*1 P61/TMRI1/ P60/TMRI0/ P27/ PO7/ TIOCB5/ P26/ PO6/ TIOCA5/ P25/ PO5/TIOCB4/( P24/ PO4/TIOCA4/( P23/ PO3/TIOCD3/( P22/ PO2/TIOCC3/( P21/PO1/TIOCB3/( P20/PO0/TIOCA3/( P17/ PO15/TIOCB2/TCLKD/ P16/PO14/TIOCA2/ P15/ PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/ PO11/TIOCD0/TCLKB P12/ PO10/TIOCC0/TCLKA P11/ PO9/TIOCB0 P10/ PO8/TIOCA0 P75/ P74/ P73/
Rev. 2.0, 04/02, page
/SDRAM
/DQML /DQMU XTAL EXTAL PF7/ PLLVcc
PLLVss PF6/ PF5/ PF4/ PF3/ PF2/ PF1/ PF0/ P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/
P51/RxD2/ P50/TxD2/ PH1/ PH0/ PG3/ PG2/ PG1/ PG0/
P52/SCK2/ P53/ PH2/ PH3/ PG4/ PG5/ PG6/
Note:
should unconnected.
Figure H8S/2678R Series Arrangement
Rev. 2.0, 04/02, page
PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23
P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/ P55/AN13/ P56/AN14/DA2/ P57/AN15/DA3/ AVss DCTL P35/SCK1/( )/(CKE) P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/ P81/ P82/
FP-144H (Top view)
PD7/D15 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 P61/TMRI1/ P60/TMRI0/ P27/PO7/TIOCB5/ P26/PO6/TIOCA5/ P25/PO5/TIOCB4/( P24/PO4/TIOCA4/( P23/PO3/TIOCD3/( P22/PO2/TIOCC3/( P21/PO1/TIOCB3/( P20/PO0/TIOCA3/( P17/PO15/TIOCB2/TCLKD/ P16/PO14/TIOCA2/ P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 P75/ P74/ P73/
1.3.2 Table
Arrangement Each Operating Mode Arrangement Each Operating Mode
Name Mode Modes Modes P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 Mode P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 P85/(IRQ5) P84/(IRQ4) EXPE P83/(IRQ3) EXPE Flash Memory Programmer Mode
P83/ETEND3/ (IRQ3)
P84/EDACK2/ (IRQ4)
P85/EDACK3/ (IRQ5)
Rev. 2.0, 04/02, page
Modes PA5/A21 PA6/A22 PA7/A23 P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 Modes PA5/A21 PA6/A22 PA7/A23 P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2
Name Mode Mode PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 EXPE PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2 P75/(DACK1) P74/(DACK0) WDTOVF P73/(TEND1) P72/(TEND0) P71/(DREQ1) P70/(DREQ0) EXPE Flash Memory Programmer Mode
Rev. 2.0, 04/02, page
Modes P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*
Name Mode Modes P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*
Flash Memory EXPE Programmer Mode
Mode P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*
EXPE P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*
P17/PO15/ TIOCB2/TCLKD
P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/(IRQ14)
P27/PO7/ TIOCB5/(IRQ15)
P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*
FWE*1 Vss*2 I/O7
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Rev. 2.0, 04/02, page
Modes P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU* PF2/LCAS/ IRQ15/DQML* PF3/LWR PF6/AS PLLVss PLLVcc PF7/ EXTAL XTAL STBY
Name Mode Modes P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU* PF2/LCAS/ IRQ15/DQML* PF3/LWR PF6/AS PLLVss PLLVcc PF7/ EXTAL XTAL STBY
Flash Memory EXPE Programmer Mode I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Mode P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU* PF2/LCAS/ IRQ15/DQML* PF3/LWR PF6/AS PLLVss PLLVcc PF7/ EXTAL XTAL STBY
EXPE P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU* PF2/LCAS/ IRQ15/DQML* PF3/LWR PF6/AS PLLVss PLLVcc PF7/ EXTAL XTAL STBY
P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF1/IRQ14
PF2/IRQ15
PLLVss PLLVcc PF7/ EXTAL XTAL STBY
EXTAL XTAL
Rev. 2.0, 04/02, page
Modes PG0/CS0 PG1/CS1 PG2/CS2/ RAS2* /RAS*
Name Mode Modes PG0/CS0 PG1/CS1 PG2/CS2/ RAS2* /RAS*
Flash Memory EXPE Programmer Mode
Mode PG0/CS0 PG1/CS1 PG2/CS2/ RAS2* /RAS*
EXPE PG0/CS0 PG1/CS1 PG2/CS2/ RAS2* /RAS*
PG3/CS3/ RAS3* /CAS*
PG3/CS3/ RAS3* /CAS*
PG3/CS3/ RAS3* /CAS*
PG3/CS3/ RAS3* /CAS*
PH0/CS4/ RAS4* /WE*
PH0/CS4/ RAS4* /WE*
PH0/CS4/ RAS4* /WE*
PH0/CS4/ RAS4* /WE*
PH1/CS5/ RAS5*
PH1/CS5/ RAS5*
PH1/CS5/ RAS5*
PH1/CS5/ RAS5*
SDRAM*
SDRAM*
SDRAM*
SDRAM*
P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3
P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*
P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*
P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*
P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH3/(IRQ7)
PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*
PG4/BREQO PG5/BACK PG6/BREQ P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4
PG4/BREQO PG5/BACK PG6/BREQ P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4
PG4/BREQO PG5/BACK PG6/BREQ P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4
PG4/BREQO PG5/BACK PG6/BREQ P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4
P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4
Rev. 2.0, 04/02, page
Modes P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss
Name Mode Modes P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss
Flash Memory EXPE Programmer Mode
Mode P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss
EXPE P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss
P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss
NC*3
DCTL*2 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2)
DCTL*2 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2)
DCTL*2 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2)
DCTL*2 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2)
DCTL*2 P35/SCK1
P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/(IRQ0)
P81/(IRQ1)
P82/(IRQ2)
Notes: used only flash memory version H8S/2678 Series. masked ROMless versions H8S/2678 Series, this pin. Only H8S/2678R Series. Only H8S/2678 Series.
Rev. 2.0, 04/02, page
1.3.3 Table
Functions Functions
FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input
Type Power
Symbol
Function connection power supply. pins should connected system power supply. connection ground. pins should connected system power supply Power supply on-chip oscillator. Ground on-chip oscillator. connection crystal oscillator. section Clock Pulse Generator typical connection diagrams crystal oscillator external clock input. connection crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator typical connection diagrams crystal oscillator external clock input.
Input
PLLVCC PLLVSS Clock XTAL
Input Input Input
EXTAL
Input
Output Supplies system clock external devices. Output When synchronous DRAM connected, this connected synchronous DRAM. details, refer section Controller. Input These pins operating mode. These pins should changed while operating.
SDRAM
Operating mode control
144, 144,
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FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input
Type Operating mode control
Symbol DCTL
Function When this driven high, SDRAM dedicated synchronous DRAM output. When using synchronous DRAM interface, drive this low. level this must changed during operation.
System control STBY
Input Input
When this driven low, chip reset. When this driven low, transition made hardware standby mode. Requests chip release external master.
BREQ BREQO
Input
Output External request signal used when internal master accesses external space when external released. Output Indicates that been released external master. Input Enables/disables flash memory. This only used flash memory version.
BACK
Address
Output These pins output address.
Data
Input/ output
These pins constitute bidirectional data bus.
control
112, 111, 112, 111,
Output Signals that select division areas external address space. Output When this low, indicates that address output address valid. Output When this low, indicates that external address space being read.
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FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series)
Type control
Symbol
Function
Output Strobe signal indicating that external address space written, upper half (D15 data enabled. Write enable signal DRAM interface space.
Output Strobe signal indicating that external address space written, lower half data enabled. Output Upper column address strobe signal 16-bit DRAM interface space. Column address strobe signal 8bit DRAM interface space.
UCAS
LCAS DQMU
Output Lower column address strobe signal 16-bit DRAM interface space. Output Upper data mask enable signal 16-bit synchronous DRAM 16-bit synchronous DRAM interface. Data mask enable signal 8-bit synchronous DRAM interface space.
DQML
Output Lower-data mask enable signal 16-bit synchronous DRAM interface space. Output address strobe signal synchronous DRAM interface. signal address strobe signal when areas continuous DRAM space.
RAS/RAS RAS3 RAS5
address strobe signal synchronous DRAM synchronous DRAM interface. Output Column address strobe signal synchronous DRAM synchronous DRAM interface. Output Write enable signal synchronous DRAM synchronous DRAM interface.
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FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input
Type control
Symbol WAIT
Function Requests insertion wait state cycle when accessing external 3-state address space.
(OE)
112,
112,
Output Output enable signal DRAM interface space. output pins (OE) selected port function control register (PFCR2) port
(CKE)
112,
Output Clock enable signal synchronous DRAM interface space. output pins (CKE) selected port function control register (PFCR2) port
Interrupt signals
127, 112, 111,
Input Input
Nonmaskable interrupt request pin. high when used. These pins request maskable interrupt. input pins DREQn (DREQn) selected select register (ITSR) interrupt controller.
IRQ15 IRQ0 127, (IRQ15) (IRQ0) 112, 111,
controller DREQ1 (DMAC) DREQ0 (DREQ1) (DREQ0)
Input
These signals request DMAC activation. input pins DREQn (DREQn) selected select register (ITSR) interrupt controller.
TEND1 TEND0 (TEND1) (TEND0)
Output These signals indicate DMAC data transfer. input pins TENDn (TENDn) selected port function control register (PFCR2) port
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FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series)
Type
Symbol
Function
controller DACK1 (DMAC) DACK0 (DACK1) (DACK0)
Output DMAC single address transfer acknowledge signals. input pins DACKn (DACKn) selected port function control register (PFCR2) port Input These signals request EXDMAC activation.
EXDMA controller (EXDMAC)
EDREQ3 141, 140, EDREQ0
141, 140,
ETEND3 142, 142, ETEND0 EDACK3 EDACK0 EDRAK3 EDRAK0 16-bit timer pulse unit (TPU) TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4
Output These signals indicate EXDMAC data transfer. Output EXDMAC single address transfer acknowledge signals. Output These signals notify external device acceptance start execution transfer request. Input External clock input pins.
Input/ output
TGRA_0 TGRD_0 input capture input/output compare output/PWM output pins. TGRA_1 TGRB_1 input capture input/output compare output/PWM output pins. TGRA_2 TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 TGRD_3 input capture input/output compare output/PWM output pins. TGRA_4 TGRB_4 input capture input/output compare output/PWM output pins.
Input/ output Input/ output Input/ output
Input/ output
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FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input/ output
Type 16-bit timer pulse unit (TPU)
Symbol
Function TGRA_5 TGRB_5 input capture input/output compare output/PWM output pins.
TIOCA5, TIOCB5
Programmable PO15 pulse generator (PPG) 8-bit timer TMO0 TMO1 TMCI0 TMCI1 TMRI0 TMRI1 Watchdog timer (WDT) Serial communication interface (SCI)/smart card interface (SCI_0 with IrDA function)
107, 138,
Output Pulse output pins.
Output Waveform output pins with output compare function. Input Input External event input pins. Counter reset input pins.
WDTOVF TxD2 107, 138, TxD1 TxD0/IrTx RxD2 RxD1 RxD0/ IrRxD SCK2 SCK1 SCK0 108, 135,
Output Counter overflow signal output watchdog timer mode. Output Data output pins.
108, 135,
Input
Data input pins.
109, 133,
109, 133,
Input/ output Input
Clock input/output pins.
converter
AN15 AN12, ADTRG
127, 127, 123, 123, 130, 129, 126, 130, 129, 126,
Analog input pins converter.
Input
input external trigger start conversion.
converter
Output Analog input pins converter. Input analog power-supply converter converter. When converter converter used, this should connected system power supply
converter, AVCC converter
Rev. 2.0, 04/02, page
FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input
Type
Symbol
Function ground converter converter. This should connected system power supply
converter, AVSS converter
Vref
Input
reference voltage input converter converter. When converter converter used, this should connected system power supply
ports
Input/ output Input/ output Input/ output Input Input
Eight input/output pins. Eight input/output pins. input/output pins. Eight input pins. Four input pins.
135, 135, 123, 123,
Input/ output
Four input/output pins.
Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output
input/output pins. input/output pins. input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins.
Rev. 2.0, 04/02, page
FP-144G FP-144H (H8S/2678 (H8S/2678R Series) Series) Input/ output Input/ output Input/ output Input/ output Input/ output
Type ports
Symbol
Function Eight input/output pins. Eight input/output pins. Eight input/output pins. Seven input/output pins. Four input/output pins.
113, 113, 112, 111, 106, 112, 111, 106,
Rev. 2.0, 04/02, page
Section
H8S/2600 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2600 sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. This section describes H8S/2600 CPU. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
Features
Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers also usable sixteen 8-bit registers eight 32-bit registers Sixty-nine basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes High-speed operation frequently-used instructions execute states 8/16/32-bit register-register add/subtract: state 8-bit register-register multiply: states 8-bit register-register divide: states 16-bit register-register multiply: states 16-bit register-register divide: states
CPUS260A_020020020400
Rev. 2.0, 04/02, page
operating modes Normal mode* Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection Note: Normal mode available this LSI. 2.1.1 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. number execution states MULXU MULXS instructions
Execution States Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
addition, there differences address space, register functions, power-down modes, etc., depending model. 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8S/2600 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit 32-bit control registers, have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space.
Rev. 2.0, 04/02, page
Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. multiply-and-accumulate instruction been added. Two-bit shift rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. Note: Normal mode available this LSI. 2.1.3 Differences from H8/300H
comparison H8/300H CPU, H8S/2600 following enhancements. Additional control register 8-bit 32-bit control registers have been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. multiply-and-accumulate instruction been added. Two-bit shift rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2600 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space. mode selected mode pins. 2.2.1 Normal Mode
exception vector table stack have same structure H8/300 CPU.
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Address Space H8S/2600 provides linear access maximum 64-kbyte address space. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction instructions addressing modes used. Only lower bits effective addresses (EA) valid. Exception Vector Table Memory Indirect Branch Addresses normal mode area starting H'0000 allocated exception vector table. branch address stored bits. exception vector table normal mode shown figure 2.1. details exception vector table, section Exception Handling. memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table. Stack Structure When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2.2. pushed onto stack interrupt control mode details, section Exception Handling. Note: Normal mode available this LSI.
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved system use)
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode)
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch Notes: When used, stored stack. when used. lgnored when returning.
Exception Handling
Figure Stack Structure Normal Mode 2.2.2 Advanced Mode
Address Space Linear access provided 16-Mbyte maximum address space. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction instructions addressing modes used.
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Exception Vector Table Memory Indirect Branch Addresses advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2.3). details exception vector table, section Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved system use) H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also used exception vector table. Stack Structure advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2.4. pushed onto stack interrupt control mode details, section Exception Handling.
Rev. 2.0, 04/02, page
Reserved bits)
EXR*1 Reserved*1, bits)
Subroutine Branch Notes: When used, stored stack. when used. Ignored when returning.
Exception Handling
Figure Stack Structure Advanced Mode
Rev. 2.0, 04/02, page
Address Space
Figure shows memory H8S/2600 CPU. H8S/2600 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area
H'00FFFFFF Cannnot used this
Data area
H'FFFFFFFF Normal Mode* Note: Normal mode cannot used this LSI. Advanced Mode
Figure Memory Note: Normal mode available this LSI.
Rev. 2.0, 04/02, page
Registers
H8S/2600 internal registers shown figure 2.6. There types registers: general registers control registers. Control registers 24-bit program counter (PC), 8bit extended register (EXR), 8-bit condition code register (CCR), 64-bit multiplyaccumulate register (MAC).
General Registers (Rn) Extended Registers (En)
(SP)
Control Registers (CR)
Sign extension MACL MACH
Legend
:Stack pointer :Program counter :Extended register :Trace :Interrupt mask bits :Condition-code register :Interrupt mask :User interrupt mask bit* :Half-carry flag :User :Negative flag :Zero flag :Overflow flag :Carry flag :Multiply-accumulate register
Note: cannot used interrupt mask this LSI.
Figure Registers
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2.4.1
General Registers
H8S/2600 eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. Figure illustrates usage general registers. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. usage each register selected independently. General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Address registers 32-bit registers 16-bit registers 8-bit registers
registers (extended registers) registers (ER0 ER7) registers registers (R0L R7L) registers (R0H R7H)
Figure Usage General Registers
Rev. 2.0, 04/02, page
Free area (ER7)
Stack area
Figure Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded 2.4.3 Extended Register (EXR)
8-bit register that manipulated LDC, STC, ANDC, ORC, XORC instructions. When these instructions except instruction executed, interrupts including will masked three states after execution completed.
Name Initial Value Description Trace When this trace exception started each time instruction executed. When this cleared instructions executed sequence.
Reserved These bits always read These bits designate interrupt mask level details, refer section Interrupt Controller.
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2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions.
Name Initial Value Description Interrupt Mask Masks interrupts other than when accepted regardless setting. hardware start exception-handling sequence. details, refer section Interrupt Controller. Undefined User Interrupt Mask written read software using LDC, STC, ANDC, ORC, XORC instructions. This cannot used interrupt mask this LSI. Undefined Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. Undefined User written read software using LDC, STC, ANDC, ORC, XORC instructions. Undefined Negative Flag Stores value most significant data sign bit. Undefined Zero Flag indicate zero data, cleared indicate non-zero data.
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Name
Initial Value Undefined
Description Overflow Flag when arithmetic overflow occurs, cleared otherwise.
Undefined
Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, indicate carry
carry flag also used accumulator manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores results multiply-and-accumulate operations. consists 32bit registers denoted MACH MACL. lower bits MACH valid; upper bits sign extension. 2.4.6 Initial Values Internal Registers
When reset exception handling loads start address from vector address, initialized, cleared bits However, general registers other bits initialized. initial value (ER7) undefined. should therefore initialized using MOV.L instruction immediately after reset.
Data Formats
H8S/2600 process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data.
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2.5.1
General Register Data Formats
Figure shows data formats general registers.
Data Type
1-bit data
Register Number
Data Format
Don't care
1-bit data Don't care
4-bit data Upper
Lower
Don't care
4-bit data Don't care Upper
Lower
Byte data
Don't care
Byte data
Don't care
Figure General Register Data Formats
Rev. 2.0, 04/02, page
Data Type Word data
Register Number
Data Format
Word data
Longword data
Legend
General register General register General register General register General register Least significant
Most significant
Figure General Register Data Formats
Rev. 2.0, 04/02, page
2.5.2
Memory Data Formats
Figure 2.10 shows data formats memory. H8S/2600 access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches. When used address register access stack, operand size should word size longword size.
Data Type Address
1-bit data Address
Data Format
Byte data
Address
Word data
Address Address 2M+1
Longword data
Address Address 2N+1 Address 2N+2 Address 2N+3
Figure 2.10 Memory Data Formats
Rev. 2.0, 04/02, page
Instruction
H8S/2600 types instructions. instructions classified function table 2.1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE* MOVTPE*
Size B/W/L B/W/L B/W/L B/W/L
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
MAC, LDMAC, STMAC, CLRMAC Logic operations Shift manipulation Branch System control AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV
Total: Notes: byte size; word size; longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used this LSI. Only register ER0, ER1, ER4, should used when using instruction.
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2.6.1
Table Instructions Classified Function
Tables 2.10 summarize instructions each functional category. notation used tables 2.10 defined below. Table Operation Notation
Symbol (EAd) (EAs) #IMM disp :8/:16/:24/:32 Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
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Table
Instruction
Data Transfer Instructions
Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. Cannot used this LSI. Cannot used this LSI. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
MOVFPE MOVTPE
PUSH
S
Note: Size refers operand size. Byte Word Longword
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Table
Instruction
Arithmetic Operations Instructions
Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. (decimal adjust) Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
ADDX SUBX ADDS SUBS MULXU
B/W/L
MULXS
DIVXU
Note: Size refers operand size. Byte Word Longword
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Table
Instruction DIVXS
Arithmetic Operations Instructions
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @ERd) Tests memory contents, sets most significant (bit (EAs) (EAd) Performs signed multiplication memory contents adds result multiply-accumulate register. following operations performed: bits bits bits bits, saturating bits bits bits bits, non-saturating Clears multiply-accumulate register zero. MAC, Transfers data between general register multiply-accumulate register.
B/W/L
B/W/L
EXTU
EXTS
TAS*
CLRMAC LDMAC STMAC Note:
Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
Rev. 2.0, 04/02, page
Table
Instruction
Logic Operations Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement (logical complement) general register contents.
B/W/L
B/W/L
B/W/L
Note: Size refers operand size. Byte Word Longword
Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* B/W/L Function (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
Note: Size refers operand size. Byte Word Longword
Rev. 2.0, 04/02, page
Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Note: Size refers operand size. Byte
Rev. 2.0, 04/02, page
Table
Instruction BXOR
Manipulation Instructions
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register me
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