200-MBaud HOTLink® Transceiver Second-generation HOTLink® technol
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CY7C924DX
200-MBaud HOTLink® Transceiver
Second-generation HOTLink® technology Fibre Channel ESCON® compliant 8B/10B encoder/decoder 12-bit pre-encoded data path (raw mode) 10-bit encoded data transport (using 8B/10B coding) Parity check/generate Synchronous asynchronous parallel interface UTOPIA compatible host interface Embedded/Bypassable 256-character synchronous FIFOs Integrated support daisy-chain ring topologies Domain individual destination device addressing 200-MBaud serial signaling rate Internal PLLs with external components Dual differential PECL serial inputs Dual differential PECL serial outputs Compatible with fiber-optic modules copper cables Built-In Self-Test (BIST) link testing Link Quality Indicator Single +5.0V ±10% supply 100-pin TQFP 0.35µ CMOS technology transmit section CY7C924DX HOTLink configured accept either 10-bit data characters each clock cycle, stores parallel data into internal Transmit FIFO. Data read from Transmit FIFO encoded using embedded 8B/10B encoder improve serial transmission characteristics. These encoded characters then serialized output from Positive (PECL) compatible differential transmission line drivers bit-rate times input reference clock. receive section CY7C924DX HOTLink accepts serial bit-stream from PECL-compatible differential line receivers and, using completely integrated Clock Synchronizer, recovers timing information necessary data reconstruction. recovered stream deserialized framed into characters, 8B/10B decoded, checked transmission errors. Recovered decoded characters reconstructed into either 10-bit data characters, written internal Receive FIFO, presented destination host system. integrated 8B/10B encoder/decoder bypassed systems that present externally encoded scrambled data parallel interface. embedded FIFOs also bypassed create reference-locked serial transmission link. those systems requiring even greater FIFO storage capability, external FIFOs directly coupled CY7C924DX device through parallel interface without additional glue-logic. parallel interface configured either FIFO (configurable UTOPIA emulation depth expansion through external FIFOs) pipeline register extender. FIFO configurations optimized transport timeindependent (asynchronous) 10-bit character-oriented data across link. Built-In Self-Test (BIST) pattern generator checker permits at-speed testing high-speed serial data paths both transmit receive sections, across interconnecting links. HOTLink devices ideal variety applications where parallel interfaces replaced with high-speed, point-topoint serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, video transmission equipment.
Functional Description
200-MBaud CY7C924DX HOTLink Transceiver pointto-point communications building block allowing transfer data over high-speed serial links (optical fiber, balanced, unbalanced copper transmission lines) speeds ranging between MBaud. transmit section accepts parallel data selectable width converts serial data, while receiver section accepts serial data converts parallel data selectable width. Figure illustrates typical connections between independent host systems corresponding CY7C924DX parts. second generation HOTLink device, CY7C924DX provides enhanced levels technology, functionality, integration over field-proven CY7B923/933 HOTLink.
Framer Deserializer
Serializer
FIFO Receive
Data Receive System Host
Decoder 8B/10B
Serial Link
8B/10B Encoder
Transmit FIFO
Transmit Data System Host
Control CY7C924DX Status Serializer FIFO Transmit Encoder 8B/10B Data Transmit Serial Link
CY7C924DX Deserializer Framer 8B/10B Decoder Receive FIFO
Control Status Receive Data
Figure HOTLink System Connections HOTLink registered trademark Cypress Semiconductor Corporation. ESCON registered trademarks International Business Machines.
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 June 2000
CY7C924DX
CY7C924DX Transceiver Logic Block Diagram
STATUS TXDATA CONTROL TXCLK MODE REFCLK STATUS RXDATA RXCLK Mode Control Output Register Address Register
Output Register
Flags Mode Receive FIFO
Input Register
Flags
Transmit FIFO
Transmit Clock Multiplier Receive Formatter Pipeline Register Byte-Unpacker Parity Generation Address Matching
Elasticity Buffer Transmit Formatter Pipeline Register Parity Checker Byte-Packer
CONTROL TXEN* RXEN* TXSTOP* TXRST* RXRST* RFEN TXBISTEN* RXBISTEN* RESET*[1:0] MODE RANGESEL SPDSEL RXMODE[1:0] FIFOBYP* EXTFIFO ENCBYP* BYTE8/10* TEST* Clock Divider RXSTATUS LFI* RXEMPTY* RXHALF* RXFULL* STATUS TXEMPTY* TXHALF* TXFULL*
Receive Control State Machine
BIST LFSR 8B/10B Decoder
BIST LFSR 8B/10B Encoder
Transmit Control State Machine
Deserializer Framer
Serial Shifter
Clock
Receive Clock/Data Recovery
Clock
LOOPBACK CONTROL DLB[1:0] LOOPTX LOOPBACK CONTROL
Routing Matrix
Signal Validation
OUTA OUTB CURSETB CURSETA
A/B*
CARDET
CY7C924DX
Configuration
RXBISTEN* CURSETB CURSETA
TQFP View
OUTB+ OUTB- OUTA+ OUTA- VDDA VDDA VDDA VDDA VDDA VSSA VSSA VSSA VSSA VSSA INA+ INB+ INA- INB-
CARDET
VDDA
VSSA
TEST* A/B* LFI* DLB[1] DLB[0] LOOPTX TXBISTEN* RXCLK TXSTOP* RXFULL* REFCLK TXRST* TXEN* RXHALF* TXSC/D* RXEMPTY* TXDATA[0] RXSOC/RXDATA[11] RXMODE[1] RXMODE[0]
VSSA
SPDSEL RANGESEL RFEN TXFULL* TXHALF* RXEN* TXCLK RXRST* RXSC/D* RXDATA[0] TXEMPTY* RXDATA[1] TXSOC/PAREN/TXDATA[11] TXSVS/TXDATA[10] TXHALT*/TXDATA[9] RXDATA[2] RESET*[1] RESET*[0]
CY7C924DX
TXINT/TXOPIN/TXDATA[8]
RXINT/RXOP/RXDATA[8]
RXDATA[9]
RXRVS/RXDATA[10]
TXDATA[1]
TXDATA[2]
RXDATA[7]
RXDATA[6]
RXDATA[5]
RXDATA[4]
RXDATA[3]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
FIFOBYP*
EXTFIFO
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage Ground Potential -0.5V +6.5V Voltage Applied Outputs High-Z State .-0.5V VDD+0.5V Output Current into Outputs (LOW).
Input Voltage -0.5V VDD+0.5V Static Discharge Voltage.> 2001 (per MIL-STD-883, Method 3015) Latch-Up Current.>
Operating Range
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 5.0V 5.0V
BYTE8/10*
ENCBYP*
CY7C924DX
Descriptions
CY7C924DX HOTLink Transceiver Name Characteristics input, sampled TXCLK REFCLK, Internal Pull-Up Parallel Transmit Data Input. width configured accept either 10-bit characters. When encoder bypassed (ENCBYP* LOW), TXDATA[7:0] functions least significant eight bits 12-bit pre-encoded transmit character. Transmit Interrupt Input. This input only interpreted both Transmit FIFO Encoder enabled. Upon state-change TXINT, character forced into transmit encoder shifter prior accessing next Transmit FIFO contents. This signal routed around, through, Transmit FIFO. When TXINT transitions from C0.0 (K28.0) special code sent. When TXINT transitions from C3.0 (K28.3) special code sent. These special codes force similar signal transition RXINT output attached CY7C924DX HOTLink Transceiver. When Transmit FIFO bypassed (FIFOBYP* LOW) encoder enabled (ENCBYP* HIGH), this input parity input associated with TXDATA[7:0], TXSC/D*, TXSVS inputs when parity enabled, ignored otherwise. When encoder bypassed (ENCBYP* LOW), TXDATA[8] functions 12-bit pre-encoded transmit character. TXHALT*/ TXDATA[9] input, sampled TXCLK REFCLK, Internal Pull-Up Transmit FIFO Halt Immediate Input. When TXHALT* asserted LOW, transmission data suspended HOTLink transmits characters (K28.5). When TXHALT* deasserted HIGH, normal data processing proceeds. When encoder bypassed (ENCBYP* LOW), TXDATA[9] functions 10th 12-bit pre-encoded transmit character. TXPER output, changes Transmit Parity Error Output. following TXCLK When FIFOs bypassed (FIFOBYP* LOW) Encoder enREFCLK abled (ENCBYP* HIGH) this output indicates that parity errors have been found TXDATA[7:0], TXSC/D*, TXSVS, TXOPIN inputs. input, sampled TXCLK REFCLK, Internal Pull-Up Transmit Send Violation Symbol input. When Transmit FIFO enabled, this input interpreted along with TXSOC TXSC/D* (see Table details). When encoder bypassed (ENCBYP* LOW) 10-bit mode (BYTE8/10* LOW), TXDATA[10] functions 11th 12-bit preencoded transmit character. Transmit Start Cell Input. When Transmit FIFO enabled (FIFOBYP* HIGH), this input used message frame delimiter indicate beginning data packet. interpreted along with TXSVS TXSC/D* (see Table details). When Transmit FIFO bypassed (FIFOBYP* LOW), this input Parity Enable input which enables parity checking TXDATA[7:0], TXSC/D*, TXSVS, TXOPIN inputs. When encoder bypassed (ENCBYP* LOW) 10-bit mode (BYTE8/10* LOW), TXDATA[11] functions 12th (MSB) 12-bit pre-encoded transmit character. Signal Description Transmit Path Signals TXDATA[7:0]
TXINT/ TXOPIN/ TXDATA[8]
input, sampled TXCLK REFCLK, Internal Pull-Up
TXSVS/ TXDATA[10]
TXSOC/ PAREN/ TXDATA[11]
input, sampled TXCLK REFCLK, Internal Pull-Up
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name TXSC/D* Characteristics input, sampled TXCLK REFCLK, Internal Pull-Up input, sampled TXCLK REFCLK, Internal Pull-Up input, sampled TXCLK, Internal Pull-Up Signal Description Transmit Special Character Data Select Input. When Transmit FIFO enabled, this input interpreted along with TXSVS TXSOC (see Table details). When encoder bypassed (ENCBYP* LOW) TXSC/D* ignored. Transmit Enable Input. Data enable TXDATA[11:0] data write operations. Active HIGH when configured Cascade timing, active when configured UTOPIA timing. Transmit Stop Start_Of_Cell Input. While Transmit FIFO enabled, this signal used prevent queued data characters from being serially transmitted. While TXSTOP* deasserted (HIGH), data flows through Transmit FIFO without interruption. When TXSTOP* asserted (LOW), data transfers continue until TXSOC detected character stream, which point data transmission ceases. TXSTOP* momentarily deasserted then reasserted, single "cell" (delimited bits) transmitted. Stopped transfers empty FIFO conditions padded with C5.0 (K28.5) characters. When transmit FIFO bypassed (FIFOBYP* LOW), TXSTOP* function. This input left open tied HIGH. TXCLK clock input, Internal Pull-Up 3-state output, changes following TXCLK REFCLK Transmit FIFO Clock. input clock parallel interface when Transmit FIFO enabled. Used sample Transmit FIFO related interface signals. Transmit FIFO Full Status Flag. Active when configured UTOPIA timing, active HIGH when configured Cascade timing. When Transmit FIFO enabled (FIFOBYP* HIGH), TXFULL* Indicates Transmit FIFO full condition. When TXFULL* first asserted, Transmit FIFO accept minimum eight additional write cycles without loss data. When Transmit FIFO bypassed (FIFOBYP* LOW), with RANGESEL HIGH SPDSEL LOW, TXFULL* toggles half REFCLK rate provide character rate indication. Data accepted when TXFULL* indicates non-full condition. TXHALF* 3-state output, changes following TXCLK REFCLK 3-state output, changes following TXCLK REFCLK Transmit FIFO Half-full Status Flag. Active LOW. When Transmit FIFO enabled, TXHALF* asserted when Transmit FIFO half full (128 characters). TXHALF* only High-Z state assertion RESET*[1:0] LOW. Transmit FIFO Empty Status Flag. Active when configured UTOPIA timing, active HIGH when configured Cascade timing. When Transmit FIFO enabled, TXEMPTY* asserted either when data been loaded into Transmit FIFO, when Transmit FIFO been emptied either Transmit FIFO reset normal transmission FIFO contents. When TXBISTEN* asserted LOW, TXEMPTY* becomes transmit BISTloop counter indicator (regardless logic state FIFOBYP*). this mode TXEMPTY* asserted TXCLK period each transmitted BIST sequence. When Transmit FIFO bypassed, TXEMPTY* asserted indicate that transmitter accept data. TXEMPTY* also used BIST progress indicator when TXBISTEN* asserted.
TXEN*
TXSTOP*
TXFULL*
TXEMPTY*
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name TXRST* Characteristics input, internal pull-up, sampled TXCLK, Internal Pull-Up input, asynchronous, Internal Pull-Up Transmit FIFO Reset. When TXRST* sampled asserted (LOW) eight more TXCLK cycles, reset operation started Transmit FIFO. This input ignored when Transmit FIFO bypassed. Transmitter BIST Enable. When TXBISTEN* LOW, transmitter generates 511-character repeating sequence, that used validate link integrity. transmitter returns normal operation when TXBISTEN* HIGH. Transmit FIFO read operations suspended when BIST active. Parallel Data Output Serial Address Register Access. These outputs change following rising edge RXCLK, when enabled output data (the device addressed selected RXEN*). contents this interpreted differently based levels present ENCBYP*, BYTE8/10*, RXSC/D*, when accessing Serial Address Register. When Decoder bypassed (ENCBYP* LOW), RXDATA[7:0] functions least significant eight bits 12-bit pre-encoded receive character. RXINT/ RXOP/ RXDATA[8] Bidirectional TTL, changes following RXCLK, sampled RXCLK Receive Interrupt Output. When Receive FIFO Decoder enabled (FIFOBYP* ENCBYP* HIGH) C0.0 (K28.0) special code received, RXINT HIGH. When C3.0 (K28.3) special code received RXINT LOW. These special codes assumed generated response equivalent transitions TXINT input attached CY7C924DX HOTLink transceiver. This signal extracted prior Receive FIFO (except Receive Discard Policy associated command codes considered "data" entered into Receive FIFO discarded. When Receive FIFO bypassed Decoder enabled (FIFOBYP* ENCBYP* HIGH), this output contains parity RXDATA[7:0] RXSC/D* outputs. When Decoder bypassed (ENCBYP* LOW), RXDATA[8] functions 12-bit undecoded receive character. RXDATA[9] Bidirectional TTL, changes following RXCLK, sampled RXCLK Receive Data Output. When Decoder enabled 10-bit mode (ENCBYP* HIGH BYTE8/10* LOW), this input 10th (MSB) 10-bit decoded unpacked data character. When Decoder enabled 8-bit mode this input ignored. When Decoder bypassed (ENCBYP* LOW), RXDATA[9] functions 10th 12-bit undecoded receive character. Signal Description
TXBISTEN*
Receive Path Signals RXDATA[7:0] Bidirectional TTL, changes following RXCLK, sampled RXCLK
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name RXRVS/ RXDATA[10] Characteristics Bidirectional TTL, changes following RXCLK, sampled RXCLK, Internal Pull-Up Signal Description Received Violation Symbol Indicator. normal data accesses this signal used output. decoded conjunction with RXSC/D* RXSOC, Table indicate presence specific Special Character codes received data stream. RXRVS used report BIST pattern mismatches when RXBISTEN* LOW. When accessing Serial Address Register, this signal used "read/write" control input. RXRVS allows host system write Serial Address Register (RXDATA[9:0] RXSC/D* inputs). RXRVS HIGH allows host system read Serial Address Register (RXDATA[9:0] RXSC/D* outputs). When Decoder bypassed (ENCBYP* LOW) 10-bit mode (BYTE8/10* LOW), RXDATA[10] functions 11th 12-bit undecoded receive character. When 8-bit mode this output unused driven LOW. RXSOC/ RXDATA[11] Bidirectional TTL, changes following RXCLK, sampled RXCLK Receive Start Cell. Active HIGH. This output decoded conjunction with RXSC/D* RXRVS, Table indicate presence specific Special Character codes received data stream. When Decoder bypassed (ENCBYP* LOW) 10-bit mode (BYTE8/10* LOW), RXDATA[11] functions 12th (MSB) 12bit undecoded receive character. When 8-bit mode this output unused driven LOW. Received Special Character Data Indicator. normal data accesses this signal used output. decoded conjunction with RXSOC RXRVS, Table indicate presence specific Special Character codes received data stream. When accessing Serial Address Register, this signal used input select addressing mode. RXSC/D* HIGH configures Serial Address Register Unicast address matching. RXSC/D* configures Serial Address Register Multicast address matching. Receive Enable. Data enable RXDATA[11:0] data write read operations. Active HIGH when configured Cascade timing, active when configured UTOPIA timing. Used select parallel read interface device. Also controls read write access Serial Address Register. Receive Clock. When Receive FIFO enabled, this clock Receive interface input clock used control Receive FIFO read, reset, serial register access operations. When Receive FIFO bypassed, this clock output continuously character rate data being received (1/10th serial bit-rate). Receive FIFO Full Flag. Active when configured UTOPIA timing, active HIGH when configured Cascade timing. When Receive FIFO addressed, RXFULL* asserted when Receive FIFO room eight fewer writes. RXCLK input continuous Receive FIFO accessed rate slower than data being received, RXFULL* indicate loss data. When Receive FIFO bypassed, RXFULL* RXHALF* deasserted indicate that valid data present. RXFULL* also used BIST progress indicator, pulses asserted once every pass through 511character BIST loop.
RXSC/D*
Bidirectional TTL, changes following RXCLK, sampled RXCLK
RXEN*
input, sampled RXCLK, Internal Pull-Up
RXCLK
Bidirectional clock, Internal Pull-Up
RXFULL*
3-state output, changes following RXCLK
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name RXHALF* Characteristics Signal Description output, changes Receive FIFO Half-full Flag. Active LOW. following RXCLK When Receive FIFO enabled, this signal asserted (LOW) when Receive FIFO half full (128 characters). When Receive FIFO bypassed, RXHALF* deasserted (HIGH). RXHALF* forced High-Z state only during "full-chip" reset (i.e., while RESET*[1:0] LOW). RXEMPTY* 3-state output, changes following RXCLK Receive FIFO Empty Flag. Active when configured UTOPIA timing, active HIGH when configured Cascade timing. When Receive FIFO enabled, RXEMPTY* asserted when data remains Receive FIFO. read operation occurring when RXEMPTY asserted results change FIFO status, data from last valid read remains RXDATA bus. When Receive FIFO bypassed Decoder enabled, RXEMPTY* used valid data indicator. When deasserted indicates that valid data selected RXMODE[1:0]) present RXDATA outputs. When asserted indicates that C5.0 (K28.5) present RXDATA output bus. both Receive FIFO Decoder bypassed, RXEMPTY* deasserted indicate that received characters valid. RXRST* input, sampled RXCLK, Internal Pull-Up input, asynchronous, Internal Pull-Up Receive FIFO Reset. When Receive FIFO addressed RXRST* sampled while asserted (LOW) eight more RXCLK cycles, Receive FIFO reset initiated. RXRST* input also asserted access Serial Address Register. Reframe Enable. Used control when framer allowed adjust character boundaries based detection more K28.5 characters data stream. When HIGH, framer allowed adjust character boundaries relative received serial data stream. When LOW, boundary fixed. Receiver BIST Enable. When active, receiver configured perform character-for-character match incoming data stream with 511-character BIST sequence. result character mismatches indicated RXRVS. Completion each 511-character BIST loop accompanied assertion pulse RXFULL* flag. Address Match. Active LOW. Used qualifier TXEN*, RXEN*, TXRST*, RXRST*. Also controls three-state enables TXFULL*, TXEMPTY*, RXFULL*, RXEMPTY* signals. Serial-in Serial-out LOOP Select. This input controls LOOP-through function which serial data recovered Clock/Data Recovery then retransmitted using Transmit bit-rate reference. selects between output Transmit FIFO output Elasticity Buffer input Transmit Encoder. When LOW, Transmit FIFO source data transmission. When HIGH, Elasticity Buffer source data transmission. Reference Clock. This clock input used timing reference transmit receive PLLs. When Transmit FIFO bypassed, REFCLK also used clock external transmit data interface. Table relationships between REFCLK, SPDSEL, RANGESEL, BYTE8/10*.
RFEN
RXBISTEN*
input, asynchronous, Internal Pull-Up
Control Signals input, sampled TXCLK, RXCLK, REFCLK input, asynchronous, Internal Pull-Down
LOOPTX
REFCLK
input clock
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name SPDSEL Characteristics Static control input levels Normally wired HIGH Speed Select. Used select operating data rate ranges device. When operating symbol rate between MBaud, SPDSEL must HIGH. When operating symbol rate between MBaud, SPDSEL must (see Table Signal Description
RANGESEL
Range Select. Static control input levels Selects proper prescaler REFCLK input. Table various Normally wired HIGH relationships between REFCLK, SPDSEL, RANGESEL, BYTE8/10*. When Transmit FIFO bypassed (FIFOBYP* LOW), with RANGESEL HIGH SPDSEL LOW, TXFULL* toggles half REFCLK rate provide character rate indication, show when data accepted. Static control input levels Normally wired HIGH External FIFO Select. EXTFIFO modifies active level RXEN* TXEN* inputs timing Transmitter Receiver data buses. When configured external FIFOs (EXTFIFO LOW), TXEN* assumed driven pipeline register RXEN* assumed driven controller pipeline register. this mode active data transition transmit data within same clock transmit interface selected TXEN*. When configured external FIFOs (EXTFIFO HIGH), TXEN assumed driven empty flag attached CY7C42X5 FIFO, RXEN assumed driven Almost Full flag attached CY7C42X5 FIFO. this mode active data transition transmit data clock cycle following clock edge where transmit interface selected TXEN*. EXTFIFO also modifies output state Receive Transmit FIFO flags. When configured external FIFOs (EXTFIFO HIGH), Full Empty FIFO flags active HIGH (the Half-full flag always active LOW). When configured external FIFOs (EXTFIFO LOW), FIFO flags active LOW.
EXTFIFO
FIFOBYP*
Static control input levels Normally wired HIGH
FIFO Bypass Select. Active LOW. When LOW, Transmit Receive FIFOs bypassed. this mode TXCLK used. Instead transmit data must synchronous REFCLK. Transmit FIFO status flags synchronized REFCLK. received data synchronous RXCLK output. Receive FIFO status flags synchronized RXCLK (the recovered Receive Character clock). When HIGH, Transmit Receive FIFOs enabled. this mode Transmit FIFO writes synchronized TXCLK, Receive FIFO reads synchronous RXCLK input.
ENCBYP*
Static control input levels Normally wired HIGH
Encoder Bypass Select. Active LOW. When LOW, both Encoder Decoder bypassed. Data transmitted format, without encoding, first. Received data presented parallel characters interface without decoding. When HIGH, data passed through both 8B/10B Encoder Transmit path Decoder Receive path.
RXMODE[1:0]
Receive Discard Policy Select. Static control input levels These inputs select between four data handling fill-character discard Normally wired HIGH modes receiver. Table
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver Name BYTE8/10* Characteristics Static control input levels Normally wired HIGH Signal Description Parallel Data Character Size Select. Selects input data character width. When BYTE8/10* HIGH, device 8-bit mode. When BYTE8/10* LOW, part 10-bit mode. encoder enabled (ENCBYP* HIGH), data encoded using 8B/10B code rules found Table Table When ENCBYP* LOW, part passes input bits (when BYTE8/10* HIGH) input bits (BYTE8/10* LOW) directly serial stream without encoding decoding. affected groupings function Table Table RESET*[1:0] input, asynchronous Global Logic Reset. These inputs pulsed more REFCLK periods reset internal logic. They must tied together driven concurrently ensure valid reset.
TEST*
input, Factory Test Mode Select. asynchronous. Used force part into diagnostic test mode used factory test. Normally wired HIGH This tied HIGH during normal operation. PECL differential outputs Differential Serial Data Outputs. These PECL compatible outputs capable driving terminated transmission lines commercial fiber-optic transmitter modules. unused output pair powered down leaving outputs unconnected strapping associated CURSETx VDD.
Analog Control OUTA± OUTB±
CURSETA
Analog input
Current-set Resistor Input OUTA±. precision resistor connected between this input clean ground output differential amplitude currents OUTA± differential driver.
CURSETB
Analog input
Current-set Resistor Input OUTB±. precision resistor connected between this input clean ground output differential amplitude currents OUTB± differential driver.
INA± INB±
PECL compatible differential input
Differential Serial Data Inputs. These inputs accept serial data stream deserialization decoding. Only serial stream time receiver extract data content. This stream selected using A/B* input. These inputs also routed OUTB± serial outputs using DLB[1:0] inputs. Receive Data Input Selector. Determines which internal external serial bit-stream passed receiver clock data recovery circuit. Table details. Loop-back Select Inputs. Selects connections between serial inputs outputs. Controls diagnostic loop-back serial loop-through functions. Table details. Carrier Detect Input. Used allow external device signify valid signal being presented high speed PECL compatible input buffers, typical Optical Module. When CARDET deasserted LOW, LFI* indicator asserts signifying Link Fault. This input tied copper media applications.
A/B*
input, asynchronous, Internal Pull-Up input, asynchronous, Internal Pull-Down PECL input, asynchronous
DLB[1:0]
CARDET
CY7C924DX
Descriptions (continued)
CY7C924DX HOTLink Transceiver LFI* Name Characteristics output, changes following RXCLK Signal Description Link Fault Indication Output. Active LOW. LFI* changes synchronous with RXCLK. This output driven when serial link currently selected A/B* suitable data recovery. This caused Serial Data Amplitude below acceptable levels. Input transition density sufficient clock recovery. Serial Data stream outside acceptable frequency range operation. CARDET LOW. Power VDDA VSSA Power PECL signals internal analog circuits.
Ground PECL signals internal analog circuits.
Power CMOS signals internal logic circuits.
Ground CMOS signals internal logic circuits.
CY7C924DX
CY7C924DX HOTLink Operation
Overview CY7C924DX designed move parallel data across both short long distances with minimal overhead host system intervention. This accomplished converting parallel characters into serial bit-stream, transmitting these serial bits high speed, converting received serial bits back into original parallel data format. CY7C924DX offers large feature set, allowing used wide range host systems. Some configuration options are: 8-bit 10-bit character size user definable data packet frame structure 2-octave data rate range asynchronous (FIFOed) synchronous data interface 8B/10B encoded non-encoded (raw data) with without parity check/generate embedded bypassable FIFO data storage multi-PHY capability point-to-point, point-to-multipoint, ring data-transport This flexibility allows CY7C924DX meet datatransport needs almost system. Transmit Data Path Transmit Data Interface/Transmit Data FIFO transmit data interface host system configurable either asynchronous buffered (FIFOed) parallel interface synchronous pipeline register. itself configured operation with 8-bit 10-bit data. When configured asynchronous operation (where hostbus interface clock operates asynchronous serial character stream clocks), host interface becomes that synchronous FIFO clocked TXCLK. these configurations internal 256-character Transmit FIFO enabled. allows host interface written rate from MHz. When configured synchronous operation, transmit interface clocked REFCLK operates synchronous internal character bit-stream clocks. input register must written character rate, REFCLK operate character rate twice character rate. Both asynchronous synchronous interface operations support interface timing models: UTOPIA Cascade. UTOPIA timing model designed match active levels, timing, signal sequencing called AForum UTOPIA specification. Cascade timing model designed match host that resembles synchronous FIFO. These timing models allow CY7C924DX directly couple host systems, registers, state machines, FIFOs, etc., with minimal many cases external glue logic. Encoder Data from host interface Transmit FIFO next passed Encoder block. CY7C924DX contains internal 8B/10B encoder that used improve serial transport characteristics data. parity checking enabled, characters checked valid parity. those sysSerializer/Line Driver data from Encoder passed Serializer. This Serializer operates either 2.5, times rate REFCLK input times when unencoded 10-bit mode). serialized data output from PECL-compatible differential line drivers configured drive transmission lines optical modules. Receive Data Path Line Receiver/Deserializer/Framer Serial data received PECL-compatible differential line receivers. data passed both Clock Data Recovery (Phase Locked Loop) Deserializer that converts serial data into parallel characters. Framer adjusts boundaries these characters match those original transmitted characters. Decoder parallel characters passed through 10B/8B Decoder returned their original form. parity generation enabled, parity added received characters this point. systems that make external decoding descrambling, decoder bypassed. Receive Data Interface/Receive Data FIFO Data from decoder passed either Receive FIFO passed directly output register. output register configured operation with 8-bit 10-bit data. When configured asynchronous buffered (FIFOed) interface, data passed through 256-character Receive FIFO that allows data read rate from MHz. When configured synchronous operation (Receive FIFO bypassed) data clocked Receive Output register byte rate, MHz. receive interface also configurable both UTOPIA Cascade timing models. tems that contain their encoder scrambler, this Encoder bypassed.
CY7C924DX HOTLink Transceiver Block Diagram Description
Transmit Input/Output Register Transmit Input Register, shown Figure captures data processed HOTLink Transmitter, allows input timing made compatible with asynchronous synchronous host system buses. These buses take form UTOPIA compliant interfaces, external FIFOs, state machines, other control structures. Data present TXDATA[11:0] TXSC/D* inputs captured rising edge selected sample clock. transmit data bitassignments vary depending data encoding, parity, bus-width selected. These bit-assignments shown Table list functional names these different signals. Note that function several these signals changes different operating modes. logical sense enable FIFO flag signals depends intended interface convention EXTFIFO pin. transmit interface supports both synchronous asynchronous clocking modes, each supporting both UTOPIA
CY7C924DX
Table Transmit Input Signal Transmit Encoder Mode[1] Encoded 8-bit Character Stream ENCBYP* BYTE8/10* TXDATA Input TXSC/D* TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXINT/TXOPIN/TXDATA[8] (FIFOBYP* HIGH) TXINT/TXOPIN/TXDATA[8] (FIFOBYP* LOW) TXHALT*/TXPER/TXDATA[9] (FIFOBYP* HIGH) TXHALT*/TXPER/TXDATA[9] (FIFOBYP* LOW) TXSVS/TXDATA[10] TXSOC/TXPAREN/TXDATA[11] (FIFOBYP* HIGH) TXSOC/TXPAREN/TXDATA[11] (FIFOBYP* LOW) TXSC/D* TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXINT TXOPIN TXHALT* TXPER (output) TXSVS TXSOC TXPAREN TXD[0][2] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[8] TXD[9] TXD[9] TXSC/D* TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[8] TXD[9] TXD[9] TXSVS TXSOC TXD[0][2] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[8] TXD[9] TXD[9] TXD[10] TXD[11] TXD[11] HIGH HIGH Pre-encoded 10-bit Character Stream HIGH Encoded 10-bit Character Stream HIGH Pre-encoded 12-bit Character Stream
Notes: open cells ignored. First shifted out. Others follow numerical order creating pattern.
Cascade timing models. selection specific clocking mode determined RANGESEL SPDSEL inputs FIFO Bypass (FIFOBYP*) signal. TXDATA[11:0] TXSC/D* TXEN* REFCLK TXCLK Synchronous Interface Synchronous interface clocking operates entire transmit data path synchronous REFCLK. enabled connecting FIFOBYP* disable internal FIFOs. Asynchronous Interface Asynchronous interface clocking controls writing host data into Transmit FIFO. enabled setting FIFOBYP* HIGH enable internal FIFOs. these configurations, writes Transmit Input Register, associated transfers Transmit FIFO, controlled TXCLK. remainder transmit data path clocked REFCLK synthesized derivatives REFCLK. UTOPIA Timing Model UTOPIA timing model allows multiple CY7C924DX transmitters addressed accessed from common host
Transmit Input Register
Encoder Block
Transmit FIFO
Figure Transmit Input Register
CY7C924DX
bus, using protocols defined AForum UTOPIA interface standards. enabled setting EXTFIFO LOW. UTOPIA timing, TXEMPTY* TXFULL* outputs TXEN* input, active signals. CY7C924DX addressed AM*, becomes "selected" when TXEN* asserted LOW. Following selection, data written into Transmit FIFO every clock cycle where TXEN* remains LOW. Cascade Timing Model Cascade timing model variation UTOPIA timing model. Here TXEMPTY* TXFULL* outputs, TXEN input, active HIGH signals. Cascade timing makes same address selection sequences UTOPIA timing, write data accesses delayed write. This delayed write necessary allow direct coupling external FIFOs, state machines that initiate write operation clock cycle before data available bus. Cascade timing enabled setting EXTFIFO HIGH. When used FIFO depth expansion, Cascade timing allows size internal Transmit FIFO expanded almost unlimited depth. allows CY7C42x5 series synchronous FIFO attached transmit interface without extra logic, shown Figure Transmit FIFO Transmit FIFO used buffer data captured input register later processing transmission. This FIFO sized hold 14-bit characters. When Transmit FIFO enabled, Transmit FIFO write enabled (the device selected TXEN* sampled asserted), data command captured transmit input register stored into Transmit FIFO. Transmit FIFO write operations clocked TXCLK. Transmit FIFO presents Full, Half-Full, Empty FIFO flags. These flags provided synchronous TXCLK. When Transmit FIFO enabled, allows operation with Mooretype external controlling state machine. When configured Cascade timing, timing active levels these signals also designed support direct expansion Cypress CY7C42x5 synchronous FIFOs. Regardless width 10-bit characters) Transmit FIFO clocked rate from MHz. This gives Transmit FIFO maximum bandwidth million characters second. Since serial outputs only move million characters second their fastest operating rate, CY7C42x5 FIFO WEN* WEN* WCLK REN* RCLK CY7C924DX TXEN TXFULL TXDATA TXSC/D* TXCLK there ample time service multiple CY7C924DX HOTLinks with single controller. read port Transmit FIFO connected logic block that performs data formatting validation. data read operations from Transmit FIFO controlled Transmit Control State Machine that operates synchronous REFCLK. Transmit Formatter Validation Transmit Formatter validation logic performs three primary functions: Parity checking Data format control Byte-packing addition these logic functions, this block also controls timing transfer data from Transmit Input Register, Transmit FIFO, Elasticity Buffer. Parity Checking Parity checking enabled 8-bit encoded mode when internal FIFOs disabled (FIFOBYP* LOW) PAREN (TXSOC) HIGH. parity supported, which requires least data always logic-1. eight data bits (TXDATA[7:0]), TXSC/D*, TXSVS, TXOPIN (TXDATA[8]) covered parity checking hardware. parity error detected character, that character transmitted, replaced with C0.7 Exception character (see Special Character codes Table 11). This prevents data from knowingly being transmitted informs receiver that error detected source data stream. Parity errors reported transmit interface through TXPER output. This output pulses HIGH REFCLK period, more cycles after cycle where parity error detected. Transmit Data Formatting CY7C924DX supports number protocol enhancements over physical-layer device. These enhancements made possible part through Transmit Receive FIFOs. These FIFOs allow CY7C924DX manage data stream much greater extent than possible before. addition standard 8B/10B encoding used improve serial data transmission, CY7C924DX also supports: marking packet cell boundaries using TXSOC expanded command ability address route packets frames specific receivers three these capabilities supported both 10bit encoded character sizes, made possible through TXSOC bit. This interpreted, along with TXSC/D* TXSVS, those modes where both Transmit FIFO Encoder enabled. three bits determine data associated with them processed transmission. These operations listed Table entries Table where TXSOC generate same characters serial data stream standard CY7B923 HOTLink Transmitter, which uses ANSI standard 8B/10B character set. data, command, exception character encodings listed Data Special Char-
TXCLK
EXTFIFO
Figure External FIFO Depth Expansion CY7C924DX Transmit Data Path
CY7C924DX
acter code tables (Tables found near this data sheet. Table Transmit Data Formatting TXSC/D* TXSOC TXSVS code sent Encoder prior sending data character. 111b character format used send serial addresses attached receivers. These serial addresses allow host direct (the following) data specific destination destinations, when CY7C924DX devices connected ring topology. Serial Address marker also used send packet identification fields, sequence numbers, other high-level routing information those point-to-point connections that require physical address capabilities, however, reporting address field contents affected present receiver discard policy. This marking tagging capability performed with 100b 110b character formats without concern receiver discard policy. When character read from Transmit FIFO with these bits set, C10.0 Special Character sent Encoder prior sending associated data character. Byte-Packer byte-packer logical construct, used control efficient segmentation 10-bit source data into 8-bit characters. This conversion allows these characters transported using 8B/10B encoding, with same encoding overhead (20%) when sending 8-bit characters. Because serializer continues operate using 10-bit transmission characters, this encoding mode only operate with Transmit FIFO enabled. byte-packer operates taking pieces more 10bit characters, combining them into 8-bit groups, passing these groups 8B/10B encoder. takes exactly five 8-bit characters transport four 10-bit characters. allocation performed, shown Figure where low-order eight bits first 10-bit character (A[7:0]) passed encoder first clock cycle. During second clock cycle remaining bits first character combined with lower bits second 10-bit character (B[5:0]+A[9:8]). third clock cycle remaining four bits second 10-bit character combined with lower four bits third 10-bit character (C[3:0]+B[9:6]). fourth clock cycle remaining bits third 10-bit character combined with lower bits fourth 10-bit character (D[1:0]+C[9:4]). fifth clock cycle remaining eight bits fourth 10-bit character passed encoder (D[9:2]). This process repeats additional data characters present FIFO. time Transmit FIFO emptied, portion 10-bit character been transmitted, remaining bits 8-bit character filled with dummy bits before that character passed encoder. 8-bit character containing these dummy bits immediately followed
Data Format Operation Normal Data Encode Replace Character with C0.7 Exception Normal Command Encode Replace Character with C0.7 Exception Send Start Cell Marker (C8.0) Data Character Replace Character with C0.7 Exception Send Extended Command Marker (C9.0) Data Character Send Serial Address Marker (C10.0) Data Character
When TXSOC read from Transmit FIFO) HIGH, extra character inserted into data stream. This extra character always Special Character code (see Table that used inform remote receiver that immediately following character should interpreted differently from normal meaning. associated character present TXDATA[x:0] always encoded data character. 100b combination (TXSOC TXSC/D* TXSVS used marker start cell, frame, packet data being sent across interface. When character read from Transmit FIFO with this combination bits set, C8.0 Special Character code sent Encoder prior sending associated data character. 101b character format same function 001b 011b normal data modes. instructs encoder discard associated data character replace with C0.7 Exception character. 110b character format used expand command space beyond that available with default 8B/10B code. 8B/10B code normally supports data space data characters, command (non-data) space twelve command characters (C0.0-C11.0 Table 11). those data links where this sufficient, 110b format used mark associated data extended command. This expands command space commands addition some present twelve). When character read from Transmit FIFO with these bits set, C9.0 Special Charac-
CY7C924DX
C5.0 (K28.5) fill character, which resets sequencer boundaries first character position. Encoder Block Encoder logic block performs primary functions: encoding data serial transmission generating BIST (Built-In Self Test) patterns allow at-speed link device testing. BIST LFSR Encoder logic block operates data stored register. This register accepts information directly from Transmit FIFO, Transmit Input Register, 10/8 Byte-Packer, from Transmit Control State Machine when inserts special characters into data stream. This same register converted into Linear Feedback Shift Register (LFSR) when Built-In Self-Test (BIST) pattern generator enabled (TXBISTEN* LOW). When enabled, this LFSR generates 511-character sequence that includes Data Special Character codes, including explicit violation symbols. This provides predictable pseudorandom sequence that matched identical LFSR Receiver. specific patterns generated described detail Cypress application note "HOTLink Built-In Self-Test." sequence generated CY7C924DX identical that CY7B923 CY7C929, allowing interoperable systems built when used compatible serial signaling rates. Encoder data passed through Transmit FIFO formatter, received directly from Transmit Input Register, seldom form suitable transmission across serial link. characters must usually processed transformed guarantee: minimum transition density allow serial receiver extract clock from data stream) DC-balance signaling prevent baseline wander) Source 10-bit Character Stream
DDDDDDDDDD 9876543210 CCCCCCCCCC 9876543210 BBBBBBBBBB 9876543210 AAAAAAAAAA 9876543210
run-length limits serial data limit bandwidth link) some allow remote receiver determine correct character boundaries (framing). CY7C924DX contains integrated 8B/10B encoder that accepts 8-bit data characters converts these into 10-bit transmission characters that have been optimized transport serial communications links. 8B/10B encoder bypassed those system that operate with external 8B/10B encoders, alternate forms encoding scrambling ensure good transmission characteristics. operation 8B/10B encoding algorithm described detail later this data sheet, complete encoding tables listed Tables When Encoder enabled, transmit data characters passed through Transmit FIFO formatter) converted either 10-bit Data symbol 10-bit Special Character, depending upon state TXSC/D* input. TXSC/D* HIGH, data inputs represent Special Character code encoded using Special Character encoding rules Table TXSC/D* LOW, data inputs encoded using Data Character encoding Table When operated without parity checking, each character used override contents remaining bits character. this (TXSVS) HIGH, respective character replaced with (C0.7) character. This used check error handling system-logic receiver controller proprietary applications. 8B/10B encoder standards compliant with ANSI/NCITS X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit Ethernet), ESCON FICON channels, AForum standards data transport. 8B/10B coding function Encoder bypassed systems that include external coder scrambler function part controller host system. This performed setting ENCBYP* LOW. With encoder bypassed, each 10-bit character captured Transmit Input Register) passed directly Transmit Shifter Transmit FIFO) without modification. Transmit Shifter Transmit Shifter accepts 10-bit parallel data from Encoder block once each character time, shifts serial interface output buffers using PLL-multiplied bit-clock. This bit-clock runs 2.5, times REFCLK rate times when BYTE8/10* LOW) selected RANGESEL SPDSEL (see Table Timing parallel transfer controlled counter dividers Clock Multiplier affected signal levels timing input pins. Bits each character shifted first, required ANSI IEEE standards 8B/10B coded serial data streams. Routing Matrix
DDDDDDDD 98765432 DDCCCCCC 10987654 CCCCBBBB 32109876 BBBBBBAA 54321098 AAAAAAAA 76543210
Last Character Sent
First Character Sent Figure Byte-Packer 10-to-8 Character Mapping
Routing Matrix precision multiplexors that allow various combinations Transmit Shifter, buffered INA± INB± serial line receiver inputs, reclocked serial line receiver input transmitted from OUTB± serial data outputs. signal routing transmit serial outputs controlled primarily DLB[1:0] inputs listed Table
CY7C924DX
Table Transmit Data Routing Matrix DLB[1] DLB[0]
TRANSMIT SHIFTER A/B* OUTB RECEIVE OUTA
Data Connections
determine peak-to-peak signal-swing output. This amplitude relationship controlled load impedance driver, resistance RCURSET resistor that driver, listed
CURSET
TRANSMIT SHIFTER A/B* OUTB RECEIVE OUTA
VOPP difference voltage levels output differential driver when that output driving HIGH LOW, ZLOAD that load seen output when sourcing sinking current. With known load impedance desired signal swing, possible calculate value associated CURSETA CURSETB resistor that sets this current. Unused differential output drivers should left open, reduce their power dissipation connecting their respective CURSETx input VDD. Transmit Clock Multiplier Transmit Clock Multiplier accepts external clock REFCLK input, multiples that clock 2.5, when BYTE8/10* encoder disabled) generate bit-rate clock transmit shifter. also provides character-rate clock used Transmit Controller state machine. clock multiplier accept REFCLK input between MHz, however, this clock range limited operation mode CY7C924DX selected SPDSEL RANGESEL inputs, limited extent, BYTE8/10* FIFOBYP* signals. operating serial signalling rate allowable range REFCLK frequencies listed Table Table Speed Select Range Select Settings Serial Data Rate (MBaud) 50-100 50-100 100-200 100-200 REFCLK[4] Frequency (MHz) 10-20 20-40 10-20 20-40
TRANSMIT SHIFTER A/B* OUTB RECEIVE OUTA
TRANSMIT SHIFTER A/B* OUTB RECEIVE OUTA
Serial Line Drivers serial interface PECL Output Drivers (ECL referenced +5V) transmission line drivers serial media. OUTA± receives data directly from transmit shifter, while OUTB± receives data from Routing Matrix. These outputs (OUTA± OUTB±) capable direct connection optical modules, also directly drive ACcoupled transmission lines. PECL-compatible Output Drivers viewed programmable current sources. output voltage determined output current load impedance ZLOAD. desired output voltage swing therefore controlled current-set resistor RCURSET associated with that driver. Different RCURSET values required different line impedance/amplitude combinations. output swing designed center around VDD-1.33V. Each output must externally biased VDD-1.33V. This differential output-swing specified ways: either peak-to-peak voltage into single-end load, absolute differential voltage into differential load. When specified into single-ended load (one outputs switching into load), single output will both source sink current changes between HIGH levels. voltage difference between this HIGH level level
SPDSEL HIGH HIGH
RANGESEL HIGH[3] HIGH
Notes: When SPDSEL FIFOs bypassed (FIFOBYP* LOW), RANGESEL input ignored internally mapped setting. When configured 12-bit pre-encoded data (BYTE8/10* ENCBYP* both LOW) allowable REFCLK ranges 8.33to 16.67 16.67 33.33 MHz.
Transmit Control State Machine Transmit Control State Machine responds multiple inputs control data stream passed encoder. operates response state FIFOBYP* LOOPTX inputs presence data Transmit FIFO contents Transmit FIFO contents Elasticity Buffer state transmitter BIST enable (TXBISTEN*) state external halt signals (TXHALT* TXSTOP*)
CY7C924DX
These signals used Transmit Control State Machine control data formatter, read access Transmit FIFO Elasticity Buffer, Byte-Packer, BIST. They determine content characters passed Encoder Transmit Shifter. When Transmit FIFO bypassed, Transmit Control State Machine operates synchronous REFCLK. this mode, data from TXDATA other source) passed directly from Input Register Pipeline Register. data enabled into Input register (TXEN* deasserted TXFULL* asserted) then Transmit Control State Machine presents C5.0 Special Character code Encoder maintain link synchronization. both Encoder Transmit FIFO bypassed data enabled into Input Register, Transmit Control State Machine injects alternating disparity sequence preencoded (10-bit) forms C5.0 characters. This also occurs Encoder bypassed, Transmit FIFO enabled, Transmit FIFO empty. However, since disparity tracking part Encoder, transmitted C5.0 characters generate running disparity error remote receiver. attached receiver Decoder enabled, these characters reported normal C5.0, C1.7 C2.7 (K28.5 with incorrect running disparity). External Control Data Flow Transmit Control State Machine supports three different types external control: TXSTOP* TXHALT* TXINT These control signal inputs only interpreted when Transmit FIFO enabled. They effect transmission data bringing external signals state machine without sending signals through Transmit FIFO. TXSTOP* used stop transmission next packet cell data Transmit FIFO. When asserted (LOW) Transmit Control State Machine continues read process characters Transmit FIFO until location read with TXSOC set. Once TXSOC detected, state machine sends C5.0 fill characters until TXSTOP* deasserted (HIGH) more character times. When TXSTOP* sampled deasserted allows next character with TXSOC read from Transmit FIFO passed Encoder. When TXSTOP* used control flow data, asserted (LOW) most time. allow cell frame pass, only needs deasserted (HIGH) TXCLK cycle (assuming transmit controller cell boundary). Once first character cell transmitted remainder that cell also processed. This allows host system control transmission data across interface cell-by-cell packet-by-packet basis. TXHALT* (TXDATA[9]) immediate form TXSTOP*. Instead continuing transmit data until TXSOC found, assertion TXHALT* causes character processing stop next FIFO character location. additional data read from Transmit FIFO until TXHALT* deasserted (HIGH). NOTE: Encoder bypassed, TXDATA[9] data input TXHALT*. Since this mode interface does interpret TXSOC bit, TXSTOP* signal assumes same functionality TXHALT*. TXINT used send interrupt characters from local transmitter remote receiver. While also bypasses Transmit FIFO, does stop data transmission least directly). Transmit Control State Machine responds transitions TXINT input. When TXINT transitions from C0.0 (K28.0) Special Character code sent. When TXINT transitions from C3.0 (K28.3) Special Character code sent. reception these characters generates equivalent action attached receiver's RXINT status output. combination RXHALF*, TXINT, RXINT, TXHALT* used prevent remote FIFO overflow, which would result lost data. This back-pressure mechanism significantly improve data integrity systems that cannot guarantee full bandwidth host system times. Elasticity Buffer short (8-character) FIFO contained between receive transmit paths. This FIFO used separate time domains received serial data stream outbound transmit data stream. This permits retransmission received data without worry jitter gain jitter transfer. This allows error-free transmission same data, when configured daisy-chain ring configurations, unlimited number destinations. This Elasticity Buffer enabled when LOOPTX input asserted HIGH. This directs receiver place non-C5.0 (K28.5) characters into Elasticity Buffer. LOOPTX also directs Transmit Control State Machine read data from Elasticity Buffer instead from Transmit FIFO. While retransmitting data from Elasticity Buffer, Transmit FIFO available pre-loading data transmitted. Once LOOPTX deasserted (LOW), normal data transmission from Transmit FIFO resumes. This LOOPTX capability only possible when sending 8-bit encoded data streams. cannot used with byte-packed non-encoded data streams, requires that Transmit Receive FIFOs enabled. also requires that receiver configured process embedded commands (receiver Discard Policy cannot Serial Line Receivers differential line receivers, INA± INB±, available accepting serial data streams, with active input selected using A/B* input. DLB[1:0] inputs allow transmit Serializer output selected third input serial stream, this path generally used only diagnostic purposes. serial line receiver inputs differential, will accommodate wire interconnect with filtering losses transmission line attenuation greater than (VDIF peak-to-peak differential) directly connected fiber-optic interface modules (any logic family, limited 100K). common-mode tolerance these line receivers accommodates wide range signal termination voltages. seen Table these inputs configured allow single-pin control most applications. those systems requiring selection only INA± INB±, DLB[1:0] signals tied LOW, selection performed using only A/B*. those systems requiring only single input local loopback,
CY7C924DX
A/B* tied HIGH LOW, DLB[1] signal tied DLB[0] used loopback control. level-restored (10b) reclocked (11b) settings make transmit data outputs. When configured level-restored reclocked data, selected input retransmitted OUTB±. level-restored connection simply buffers input signal allowing "bus-like" connection constructed without concern multi-drop PECL signal layout issues. reclocked connection buffers PLL-filtered copy selected input data stream. This removes most highfrequency jitter that accumulates signal when sent over long transmission lines. Unlike data retransmitted from Elasticity Buffer, output data stream clocked recovered clock, derivative local REFLCK input. This allows data source provide data multiple recipients, suffer from jitter peaking when communicated through several PLLs. reclocked connection required when sending non-8B/10B coded data streams, data streams that cannot tolerate data forwarding policies Elasticity Buffer. This reclocked output stream also beneficial systems requiring very latency. internal data delays reclocked serial stream small number bits, while data sent through Elasticity Buffer incurs delay small number characters. Signal Detect selected Line Receiver (that routed clock data recovery PLL) simultaneously monitored for: analog amplitude (>400 pk-pk) transition density received data stream outside normal frequency range (±400 ppm) carrier detected. these conditions must valid Signal Detect block indicate valid signal present. This status presented LFI* (Link Fault Indicator) output, which changes synchronous RXCLK. While link status monitored internally times, necessary have transitions RXCLK allow this signal change externally. Clock/Data Recovery extraction bit-rate clock recovery data bits from received serial stream performed within Clock/Data Recovery (CDR) block. clock extraction function performed high-performance embedded phase-locked loop (PLL) that tracks frequency incoming stream aligns phase internal bit-rate clock transitions serial data stream. makes clock present REFCLK input. used ensure that (within CDR) operating correct frequency (rather than some harmonic rate), improve acquisition time, limit unlocked frequency excursions when data present serial inputs. Regardless type signal present, will attempt recover data stream from frequency recovered data stream outside limits range controls, will track REFCLK instead data stream. When frequency selected data stream returns valid frequency, allowed track received data stream. frequency REFCLK required within ±400 frequency clock that drives REFCLK signal remote transmitter ensure lock incoming data stream. systems using multiple redundant connections, LFI* output used select alternate data stream. When LFI* indication detected, external logic toggle selection INA± INB± inputs through A/B* input. When port switch takes place, necessary reacquire serial stream frame incoming characters. Clock Divider This block contains clock division logic, used transfer data from Deserializer/Framer Decoder once every character (once every twelve bits) clock. This counter free running generates outputs bit-rate divided when BYTE8/10* ENCBYP* LOW). When Receive FIFO bypassed, these generated clocks driven RXCLK pin. Deserializer/Framer circuit extracts bits from serial data stream clocks these bits into Shifter/Framer bit-clock rate. When enabled, Framer examines data stream looking C5.0 (K28.5) characters possible positions. location this character data stream used determine character boundaries following characters. framer operates three different modes, selected RFEN input. When RFEN first asserted (HIGH), framer allowed reset internal character boundaries detected C5.0 character. Once RFEN been HIGH greater than approximately 2000 character clock cycles, multi-byte framer enabled. This requires C5.0 characters within span five characters, with both C5.0 characters located identical 10-bit character boundary locations, before framer allowed reset internal character boundary. RFEN LOW, framer disabled changes made character boundaries. framer CY7C924DX operates shifting internal character position align with character clock. This ensures that recovered clock does contain significant phase changes/hops during normal operation framing, allows recovered clock replicated distributed other circuits using PLL-based logic elements. Decoder Block decoder logic block performs primary functions: decoding received transmission characters back into Data Special Character codes, comparing generated BIST patterns with received characters permit at-speed link device testing. 10B/8B Decoder framed parallel output Deserializer passed 10B/8B Decoder where, Decoder enabled, transformed from 10-bit transmission character back original Data Special Character codes. This block uses standard decoder patterns Tables this data sheet. Data patterns indicated RXSC/D*,
CY7C924DX
Special Character codes indicated HIGH. Invalid patterns disparity errors signaled errors HIGH RXRVS, specific Special Character codes. Decoder bypassed BYTE8/10* HIGH, (10) data bits each transmission character passed unchanged from framer Pipeline Register. When Decoder bypassed BYTE8/10* LOW, twelve (12) data bits each transmission character passed unchanged from framer Pipeline Register. BIST LFSR output register Decoder block normally used accumulate received characters delivery Receive Formatter block. When configured BIST mode (RXBISTEN* LOW), this register becomes signature pattern generator checker logically converting Linear Feedback Shift Register (LFSR). When enabled, this LFSR generates 511-character sequence that includes Data Special Character codes, including explicit violation symbols. This provides predictable pseudo-random sequence that matched identical LFSR Transmitter. When synchronized with received data stream, checks each character Decoder with each character generated LFSR indicates compare errors RXRVS output Receive Output Register. LFSR initialized BIST hardware BIST loop start code D0.0 (D0.0 sent only once BIST loop). Once start BIST loop been detected receiver, RXRVS asserted pattern mismatches between received characters internally generated character sequence. Code rule violations running disparity errors that occur part BIST loop cause error indication. RXFULL* pulses asserted RXCLK cycle BIST loop used check test pattern progress. specific patterns checked receiver described detail Cypress application note "HOTLink Built-In SelfTest." sequence compared CY7C924DX identical that CY7B933, allowing interoperable systems built when used compatible serial signaling rates. large number errors detected, receive BIST state machine aborts compare operations resets LFSR D0.0 state look start BIST sequence again. Receive Formatter Receive Formatter performs four primary functions: Data Formatting Address Matching Byte-Unpacking Parity Generation Receive Data Formatting protocol enhancements transmit path mirrored receive path logic. majority these enhancements require that Receive FIFO enabled allow CY7C924DX manage data stream. addition standard 10B/8B decoding used character reception recovery, CY7C924DX also supports: marking packet cell boundaries using RXSOC expanded control/command character ability accept discard data based embedded address ability filter receive data non-essential information these capabilities supported both 10-bit character sizes, made possible through RXSOC bit. RXSOC generated upon reception C8.0, C9.0, C10.0 Special Character codes, those modes where both Receive FIFO Decoder enabled. entries Table show RXSOC, RXSC/D*, RXRVS bits formatted indicate reception specific characters character combinations. Normal Data Special Character code characters indicated RXSOC being (0). This allows standard Special Characters codes also reported output. Table Receive Data Formatting RXSC/D* RXSOC RXRVS
Data Format Indication Normal Data Character Reserved Normal Command Character Received C0.7 Exception Character Other Character Exception listed Table Received Start Cell Marker (C8.0) Data Character Received Illegal Sequence Received Extended Command Marker (C9.0) Data Character (interpreted command) Received Serial Address Marker (C10.0) Data Character (interpreted address)
Individual character errors that part supported sequences (Start Cell, Extended Command, Serial Address) marked 011b (RXSOC RXSC/D* RXRVS decode. Anytime RXSOC reported HIGH least C8.0, C9.0, C10.0 characters received valid character. immediately following character valid Data character, then corresponding combination RXSOC, RXSC/D*, RXRVS indicate type information received. immediately following character Special Character code type (even C5.0), then 101b posted indicate illegal sequence received. illegal sequence caused remote transmitter sending incorrect information, receiving data corrupted during transmission. When such error detected, 101b status bits posted associated data field Special Character code that received without error (C8.0, C9.0, C10.0 reported D8.0, D9.0, D10.0 along with 101b status). This information provided assist debugging link protocol faults. 100b indication used mark associated Data character first character frame, packet, cell, other data construct used system. Data characters Special Character codes that follow this marker written
CY7C924DX
Receive FIFO present address matching requirements satisfied). 110b indication used mark associated data character first character extended command. reality there limit number immediately following data characters that considered part this command. most common interpretation based configured width, such that single-character configurations support associated character extended command, providing extended commands 8-bit data 1024 10-bit byte-packed data. This marker treated internally same 100b Start Cell indication, which allows used mark boundary user-specific information. boundary cell marker, immediately following data data field, header, stream identifier, transaction number, packet length indicator, number pieces information connected data transfer. NOTE: reality, 100b 110b indicators used interchangeably; i.e., 100b indication used mark extended commands while 110b indication used mark start cells. 111b indication used mark start Serial Address field. Unlike Start Cell Extended Command markers, which have specific data-field length associated with them, associated Serial Address always comprised immediately following single data character, supports fixed 8-bit 10-bit address field format 8-bit 10bit byte-packed data formats. When this serial address received passed Receive FIFO discarded (see Table Address Matching those modes where address matching enabled, CY7C924DX's ability accept discard data controlled remote transmitter. This often useful configurations with more data sources multiple data destinations. Each CY7C924DX contains 8-bit 10-bit Serial Address Register that compared with first data character received following Serial Address marker (C10.0). This character constitutes address, which configured modes address matching. first mode used multicast addresses, where bit-wise performed each address character received, with contents each bits Serial Address Register. same locations register received data both `1', multicast address match declared following data Special Character codes interpreted passed Receive FIFO. multicast address field ever received (FFh 3FFh), receiver always accepts data. This setting broadcast address used send data receivers. This setting also special meaning when written Serial Address Register. When multicast address field written (FFh 3FFh) state, receiver operates promiscuous mode, receives data, regardless contents serial address commands received. This also default power-up state Serial Address register. second mode operation address matching when Serial Address register contains unique device address, compared with character received following C10.0 Serial Address marker. This unicast address requires exact match between bits declare match found allow following data pass. When Elasticity Buffer enabled, received characters (except C5.0) written Elasticity Buffer, regardless state configuration present address match. This allows more sources send data multiple receivers with receivers connected ring daisy-chain topology. prefacing cells containing data with address field, possible have each receiver only process data specifically directed Byte-Unpacker Byte-Unpacker used re-assemble 10-bit characters from received stream decoded 8-bit characters. This reassembly process designed allow transmission same embedded commands, serial addresses, Start Cell markers that used with 8-bit data characters. Because change time received encoded character versus delivered 10-bit data character, this unpacking process only possible with Receive FIFO enabled. byte-unpacker reverses character segmentation shown Figure takes five data characters combines them into four 10-bit characters. This five-state unpacking process re-started detection Special Character code Decoder, including C5.0 (K28.5) fill character. Since usage Elasticity Buffer inserts deletes C5.0 characters necessary) handle speed differences between receive transmit character clocks, possible send byte-packed data through Elasticity Buffer. send 10-bit packed data from source multiple destinations necessary either star topology interconnect, make buffered reclocked serial inputto-output connections controlled Routing Matrix. Parity Generation Parity generation enabled only when receive FIFO bypassed (FIFOBYP* LOW) decoder enabled (ENCBYP* LOW). this mode parity provided RXDATA[8] output. This ensures that least data always logic-1. generated parity valid RXD[7:0], RXSC/D*, RXRVS signals. Receive Control State Machine Receive Control State Machine responds multiple input conditions control routing handling received characters. controls staging characters across various registers Receive FIFO. also interprets embedded Special Character codes, converts appropriate ones specific combinations Receive FIFO. controls various discard policies error control within receiver, operates response received character stream detection validation serial addresses room additional data Receive FIFO state receiver BIST enable (RXBISTEN*) state LOOPTX state FIFOBYP*
CY7C924DX
These signals conditions used Receive Control State Machine control Receive Formatter, write access Receive FIFO, write access Elasticity Buffer, Byte-Unpacker, Receive Output register, BIST. They determine content characters passed each these destinations, Receive Control State Machine always operates synchronous recovered character clock (bit-clock/10 bitclock/12). When Receive FIFO bypassed, RXCLK becomes output that changes synchronous internal character clock. RXCLK operates same frequency internal character clock. Discard Policies When Receive FIFO enabled, Receive Control State Machine ability selectively discard specific characters from data stream that determined present configuration being unnecessary. When discarding enabled, reduces host system overhead necessary keep Receive FIFO from overflowing losing data. discard policy configured part operating mode using RXMODE[1:0] inputs. four discard policies listed Table Table Receiver Discard Policies Policy Policy Description Keep received characters Process Commands, discard last C5.0 character Process Commands, discard C5.0 characters Process Commands, discard C5.0 characters, discard serial addresses RXCLK Policy simplest also applies conditions where Receive FIFO bypassed. this mode, every character that received placed into Receive FIFO (when enabled) into Receive Output Register. discard policy Start Cell, extended command, serial address commands processed they received. C5.0 character, which automatically transmitted when data present Transmit FIFO, treated differently here. this mode, whenever more adjacent C5.0 characters received, them discarded except last received before other character type. This allows these fill characters removed from data stream, does change data flow protocols (like Fibre Channel) that single C5.0 character delimiter. Policy identical policy except that C5.0 characters removed from data stream. Policy super-set policy where serial address also discarded. When FIFOs bypassed (FIFOBYP* LOW), characters actually discarded, receiver discard policy used control external filtering data. RXEMPTY* FIFO flag used indicate character output valid not. discard policy RXEMPTY* flag always deasserted indicate that valid data always present. discard policy RXEMPTY* flag indicates empty condition last C5.0 character RCLK WCLK RXCLK CY7C42x5 FIFO REN* REN* WEN* CY7C924DX RXEN RXEMPTY RXDATA RXSC/D* before other character presented. discard policies RXEMPTY* flag indicates empty condition C5.0 characters. When other character present, this flag indicates that valid "interesting" Data Special Characters present. Receive FIFO Receive FIFO used buffer data captured from selected serial stream later processing host system. This FIFO sized hold 256, 14-bit characters. When FIFO enabled, written Receive Control State Machine. When data present Receive FIFO indicated RXFULL*, RXHALF*, RXEMPTY* Receive FIFO status flags), read from Output Register asserting RXEN*. read port Receive FIFO configured same timing models transmit interface: UTOPIA Cascade. Both forms FIFO interface. UTOPIA timing model active RXEMPTY* RXFULL* status flags, active RXEN* enable. When configured Cascade operation, these same signals active HIGH. Either timing model supports connection various host interfaces, state machines, external FIFOs depth expansion (see Figure
EXTFIFO
Figure External FIFO Depth Expansion CY7C924DX Receive Data Path Receive FIFO presents Full, Half-Full, Empty FIFO status flags. These flags provided synchronous RXCLK allow operation with Moore-type external controlling state machine. When configured with Receive FIFO enabled, RXCLK input. When Receive FIFO bypassed (FIFOBYP* LOW), RXCLK output operating received character rate. Receive Input Register input register clocked rising edge RXCLK. samples numerous signals that control reading Receive FIFO operation Receive Control State Machine. Receive Output Register Receive Output Register changes response rising edge RXCLK. Receive FIFO status flag outputs this register placed High-Z state when CY7C924DX addressed (AM* sampled HIGH).
CY7C924DX
RXDATA output drivers enabled when device selected RXEN* being asserted RXCLK cycle immediately following that which device addressed (AM* sampled LOW), RXEN* being sampled RXCLK. This initiates Receive FIFO read cycle. Table Receive Output Signal Receive Decoder Mode[1] Decoded 10-bit Character Stream (8-bit characters) ENCBYP* BYTE8/10* RXDATA RXSC/D* RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXINT/RXOP/RXDATA[8] (FIFOBYP*=HIGH) RXINT/RXOP/RXDATA[8] (FIFOBYP*=LOW) RXDATA[9] RXRVS/RXDATA[10] RXSOC/RXDATA[11] RXSC/D* RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXINT RXOP (LOW) RXRVS RXSOC RXD[0][5] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[8] RXD[9] RXSC/D* RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[8] RXD[9] RXRVS RXSOC RXD[0][5] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[8] RXD[9] RXD[10] RXD[11] HIGH HIGH Decoded 10-bit Byte-Packed Character Stream (10-bit characters) HIGH Just with TXDATA Transmit Input Register, receive outputs also mapped specific decoding, parity, bus-width selected ENCBYP*, BYTE8/10* FIFOBYP* inputs. These assignments shown Table
Undecoded 10-bit Character Stream HIGH
Undecoded 12-bit Character Stream
Note: First shifted Others follow numerical order interpreted from pattern.
When Decoder Receive FIFO both enabled, Receive Control State Machine interprets discards (except discard policy received C0.0 C3.0 command codes clear directives RXINT output. This allows RXINT output duplicate state transitions pre-
sented TXINT input source link. This RXINT output used, along with TXHALT*, TXINT, RXHALF*, implement back-pressure mechanism Receive FIFO, other time dependent signalling.
CY7C924DX
Receive FIFO Decoder bypassed, received characters passed directly Receive Output Register. framing enabled, K28.5 characters have been detected meeting present framing requirements, output characters will appear proper character boundaries. framing disabled (RFEN LOW) K28.5 characters have been detected data stream, received characters output their proper 10-bit boundaries. this mode, some form external framing decoding/descrambling must used recover original source data. Serial Address Register receiver capable selectively accepting discarding received data based address received data stream. address matching capability allows choice matching either domains (multicast) exact addresses (unicast). 10-bit Serial Address Register represents single character address field shown Figure multicast mode bit-specific allows allocation separate domains. unicast address mode match character specific identifies 1024 destination addresses. device either belong more domains, have single unique address. When serial address received match detected, address, data following that address, passed Receive FIFO (except discard policy where address discarded). This continues until serial address received that does match contents Address Register, whereupon writes Receive FIFO inhibited. Serial Address Register power-up default state where multicast field ones condition (FFh 3FFh). When this value receiver accepts data, regardless presence content received serial address. This "promiscuous" address also forced momentary assertion RESET*[1:0] pair.
Address Register Content
RXDATA[9] Serial Address Register RXSC/D* RXDATA[0]
RXRST*
RXRVS
RXEN*
Multicast Address write Unicast Address write Multicast Address read Unicast Address read
Figure Serial Address Register Format Access Serial Address Register only used when receiver operated with Receive FIFO enabled (FIFOBYP* HIGH) operating modes where discard policy (see Table list discard policies). Serial Address Register Access Serial Address Register accessed through RXDATA bus. Both reads writes register require device addressed (AM* LOW) RXRST* asserted (LOW). When accessed write read operations, RXRVS signal used read/write selector, RXSC/D* used select operating mode (multicast unicast) Serial Address Register.
CY7C924DX
CY7C924DX Electrical Characteristics Over Operating Range
Parameter Outputs VOHT VOLT IOST IOZL Inputs VIHT VILT IIHT IILT IIHPD IILPU VOHE VOLE VODIF Input HIGH Voltage Input Voltage Input HIGH Current Input Current Input HIGH Current Input Current Output HIGH Voltage (VDD referenced) Output Voltage (VDD referenced) Output Differential Voltage |(OUT+) (OUT-)| Input HIGH Voltage (VDD referenced) Input Voltage (VDD referenced) Input HIGH Current Input Current Input Differential Voltage |(IN+) (IN-)| Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current Power Supply Current VIHH Max. VILL Min. Freq. Max. -200 Typ. Max. VIHE(min.) VILE(max.) 2500 0.0V VCC, Pins with internal pull-down 0.0V, Pins with internal pull-up
Description Output HIGH Voltage Output Voltage Output Short Circuit Current High-Z Output Leakage Current
Test Conditions VOUT
Min.
Max.
Unit
-0.5 +300 -300 1.03 0.83 1.62 1100
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA-, OUTB+, OUTB- Load 1.33V RCURSET= Load 1.33V RCURSET= Load 1.33V RCURSET=
Receiver Single-ended PECL-Compatible Input Pin: CARDET VIHE VILE IIHE IILE VDIFF VIHH VILL IIHH IILL[8] 1.165 1.475
Differential Line Receiver Input Pins: INA+, INA-, INB+, INB-
Miscellaneous
Capacitance[10]
Parameter CINTTL Description Input Capacitance Test Conditions 25°C, MHz, 5.0V 25°C, MHz, 5.0V Max. Unit
PECL input Capacitance CINPECL Notes: Tested output time, output shorted less than second, less than duty cycle. output current (resulting voltage swing) using single resistor between CURSETx VSS. This CURSET resistor value calculated RCURSET (100 *ZO)/VODIF, where differential load between true compliment outputs differential driver. guarantee positive currents PECL voltages, external pull-down resistor must present. Maximum measured with MAX, RFEN LOW, outputs unloaded. Typical measured with 5.0V, 25°C, RFEN LOW, outputs unloaded. Tested initially after design process changes that affect these parameters, 100% tested.
CY7C924DX
Test Loads Waveforms
5.0V OUTPUT (Includes fixture probe capacitance)
[11]
1.33V (Includes fixture probe capacitance)
[11]
Test Load
3.0V =1.5V 0.0V 2.0V 0.8V 3.0V 2.0V 0.8V
PECL Test Load
VIHE VILE
Note
VIHE VILE
=1.5V
Input Test Waveform
PECL Input Test Waveform
CY7C924DX Transmitter Switching Characteristics, FIFO Enabled Over Operating Range
Parameter tTXCLK tTXCPWH tTXCPWL tTXCLKR[10] tTXCLKF[10] tTXA tTXDS tTXDH tTXENS tTXENH tTXRSS tTXRSH tTXAMS tTXAMH tTXZA tTXOE tTXAZ TXCLK Period TXCLK HIGH Time TXCLK Time TXCLK Rise Time[12] TXCLK Fall Time[12] Flag Access Time From TXCLK Output Transmit Data Set-Up Time TXCLK Transmit Data Hold Time from TXCLK Transmit Enable Set-Up Time TXCLK Transmit Enable Hold Time from TXCLK Transmit FIFO Reset (TXRST*) Set-Up Time TXCLK Transmit FIFO Reset (TXRST*) Hold Time from TXCLK Transmit Address Match (AM*) Set-Up Time TXCLK Transmit Address Match (AM*) Hold Time from TXCLK Sample TXCLK, Output High-Z Active HIGH Sample TXCLK Output Valid Sample HIGH TXCLK Output High-Z Description TXCLK Clock Cycle Frequency With Transmit FIFO Enabled Min. Max. Unit
Notes: Cypress uses constant current (ATE) load configurations forcing functions. This figure reference only. Input/output rise fall time measured between 0.8V 2.0V.
CY7C924DX
CY7C924DX Receiver Switching Characteristics, FIFO Enabled Over Operating Range
Parameter fRIS tRXCLKIP tRXCPWH tRXCPWL tRXCLKIR[10] tRXCLKIF[10] tRXENS tRXENH tRXRSS tRXRSH tRXAMS tRXAMH tRXA
[13]
Description RXCLK Clock Cycle Frequency With Receive FIFO Enabled RXCLK Input Period RXCLK Input HIGH Time RXCLK Input Time RXCLK Input Rise Time RXCLK Input Fall Time
[12] [12]
Min.
Max.
Unit
Receive Enable Set-Up Time RXCLK Receive Enable Hold Time from RXCLK Receive FIFO Reset (RXRXT*) Set-Up Time RXCLK Receive FIFO Reset (RXRXT*) Hold Time from RXCLK Receive Address Match (AM*) Set-Up Time RXCLK Receive Address Match (AM*) Hold Time from RXCLK Flag Data Access Time from RXCLK Output Sample RXCLK, Output High-Z Active HIGH LOW, Sample RXEN* Asserted RXCLK, Output High-Z Active HIGH Sample RXCLK Output Valid,[13] Sample RXEN* Asserted RXCLK RXDATA Outputs Valid Sample HIGH RXCLK Output High-Z,[13] Sample RXEN* Deasserted RXCLK RXDATA Outputs High-Z
tRXZA[13]
tRXOE[13] tRXAZ[13]
CY7C924DX Transmitter Switching Characteristics, FIFO Bypassed Over Operating Range
Parameter tTRA tREFDS tREFDH tREFENS tREFENH tREFAMS tREFAMH tREFZA tREFOE tREFAZ Description Flag Access Time From REFCLK Output Write Data Set-Up Time REFCLK Write Data Hold Time from REFCLK Transmit Enable Set-Up Time REFCLK Transmit Enable Hold Time from REFCLK Transmit Address Match (AM*) Set-Up Time REFCLK Transmit Address Match (AM*) Hold Time from REFCLK Sample REFCLK, Output High-Z Active HIGH Sample REFCLK Flag Output Valid Sample HIGH REFCLK Flag Output High-Z Min. Max. Unit
Note: Parallel data output specifications only valid outputs loaded with similar loads.
CY7C924DX
CY7C924DX Receiver Switching Characteristics, FIFO Bypassed Over Operating Range
Parameter fROS[14] Description RXCLK Clock Output Frequency-100 MBaud (RANGESEL HIGH, ENCBYP* HIGH BYTE8/10* HIGH) RXCLK Clock Output Frequency-50 MBaud (RANGESEL LOW, ENCBYP* HIGH BYTE8/10* HIGH) RXCLK Clock Output Frequency-100 MBaud 12-bit Encoder Bypass Operation (RANGESEL HIGH, ENCBYP* BYTE8/10* LOW) RXCLK Clock Output Frequency-50 MBaud 10-bit Operation (RANGESEL LOW, ENCBYP* BYTE8/10* LOW) tRXCLKOP tRXCLKOD tRXCLKOR[10] tRXCLKOF[10] tRXENS tRXENH tRXZA[13] tRXOE[13] tRXAZ[13] RXCLK Output Period RXCLK Output Duty Cycle RXCLK Output Rise Time RXCLK Output Fall Time
[12] [12]
Min. 8.33
Max. 16.67
Unit
4.16
8.33
0.25 0.25
Receive Enable Set-Up Time RXCLK Receive Enable Hold Time from RXCLK Sample RXCLK, Outputs High-Z Active Sample RXEN* Asserted RXCLK RXDATA Outputs High-Z Active Sample RXCLK Flag Output Valid Sample RXEN* Asserted RXCLK RXDATA Output Low-Z Sample HIGH RXCLK Flag Output High-Z Sample RXEN* Deasserted RXCLK RXDATA Output High-Z
CY7C924DX Receiver Switching Characteristics Over Operating Range
Parameter tB[17] tIN_J tEFW Time Peak-to-Peak Input Jitter Tolerance Static Alignment
[10, [10, [15,
Description
Min.
Max. 20.0
Unit
Error Free Window
0.65
Notes: period will match period transmitter reference (REFCLK) when receiving serial data. When data interrupted, RXCLK drift REFCLK ±2500 ppm. Receiver (Unit Interval) calculated 1/(fREF when operated 8-bit mode data being received, 1/(fREF *10) remote transmitter data being received. operating link this equivalent when REFCLK character rate. These equations change 1/(fREF when operated 10-bit mode with Encoder bypassed. alternate multiply ratios selected SPDSEL RANGESEL), numerator multiplied respectively. specification Duty Cycle Distortion (DCD), Data Dependant Jitter (DDJ), Random Jitter (RJ). PECL switching threshold midpoint between VOHE, VOLE specifications (approximately 1.33V). Static alignment measure alignment Receiver sampling point center bit. Static alignment measured absolute difference left right edge shifts (|tSH_L tSH_R|) until character error occurs. Error Free Window measure time window between centers where transition occur without causing sampling error. measured over operating range, input jitter
CY7C924DX
CY7C924DX Transmitter Switching Characteristics Over Operating Range
Parameter tB[17] tRISE tFALL Time PECL Output Rise Time 20-80% (PECL Test Load) PECL Output Fall Time 80-20% (PECL Test Load) Deterministic Jitter (peak-peak) Random Jitter
[10, [10] [10, [10] [10]
Description
Min.
Max. 20.0 1700 1700 0.02 0.008 0.08
Unit
Transmitter Total Output Jitter (pk-pk)
CY7C924DX REFCLK Input Switching Characteristics Over Operating Range
Conditions Parameter fREF Description REFCLK Clock Frequency-50 MBaud, 10-bit mode, encoder bypass, REFCLK character rate REFCLK Clock Frequency-50 MBaud, 8-bit mode, REFCLK character rate REFCLK Clock Frequency-50 MBaud, 10-bit mode, encoder bypass, REFCLK character rate REFCLK Clock Frequency-50 MBaud, 8-bit mode, REFCLK character rate REFCLK Clock Frequency-100 MBaud, 10-bit mode, encoder bypass, REFCLK character rate REFCLK Clock Frequency-100 MBaud, 8-bit mode, REFCLK character rate REFCLK Clock Frequency-100 MBaud, 10-bit mode, encoder bypass, REFCLK character rate REFCLK Clock Frequency-100 MBaud, 8-bit mode, REFCLK character rate tREFCLK tREFH tREFL tREFRX REFCLK Period REFCLK HIGH Time REFCLK Time REFCLK Frequency Referenced Received Clock Period
[23]
SPDSEL
RANGESEL BYTE8/10*
Min. 8.33
16.67
Unit
1[22]
16.67
33.33
1[22]
8.33
16.67
16.67
33.3
-0.04
+0.04
Notes: While sending continuous K28.5s, outputs loaded VDD-1.33V, over operating range. While sending continuous K28.7s, after 100,000 samples measured cross point differential outputs, time referenced REFCLK input, over operating range. When configured synchronous operation with FIFOs bypassed (FIFOBYP* LOW), RANGESEL HIGH SPDSEL input ignored operation forced 100-200 MBaud range. REFCLK phase frequency relationship with RXCLK only acts centering reference reduce clock synchronization time. REFCLK must within ±0.04% transmitter reference (REFCLK) frequency, necessitating ±200-PPM crystal.
CY7C924DX
CY7C924DX HOTLink Transmitter Switching Waveforms
Asynchronous (FIFO) Interface Cascade Timing Write Cycle tTXCLK tTXCLKH tTXCLKL
TXCLK
tTXDS
TXDATA[11:0], TXSC/D* Note
tTXDH
TXENH
TXEN
OPERATION
tTXENS
tTXA TXFULL TXHALF* TXEMPTY TXPERR tTXA
Asynchronous (FIFO) Interface UTOPIA Timing Write Cycle
tTXCLK tTXCLKH tTXCLKL
TXCLK
tTXDS
TXDATA[11:0], TXSC/D* Note
TXDH
tTXENS
TXEN*
tTXENH
OPERATION
tTXA TXFULL* TXHALF* TXEMPTY* TXPERR
tTXA
Notes: When transferring data Transmit FIFO from depth expanded external FIFO, data captured from external FIFO clock cycle following actual enable. When writing data from UTOPIA compliant interface, write data captured same clock cycle data.
CY7C924DX
CY7C924DX HOTLink Transmitter Switching Waveforms (continued)
Asynchronous (FIFO) Interface Output Enable Timing tTXCLKH
TXCLK
tTXCLK tTXCLKL
tTXDS
TXDATA[11:0], TXSC/D* Note
tTXDH
tTXENS
TXEN*
TXENH
OPERATION
tTXAMS tTXRSS
TXRST*
tTXAMH, TXRSH,
TXOE
TXFULL* TXHALF* TXEMPTY* TXPERR
tTXOAZ
tTXOZA
Synchronous Interface Cascade Timing Write Cycle
tREFCLK tREFH tREFL
REFCLK
tREFDS
TXDATA[11:0], TXSC/D* Note
tREFDH
REFENH
TXEN
OPERATION
REFENS
tTRA TXFULL TXHALF* TXEMPTY TXPERR tTRA
Note: Transmit FIFO Writes permitted while status flag outputs High-Z, however operation this mode encouraged since this mask FIFO full condition, causing data lost.
CY7C924DX
CY7C924DX HOTLink Transmitter Switching Waveforms (continued)
Synchronous Interface UTOPIA Timing Write Cycle tREFCLK tREFH REFL
REFCLK
tREFDS
TXDATA[11:0], TXSC/D* Note
tREFDH
tREFENS
TXEN*
REFENH
OPERATION
tTRA TXFULL* TXHALF* TXEMPTY* TXPERR
Synchronous Interface Output Enable Timing tREFH
REFCLK
tREFCLK tREFL
tREFDS
TXDATA[11:0], TXSC/D* Note
tREFDH
tREFENS
TXEN*
tREFENH
OPERATION
tREFAMS
tREFAMH
tREFOE
TXFULL* TXHALF* TXEMPTY* TXPERR
tREFOAZ
tREFOZA
CY7C924DX
CY7C924DX HOTLink Receiver Switching Waveforms
Cascade Timing Read Cycle tRXCLKOH tRXCLKIH
RXCLK
tRXCLKOP tRXCLKIP tRXCLKOL tRXCLKIL
tRXENS
RXEN
READ
tRXENH
OPERATION READ
RXEMPTY RXDATA[11:0] RXSC/D* RXINT, LFI* RXFULL RXHALF* Note
FIFO EMPTY
VALID DATA
Note
UTOPIA Timing Read Cycle tRXCLKOH tRXCLKIH
RXCLK
tRXCLKOP tRXCLKIP tRXCLKOL tRXCLKIL
tRXOENS tRXIENS
RXEN*
READ
tRXIENH, tRXOENH
RXEMPTY* RXDATA[11:0] RXSC/D* RXINT, LFI* RXFULL* RXHALF*
FIFO EMPTY
VALID DATA
Note
Notes: When transferring data from Receive FIFO depth expanded external FIFO, data sent external FIFO same clock cycle RXEMPTY indicates data available. inhibited reads, Receive FIFO goes empty, data outputs change. When reading data from UTOPIA compliant interface, data captured same clock cycle FIFO flag indicates data available, when FIFO indicates empty.
CY7C924DX
CY7C924DX HOTLink Receiver Switching Waveforms (continued)
Output Enable Timing tRXCLK tRXCLKH
RXCLK
tRXCLKL
tRXOENS tRXIENS
RXEN*
tRXIENH, RXOENH
OPERATION
tRXOAMS tRXIAMS
tRXIAMH, RXOAMH
RXFULL* RXHALF* RXEMPTY* RXDATA[11:0] RXINT RXSC/D*
tRXOE
DATA
tRXAZ
Note
RXOOZA tRXIOZA
tREFCLK tREFL tREFH
REFCLK
Static Alignment
tB/2 INA± INB± tB/2
Error-Free Window
tEFW INA± INB± SAMPLE WINDOW CENTER CENTER
Note: Receive FIFO Reads inhibited while outputs High-Z RXBISTEN* active.
CY7C924DX
CY7C924DX HOTLink Transceiver Operation
interconnection more CY7C924DX Transceivers form general-purpose communications subsystem capable transporting user data MBytes second over several types serial interface media. CY7C924DX highly configurable with multiple modes operation. transmit section CY7C924DX, data moves from input register, through Transmit FIFO, 8B/10B Encoder. encoded data then shifted serially OUTx± differential PECL compatible drivers. bit-rate clock generated internally from 2.5x, clock multiplier. more complete description found section CY7C924DX HOTLink Transmit-Path Operating Mode Description. receive section CY7C924DX, serial data sampled receiver INx± differential line receiver inputs. receiver clock data recovery locks onto selected serial stream generates internal bit-rate sample clock. stream deserialized, decoded, presented Receive FIFO, along with character clock. data FIFO then read either slower faster than incoming character rate. more complete description found section CY7C924DX HOTLink Receive-Path Operating Mode Description. Transmitter Receiver parallel interface timing functionality configured Cascade directly external FIFOs depth expansion, emulate UTOPIA interface, couple directly registers, couple directly state machines. These interfaces accept output either: 8-bit characters 10-bit characters (for byte-packed encoded transport) 10-bit pre-encoded characters (pre-scrambled pre-encoded) 12-bit pre-encoded characters (pre-scrambled pre-encoded) numbering content parallel transmit interface shown Table When operated with 8B/10B Encoder bypassed, TXSC/D* RXSC/D* bits ignored. HOTLink Transceiver serial interface provides seamless interface various types media. minimal number external passive components required properly terminate transmission lines provide LVPECL loads. power supply decoupling, single capacitor range 0.02 required power/ground pair. Additional information interfacing these components various media found HOTLink Design Considerations application note. Asynchronous Byte-Packed Asynchronous Pre-encoded Synchronous Encoded this mode, Transmit FIFO bypassed, while 8B/10B encoder enabled. character accepted Transmit Input Register rising edge REFCLK, passed Encoder where encoded serial transmission. Serializer operates synchronous REFCLK, which multiplied generate serial data bit-clock. this mode TXSOC, TXRST*, TXINT, TXHALT*, TXSTOP* inputs (when they used data bits) interpreted tied either HIGH LOW. place CY7C924DX into synchronous modes, FIFOBYP* must LOW. This mode usually used products that must meet specific predefined protocol requirements, cannot tolerate uncontrolled insertion C5.0 fill characters. host system required provide data every rising edge REFCLK (along with TXEN*) maintain data stream. TXEN* asserted, Encoder loaded with C5.0 (K28.5) sync characters. Because Encoder enabled, transmitted C5.0 characters follow 8B/10B encoding rules. Input Register Mapping Encoded modes, bits TXDATA input mapped into characters shown Table including TXSVS bit, eight bits data, TXSC/D* select either Special Character codes Data characters. When internal FIFO enabled, TXINT TXSOC bits associated with TXDATA bus. When internal FIFO disabled TXPAREN TXOPIN associated with TXDATA bus. When parity generation enabled (TXPAREN HIGH) TXOPIN interpreted parity remaining bits character. When parity generation disabled (TXPAREN LOW) TXOPIN ignored TXSVS HIGH, (C0.7) character passed encoder, regardless contents other TXDATA inputs. TXSVS LOW, associated TXDATA character encoded remaining bits that character. TXSC/D* controls encoding TXDATA[7:0] TXDATA[9:0] bits each character. used identify input character represents Data Character Special Character code. TXSC/D* LOW, character encoded using Data Character codes listed Table TXSC/D* HIGH, character encoded using Special Character codes listed Table Parity Synchronous Encoded operation allows parity checking characters written Transmit Input Register. parity error detected TXPERR output goes HIGH REFCLK period. specific character characters having parity errors replaced Encoder with (C0.7) character, which then detected remote receiver. Synchronous Pre-encoded synchronous pre-encoded mode, both Transmit FIFO 8B/10B encoder bypassed, data passes directly from Transmit Input Register Serializer. Serializer operates synchronous REFCLK, which multi-
CY7C924DX HOTLink Transmit-Path Operating Mode Descriptions
HOTLink Transmitter configured into several operating modes, each providing different capabilities fitting different transmission needs. These modes selected using FIFOBYP*, ENCBYP* BYTE8/10* inputs CY7C924DX Transceiver. These modes reduced five primary classes: Synchronous Encoded Synchronous Pre-encoded Asynchronous Encoded
CY7C924DX
plied when BYTE8/10* HIGH selected SPDSEL RANGESEL inputs) generate serial data bit-clock. this mode TXINT, TXHALT*, TXSVS TXSOC inputs used part data input bus. place CY7C924DX into synchronous modes, FIFOBYP* must LOW. This mode usually used products containing external encoders scramblers, that must meet specific protocol requirements. host system required provide data every rising edge REFCLK (along with TXEN*) maintain data stream. TXEN* asserted, Serializer loaded with C5.0 (K28.5) sync characters. However, because bypassed encoder able track running disparity previously transmitted character, transmitted C5.0 characters received with running disparity code-rule violation. this mode each input character (TXDATA[0]) shifted first, followed sequentially TXDATA[1] through TXDATA[9]. Asynchronous Encoded Asynchronous Encoded mode most powerful operating mode CY7C924DX. Both Transmit FIFO Encoder enabled. This allows transmission normal data streams, while offering added benefits embedded cell packet markers, expanded command set, serial addressing, in-band bypass-signaling (for flow control other purposes). Serializer operates synchronous REFCLK, which multiplied 2.5, generate serial data bit-clock selected SPDSEL RANGESEL). this mode TXSOC, TXRST*, TXINT, TXHALT*, TXSTOP* inputs interpreted. This mode supports same Input Register mapping Synchronous Encoded mode, with addition TXSOC bit. Because both Transmit FIFO Encoder enabled, input FIFO loaded rate supported FIFO MHz), without generating decoder errors receive link. characters added data stream support these additional capabilities automatically extracted Receive Control State Machine CY7C924DX Receiver. Embedded Cell Marker embedded cell marker used mark start cells frames information passed from link other. This marker asserting TXSOC HIGH, with TXSC/D* TXSVS both LOW, along with remaining data TXDATA bus. When character characters) accompanying this marker read from output Transmit FIFO, C8.0 (K23.7) character inserted into data stream prior following data characters being read from Transmit FIFO. Expanded Commands standard 8B/10B Character contains possible data characters, only twelve special command characters. allow larger selection command codes, Special Character code selected expand command set. expanded command marker used mark associated data (28) possible commands codes. This marker generated asserting both TXSOC TXSC/D* HIGH, with TXSVS being LOW, along with associated data TXDATA bus. When character accompanying this marker read from output Transmit FIFO, C9.0 (K27.7) character inserted into data stream prior data characters read from Transmit FIFO. Serial Addressing CY7C924DX receiver ability accept reject data based internal address-controlled switch. This switch turned when serial address (matching receiver address settings) received. serial address transmitted asserting TXSOC, TXSC/D*, TXSVS HIGH. When character accompanying this marker read from output Transmit FIFO, C10.0 (K29.7) character inserted into data stream prior data characters read from Transmit FIFO. serial address either 10.bits depending level BYTE8/10*. In-Band Bypass-Signaling In-band bypass-signaling allows signal sent remote receiver without that signal having pass through Transmit Receive) FIFO. When TXINT transitions from C0.0 (K28.0) special character sent. When TXINT transitions from C3.0 (K28.3) special code sent. These special codes used force similar signal transition RXINT output attached CY7C924DX HOTLink Receiver. This input used transport data rate signal (like serial RS-232/UART signal) across interface, without significant impact actual data being transported across link. also used transparently propagate FIFO flow control information across link directly connecting RXHALF* flag local receiver TXINT local transmitter. RXINT remote link then connected TXHALT* input halt data transfers remote link until local Receive FIFO sufficient room continue. Asynchronous Byte-Packed Asynchronous byte-packed mode contains same features asynchronous encoded, with support 10-bit source data. This data byte-packed through 8B/10B encoder deliver data across interface. When sending extended commands, larger 10-bit character size enlarges extended command space 1024 (210) possible commands codes. Asynchronous Pre-encoded Asynchronous pre-encoded modes, Transmit FIFO enabled. This means that words clocked into input register written Transmit FIFO before being sent Serializer. Serializer operates synchronous REFCLK, which multiplied when BYTE8/10* LOW) generate serial data bit-clock. this mode TXINT TXHALT* inputs used part 10-bit input character. TXSVS, TXSOC TXSTOP* still available stop reading data from Transmit FIFO. These modes usually used products containing external encoders scramblers, that must meet specific protocol requirements. host system must provide data every rising edge TXCLK (along with TXEN*) maintain
CY7C924DX
data stream (without overfilling Transmit FIFO). Transmit FIFO ever goes empty, Serializer loaded with alternating disparity string C5.0 (K28.5) sync characters (when BYTE8/10* HIGH) pattern 0110000100011 (when BYTE8/10* LOW). Depending system implementation this significant issue. remote receiver configured decode 8B/10B coded characters, will probably detect running disparity errors because bypassed Encoder able track running disparity previously transmitted character. However, since these pre-encoded modes generally used with alternate forms scrambling encoding, this generally issue. maintain data stream without adding these C5.0 SYNC codes, necessary that Transmit FIFO loaded faster than rate that data read from that FIFO. Synchronous Decoded these modes, Receive FIFO bypassed, while 10B/8B Decoder enabled. Framed characters output from Deserializer decoded, passed direct Receive Output Register. Deserializer operates synchronous recovered bit-clock, which divided generate output RXCLK clock. this mode RXRST* input interpreted biased either HIGH LOW. These modes usually used products that must meet specific protocol requirements. decoded characters provided RXDATA outputs once every rising edge RXCLK. RXEMPTY asserted HIGH along with data, characters output register C5.0 (K28.5) sync character, discard policy non-0. Because decoder enabled, received characters checked compliance 8B/10B decoding rules. Output Register Mapping RXDATA[11:0] output mapped into character consisting eight bits data, bits that carry Violation Parity information. accompanying RXSC/D* identifies character either control data. bits accompanying each character interpreted differently depending configuration selected. When parity generation enabled, parity contains parity RXDATA bus. When parity generation disabled, these bits have combinations that identify meaning remaining bits character. RXRVS HIGH RXSC/D* LOW, decoder outputs C0.7, C1.7, C2.7 C4.7 response reception either (C0.7) character other invalid character. Parity Synchronous Decoded modes allows parity generation decoded characters. characters detected with parity errors transmitter, they will have been replaced with (C0.7) character. C0.7 character received indication parity error transmitter. Synchronous Undecoded this mode, both Receive FIFO 10B/8B Decoder bypassed, data passes directly from Deserializer output register. Deserializer operates synchronous recovered bit-clock, which divided generate output RXCLK clock. this mode RXRST* input interpreted biased either HIGH LOW. This mode usually used products containing external decoders descramblers that must meet specific protocol requirements. data provided RXDATA outputs once every rising edge RXCLK. Received characters checked specific coding requirements decoding errors reported. Asynchronous Decoded Asynchronous Decoded modes most powerful operating modes CY7C924DX HOTLink Receiver. Both Receive FIFO Decoder enabled. This allows reception normal data streams, while offering added benefits embedded cell markers, expanded command set, serial address support, in-band bypass-signaling (for flow control other purposes). characters added data stream support these additional capabilities auto-
CY7C924DX HOTLink Receive-Path Operating Mode Descriptions
HOTLink Receiver configured into several operating modes, each providing different capabilities fitting different reception needs. These modes selected using FIFOBYP*, ENBYP*, BYTE8/10* inputs CY7C924DX Transceiver. These modes reduced five primary classes: Synchronous Decoded Synchronous Undecoded Asynchronous Decoded Asynchronous Byte-Packed Asynchronous Undecoded these modes, serial data received differential line receiver inputs routed Deserializer Framer. clock data recovery block used extract bit-rate clock from transitions data stream, uses that clock capture bits from serial stream. These bits passed Deserializer where they formed into 12-bit characters. align incoming stream proper character boundaries, Framer must enabled asserting RFEN HIGH. Framer logic-block checks incoming stream unique pattern that defines character boundaries. This logic filter looks ANSI X3.230 symbol defined "Special Character Comma" (K28.5 C5.0). Once K28.5 found, Framer captures offset data stream from present character boundaries, resets boundary reflect this offset, thus framing data correct character boundaries. Since noise induced errors cause incoming data corrupted, since many combinations corrupt legal data create aliased K28.5, framer also disabled deasserting RFEN LOW. option exists framer require multiple K28.5 characters, meeting specific criteria, before character boundaries reset. This multi-byte mode Framer enabled keeping RFEN asserted HIGH greater than approximately 2000 character clock cycles. multi-byte framing, receiver must find pair K28.5 characters, both identical 10-bit boundaries, within 5-character span bits).
CY7C924DX
matically extracted Receive Control State Machine CY7C924DX Transceiver. deserializer operates synchronous recovered bitclock, which divided generate Receive FIFO write clock. Characters read from Receive FIFO, using external RXCLK input, when addressed selected RXEN*. this mode RXRST* input interpreted. Asynchronous Decoded modes support same Output Register mapping Parity generation capabilities Synchronous Decoded modes. Because both Receive FIFO Decoder enabled, output FIFO read rate supported FIFO, however, Receive FIFO ever indicates full condition (RXFULL* asserted), data lost. Embedded Cell Marker embedded cell marker used mark start cells frames information passed from link other. When C8.0 (K23.7) character detected data stream, following character written Receive FIFO along with RXSOC HIGH, RXSC/D* RXRVS LOW. When character accompanying this marker read from Receive FIFO with these same bits set, indicates start cell frame. Expanded Command standard 8B/10B Character contains possible data characters, only twelve Special Character codes. allow larger selection command codes, Special Character code selected expand command set. Expanded Command marker used mark associated data (28) possible commands codes. When C9.0 (K27.7) character detected data stream, following character written Receive FIFO along with both RXSOC RXSC/D* HIGH, RXRVS LOW. When character accompanying this marker read from Receive FIFO with these same bits set, used indicate that data RXDATA Expanded Command. Serial Addressing CY7C924DX receive path directed accept characters, only accept that data specifically addressed This address control managed through embedded Address Compare Register receiver logic. This register supports either domain (multicast) exact-match (unicast) based compares address field received across serial link. When C10.0 (K29.7) special code received, immediately following data character contains address field that compared with receiver Serial Address Register contents. When CY7C924DX configured multicast address matching, received address field compared bit-wise with Serial Address Register. valid match between bits sets switch allow following data written into Receive FIFO. When CY7C924DX configured unicast address matching, received address field compared exact match with Serial Address Register. exact match found, switch receiver accept following data until next serial address marker found. In-Band Bypass-Signaling In-band bypass-signaling allows signal received local receiver without that signal having pass through Receive Transmit) FIFO. When C0.0 (K28.0) character received, RXINT output HIGH. When C3.0 (K28.3) character received, RXINT output LOW. These special codes generated forcing similar transitions into TXINT input CY7C924DX HOTLink Transmitter sourcing data stream. This output used transport data-rate signal (like serial RS-232/UART signal) across interface, without significant impact actual data being transported across link. also used transparently propagate FIFO flow-control information across link directly connecting RXHALF* flag local receiver TXINT local transmitter. RXINT remote link then connected TXHALT* input halt data transfers remote link until local Receive FIFO sufficient room continue. Asynchronous Byte-Packed Asynchronous byte-packed mode contains same features asynchronous decoded, with support 10-bit source data. received characters decoded first back into 8-bit data characters, which then re-assembled into 10-bit source data. Because time difference involved with packing unpacking operations, this mode only used with internal FIFOs enabled. When receiving extended commands, larger 10-bit character size enlarges extended command space 1024 (210) possible commands codes. When receiving serial address, larger 10-bit character size also increases Serial Address Register bits. This allows separate domains multicast addressing 1024 unique addresses unicast addressing. Asynchronous Undecoded Asynchronous Undecoded modes, Receive FIFO enabled. This means that characters received from serial interface written Receive FIFO before being passed output register. Deserializer operates synchronous recovered bit-clock, which divided generate Receive FIFO write clock. Data read from Receive FIFO, using RXCLK input clock, when addressed selected RXEN*. These modes usually used products co
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