PEDL7662-02 This version: Oct. 1999 MSM7662 Previous version Oct. 1998

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PEDL7662-02
PEDL7662-02 This version: Oct. 1999 MSM7662 Previous version Oct. 1998
Semiconductor MSM7662
Semiconductor NTSC/PAL Digital Video Decoder
GENERAL DESCRIPTION
MSM7662 device that decodes NTSC analog video signals into YCbCr digital data based ITU-RBT.601. device built-in channels converters accept composite video video signals input video signals. Composite video signals converted YCbCr digital data 2-dimensional separation circuit with adaptive filter. Analog video signals sampled clock pixel frequency twice pixel frequency. decimation filter built-in sampling twice pixel frequency. Input signals synchronized internally high-speed locking color burst possible. Because FIFO buffer built into output format circuit, jitter-free output obtained even non-standard signals.
APPLICATION EXAMPLES
Since synchronization input signals high-speed locking color burst possible, device optimized applications used switching multiple cameras. also used various image processing applications because jitter-free output data through built-in FIFO buffer. 8-bit (YCbCr), 16-bit (8-bit 8-bit (CbCr)), 24-bit (RGB) output interfaces selected output mode that various devices such monitoring system, digital video memory, digital video processing unit video communication unit selected receiving side.
FEATURES feature found MSM7661B)
Input analog signal NTSC/PAL composite video signal S-video signal Maximum composite S-video composite analog inputs connected (switchable external pins internal registers) Built-in clamp circuits video amps Built-in 8-bit converters channels) selectable output interfaces ITU-RBT.656 (conditional) 8-bit (YCbCr) 8-bit (YCbCr) YCbCr 2/YCbCr (limit) 16-bit (YCbCr) 8-bit 8-bit (CbCr) YCbCr 2/YCbCr (limit) 24-bit 8-bit 8-bit 8-bit 2-dimensional separation using adaptive comb filter (this filter bypassed S-video signal input) NTSC format: lines lines, format: lines virtual lines) Selectable data signal synchronization synchronization modes, internal FIFO modes (FIFO-1, FIFO-2) external field memory modes (FM-1, FM-2), selectable (FIFO-1 normally selected).
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PEDL7662-02 Semiconductor MSM7662
13.5 (13.5/27 MHz) NTSC/PAL ITU-RBT.601 12.272727 (12.272727/24.545454 MHz) NTSC Square pixel 14.31818 (14.31818/28.63636 MHz) NTSC 4fsc 14.75 (14.75/29.5 MHz) Square Pixel Built-in AGC/ACC circuits, compatible with wide range input levels Input level range: +3.5 (0.4 Switchable between AGC/MGC (fixed gain) ACC/MCC (fixed gain) Decimation filter built into input stage, allows easy configuration filter prior converter (when input twice pixel frequency) Automatic NTSC/PAL recognition (only ITU-RBT.601) Sleep mode Multiplex signal recognition (closed caption) During vertical blanking interval, data output 8-bit data. I2C-bus interface single power supply (I/O tolerance) Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB)
Compatible pixel frequencies (normal/twice pixel frequency)
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BLOCK DIAGRAM
Semiconductor
CLKX2O INS[2:0] GAINS[2:0] CLKXO
CLKX2 CLKSEL
PLLSEL
VSYNC_L HVALID
VVALID
STATUS1
STATUS3
HSYNC_L
ODD/EVEN
STATUS2
Synchronization Block VRT2 ADIN2 AMPOUT2 CLPOUT2 VRB2 VIN6 VIN5
Matrix
M[7:4] M[2:1]
ANALOG AGC&
Decimation Filter Decimation Filter
Prologue Block
Luminance Block DIGITAL (AGC LPF) Epilogue Block
Dim. separate) Line Memory Chrominance Block (ACC LPF)
ITU-656 bits (YCbCr)
Y[7:0] (G[7:0])
VIN4 VIN3 VIN2 VIN1 VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 VRT1
ANALOG AGC& I2C-bus Control Logic Test Control Logic
Output Formatter
bits bits (CbCr)
C[7:0] (R[7:0])
bits bits bits
B[7:0]
PEDL7662-02
MSM7662
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MODE[3:0]
RESET_L
SLEEP
SCAN
TEST[2:0]
PEDL7662-02
Semiconductor
GAINS[0] GAINS[1] GAINS[2] DAGND INS[0] INS[1] INS[2] DGND DVDD
DAVDD VRT2 VIN6 VIN5 ADDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD
MSM7662
CONFIGURATION (TOP VIEW)
STATUS1
STATUS2
STATUS3
CLKX2O
CLKXO
HSYNC_L VSYNC_L VVALID HVALID ODD/EVEN C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] DGND DVDD Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] DVDD DGND
CLKX2 B[4]
DAGND
MODE[0]
MODE[1]
MODE[2]
MODE[3]
SCAN
TEST[2]
TEST[1]
TEST[0]
SLEEP
RESET_L
DVDD
DGND
PLLSEL
CLKSEL
B[7]
B[6]
B[5]
B[3]
B[2]
DGND
DVDD
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
B[1]
100-Pin Plastic TQFP
B[0]
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PEDL7662-02 Semiconductor MSM7662
DESCRIPTIONS
Symbol DAVDD VRT2 VIN6 VIN5 AVDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD DAGND Type Description Digital power supply converter converter reference voltage (high side) S-video chroma signal S-video chroma signal (C-2) input (leave open connect AGND when used) Composite-5 S-video chroma signal (C-1) input (leave open connect AGND when used) Analog power supply Analog ground converter input S-video chroma signal S-video chroma signal output S-video chroma signal clamp voltage output converter reference voltage (low side) S-video chroma signal Analog ground Analog ground converter reference voltage (low side) composite/S-video (luminance signal) Composite/S-video (luminance signal) clamp voltage output Composite/S-video (luminance signal) output converter input composite/S-video (luminance signal) S-video (luminance signal) clamp voltage input Analog ground Analog power supply Composite-4 input (leave open connect AGND when used) Composite-3 input (leave open connect AGND when used) Composite-2 S-video luminance signal (Y-2) input (leave open connect AGND when used) Composite-1 S-video luminance signal (Y-1) input (leave open connect AGND when used) converter reference voltage (high side) composite/S-video (luminance signal) Digital power supply converter Digital ground converter
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PEDL7662-02 Semiconductor MSM7662
DESCRIPTIONS (continued)
Symbol MODE[0] MODE[1] MODE[2] MODE[3] Type Description switching input during external setting mode (pulled-down internal resistors) Internal/external pins switched register MRA[0] default register MRA[0] external mode. MODE [3:2] Output mode selection ITU-RBT.656 (with 8-bit YCbCr SAV, EAV, blank processing) 8-bit (YCbCr) 16-bit (YCbCr) (ITU-RBT.601) 24-bit MODE Input mode selection NTSC Invalid ITU-RBT.601 signal input while register MRC[7] automatic NTSC/PAL recognition. MODE Input mode selection ITU-RBT.601 Square Pixel NTSC 4fsc register [3:1] only. SCAN TEST[2] TEST[1] TEST[0] SLEEP RESET_L DVDD DGND PLLSEL CLKSEL used. left open fixed (pulled down internal resistor). used. left open fixed (pulled down internal resistor). used. left open fixed (pulled down internal resistor). used. left open fixed (pulled down internal resistor). normal operation, sleep operation Reset input (active "L"). After powering sure reset. Digital power supply Digital ground I2C-bus clock input I2C-bus data used. left open fixed (pulled down internal resistor). Clock select input (pulled down internal resistor). double-speed input mode Data output B[7] B[0] normal input mode When double-speed input mode used, input double frequency system clock. B[7]: MSB, B[0]: During output mode: 8-bit data output Other than output mode: Hi-Z Output mode register [7:6]. DGND DVDD Digital ground Digital power supply
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PEDL7662-02 Semiconductor MSM7662
DESCRIPTIONS (continued)
Symbol Type Data output Description Y[7]: MSB, Y[0]: During ITU-RBT.656 output mode: YCbCr 8-bit data output Y[7] Y[0] During 8-bit (YCbCr) output mode: YCbCr 8-bit data output During 16-bit (YCbCr) output mode: 8-bit data output During 24-bit output mode: 8-bit data output Output mode register [7:6]. DVDD DGND Digital power supply Digital ground Data output C[7]: MSB, C[0]: During ITU-RBT.656 output mode: Hi-Z C[7] C[0] During 8-bit (YCbCr) output mode: Hi-Z During 16-bit (YCbCr) output mode: CbCr 8-bit data output During 24-bit output mode: 8-bit data output Output mode register [7:6]. ODD/EVEN HVALID VVALID VSYNC_L HSYNC_L Field display output field odd, output. Horizontal valid pixel timing output section valid, output. Vertical valid line timing output section valid, output. Vertical sync signal sync) output Horizontal sync signal sync) output Pixel clock output During double-speed input mode (pin half system clock CLKXO frequency output. During normal input mode (pin same frequency system clock frequency output. CLKX2O DGND DVDD System clock output System clock input directly output. Digital ground Digital power supply System clock input (selected operation mode) Normal input mode NTSC ITU-RBT.601 CLKX2 NTSC Square Pixel NTSC 4fsc ITU-RBT.601 Square Pixel 13.5 12.272727 14.31818 13.5 14.75 Double-speed input mode 24.545454 28.63636 29.5
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PEDL7662-02 Semiconductor MSM7662
DESCRIPTIONS (continued)
Symbol Type Status signal output Selected internal register OMR[0] STATUS[3] OMR[0]: OMR[0]: FIFO overflow detection (default) non-detection, detection CSYNC output Status signal output Selected internal register OMR[1] STATUS[2] OMR[1]: OMR[1]: NTSC-PAL recognition (default) NTSC, HLOCK sync detection output non-detection, detection STATUS[1] M[7] M[6] M[5] M[4] M[3] M[2] interval multiplex signal detection output non-detection, detection Field memory control signal; output Field memory control signal; output Field memory control signal; RSTR output Field memory control signal; RSTW output Test output pin, normally output I2C-bus slave address select 1000001X 1000011X internal pull-up pull-down resistor) setting either external internal register order select analog unit gain value (MGC) video signal input pin. internal pull-up pull-down resistor) external mode M[1] Gain value setting: pins (GAINS[2:0]) used Input setting: pins (INS[2:0]) used register mode Gain value setting: register ADC2[6:4] Input setting: register ADC1[2:0] Internal register setting invalid when external mode set. Selection external field memory control signal output M[0] field memory used, M[0] M[7:4] outputs invalid M[7:4] outputs valid DGND DVDD Digital ground Digital power supply Description
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PEDL7662-02 Semiconductor MSM7662
DESCRIPTIONS (continued)
Symbol GAINS[2] GAINS[1] GAINS[0] Type Description Inputs amplifier gain switch setting during external setting mode External mode: (M[1]) (pulled down internal resistors) GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] INS[2] INS[1] INS[0] Gain value times) 1.00 1.35 1.75 2.30 3.00 3.80 5.00 Undefined
Inputs signal input switch setting during external setting mode External mode: (M[1]) (pulled down internal resistors) INS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Input VIN1 (pin Composite-1 VIN2 (pin Composite-2 VIN3 (pin Composite-3 VIN4 (pin Composite-4 VIN5 (pin Composite-5 VIN1 (pin VIN5 (pin VIN2 (pin VIN6 (pin Prohibited setting (ADC enters sleep state)
DAGND
Digital ground converter
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PEDL7662-02 Semiconductor MSM7662
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol TSTG Condition 25°C Rating -0.3 +4.5 -0.3 +5.5 +150 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage Digital Level Input Voltage Digital Level Input Voltage Analog Video Signal Input Operating Temperature Symbol VIH1 VIH2 (*1) VAIN Condition SYNC white peak level Min. Typ. Max. (*2) (*2) Unit VP-P
CLKSEL, SDA, CLKXO Since inputs have tolerance possible apply inputs.
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PEDL7662-02 Semiconductor MSM7662
ELECTRICAL CHARACTERISTICS
Characteristics
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Level Output Voltage Level Output Voltage Symbol Condition (*1) (*2) IOL= (*1) IOL= (*2) Input Leakage Current Output Leakage Current Output Voltage Output Current SDAVL SDAIO Rpull_down (*3) Min. Typ. Max. Unit
HSYNC_L, VSYNC_L, SYSSEL, C[7:0], B[7:0], ODD, VVALID, HVALID, CLKXO, HSY, M[7:0] Y[7:0], CLKX2O MODE[3:0], SCAN, TEST[2:0], PLLSEL, CLKSEL, GAINS[2:0], INS[2:0]
Characteristics (Analog Unit)
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter AMPOUT Output Voltage CLPOUT Output Voltage Output Voltage Output Voltage ADIN Input Current Symbol VOAMP VOCLP VIADIN VIVIN IIVIN Condition Capacitive coupling Min. 0.15 Typ. Max. Unit VP-P
connected between
Characteristics
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Power Supply Current (Operating) Symbol Condition CLKX2 Power Supply Current (Operating) Power Supply Current (Sleep) IDOFF CLKX2 Min. Typ. Max. Unit
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PEDL7662-02 Semiconductor Characteristics (Double Speed Mode)
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Frequency 1/tCLKX2 NTSC 4fsc NTSC Square Pixel Square Pixel CLKX2 Duty Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Clock Delay Time (CLKX2-CLKXO) Output Clock Delay Time (CLKX2-CLKX2O) Clock Cycle Time Level Cycle RESET_L Width tD_D2 tOD21 tOD22 tOD23 tODX21 tODX22 tODX23 tOD2X21 tOD2X22 tOD2X23 tCXD21 tCXD22 tC_SCL tL_SCL tRST_W CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL Rpull_up Rpull_up Min. Typ. 27.0 28.63636 24.545454 29.5 Max. (24) (20) (28) (11) Unit
MSM7662
Output load: Values parentheses indicate delay time when 8-bit YCbCr format data output from pin. clock frequency accuracy within ±100 ppm.
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PEDL7662-02 Semiconductor Characteristics (Single Speed Mode)
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Frequency 1/tCLKX2 NTSC 4fsc NTSC Square Pixel Square Pixel CLKX2 Duty Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Data Delay Time Output Clock Delay Time (CLKX2-CLKXO) Output Clock Delay Time (CLKX2-CLKX2O) Clock Cycle Time Level Cycle RESET_L Width tD_D1 tOD11 tOD12 tOD13 tODX11 tODX12 tODX13 tOD2X11 tOD2X12 tOD2X13 tCXD11 tCXD12 tC_SCL tL_SCL tRST_W CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL Rpull_up Rpull_up Min. Typ. 13.5 14.31818 12.272727 14.75 Max. Unit
MSM7662
Output load: clock frequency accuracy within ±100 ppm.
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PEDL7662-02 Semiconductor MSM7662
INPUT OUTPUT TIMING
Clock Output Timing
CLKSEL: tCLKX1 CLKSEL: tCLKX2
CLKX2 tCXD21 CLKX2O tCXD11 CLKXO tOD11 tOD2X11 tODX11 tOD12 tOD2X12 HVALID, VVALID, HSYNC_L, VSYNC_L tODX12 tOD13 tOD2X13 tODX13 tCXD21 tOD21 tOD2X21 tODX21 tOD22 tOD2X22 tODX22 tOD23 tOD2X23 tODX23 tCXD22
Y[7:0], C[7:0] B[7:0]
STATUS[3:1] M[7:4]
Data Delay (when standard signal input)
Analog Video Data delay Blank delay Decoder output Blank Active Data
pixel rate, absorption difference Video Mode NTSC NTSC NTSC, NTSC, Input Signal Composite Composite Composite Composite S-Video S-Video FIFO/FM Mode FIFO-1 FIFO-1 FIFO-1 Amount Delay 358T 358T 358T 358T 358T 358T
data delay equal blank delay. depends sampling mode. numeric value value) changed according signal state. Since output period fixed during FIFO mode, amount delay changed. separation performed using TRAP filter during mode, added. 14/62
PEDL7662-02 Semiconductor I2C-bus Interface Input/Output Timing basic input/output timing I2C-bus indicated below. MSM7662
Start condition
tC_SCL
Stop condition
Data line stable: data valid
Change data allowed
I2C-bus Timing
tBFU tHD:STA tLOW tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO tHD:STA
Symbol fSCL tBUF tHD: tLOW tHIGH tSU: tHD: tSU: tSU: Frequency Open Period
Parameter
Min.
Max.
Unit
Start Condition Hold Time Clock Period Clock High Period Start Condition Setup Time Data Hold Time Data Setup Time Line Rise Time Line Fall Time Stop Condition Setup Time
I2C-bus timing conforms this table. However, I2C-bus operate faster than speeds, specified above. Actually, frequency about MHz. hold time setup time that case must conform ratio described above table.
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PEDL7662-02 Semiconductor MSM7662
FUNCTIONAL DESCRIPTION
Analog Unit Analog input select: Compatible with composite video signals S-video signals. Input selection switched register control I2C-bus external pins. (See below chart combinations.) Clamp function: analog clamp digital pulse clamp used. Analog clamp Analog clamp Digital clamp (hybrid clamp) Digital clamp Only digital clamp pedestal clamp. Related register MRB[3:2] amp: function operates depending upon input level. Manual gain setting also possible. This function operates stages, analog unit digital unit. Digital decoded data output conformance with ITU-RBT.601. Refer explanation M[1] (pin 90). Related register ADC2[6:4] converter: internal 8-bit converters sample twice pixel frequency. (Sampling pixel frequency possible changing register setting.) Related register ADC1[2:0] List Analog Input Conditions
Input Signal Composite-1 Input* Composite-2 Input Composite-3 Input Composite-4 Input Composite-5 Input S-video-1 Input S-video-2 Input inputs Control Register INS[2:0] ADC1[2:0] VIN1 [000] [001] [010] [011] [100] [101] [110] [111] [000] [001] [010] [011] [100] [101] [110] [111] Luminance Luminance (Sleep) Composite Composite Composite Composite Composite Chroma Chroma VIN2 Input VIN3 VIN4 VIN5 VIN6 Selection
Blank spaces: non-selectable register default setting after reset M[1] setting external mode, internal register mode
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PEDL7662-02 Semiconductor Manual Gain Control (analog gain)
Gain Setting Pins GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Register ADC2[6:4] [000] [001] [010] [011] [100] [101] [110] [111] Gain Value Typ. Value (multiplication factor) 1.35 1.75 Undefined
MSM7662
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PEDL7662-02 Semiconductor Decoder Unit Prologue Block prologue block inputs data performs separation. Data input either pixel frequency (ITU-RBT.601: 13.5 MHz) twice pixel frequency (ITU-RBT.601: MHz). input twice pixel frequency, data processed after passing through decimator circuit convert pixel frequency. decimator circuit bypassed changing register setting, regardless whether data input normal pixel frequency twice pixel frequency. composite signal (CVBS) input, default setting performs separation using 2dimensional adaptive comb filter. following operating modes selected I2C-bus. Default settings indicated asterisk (*). default state selected reset. Video input mode selection (related register MRC[7]) NTSC/PAL auto-select* (only ITU-RBT.601) Dependent upon operating mode selected When ITU-RBT.601 selected, video input mode automatically depending upon number lines field. Operating mode selection (related register MRA[3:1]) NTSC ITU-RBT.601 13.5 MHz* NTSC Square Pixel 12.272727 NTSC 4fsc 14.31818 ITU-RBT.601 13.5 Square Pixel 14.75 Even input twice pixel frequency, internal processing performed pixel frequency. Decimator circuit pass/bypass selection (related register MRC[4]) Pass through decimator circuit* Bypass decimator circuit Compatible only when input twice pixel frequency. separation mode selection (related register MRB[1:0]) adaptive comb filter* non-adaptive comb filter comb filter (use trap filter) adaptive comb filter NTSC signal makes correlation between consecutive lines, separation performed 3-line 2-line comb filter according format correlation. adaptive comb filter signal makes correlation between only lines performs separation switching between 2-line comb filter trap filter. non-adaptive comb filter performs separation removing luminance component based average preceding following lines (when there correlation between lines). (the average lines case signal) When comb filter used, separation performed trap filter. MSM7662
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PEDL7662-02 Semiconductor S-video signal input, these separation circuits bypassed. functions this block only operate when lines valid image information. During blanking interval, CVBS signals processed. Luminance Block luminance block removes synchronous signals from signals containing luminance components after separation. signals compensated then output luminance signals. modes gain control functions selected luminance signal output level: (Auto Gain Control) Pedestal Clamp. mode, luminance level amplification determined comparing SYNC depth with reference value. default 40IRE changed register setting. input sync clamp. Pedestal Clamp mode, signal output level clamped pedestal level input. Signal amplification black level changed from clamped position register settings. This block select follwing operating modes. Selection luminance level limiter usage (related register LUMC[7]) use* When limiter used, luminance level limited 235. Selection prefilter sharp filter usage (related register LUMC[6]) use* These filters used enhance edges luminance component signals. filters operate pairs. their characteristics, refer Filter Characteristics described later. Selection aperture bandpass filter coefficient (related register LUMC[5:4]) Middle range* High range Coring range selection (related register LUMC[3:2]) Off* ±4LBS ±5LBS ±7LBS Aperture weighting coefficient selection (related register LUMC[1:0]) 0.25 0.75 1.50 Both coring aperture compensation processes perform contour compensation. Selection pixel position compensating circuit usage (related register MRC[6]) Use* MSM7662
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PEDL7662-02 Semiconductor MSM7662
loop filter time constant selection (related register AGCLF[7:6]) Slow convergence time Medium Fast Fixed These designed times from input gain being rapidly lowered value stable state when normal signals input till output being returned (actually these times differ depending signal state). Fixed: manual gain setting possible register AGCLF[5:0] Parameter fine adjustment sync depth (related register AGCLF[5:0]) reference level changed. Parameter fine adjustment sync removal level (related register SSEPL[6:0]) black level adjusted. default setting outputs pedestal position black level (=16). 10)Pedestal clamp selection (related register SSEPL[7]) pedestal clamp* pedestal clamp this time, does operate, operates) Chrominance Block This block processes chroma signals. following operating modes selected. Selection chroma bandpass filter usage (related register CHRC[2]) use* loop filter time constant selection (related register ACCLF[6:5]) Slow convergence time 1696 Medium Fast Fixed These designed times from input gain being rapidly lowered value stable state when normal signals input till output being returned (actually these times differ depending signal state). Fixed: manual gain setting possible register ACCLF[4:0] reference level fine adjustment (related register ACCLF[4:0]) reference level changed. Parameter burst level fine adjustment (related register CHRC[1:0]) Threshold level which chroma amplitude becomes valid selected based upon color burst ratio. 0.25* 0.125 Off: color killer function turned off. decoloration occurs while decoding still picture, setting threshold level "off" will reduce decoloration. Color killer mode selection (related register MRB[5]) Auto color killer mode* Forced color killer Parameter fine adjustment color subcarrier phase (related register HUE[7:0]) control function 20/62
PEDL7662-02 Semiconductor MSM7662
this block, chroma signals pass through bandpass filter unnecessary band. maintain constant chroma level, these signals then pass through compensating circuit demodulated. (The filter bypassed.) demodulated result does reach constant level, color killer signals generated gain. This functions auto color killer control circuit. demodulated results pass through low-pass filter output chrominance signals. Synchronization Block This block processes sync signals. Synchronous signals generated chip output internal use. Various signals output from this block following operating modes selected. Adjustment SYNC threshold level (internal sync) (related register STHR[7:0]) SYNC detection level set. Fine adjustment (Horizontal Sync Clamp) signal (related registers HSYT[7:4], HSYT[3:0], MRB[3:2]) 2-1) Fine adjustment signal (start side) 2-2) Fine adjustment signal (stop side) signal provides sync-tip clamp timing converter. This signal used digital clamp, observed from outside. Fine adjustment HSYNC_L signal (related register HSDL[7:0]) HSYNC_L signal output position adjusted. HVALID control (related registers HVALT[7:4], HVALT[3:0]) 4-1) Fine adjustment HVALID signal (start side) 4-2) Fine adjustment HVALID signal (stop side) Data signals transferred rising edge HVALID signal. VVALID control (related registers VVALT[7:4], VVALT[3:0]) 5-1) Fine adjustment VVALID signal (start side) 5-2) Fine adjustment VVALID signal (stop side) FIFO Field Memory mode selection (related register MRB[7:6]) FIFO-1 mode*: Sets outputs standard value number pixels from internal FIFO. This mode also compatible degree) with non-standard signals. FIFO-2 mode: Sets outputs constant pixel number corresponding input interval number pixels from internal FIFO. FM-1 mode: This mode outputs decoded results according SYNC signal. Usage external field memory required manage number pixels absorb jitter. Memory control signals generated externally. FM-2 mode: This mode compatible with considerably distorted non-standard signals. Jitter absorbed using external field memory standard value pixel number. Field memory control signals output simultaneously from M[7:4]. Field memory control signals FM-2 mode uses external field memory instead internal FIFO, field memory control signals supplied from pins M[7:4]. this time, M[0] requires "H".
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PEDL7662-02 Semiconductor Epilogue Block Epilogue Block outputs signal from Chrominance block signal from Luminance block format based signal obtained from control register setting. This block select following modes. Output mode selection (related register MRA[7:6]) 1-1) ITU-RBT.656 (SAV, EAV, blank processing) 1-2) 8-bit (YCbCr) output pixel clock) synchronization with HSYNC_L, VSYNC_L 1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock) synchronization with HSYNC_L, VSYNC_L 1-4) 24-bit bits each) synchronization with HSYNC_L, VSYNC_L Enable Blue Back display when synchronization fails (related register MRB[4]) input when signal output when synchronization fails, vertical synchronizing signal (VSYNC_L) output. Selection YCbCr signal output format (related register MRC[5]) YCbCr YCbCr 4:1:1 chrominance signal component) outputs data output format described later. Output enable selection (related register OMR[2]) High-impedance Output enable* This setting valid during sleep mode only. data output pins sync signal output pins become high impedance. Multiplex signal (VBI data) detection level adjustment (related register OMR[5:3]) levels detect multiplexed signals sent during vertical blanking period configured variable. binary values after input signals A-to-D converted employed levels detect multiplexed signals, levels eight steps basis value obtained from reducing SYNC level Various mode detection (related register OMR[1:0]) NTSC/PAL detection Multiplex signal detection HSYNC synchronization detection Internal FIFO overflow detection Output signal phase control (related registers OPCY[1:0], OPCC[1:0]) phases each adjusted range pixels. Control Block This serial interface block based standard Phillips Corporation. registers subaddress Hex14 write-only registers register subaddress Hex20 read-only register. license chip systems granted basis patent Phillips Corporation purchasing chip. Test Control Block This block used test chip. Normally this block used. MSM7662
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PEDL7662-02 Semiconductor Input Signal Level figure below shows recommended range input signal, received 8-bit straight binary format.
reserved
MSM7662
Iuminance
chrominance
NTSC:60 (PAL:63) sync
input black level input sync-tip level CVBS[7:0] input range
above input conditions ideal. Because analog signals normally input different levels, exact settings described above difficult achieve. While maintaining ratio White Peak (100%)/SYNC 100IRE/40IRE (NTSC), input signal within converter's voltage range/the digital output will output digital operation with pedestal position black level (16) white peak position (100%) peak level (235) even peak level does reach (200
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PEDL7662-02 Semiconductor Output format ITU-RBT.656 output, 8-bit (YCbCr) output, 16-bit (8-bit Y/8-bit CbCr) output have following formats. YCbCr 4:2:2 format 4:1:1 format shown below. output format changed register settings.
Output (MSB) (LSB) (MSB) (LSB) point point Pixel Byte Sequence Output (MSB) (LSB) (MSB) (LSB) point point YCbCr 4:1:1 format Pixel Byte Sequence
MSM7662
YCbCr 4:2:2 format
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PEDL7662-02 Semiconductor MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal vertical synchronizing signal timing follows. default output shown below, internal processing synchronizing signal performed before
CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID
Vertical Synchronizing Signal
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PEDL7662-02 Semiconductor MSM7662
CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID
Vertical Synchronizing Signal
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PEDL7662-02 Semiconductor Converter Support Signal waveform signal, shown below, provides clamp timing converter when clamp (digital clamp) selected. start edges clamp pulse have variable range from sync pedestal position. (HSY internal signal.) MSM7662
CVBS BURST
COLOR BURST
sync
Pedestal
Converter Support Signal Output Timing ITU-RBT.656 output
clock periods normal (1/27 MHz) start active video timing reference code active video timing reference code Digital line {1716T (NTSC, 525), 1728T (PAL, 625)} Multiplexed video data Digital active line Video data block (1440T)
Digital line blanking 276T (NTSC, 525) 288T (PAL, 625)
ITU-RBT.656 Output (Data line which video data presents) During blanking interval, data output with value. Note: Digital line 1716T (NTSC, 525) 1728T (PAL, 625) maintained next line. Digital active line 1440T line immediately after VVALID falls 10th 11th line after VSYNC_L rises will fluctuate pixel compensation. Especially when non-standard signal input, line immediately after VVALID falls will fluctuate largely instability input signal. phenomena such increase number lines standard signal decrease number lines nonstandard signal, possible guarantee correct functionality. 27/62
PEDL7662-02 Semiconductor Contents Both consist words. Their configuration shown below.
Word First Second Third Fourth (MSB) (LSB) during field during field elsewhere during field blanking Protection
MSM7662
word relationship between Protection bits word shown below.
Function (MSB) Fixed
Usually, during blanking, however when data detected desired output, MRC[3] SAV, V-status Mode Register (MRC) "1".
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PEDL7662-02 Semiconductor Output Data Format MSM7662
CLKX2 HVALID Y[7:0]
8-bit (YCbCr: clock) Output
CLKX2 CLKO HVALID Y[7:0] C(7:0) Y(n-2) Y(n-1)
Cb(n-2) Cr(n-2)
16-bit 8-bit, CbCr: 8-bit) Output
CLKX2 CLKO HVALID R[7:0] G[7:0] B[7:0] R(n-2) G(n-2) B(n-2) R(n-1) G(n-1) B(n-1)
24-bit 8-bit, 8-bit, 8-bit) Output Note: When single-speed clock (13.5 MHz, etc.) input 16-bit 24-bit (RGB) output mode, waveform CLKX2 changes single speed waveform, format after that changed. 29/62
PEDL7662-02 Semiconductor MSM7662
Timing when using external field memory Field memory timing FM-2 mode, using control signals from decoder Field memory: MSM51V8222, units used Four memory control signals supplied from decoder, M[4]: RSTW, M[5]: RSTR, M[6]: WE:, M[7]: NTSC Signal (13.5 MHz)
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
NTSC: Field
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
NTSC: EVEN Field 30/62
PEDL7662-02 Semiconductor Signal (13.5 MHz)
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
MSM7662
PAL: Field
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
PAL: EVEN Field
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PEDL7662-02 Semiconductor Horizontal Synchronizing Signal horizontal synchronizing signal timing shown below.
Front-porch Y[7:0] Hsync back-porch
MSM7662
HVALID HSYNC_L pixels
Horizontal Timing Relation between Video Mode Pixel Number (default settings when standard signal input)
Video Mode NTSC Pixel Type ITURBT.601 Square pixel 4fsc ITURBT.601 Square pixel Pixel Rate (MHz) 13.5 12.272727 14.31818 13.5 14.75 Total Pixels Active Pixels FrontPorch Hsync BackPorch HBLK Total
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PEDL7662-02 Semiconductor Synchronizing Signal Timing (default timing when standard signal input)
HVALID 1/13.5
MSM7662
VVALID
pixels HSYNC_L pixels HVALID pixels
HSYNC_L
VSYNC_L about 10.4 (ODD) (EVEN)
about 21.6
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PEDL7662-02 Semiconductor Data Detection (when Composite signal input): STATUS1 Timing data detection results output from STATUS1 pin.
Detection level OMR[5:3] video
MSM7662
STATUS1 HVALID
HSYNC_L
Y[7:0]
Data Detection (when S-Video signal input): STATUS1 Timing data detection results output from STATUS1 pin.
Detection level OMR[5:3] video
STATUS1 HVALID
HSYNC_L
Y[7:0]
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PEDL7662-02 Semiconductor MSM7662
FORMAT
I2C-bus interface input format shown below.
Write Mode
Slave Addres Subaddress Data Data
Read Mode
Slave Addres Symbol Slave Address Subaddress Data Start condition Slave address 1000001X, write signal ["0"] read signal ["1"] Slave address M[2] (pin 89). Acknowledge. Generated slave Subaddress byte Data write address designated subaddress. Stop condition Subaddress Slave Addres Description Data
mentioned above, write operation executed from subaddress subaddress continuously. When write operation executed subaddresses discontinuously, Acknowledge Stop condition formats input repeatedly after Data Data read subaddress 0x20 only. following matters occurs, decoder will return (Acknowledge). slave address does match. non-existent subaddress specified. write attribute register does match (read ["1"]/write ["0"] control bit). input timing shown below.
Start Condition
Slave Address
Address
Data Stop Condition
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PEDL7662-02 Semiconductor MSM7662
OPERATING MODE SETTING
There types video mode settings. External mode: direct setting from dedicated pins Register setting mode: specification internal register settings These modes switched mode register MRA[0]. reset state (default) external mode. following registers external mode. MRA[7:6] Output mode ITU-RBT.656 (SAV, EAV, blank processing) *01: (YCbCr) HSYNC_L VSYNC_L used synchronization ITU-RBT.601 CbCr) *000: NTSC ITU-RBT.601 13.5 (27.0 MHz) 001: NTSC Square Pixel 12.272727 (24.545454 MHz) 010: NTSC 4fsc 14.31818 (28.63636 MHz) 100: ITU-RBT.601 13.5 (27.0 MHz) 101: Square Pixel 14.75 (29.5 MHz)
MRA[3:1]
Sampling mode
Note:
010: NTSC 4fsc cannot externally.
Setting Example NTSC, (ITU-RBT.601), Composite input, 8-bit (YCbCr) Output
name MODE[3] MODE[2] MODE[1] MODE[0] CLKSEL PLLSEL INS[2:0] GAINS[2:0] TEST[2:0] SCAN M[2] M[1] M[0] SLEEP high
Condition
Notes ITU-RBT.656 8-bit (YCbCr) 16-bit CbCr) NTSC ITU-RBT.601 Square Pixel twice pixel frequency pixel frequency
Normally level
1000001, high 1000011 Normally level normal operation sleep operation
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PEDL7662-02 Semiconductor MSM7662
INTERNAL REGISTERS
Register List
Register Function Mode Register (MRA) Mode Register (MRB) Mode Register (MRC) Horizontal Sync Trimmer (HSYT) Sync Threshold Level Adjust (STHR) Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALT) Vertical Valid Trimmer (VVALT) Luminance Control (LUMC) Sync Separation Level (SSEPL) Chrominance Control (CHRC) Loop Filter Control (ACCLF) Control (HUE) Write Sub/Read address Write Write Write Write Write Write Write Write Write Write Write Write Write Data byte MRA7 MRA6 MRA5 MRA4 MRA3 MRA2 MRA1 MRA0 MRB7 MRB6 MRB5 MRB4 MRB3 MRB2 MRB1 MRB0 MRC7 MRC6 MRC5 MRC4 MRC3 MRC2 MRC1 MRC0 HSYT7 HSYT6 HSYT5 HSYT4 HSYT3 HSYT2 HSYT1 HSYT0 STHR7 STHR6 STHR5 STHR4 STHR3 STHR2 STHR1 STHR0 HSDL7 HSDL6 HSDL5 HSDL4 HSDL3 HSDL2 HSDL1 HSDL0 HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0 VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC7 CHRC6 CHRC5 CHRC4 CHRC3 CHRC2 CHRC1 CHRC0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0 HUE7 HUE6 HUE5 HUE4 HUE3 HUE2 HUE1 HUE0 OPCY7 OPCY6 OPCY5 OPCY4 OPCY3 OPCY2 OPCY1 OPCY0 OPCC7 OPCC6 OPCC5 OPCC4 OPCC3 OPCC2 OPCC1 OPCC0 OMR7 OMR6 OMR5 OMR4 OMR3 OMR2 OMR1 OMR0 ADC17 ADC16 ADC15 ADC14 ADC13 ADC12 ADC11 ADC10 ADC27 ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20 ADC37 ADC36 ADC35 ADC34 ADC33 ADC32 ADC31 ADC30 ZLD7 ZLD6 ZLD5 ZLD4 ZLD3 ZLD2 ZLD1 ZLD0 STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0
AGC/Pedestal Loop Filter Control (AGCLF) Write
Output Phase Control Data (OPCY) Write Output Phase Control Data (OPCC) Write Optional Mode Register (OMR) Register (ADC1) Register (ADC2) Register (ADC3) Level Detect Register (ZLD) Stataus Register (STATUS) Write Write Write Write Write Read
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PEDL7662-02 Semiconductor MSM7662
Register Parameters
Registers controlled from I2C-bus listed below. asterisk indicates that register setting value default value.
Mode Register (MRA)
Register Name Default Recommended Value
Write only
<address: $00>
MRA[7] MRA[6] MRA[5] MRA[4] MRA[3] MRA[2] MRA[1] MRA[0]
ITU-RBT.656 *01: bits bits bits Video output mode selected. MRA[5] Chroma format Offset binary complement MRA[4] Undefined S-video input MRA[3:1] Input Sampling mode *000: NTSC ITU-RBT.601 13.5 001: NTSC Square Pixel 12.272727 010: NTSC 4fsc 14.31818 100: ITU-RBT.601 13.5 101: Square Pixel 14.75 110, 111: Undefined Sampling rate selected MRA[0] MODE[3:0] select External mode Register mode Note: Only setting MODE[3:0] valid this external mode.
MRA[7:6]
Video output mode
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PEDL7662-02 Semiconductor Mode Register (MRB)
Register Name Default Recommended Value
MSM7662 Write only <address: $01>
MRB[7] MRB[6] MRB[5] MRB[4] MRB[3] MRB[2] MRB[1] MRB[0]
*00: FIFO-1 (use internal memory) FIFO-2 (use internal memory) FM-1 (use external memory, external control) FM-2 (use external memory, control signals supplied from M[7:4]) Note: FIFO-1 mode, number pixels output standard setting value. FIFO-2 mode, number pixels fixed accordance with input period output. FM-1 FM-2 modes, decoded result output without changes according SYNC signal. field memory required externally output fixed number pixels those modes. FM-2 mode, field memory control signal output from M[7:4]. MRB[5] Color killer mode Auto color killer (Chrominance signal level color burst level below specified value.) Forced color killer (Chrominance signal level forced "0".) MRB[4] Blue Back (Video signal demodulated output regardless synchronization detection.) AUTO (Blue Back output when synchronization detected.) Note: When Blue Back output selected, level input during signal output, vertical synchronizing signal (VSYNC_L) output. MRB[3:2] Clamp mode *00: Analog clamp Analog, Digital hybrid clamp Digital clamp (HSY clamp) Undefined Clamp mode selected. MRB[1:0] separation mode *00: Adaptive comb filter (Correlation lines monitored operating mode selected.) Non-adaptive comb filter (Operating mode always fixed.) trap filter. (Comb filter used.) Undefined Note: Adaptive comb filter 2/3-line comb filter NTSC Comb filter/trap filter Non-adaptive comb filter 3-line comb filter NTSC 2-line cosine comb filter
MRB[7:6]
Synchronization mode
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PEDL7662-02 Semiconductor Mode Register (MRC)
Register Name Default Recommended Value
MSM7662 Write only <address: $02>
MRC[7] MRC[6] MRC[5] MRC[4] MRC[3] MRC[2] MRC[1] MRC[0]
Auto Note: This register decides automatically when sampling frequency input signals ITU-RBT.601. MRC[6] pixel alignment pixel position compensating circuit. pixel position compensating circuit. MRC[5] Pixel sampling rate (4:2:2) (4:1:1) MRC[4] Data-pass control DECIMATOR sampling. DECIMATER. Note: This register valid when clock MHz) input. MRC[3] SAV, V-status During blanking, During blanking, while data detected, MRC[2] output level MRC[1:0] Undefined Horizontal Sync Trimmer (HSYT)
Register Name Default Recommended Value
MRC[7]
NTSC/PAL auto select
Write only
<address: $03>
HSYT[7] HSYT[6] HSYT[5] HSYT[4] HSYT[3] HSYT[2] HSYT[1] HSYT[0]
HSYT[7:4] start trimmer pixels) (*$0): (-32 pixels) HSYT[3:0] stop trimmer pixels) (*$0): (-32 pixels) Note: HSYT signal provides clamp timing converter during digital clamp hybrid clamp mode. Because this signal move pedestal position, pedestal clamp used. However, this signal observed from outside. Sync. Threshold level adjust (STHR)
Register Name Default Recommended Value
Write only
<address: $04>
STHR[7] STHR[6] STHR[5] STHR[4] STHR[3] STHR[2] STHR[1] STHR[0]
STHR[7:0] Sync. depth (*$1E): Note: STHR signal changes HSYNC_L detection level. numerical unit described here determined based 80IRE obtained from doubling pedestal value standard signal, 40IRE. example, default 0x1E digital value, which reduced 15IRE.
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PEDL7662-02 Semiconductor MSM7662
Horizontal Sync Delay (HSDL)
Register Name Default Recommended Value
Write only
<address: $05>
HSDL[7] HSDL[6] HSDL[5] HSDL[4] HSDL[3] HSDL[2] HSDL[1] HSDL[0]
HSDL[7:0]
Note:
HSYNC_L delay trimmer pixel) (*$00): -128 +127 (-128 +127 pixels) HSYNC_L sync signal output position adjusted. <address: $06>
HVALT HVALT HVALT HVALT HVALT
Horizontal Valid Trimmer (HVALT) Write only
Register Name Default Recommended Value HVALT HVALT HVALT
HVALT[7:4] HVALID start trimmer pixels) (*$0): (-16 pixels) HVALT[3:0] HVALID stop trimmer pixels) (*$0): (-16 pixels) Note: HVALID start position position changed.
Vertical Valid Trimmer (VVALT)
Register Name Default Recommended Value VVALT
Write only
VVALT VVALT
<address: $07>
VVALT VVALT VVALT VVALT VVALT
VVALT[7:4] VVALID start trimmer line) (*$0): VVALT[3:0] VVALID stop trimmer line) (*$0): Note: VVALID start position position changed.
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PEDL7662-02 Semiconductor MSM7662
Luminance Control (LUMC)
Register Name Default Recommended Value
Write only
<address: $08>
LUMC[7] LUMC[6] LUMC[5] LUMC[4] LUMC[3] LUMC[2] LUMC[1] LUMC[0]
Note: Control range while limiter LUMC[6] prefilter prefilter. prefilter. LUMC[5:4] Aperture bandpass select *00: range0 (middle) range1 range2 range3 (high) LUMC[3:2] Coring range select *00: coring ±4LSB ±5LSB ±7LSB LUMC[1:0] Aperture filter weighting factor *00: 0.00 0.25 0.75 1.50 Note: These registers used contour compensation.
LUMC[7]
Output level limiter
AGC/Pedestal Loop filter control (AGCLF) Write only
Register Name Default Recommended Value
<address: $09>
AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF
AGCLF[7:6] loop filter time constant slow *01: medium fast mode Note: convergence time determined. These registers converge about times faster slow-medium-fast steps. mode, amplification determined reference level. AGCLF[5:0] reference level (*$00):
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PEDL7662-02 Semiconductor MSM7662
Sync separation level (SSEPL) Write only
Register Name Default Recommended Value SSEPL SSEPL SSEPL
<address: $0A>
SSEPL SSEPL SSEPL SSEPL SSEPL
pedestal clamp. pedestal clamp (AGC stops operating). SSEPL[6:0] Sync. separation level (*$00): Note: default setting outputs pedestal position black level. Chrominance Control (CHRC) Write only
Register Name Default Recommended Value
SSEPL[7]
Pedestal Clamp on/off
<address: $0B>
CHRC[7] CHRC[6] CHRC[5] CHRC[4] CHRC[3] CHRC[2] CHRC[1] CHRC[0]
Note: Control range while limiter CHRC[2] Chroma bandpass filter CHRC[1:0] Color kill threshold factor 0.500 color burst level *01: 0.250 color burst level 0.125 color burst level Color killer Note: color killer decision level selected based upon color burst ratio. Loop filter control (ACCLF) Write only
Register Name Default Recommended Value
CHRC[7:4] CHRC[3]
Undefined C-Output level limiter
<address: $0C>
ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF
ACCLF[7] Undefined ACCLF[6:5] loop filter time constant slow *01: medium fast mode Note: convergence time determined. These registers converge about times faster slow-medium-fast steps. mode, amplification determined reference level. ACCLF[4:0] reference level (*$00): 43/62
PEDL7662-02 Semiconductor control (HUE)
Register Name Default Recommended Value
MSM7662 Write only <address: $0D>
HUE[7] HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0]
HUE[7:0] control (*$00): -180 +178.6 degrees Note: phase controlled. changes about degrees bit.
Output phase control data (OPCY) Write only
Register Name Default Recommended Value
<address: $0E>
OPCY[7] OPCY[6] OPCY[5] OPCY[4] OPCY[3] OPCY[2] OPCY[1] OPCY[0]
OPCY[7:2] OPCY[1:0]
Note:
Undefined Output phase control data *00: normal forward clock backward clock backward clock output phase data controlled.
Output phase control data (OPCC) Write only
Register Name Default Recommended Value
<address: $0F>
OPCC[7] OPCC[6] OPCC[5] OPCC[4] OPCC[3] OPCC[2] OPCC[1] OPCC[0]
OPCC[7:2] OPCC[1:0]
Note:
Undefined Output phase control data *00: normal forward clock backward clock backward clock output phase data controlled.
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PEDL7662-02 Semiconductor Optional Mode Register (OMR) Write only
Register Name Default Recommended Value
MSM7662
<address: $10>
OMR[7] OMR[6] OMR[5] OMR[4] OMR[3] OMR[2] OMR[1] OMR[0]
HSYNC output timing select HSYNC output signal detected near sync threshold sync tip. HSYNC output signal detected sync threshold setting position. Note: When HSYNC output signal detected sync threshold setting position, hardly affected noise. OMR[6] VSYNC output timing select VSYNC_L synchronized HSYNC_L then output VSYNC_L output when VSYNC input signal detected. Note: When non-standard signal decoded, output stabilized after VSYNC_L input signal detected (setting OMR[5:3] Multiplex signal detection level (VBID etc.) 000: 001: *010: 011: 100: 101: 110: 111: Note: levels detect multiplexed signals sent during vertical blanking period set. result output from STATUS[1] STATUS[4] register. OMR[2] Hi-Z output SLEEP mode Active Hi-Z Note: This register selects either normal Hi-Z output status SLEEP mode. NTSC/PAL identification HLOCK sync detection OMR[0] Status3 output mode TV/VCR identification CSYNC Note: OMR[1:0] correspond STATUS[2:3] output output pins. OMR[1] Status2 output mode
OMR[7]
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PEDL7662-02 Semiconductor register (ADC1)
Register Name Default Recommended Value
MSM7662 Write only <address: $11>
ADC1[7] ADC1[6] ADC1[5] ADC1[4] ADC1[3] ADC1[2] ADC1[1] ADC1[0]
ADC1[7] ADC1[6] ADC1[5:4]
Video select Undefined Clamp current select
ADC1[3] ADC1[2:0]
Undefined input select
*00: 0.75 0.25 *000: ADI-VIN1 (composite-1) 001: ADI-VIN2 (composite-2) 010: ADI-VIN3 (composite-3) 011: ADI-VIN4 (composite-4) 100: ADI-VIN5 (composite-5) 101: ADI-VIN1 (Y-1), AD2-VIN5 (C-1) 110: ADI-VIN2 (Y-1), AD2-VIN6 (C-1) 111: Prohibited setting (ADC enters sleep state) <address: $12>
register (ADC2)
Register Name Default Recommended Value
Write only
ADC2[7] ADC2[6] ADC2[5] ADC2[4] ADC2[3] ADC2[2] ADC2[1] ADC2[0]
ADC2[7]
gain control mode select manual auto gain manual select 000: 1.00 *001: 1.35 010: 1.75 011: 2.30 100: 3.00 101: 3.80 110: 5.00 111: Undefined initialize condition gain select initialize initialize Undefined gain control stage select change change *10: change loop Undefined 46/62
ADC2[6:4]
ADC2[3]
ADC[2] ADC2[1:0]
PEDL7662-02 Semiconductor register (ADC3)
Register Name Default Recommended Value
MSM7662 Write only <address: $13>
ADC3[7] ADC3[6] ADC3[5] ADC3[4] ADC3[3] ADC3[2] ADC3[1] ADC3[0]
Undefined gain control margin level select 000: 001: *010: 011: 100: ADC3[3] Undefined ADC3[2:0] gain control line select 000: line 001: lines *010: lines 011: lines 100: lines Note: These registers determine analog gain control decision level. stability obtained from higher values.
ADC3[7] ADC3[6:4]
level detect register (ZLD)
Register Name Default Recommended Value ZLD[7]
Write only
ZLD[6] ZLD[5]
<address: $14>
ZLD[4] ZLD[3] ZLD[2] ZLD[1] ZLD[0]
ZLD[7:3] ZLD[2:0]
Note:
Undefined level detect width pixel) 000: Undefined 001: pixels *010: pixels 011: pixels 100: pixels 101: pixels 110: pixels 111: pixels These registers decide continuance sync level result reflected gain. stability obtained from higher values.
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PEDL7662-02 Semiconductor Status register (STATUS)
Register Name Default Recommended Value
MSM7662 Read only <address: $20>
STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS
STATUS[7:5] STATUS[4] STATUS[3] STATUS[2] STATUS[1] STATUS[0]
Undefined interval multiplex signal detection Non-detection, Detection HLOCK sync detection Non-detection, Detection NTSC/PAL identification NTSC, Fifo1/Fifo2 identification Mode Register (bit Fifo1, Fifo2 FTFO overflow detection Non-detection, Detection
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PEDL7662-02 Semiconductor Relationship between Register Setting Value Adjusted Value Horizontal Sync Trimmer Position adjustment sync clamp timing signal HSYT [7:4]
Register Setting Value (0x)
MSM7662
:Adjusting starting position
Adjusted Value (Pixel)
HSYT [3:0]
Register Setting Value (0x)
:Adjusting position
Adjusted Value (Pixel)
Horizontal Sync Delay Adjustment starting position horizontal sync signal HSDL [7:0] Unit: [pixel]
Register Setting Value (0x)
MSB[7 +112 +113 +114 +115
-128 -112 -127 -111 -126 -110 -125 -109 -124 -108 -123 -107 -122 -106 -121 -105 -120 -104 -119 -103 -118 -102 -117 -101 -116 -100 -115 -114 -113
+100 +116 +101 +117 +102 +118 +103 +119 +104 +120 +105 +121 +106 +122 +107 +123 +108 +124 +109 +125 +110 +126 +111 +127
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PEDL7662-02 Semiconductor Horizontal Valid Trimmer Position adjustment horizontal valid pixel timing signal HVALT [7:4]
Register Setting Value (0x)
MSM7662
:Adjusting starting position
Adjusted Value (Pixel)
HVALT [3:0]
Register Setting Value (0x)
:Adjusting position
Adjusted Value (Pixel)
Vertical Valid Trimmer Position adjustment vertical valid line timing signal VVALT [7:4]
Register Setting Value (0x)
:Adjusting starting position
Adjusted Value (Line)
VVALT [3:0]
Register Setting Value (0x)
:Adjusting position
Adjusted Value (Line)
Loop Filter Control AGCLF [5:0] :Adjusting sync level
Unit: [IRE], Default:
Register Setting Value (0x)
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PEDL7662-02 Semiconductor Sync Separation Level SSEPL [6:0] :Adjusting blanking level MSM7662
Unit: [IRE], Default:
Register Setting Value (0x)
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PEDL7662-02 Semiconductor Loop Filter Control ACCLF [4:0] :Adjusting color burst level MSM7662
Unit: [IRE], Default:
Register Setting Value (0x)
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PEDL7662-02 Semiconductor Control Adjustment color subcarrier phase [7:0] Unit: [degree]
Register Setting Value (0x)
MSM7662
-180.0 -157.5 -135.0 -112.5 -90.0 -67.5 -45.0 -22.5 +0.0 +22.5 +45.0 +67.5 +90.0 +112.5 +135.0 +157.5
-178.6 -156.1 -133.6 -111.1 -88.6 -66.1 -43.6 -21.1 +1.4 +23.9 +46.4 +68.9 +91.4 +113.9 +136.4 +158.9 -177.2 -154.7 -132.2 -109.7 -87.2 -64.7 -42.2 -19.7 +2.8 +25.3 +47.8 +70.3 +92.8 +115.3 +137.8 +160.3 -175.8 -153.3 -130.8 -108.3 -85.8 -63.3 -40.8 -18.3 +4.2 +26.7 +49.2 +71.7 +94.2 +116.7 +139.2 +161.7 -174.4 -151.9 -129.4 -106.9 -84.4 -61.9 -39.4 -16.9 +5.6 +28.1 +50.6 +73.1 +95.6 +118.1 +140.6 +163.1 -173.0 -150.5 -128.0 -105.5 -83.0 -60.5 -38.0 -15.5 +7.0 +29.5 +52.0 +74.5 +97.0 +119.5 +142.0 +164.5 -171.6 -149.1 -126.6 -104.1 -81.6 -59.1 -36.6 -14.1 +8.4 +30.9 +53.4 +75.9 +98.4 +120.9 +143.4 +165.9 -170.2 -147.7 -125.2 -102.7 -80.2 -57.7 -35.2 -12.7 +9.8 +32.3 +54.8 +77.3 +99.8 +122.3 +144.8 +167.3 -168.8 -146.3 -123.8 -101.3 -78.8 -56.3 -33.8 -11.3 +11.3 +33.8 +56.3 +78.8 +101.3 +123.8 +146.3 +168.8 -167.3 -144.8 -122.3 -99.8 -77.3 -54.8 -32.3 -9.8 +12.7 +35.2 +57.7 +80.2 +102.7 +125.2 +147.7 +170.2
-165.9 -143.4 -120.9 -98.4 -75.9 -53.4 -30.9 -8.4 +14.1 +36.6 +59.1 +81.6 +104.1 +126.6 +149.1 +171.6 -164.5 -142.0 -119.5 -97.0 -74.5 -52.0 -29.5 -7.0 +15.5 +38.0 +60.5 +83.0 +105.5 +128.0 +150.5 +173.0 -163.1 -140.6 -118.1 -95.6 -73.1 -50.6 -28.1 -5.6 +16.9 +39.4 +61.9 +84.4 +106.9 +129.4 +151.9 +174.4 -161.7 -139.2 -116.7 -94.2 -71.7 -49.2 -26.7 -4.2 +18.3 +40.8 +63.3 +85.8 +108.3 +130.8 +153.3 +175.8
-160.3 -137.8 -115.3 -92.8 -70.3 -47.8 -25.3 -2.8 +19.7 +42.2 +64.7 +87.2 +109.7 +132.2 +154.7 +177.2 -158.9 -136.4 -113.9 -91.4 -68.9 -46.4 -23.9 -1.4 +21.1 +43.6 +66.1 +88.6 +111.1 +133.6 +156.1 +178.6
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PEDL7662-02 Semiconductor Sync. Threshold Level Adjust Adjustment detection threshold horizontal sync signal SHTR [7:0] Unit: [IRE]/2
Register Setting Value (0x)
MSM7662
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PEDL7662-02 Semiconductor MSM7662
Filter Characteristics
Band Pass Filter (NTSC ITU-RBT.601)
Level [dB]
-100 Frequency [MHz]
Band Pass Filter (PAL ITU-RBT.601)
Level [dB]
-100 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Trap Filter (NTSC ITU-RBT.601)
Level [dB]
-100 Frequency [MHz]
Trap Filter (PAL ITU-RBT.601)
Level [dB]
-100 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Filter
Level [dB]
-100 Frequency [MHz]
Sharp Filter
Level [dB]
-100 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Decimation Filter
Level [dB]
-100 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
BASIC APPLICATION CIRCUIT EXAMPLES
Application Circuit FIFO-1 FIFO-2 Modes
Video (Composite input) Controller 1000 1000 1000
RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1
DAVDD
DVDD Y(7:0) C(7:0) B(7:0) Video
Video input)
VRB1
MSM7662
VIN(5:6) VRT2 AMPOUT2 ADIN2 CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
HVALID VVALID HSYNC_L VSYNC_L CLKX2O CLKXO CLKX2
AMPOUT
ADIN
Connect M7662 decoder video device according output interface (ITURBT.656, 8-bit [YCbCr], 16-bit [YCbCr], RGB). Video input four composite inputs S-Video inputs. Connect unused video input pins AGND. composite signal input, input side (video amp, converter, etc.) will operation state. input limited composite signal, connect (5:6), VRT2, VRB2, AMPOUT2, ADIN2, CLPOUT2 pins AGND. Externally attached components such capacitors removed. MODE[3:0] pins prescribed setting. Supply power analog, A/D, digital circuits circuit board should separated power source wherever possible. Power lines analog circuits must wide impedance.
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PEDL7662-02 Semiconductor Application Circuit FM-1 FM-2 Modes
Video (Composite input) Video input)75 Controller 1000 1000 1000 Memory control signal
MSM7662
RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1 VRB1
DAVDD
DVDD
M[7:4] Y(7:0) C(7:0) B(7:0)
Field memory Field memory Video
MSM7662
VIN(5:6) VRT2 AMPOUT2 ADIN2 CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
CLKXO HVALID VVALID HSYNC_L VSYNC_L CLKX2O CLKX2
AMPOUT
ADIN
Select either 16-bit [YCbCr] output output interface. Number field memories utilized 16-bit [YCbCr]: field memories. RGB: field memories. Video input four composite inputs S-Video inputs. Connect unused video input pins AGND. composite signal input, input side (video amp, converter, etc.) will operation state. input limited composite signal, connect (5:6), VRT2, VRB2, AMPOUT2, ADIN2, CLPOUT2 pins AGND. Externally attached components such capacitors removed. MODE[3:0] pins prescribed setting. FM-1 mode setting, externally generate supply control signals field memory. FM-2 mode setting, memory control signals from M[7:4] supplied field memory. FM-2 mode setting, output timing HSYNC_L, VSYNC_L, ODD, VVALID, HVALID becomes memory read timing. Data output from memory aligned with various sync signal timings. (See page page Supply power analog, A/D, digital circuits circuit board should separated power source wherever possible. Power lines analog circuits must wide impedance. 60/62
PEDL7662-02 Semiconductor MSM7662
PACKAGE DIMENSIONS
(Unit
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 0.55 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, TQFP, LQFP, SOJ, (PLCC), SHP, surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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PEDL7662-02 Semiconductor MSM7662
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan
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PEDL7662-02 This version: Oct. 1999 MSM7662 Previous version Oct. 1998

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