Bluetooth Baseband Controller FEDL70512-04 Issue Date: Sep.

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Bluetooth Baseband Controller FEDL70512-04 Issue Date: Sep.

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Semiconductor ML70512
Bluetooth Baseband Controller
FEDL70512-04
Issue Date: Sep. 2003
GENERAL DESCRIPTION
ML70512 CMOS digital band Bluetoothsystems. This incorporates ARM7TDMI core, features highly expandable architecture, supports interfaces variety applications. Since ML70512 Oki's Bluetooth protocol stack software installed, when used conjunction with Bluetooth transceiver data/voice communications possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
Conforms Bluetooth Specification (Ver1.1) Designed connection with RF-LSI interface, such RF-LSI interface (ML7050, ML70561), SKYWORKS RF-LSI interface (CX72303), BROADCOM RF-LSI interface (BCM2002X) that functions Bluetooth RF-LSI interface high-speed, low-power ARM7TDMIis installed core PCM-CVSD transcoder that provides high quality voice using noise filter installed power consumption flexible power management modes according operating modes Bluetooth DETACH signal provides control change power-saving mode (STOP) return request normal mode. UART interface corresponding baud rates 921.6 kbps interface provides accesses EEPROM PCM-Codec Selactable MHz, MHz, system clock Selectable 32.768 clock Built-in programmed eliminates external ROM/FLASH packages available types: 83-pin WCSP ML70512HB 84-pin ML70512LA
ARM, ARM7TDMI Thumb registered trademarks Ltd., BLUETOOTH trademark owned Bluetooth SIG, Inc. licensed Electric Industry. information contained herein change without notice owing product being under development.
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ML70512
SPECIFICATIONS
Process Package 0.16 CMOS (5-layer metal wire) 83-pin WCSP (Dimensions: 6.22 6.22 0.48 pitch: 0.50 84-pin (P-LFBGA84-0909-0.80) (Dimensions: pitch: 0.80 23.4 operation) 2.70 input-output, 1.65 1.95 internal circuits (for program) MHz, MHz, (system clock) 32.768 (LPO clock) RF-LSI interface (ML7050, ML70561) SKYWORKS RF-LSI interface (CX72303) BROADCOM RF-LSI interface (BCM2002X) UART interface 921.6 Kbps) General-purpose interface (Bits used interface depending software installed) interface (PCM Linear/A-law/µ-law selected) DETACH interface 16-bit auto reload timer (1ch) 18-bit auto reload timer (3ch) causes Crystal oscillator circuit MHz, MHz, MHz, 32.768 kHz) Internal
Supply current Operating voltage ranges Operating frequency Built-in size Built-in size Input clocks RF-LSI interface
Installed interfaces
Timers Interrupt controller Clock control circuit
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ML70512
PLACEMENT
ML70512HB: 83-pin WCSP (P-VFLGA83-6.22 6.22-0.50-W)
SCLKO
Core Core
SYNC
Core CIO5 PCMIN
CIO0 (SCL)
Core CIO1 (SDA)
CIO4
RFSEL2
CIO3
RFSEL0
Core
CIO2 RFSEL1 DETACH RESET SCLKN
SFRQ CIO6 SEL1
AGND0 SCLKP AVDD0 AGND0 Core
SOUT PLL_ PLL_
LVDD RSSI _CLK Core SFRQ SEL0
AVDD1 AGND1 AVDD0 AVDD1 AGND1 LOCK Core
PLL_ DATA
PLL_
PLL_PS
RSSI Core
PLL_LE
SCLK XC32KN XC32KP
VIEW
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ML70512
ML0512LA: 84-pin (P-TFBGA84-0909-0.80)
Core AVDD1 AGND1 AVDD0 AGND0 SCLKN RESET RFSEL0 RFSEL2 CIO4 CIO2
XC32KP AVDD1 AGND1 AGND0
SCLK XC32KN AVDD0 SFRQ SEL0 RSSI
Core SCLKP DETACH RFSEL1 CIO0 (SCL) CIO5
Core CIO1 (SDA) Core SYNC Core
Core
LOCK
PCMIN PCMCLK CIO6 SFRQ SEL1 Core SCLKO Core CIO3
PLL_LE PLL_PS PLL_ DATA
PLL_
RSSI_ PLL_
LVDD
PLL_
SOUT
VIEW
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DESCRIPTIONS
Name Direction [*0] Internal Pull Down, Schmitt Initial Value PLL_LE Placement Description ML70512HB ML70512LA ML7050: Transmit data output CX72303: Transmit data output BCM2002X: Transmit data output ML70561: Transmit data output ML7050: Receive data input CX72303: Receive data input BCM2002X: Receive data input ML70561: Receive data input ML7050: Serial write data CX72303: Serial write data BCM2002X: Transmit enable ML70561: Transmit enable (Active ML7050: Serial clock CX72303: Serial clock BCM2002X: Serial clock ML70561: Serial clock ML7050: Serial road enable Negate, Assert CX72303: Serial enable Assert, Negate BCM2002X: RF-LSI synthesizer Negate, Assert ML70561: RF-LSI synthesizer Negate, Assert ML7050: Receive field strength data input CX72303: Serial read data BCM2002X: Serial read data ML70561: Serial read data ML7050: Receive field strength data clock CX72303: RF-LSI receiving characteristic control BCM2002X: System clock request ML70561: System clock request ML7050: Local power control Assert, Negate CX72303: Power control Negate, Assert BCM2002X: Select serial transmit mode ML70561: Select serial transmit mode
PLL_DATA
PLL_CLK
RSSI
RSSI_CLK
PLL_POW
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Name
Direction [*0]
Internal Pull Down, Schmitt
Initial Value
Placement Description ML70512HB ML70512LA ML7050: Transmit enable Assert, Negate CX72303: Transmit enable Negate, Assert BCM2002X: Serial write data ML70561: Serial write data ML7050: Receive enable Assert, Negate CX72303: Receive enable Negate, Assert BCM2002X: Receive enable ML70561: Receive enable
TX_POW
RX_POW
[*0]
Input, Output, "I/O" Input/Output
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Name Direction [*0] Internal Pull Down, Schmitt Initial Value PLL_PS PLL_OFF Placement ML70512H Description ML70512LA ML7050: CX72303: Power reset Assert (reset) Negate BCM2002X: RF-LSI receiving characteristic control ML70561: SYNCWORD detection ML7050: CX72303: BCM2002X: 1MHz clock ML70561: Clock transmit data ML7050: loop control Open loop Closed loop CX72303: Diversity output BCM2002X: Power control ML70561: Power control
PLLLOCK
Configuration
Name SCLKP SCLKN XC32KP XC32KN SCLKSEL Direction Internal Pull Down, Schmitt Initial Value Placement Description ML70512HB ML70512LA System clock (12/13/16 MHz) pins (Power level: CMOS level) Subclock pins (for oscillator) System clock frequency select Select divided internal Select subclock System clock (SCLK) frequency select/ crystal frequency select pins
SFRQSEL [1:0] SCLK input frequency (RFSEL 101) Reserved crystal frequency (RFSEL 101) 19.68 19.2 19.8
SFRQSEL
*[1]
*[2]
RF-LSI select pins
RFSEL[2:0] Others RF-LSI ML7050 (OKI) CX72303 (SKYWORKS) ML70561 (OKI) BCM2002X (BROSDCOM) Reserved
RFSEL
*[3]
*[4]
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Configuration
Name RESET DETACH SCLKO Direction Internal Pull Down, Schmitt Schmitt Schmitt Initial Value Placement Description ML70512HB ML70512LA Hardware reset (Reset Sleep (Sleep System clock (12/13/16 MHz) output pins
[*1] [*2] [*3] [*4]
SFRQSEL0: SFRQSEL1: SFRQSEL0: SFRQSEL1: RFSEL0: RFSEL1: RFSEL2: RFSEL0: H10; RFSEL1: RFSEL2:
Name PCMOUT PCMIN PCMSYNC Direction Internal Pull Down, Schmitt Pull Pull down Pull down Initial Value Placement Description ML70512HB ML70512LA data output data input sync signal kHz), Initial setting: input (can switched internal register) clock kHz/128 kHz) Initial setting: input (can switched internal register)
PCMCLK
Note: sync signal kHz) must guaranteed accuracy PCMSYNC configured input.
UART
Name SOUT Direction Internal Pull Down, Schmitt Schmitt Initial Value Placement Description ML70512HB ML70512LA transmit serial data receive serial data transmit data ready transmit ready
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ML70512
Port
Name CIO0 (SCL) CIO1 (SDA) CIO2 CIO3 CIO4 CIO5 CIO6 Direction Internal Pull Down, Schmitt Initial Value Placement Description ML70512HB ML70512LA serial clock (output) serial data (input) General port (initial state: input) General port (initial state: output) General port (initial state: output) General port (initial state: input) General port (initial state: input)
Name Direction Internal Pull Down, Schmitt Initial Value Placement Description ML70512HB ML70512LA [*4] connection
[*4] Note: wire under pin.
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ML70512
Power,
Name CoreVDD LVDD AVDD0 AVDD1 AGND0 AGND1 Direction Internal Pull Down, Schmitt Initial Value Placement Description ML70512HB [*5] [*7] [*9] [*11] [*13] [*15] [*17] ML70512LA [*6] [*8] [*10] [*12] [*14] [*16] [*18] power supply 2.70 Power supply internal circuit 1.65 1.95 RF-I/O power suply (Same voltage RF-LSI) Digital block ground Analog block power supply 1.65 1.95 Analog block ground
[*5] [*6] [*7] [*8] [*9] [*10] [*11] [*12] [*13] [*14] [*15] [*16] [*17] [*18]
VDD: VDD: Core VDD: C10, E10, G10, Core VDD: J10, GND: A10, F10, H10, GND: A10, AVDD0: AVDD0: AVDD1: AVDD1: AGND0: AGND0: AGND1: AGND1:
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Semiconductor
BLOCK DIAGRAM
Timer System Control AMBA AMBA PCM/ CVSD GPIO BT-BB Core UART DETACH Timer2 (3ch) Arbiter Default Slave 72KB 384KB IRAMC IROMC ARM7 TDMI
Default Slave
Clock AMBA Processor
ML70512
RFLSI
CTL/
DETACH
GPIO
UART
Codec
FEDL70512-04
ML70512
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DESCRIPTION INTERNAL BLOCKS
CLKGEN Block Generates clock that supplied each block through SCLKP (12/13/16 MHz) STOP/HALT function CTL/WDT Block Control frequency division function internal main clock Control clock supplied each peripheral Control reset each peripheral STOP/HALT control Watchdog timer function (interrupt/reset)
Timer Block channels 18-bit timer counter Interrupt compare function shot, interval, free-run mode
Base band Core Block
Buffer Audio Codec Buffer Packet Composer
Security Buffer Buffer
Timing
FHCNT
Packet Decomposer
Controller power supply control (PLL, Local frequency division ratio setting Receive clock regeneration function Synchronization detection (synchronizing within permissable error limit SyncWord) Receive clock re-timing function Controller hopping Sequence control Frequency hopping selection function computation's initial value selection function
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Timing Generator Bluetooth clock generation Operation interrupts depend mode (slot, scan, sniff, hold, park) Sync detection timing generation (sync window setting timing generation Transmit/Receive timing generation Multi-master timing management function Packet Composer Access code generation (SyncWord generation, appending PR*TRAILER) Packet header generation (HEC generation, scrambling, encoding) Payload generation (CRC generation, encryption, scrambling, encoding) Packet synthesis Packet Decomposer Packet decomposition (separating packet header payload) Packet header processing (FEC decoding, descrambling, error detection, header information separation) Payload processing (FEC decoding, descrambling, encryption decoding, judgement, payload separation) Security Various generation functions (initialization, link key, encryption key) Certification function Encryption function
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UART Block Full-duplex buffering method status reporting function Built-in 64-byte transmit/receive FIFO Modem control based Programmable serial interface 8-bit characters Generation verification parity, even parity, parity 1.5, stop bits Programmable Baud Rate Generator (9600 921.6 kbps) Error servicing parity, overrun, framing errors
Configuration Data Frame during Reception
SAMPLE
data bits data bits
Start
Parity
Stop
Configuration Data Frame during Transmission
SOUT
Start data bits data bits Parity Stop
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PCM-CVSD Transcoder Block Application side I/O: Codec Application-side format: linear bits/sample, sampling frequency)/A-law/µ-law Bluetooth-side format: CVSD/A-law/µ-law combinations above conversions supported PCMSYNC/PCMCLK switched (initial setting: input) Timing Short Mode PCMCLK PCMSYNC Output Mode (For data bits/sample, lower bits bits invalid.)
bits bits PCMCLK(O)
64k/128kHz
PCMOUT
DATA
DATA
DATA
DATA
Data output rising edge CLK. PCMIN PCMSYNC(O) DATA DATA DATA DATA
Data shifted falling edge
125µs (8kHz)
Timing Short Mode PCMCLK PCMSYNC Input Mode. (For data bits/sample, lower bits bits invalid.)
bits bits PCMCLK(I)
64k/128kHz
PCMOUT
DATA
DATA
DATA
DATA
Data output rising edge CLK. PCMIN PCMSYNC(I) DATA DATA DATA DATA
Data shifted falling edge
125µs (8kHz)
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Timing Long Mode PCMCLK PCMSYNC Output mode (For data bits/sample, lower bits bits invalid.)
bits bits
PCMCLK(O)
64k/128kHz
PCMOUT
DATA
DATA
DATA
DATA
DATA
Data output rising edge PCMIN PCMSYNC(O) PCMCLK period 125µs (8kHz) DATA DATA DATA
Data shifted falling edge DATA DATA
Timing Long Mode PCMCLK PCMSYNC Input Mode. (For data bits/sample, lower bits bits invalid.)
bits bits
PCMCLK(I)
64k/128kHz
PCMOUT
DATA
DATA
DATA
DATA
DATA
Data output rising edge CLK. PCMIN DATA DATA DATA
Data shifted falling edge CLK. DATA DATA
PCMCLK period (Min.) 62.5 (Max.) 125µs (8kHz)
DETACH Interface Block Generation request change (from) stop mode detection rising (falling) edge DETACH signal Generation request restore from stop mode detection signal level change
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ABSOLUTE MAXIMUM RATINGS
Parameter power supply voltage Core power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol VDD/LVDD CoreVDD/AVDD Tstg Conditions Rating -0.3 +4.5 -0.3 +2.5 -0.3 +4.5 0.62 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter power supply voltage Core power supply voltage level input voltage level input voltage Operating temperature Symbol VDD/LVDD CoreVDD/AVDD Conditions Min. 1.65 Typ. Max. 1.95 Unit
ELECTRICAL CHARACTERISTICS
Characteristics
Parameter level output voltage level output voltage Input leakage current (VDD CoreVDD 1.65 1.95 +85°C) Symbol Conditions Min. Typ. Max. Unit 3.0VVdd3.6V 2.7VVdd<3.0V Pull-down Pull-up Pull-down During operation stopped -200 23.4
Output leakage current Power supply current (during operation) Power supply current (during stand-by)
Iddo Idds
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ML70512
Power Supply Current (IDDO) Characteristics Power Saving Mode
(VDD 3.6V, CoreVDD 1.65 1.95V, 85°C) Operating mode Conditions Min. Typ. Max. Unit STOP mode (DETACH "L") 0.05 Interval:1.28sec Page Scan operating mode Window:22.5msec Poll Interval operating Interval:40slot 12.1 Interval:2000slot Sniff operating mode Attempt:4frame Hold operating mode Interval:4000slot DH1/DM1 23.4 RX:DH3/DM3 20.5 operating mode TX:DH1/DM1 RX:DH5/DM5 19.6 TX:DH1/DM1
Characteristics System clock (SCLKP) SCLKP
Tmc0 Tmc1
Parameter Tmc0 Tmc1
(VDD 3.6V, CoreVDD 1.65 1.95V, 85°C) Description Unit Duty SCLKP duration Duty SCLKP duration
Sub-clock (XC32KP)
XC32KP
Tmp0 Tmp1
Parameter Tmp0 Tmp1
(VDD 3.6V, CoreVDD 1.65 1.95V, 85°C) Description Unit Duty XC32KP duration Duty XC32KP duration
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ML70512
Reset
Power supply stable period
Vdd/LVdd
CoreVdd/AVdd
TRESW RESET
Parameter TRESW
Reset pulse width
(VDD 3.6V, CoreVDD 1.65 1.95V, 85°C) Description Unit
Note Apply RESET µsec more after power supply been settled.
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ML70512
interface
PCMCLK(I) PCMIN
Tpc0 Tpc1 Tpc2
PCMOUT
Tpc2
PCMSYNC(I)
Tpc3 Tpc4 Tpc3 Tpc4
PCMCLK(O) PCMIN
Tpc5 Tpc6
PCMOUT
Tpc7
PCMSYNC(O)
Parameter Tpc0 Tpc1 Tpc2 Tpc3 Tpc4 Tpc5 Tpc6 Tpc7 Tpc8
(Vdd 3.6V, CoreVdd 1.65 1.95V, 85°C) Description Unit PCMIN setup time relative PCMCLK (input) falling edge PCMIN hold time relative PCMCLK (input) falling edge PCMOUT delay time relative PCMCLK (input) rising edge PCMSYNC (input) setup time relative PCMCLK (input) rising edge PCMSYNC (input) hold time relative PCMCLK (input) rising edge PCMIN setup time relative PCMCLK (output) falling edge PCMIN hold time relative PCMCLK (output) falling edge PCMOUT delay time relative PCMCLK (output) rising edge Delay time from PCMCLK (output) rising edge PCMSYNC (output)
Characteristic Measuring Points
0.8VDD 0.2VDD 0.8VDD 0.2VDD
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REFERENCE VOLTAGE SUPPLY CIRCUIT
ML70512
AVDD0 0.1µF AGND0 AVDD1 0.1µF AGND1
CoreVDD
47µF
0.1µF
0.1µF
CoreVDD
LVDD
47µF
0.1µF
0.1µF
47µF 0.1µF 0.1µF
Capacitors should locate close pins.
Feed lines should separated from pins.
Example ML70512 voltage supply circuit Insert appropriate bypass capacitors between lines. Note Precautions insert bypass capacitors traces lines wider than those other signal lines. Keep length traces between bypass capacitors line between bypass capacitors line short possible. Keep length traces between bypass capacitors line between bypass capacitors line equal possible. circuit subject change according specific board design. Please contact Electric Industry Co., Ltd. detailed information.
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ML70512
REFERENCE OSCILLATOR CIUCUIT
ML70512
XC32KP
XC32KN
SCLKP
X'tal
X'tal
SCLKN
Connect this oscillator circuit only when connecting RF-LSI ML7050.
Example oscillator circuit Note values should determined according specifications external crystal X'tal 32.768 kHz). values should determined according specifications external crystal X'tal (12, MHz). Note crystal oscillator circuit should connected pins SCLKP SCLKN only when RF-LSI (ML7050) connected. other cases, system clock should input from RF-LSI SCLKP. Note case MHz, MHz, system clock (SCLKP) input, make sure crystal frequency tolerance temperature, supply voltage, aging. case 32.768 sub-clock (XC32KP) input, make sure crystal frequency tolerance ±250 temperature, supply voltage, aging. Note Precautions build crystal oscillator circuit Keep length wire traces short possible. cross crystal oscillator circuit wires over other signal line wires. keep signal line wires through which high current flows close crystal oscillator circuit. Keep grounding point capacitors oscillator circuit potential equal GND. connect capacitors lines through which high current flows. output signals from oscillator circuit. circuit subject change according specific board design. Please contact Electric Industry Co., Ltd. detailed information. recommended determine final circuit values including capacitance circuit board designed user.
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APPLICATION NOTES
Clock Selection system clock frequency selected according external SFRQSEL. SFRQSEL SFRQSEL SFRQSEL clock input external SCLKP. clock input external SCLKP. clock input external SCLKP.
clock input external SCLKP regardless SFRQSEL when BCM2002X selected (RFSEL 101). clock supply source selected according external SCLKSEL. SCLKSEL clock that divided down from internal output that generated from external pins SCLKP. (Dividing ratios selectable range 1/16. Initial value MHz).) external pins XC32KP.
SCLKSEL
Note: clock supply source CLKCNTL register CTL/WDT block once powered frequency clock selectable from high speed MHz) speed MHz). This performed Vendor Specific Command. Setting Reset Apply level RESET more than after power voltage stabilized. When system clock oscillator circuit stable RESET level, internal reset released operation starts after internal reset held input clock MHz, input clock MHz, input clock MHz. Moreover, after power voltage stable, values SCLKSEL, SFRQSEL0-1, RFSEL0-2 should determined before RESET level. Setting UART Baud Rate possible UART baud rate using Vendor Specific Commands. Available baud rate settings: (Initial value 115.2 kbps.) Setting PCM-CVSD Transcoder possible PCM-CVSD transcoders using Vendor Specific Commands. command details, contact Electric Industry Co., Ltd.
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possible following parameters using VCCTL command: PCMSYNC/PCMCLK mode (initial setting: input) Mute reception (initial setting: OFF) Mute transmission (initial setting: OFF) Aircoding CVSD (initial setting)/µ-law/A-law Interface coding Linear (initial setting)/µ-law/A-law format (data width Linear sample) 8-bit (initial setting)/14-bit/16-bit Serial interface format Short frame (initial setting)/long frame Application interface mode Codec (initial setting)/APB XTAL Input Frequency BCM2002X system clock supplied from BCM2002X, XTAL input frequency BCM2002X must 19.2, 19.68, 19.8 MHz. should applied. XTAL Input Frequency CX72303 system clock supplied from CX72303, XTAL input frequency CX72303 must MHz. should applied. Required processes when interface pins unused following tables show processes that should performed when interface pins used. pins that included following table should left open.
Name RSSI PLLLOCK Process When Used Comments
UART
Name Process When Used Comments
Name PCMIN PCMSYNC PCMCLK Process When Used Open Open Open Comments
Processes Other Pins TEST etc.
Name DETACH Process When Used Pull Comments
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System Configuration Example ML70512/ML7050
ML70512 ML7050 VDD_D RESET
RFVDD
LVDD
Poewr reset
Semiconductor
Hardware reset
Microphone PCMOUT PCMIN PCMSYNC PCMCLK
Voice input/ output peripherals MSM7702-01 MCLK
Speaker
PCMIN PCMOUT RSYNC XSYNC BCLK
PLL_LE PLL_DATA PLL_CLK PLL_OFF PLL_POW RX_POW TX_POW RSSI PLL_LE PLL_DATA PLL_CLK PLL_OFF PLL_POW RX_POW TX_POW
SCLKSEL
RSSI_CLK PLL_PS PLLLOCK SCLKO SCLKN
13MHz 20ppm
SFRQSEL1 SFRQSEL0
RFSEL2 RFSEL1 RFSEL0 SCLKP XC32KN DETACH AVDD0
32kHz 32.768kHz 250ppm
XC32KP
AGND0 AVDD1
Separate, possible, wiring from board pins.
AGND1
SOUT CIO6 CIO5
UART
T1IN T1OUT T2IN T2OUT T3IN R1OUT R1IN R2OUT R2IN
CoreVDD
DSUB9PIN MAX3245
CoreVDD CIO4(LED1) CIO3(LED0) CIO2 SDA(CIO1) SCL(CIO0)
capacitors should close pins possible.
AT24C02
FEDL70512-04
ML70512
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PACKAGE DIMENSIONS
ML70512HB 83pinWCSP (P-VFLGA83-6.22 6.22-0.50-W)
(Unit:
Package material Lead frame material treatment Package weight Rev. No./Last Revised
Epoxy resin Sn/Pb Solder plating (5µm) 0.04 TYP. 1/July 2002
Note: lead-free package available. Please contact Sales Office/Distributors more information.
Notes Mounting Surface Mount Type Package surface mount type packages very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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ML70512LA 84pin (P-LFBGA84-0909-0.80)
(Unit:
P-LFBGA84-0909-0.80
Package material Ball material Package weight Rev. No./Last Revised
Epoxy resin Sn/Pb 0.20 TYP. 1/May 2000
Note: lead-free package available. Please contact Sales Office/Distributors more information.
Notes Mounting Surface Mount Type Package surface mount type packages very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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REVISION HISTORY
Document FEDL70512-01 Date Feb. 2003 Page Previous Current Edition Edition --FEDL70512-02 Mar. 2003 -FEDL70512-03 Apr. 2003 FEDL70512-04 Sep. 2003 ---Final edition Final edition Eliminated "RESET" table "TEST Section. Final edition Partially eliminated contents "Reset" Section. Partially eliminated "SPECIFICATIONS" Section. contents Description
Partially eliminated contents Characteristics" Section. Partially eliminated contents "Power Supply Current (IDDO) Characteristics Power Saving Mode" Section. Partially eliminated contents "Setting Reset" Section.
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NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products not, unless specifically authorized Oki, authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2003 Electric Industry Co., Ltd.
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Bluetooth Baseband Controller FEDL70512-04 Issue Date: Sep.

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