GEN-M9K-20 Data Sheet MEMBER FAMILY RM9000x1, RM9000x2

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GEN-M9K-20 Data Sheet MEMBER FAMILY RM9000x1, RM9000x2

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CM5391L Preliminary
GEN-M9K-20 Data Sheet
MEMBER FAMILY
RM9000x1, RM9000x2
Protection
Spread Spectrum
Provides optional spread spectrum phase modulation control. Triangular spread spectrum modulation algorithm pin-selectable common modulation frequencies up-spread down-spread ranges.
Copyright PMC-Sierra, Inc. 2003. rights reserved. complete list PMC-Sierra's trademarks registered trademarks, visit: Document PMC-2030357, Issue
output electrical options supported: SYSCLK1: Differential LVDS-compatible SYSCLK2, SYSCLK3: Single-ended LVTTL
Nominal duty cycle with 125ps max. cycle-to-cycle phase jitter. Three copies output clock generated, controlled "output enable" inputs. Maximum output-to-output skew 100ps.
20-pin TSSOP
Characteristics
Packaging
Proprietary Confidential PMC-Sierra, Inc. customers' internal use.
Output frequency pin-selectable support frequencies MHz, including common computing frequencies 50.00 MHz, 66.67 MHz, 83.33 MHz, 100.00 MHz, 125.00 MHz, 133.33 MHz, 166.67 MHz, 200.00 MHz.
Lead-free packaging option available
Contact Information: Site: http://www.pmc-sierra.com Technical Support: apps@pmc-sierra.com
("Commercial")
Input reference frequency pin-selectable support common, inexpensive crystals 25.0000 MHz, including 10.00000 MHz, 14.31818 MHz, 16.00000 MHz, 25.00000
Temperature Range
3.3V
Uses single crystal single-ended reference input generate clock outputs with electrical characteristics frequencies appropriate drive MasterClock input PMC-Sierra's MIPS processors companion system controller devices.
Power Supply
Clock Generation
PMC-Sierra's CM5391L clock generator superior price, size, power performance other discrete solutions.
PMC-Sierra's CM5391L clock generator industry's only device tailored drive clocking inputs PMC-Sierra's leading line processors using MIPS architectures, such
Flexible Clock Generators MIPS Based Systems
CM5391L Preliminary
GEN-M9K-20 Data Sheet
IFS[1] IFS[0] OFS[2] OFS[1] OFS[0] SPREAD[2] SPREAD[1] SPREAD[0] Spread Spectrum Control
Assignment Description
CM5391L Name SYSCLK1_P, SYSCLK1_N, SYSCLK2, SYSCLK3 Type Description Clock Output Differential Pair output frequency determined OFS[2:0] inputs, outputs enabled input. Single-ended LVTTL Clock Outputs output
15,14
SPREAD[2] VDDA IFS[0] IFS[1] OFS[2]
CM5391L
Diagram
Document PMC-2030357, Issue
OFS[0] OFS[1] SYSCLK1_P SYSCLK1_N SYSCLK2 SYSCLK3 SPREAD[1] SPREAD[0]
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
SYSCLK2
SYSCLK3
SYSCLK1_N
Crystal Oscillator
SYSCLK1_P
Figure CM5391L Functional Diagram
Block Diagram
CM5391L Preliminary
GEN-M9K-20 Data Sheet
page
CM5391L
Name SYSCLK3
Type
Description frequency determined OFS[2:0] inputs, outputs enabled input.
IFS[1:0]
VDDA
Document PMC-2030357, Issue
Pull-up VDDA) pull-down VSS) resistors typical.
SPREAD[2:0]
Spread Spectrum Control: Chooses whether spread spectrum modulation enabled, which triangular modulation scheme active. There internal pull-down resistor SPREAD[2] pull-up resistor each SPREAD[1] SPREAD[0].
power supply SYSCLK1_N/P, SYSCLK2, SYSCLK3 outputs. power supply analog functions, crystal oscillator, reference digital core. Ground reference
Proprietary Confidential PMC-Sierra, Inc. customers' internal use.
OFS[2:0]
Output Frequency Select: Chooses output frequency SYSCLK1_P/N differential pair SYSCLK2, SYSCLK3 single-ended outputs. There internal pull-up resistor each pin.
Output Enable active high control enabling SYSCLK2 SYSCLK3 single-ended LVTTL outputs. There internal pull-up resistor this pin. Pulling will tri-state outputs.
Output Enable active high control enabling SYSCLK1_P/N output differential pair. There internal pull-up resistor this pin. Pulling will tristate outputs.
Input Frequency Select: Chooses input reference frequency crystal) expected input. There internal pull-up resistor1 each pin.
Crystal Reference Out: These either spanned crystal accept single-ended reference input only). expected input frequency determined IFS[1:0] inputs. case where crystal used, should left unconnected. crystal differential load capacitance must rated 10pF.
CM5391L Preliminary
GEN-M9K-20 Data Sheet
IFS[1] IFS[0] SPREAD[2] SPREAD[1] SPREAD[0] OFS[2] OFS[1] OFS[0] SYSCLK1_N
GEN-M9K-20 designed direct connection PMC-Sierra's MIPS processors. GEN-M9K-20 with RM9000x1 Application Diagram
Input Freq. Select Spread Spectrum Control Output Freq. Select Output Enable
SYSCLK3
SYSCLK2
MASTERCLOCK*
Memory Controller
SYSCLKIN
Resistor values shown typical. Designers should best-practice signal integrity guidelines when choosing values their system.
Document PMC-2030357, Issue
Notes Application Diagram
SYSCLKIN
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
SYSCLK1_P
MASTERCLOCK
FPGA
CM5391L
RM9000x1
Applications
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Device Specifications
Absolute Maximum Ratings
Storage Temperature Supply Voltage Voltage Static Discharge Voltage Latch-Up Current Input Current Lead Temperature Junction Temperature -65C +150C -0.5V +4.6V -0.5V +4.6V ±2000V ±100mA ±20mA +225C +150C
Symbol VDD33 Vih3 Vil3 IDDOP3A3 IDDOP33 CLVTTL CLVDS
Parameter 3.3V Supply Voltage VDDA 3.3V Input High Voltage 3.3V Input Voltage 3.3V Operating Current VDDA
Condition 3.3V
Normal Operating Conditions Tambient 70C)
Min. 3.135 Max. 3.465 Units
Document PMC-2030357, Issue
Load Capacitance LVDS output
Load Capacitance LVTTL output
3.3V Operating Current
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
Ambient Temperature under Bias
+70C
Maximum ratings worst case limits that device withstand without sustaining permanent damage. They indicative normal operating conditions.
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Symbol ILUP Parameter Input Current Inputs With Pull-Up Resistors Input High Current Inputs With Pull-Up Resistors Input Current Inputs With Pull-Down Resistors Input High Current Inputs With Pull-Down Resistors Input Capacitance Capacitance Transition Time Settling Time Clock Stabilization Condition VDDA Min. -200 Max.
D.C. Operating Characteristics Tambient 70C)
+200 Max. 200.00 1.39
Units
bILDWN
VDDA
IHUP
VDDA
IHDWN
VDDA
Cxtal Ttrans TSTAB
From VDDA target frequency.
ISp, ISpn Trise Tfall Tduty Tjitter
Fall Time
Rise Time
Output Short-Circuit Current 20-80% VDIFF, termination; 80-20% VDIFF, termination;
Output Short-Circuit-toGround Current
VDIFF
Differential Voltage Swing
Common Mode Voltage
fout
Output Frequency
Symbol
Parameter
Output Characteristics Differential LVDS Tambient 70C)
Condition Min. 33.33 1.05 Peak (not peak-to-peak) swing Units Depends device option.
Document PMC-2030357, Issue
Duty Cycle Cycle-To-Cycle Jitter
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
From crossing target frequency.
From VDDA crossing target frequency.
Single-ended capacitance
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Symbol fout Trise Tfall Tjitter Tskew Parameter Output Frequency Output High Voltage Output Voltage Output High Current Output Current Rise Time Fall Time Duty Cycle Cycle-To-Cycle Jitter Output-to-Output Skew Condition Depends device option. 2.4V 0.4V 0.4V 2.4V; load 2.4V 0.4V; load -51.6 Min. 33.33 Max.
200.00
-14.8 24.8
Output Characteristics Single-Ended LVTTL Tambient 70C)
Units
Assumes outputs have same loading termination.
Document PMC-2030357, Issue
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
13.6
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Functional Options
Output Frequency Selection
OFS[2:0] Freq. (MHz) 50.00 66.67 83.33 100.00 125.00 133.33 166.67 200.00
Input Frequency Selection
16.00000
25.00000
Spread Spectrum Algorithm Diagram
(1+u)f
Frequency
(1-d)f
0.5/f
Time
Spread Spectrum Algorithm Selection
Spread Spectrum Algorithm 0.6% 0.3% 0.6% disabled 0.6% 0.3% 0.6% 0.6% 0.3% 0.0% 0.6% 0.3% 0.0%
SPREAD[2:0]
Document PMC-2030357, Issue
fmod
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
14.31818
10.00000
IFS[1:0]
Freq. (MHz)
CM5391L several control inputs. These inputs select functional mode device, explained following tables.
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Theta JEDEC Board2 Conv 84.0
Thermal Information
GEN-M9K-20 Junction Temperature
CM5391L-AC Maximum Junction Temperature Long Term Reliability
GEN-M9K-20 Theta Airflow
Forced (Linear Feet Minute) Part CM5391L-AC
Part CM5391L-AC
Case Temperature +70C
Theta
JEDEC Board Theta measured value single thermal device same package 2S2P board following EIA/JESD 51-3.
Document PMC-2030357, Issue
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
GEN-M9K-20 Theta
CM5391L-AC
+70C
Part
Case Temperature
Theta
GEN-M9K-20 Theta
+70C
Ambient Temp.
76.0
73.3
CM5391L Preliminary
GEN-M9K-20 Data Sheet
1.00 DIA. 1.00 DIA.
1.00
SIDE VIEW
SEATING PLANE
0.25
(0-8
(1.00)
(SCALE: 30/1) (VIEW ROTATED C.W.)
DETAIL
PARTING LINE
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
NOTE: THIS PART COMPLIANT WITH JEDEC SPECIFICATIONS MO-153 VARIATION
Document PMC-2030357, Issue
Mechanical Information
CM5391L Preliminary
GEN-M9K-20 Data Sheet
Proprietary Confidential PMC-Sierra, Inc. customers' internal use. page
Ordering Information
Part CM5391L-AC Description 20-pin Thin Shrink Small Outline Package (TSSOP) with LVDS-compatible electrical LVTTL electrical
Support
PMC-2021479, "RM9000x1 Integrated Microprocessor Short Form Data Sheet", PMC-Sierra. PMC-2011766, "RM9000x2 Integrated Multiprocessor Short Form Data Sheet", PMC-Sierra.
Document PMC-2030357, Issue
Standards References
This document provides Assignments Mechanical Information GEN-M9K-20. packaging JEDEC-standard 20-pin TSSOP.
IBIS models high-speed outputs GEN-M9K-20 available download PMC-Sierra's site (www.pmc-sierra.com) following zero-dollar license registration.
Signal Integrity Simulation Support
Tools Support

GEN-M9K-20 Data Sheet MEMBER FAMILY RM9000x1, RM9000x2

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