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SEMICONDUCTOR DATA SHEET
Order this document DSP56367/D
01/02
Data Sheet
DSP56367
24-Bit Audio Digital Signal Processor
This document briefly descibes DSP56367 24-bit digital signal processor (DSP). DSP56367 member DSP56300 family programmable CMOS DSPs. DSP56367 targeted applications that require digital audio compression/decompression, sound field processing, acoustic equalization other digital audio algorithms. DSP56367 offers million instructions second (MIPS) using internal clock million instructions second (MIPS) using internal clock
MEMORY EXPANSION AREA
TRIPLE TIMER (SPDIF Tx.) INTERFACE HOST INTERFACE ESAI INTERFACE ESAI_1 INTERFACE PROGRAM /INSTR. CACHE PROGRAM Bootstrap MEMORY MEMORY
PIO_EB
PM_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATION UNIT CHANNELS UNIT
XM_EB
YM_EB
EXTERNAL ADDRESS SWITCH DRAM SRAM INTERFACE CACHE EXTERNAL DATA SWITCH
ADDRESS
24-BIT DSP56300 Core
CONTROL
INTERNAL DATA
DATA
POWER MNGMNT CLOCK GENERAT
PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR DATA 24X24+56->56-BIT 56-BIT ACCUMULATORS BARREL SHIFTER JTAG OnCE
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
BITS
Figure DSP56367 Block Diagram
This document contains information product. Specifications information herein subject change without notice.
Data Sheet
©2001, 2002 MOTOROLA, INC.
Table Contents
TABLE CONTENTS
SECTION SECTION SECTION SECTION APPENDIX APPENDIX SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS PACKAGING DESIGN CONSIDERATIONS POWER CONSUMPTION BENCHMARK APPENDIX IBIS MODEL. APPENDIX
TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values VIL, VOL, VIH, defined individual product specifications.
DSP56367 Data Sheet
DSP56367 Features
FEATURES
Core features described fully DSP56300 Family Manual.
DSP56300 MODULAR CHASSIS
Million Instructions Second (MIPS) with clock internal logic supply (QVCCL) 1.8V. Million Instructions Second (MIPS) with clock internal logic supply (QVCCL) 1.5V. Object Code Compatible with core. Data with multiplier-accumulator 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support instruction cache support. Six-channel controller. based clocking with wide range frequency multiplications 4096), predivider factors power saving clock divider (2i: Reduces clock noise. Internal address tracing support OnCEfor Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down STOP WAIT low-power standby modes.
ON-CHIP MEMORY CONFIGURATION
7Kx24 Y-Data 8Kx24 Y-Data ROM. 13Kx24 X-Data 32Kx24 X-Data ROM. 40Kx24 Program ROM. 3Kx24 Program 192x24 Bootstrap ROM. Program used Instruction Cache Program patching. 2Kx24 from Data 5Kx24 from Data switched Program resulting 10Kx24 Program RAM.
Data Sheet MOTOROLA DSP56367
DSP56367 Off-chip memory expansion
OFF-CHIP MEMORY EXPANSION
External Memory Expansion Port. Off-chip expansion 24-bit word Data memory. Off-chip expansion 24-bit word Program memory. Simultaneous glueless interface SRAM DRAM.
PERIPHERAL MODULES
Serial Audio Interface (ESAI): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols. Serial Audio Interface I(ESAI_1): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols ESAI_1 shares four data pins with ESAI, ESAI_1 does support HCKR HCKT (high frequency clocks) Serial Host Interface (SHI): protocols, multi master capability, 10-word receive FIFO, support 24-bit words. Byte-wide parallel Host Interface (HDI08) with support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): serial transmitter capable supporting SPDIF, IEC958, CP-340 AES/EBU digital audio formats. Pins unused peripherals (except SHI) programmed GPIO lines.
144-PIN PLASTIC LQFP PACKAGE
Data Sheet DSP56367
DSP56367 Documentation
DOCUMENTATION
Table lists documents that provide complete description DSP56367 required design properly with part. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information). Table
Document Name DSP56300 Family Manual
DSP56367 Documentation
Description Order Number DSP56300FM/AD
Detailed description 56000-family architecture 24-bit core processor instruction Brief description chip DSP56367 User's Manual
DSP56367 Product Brief DSP56367 User's Manual
DSP56367P/D DSP56367UM/AD
Data Sheet MOTOROLA DSP56367
DSP56367 Documentation
Data Sheet DSP56367
SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
input output signals DSP56367 organized into functional groups, which listed Table illustrated Figure DSP56367 operated from 1.8V supply; however, some inputs tolerate 3.3V. special notice this feature added signal descriptions those inputs. Remember, DSP56367 offers million instructions second (MIPS) using internal clock million instructions second (MIPS) using internal clock 1.3.3V.
Table DSP56367 Functional Signal Groupings
Functional Group Number Signals Port Data control Interrupt mode control HDI08 ESAI ESAI_1 Digital audio transmitter (DAX) Timer JTAG/OnCE Port Port Port Port Port Table Table Table Table Table Table Table Table Table Table Detailed Description Table Table Table Table
Power (VCC) Ground (GND) Clock Address
DSP56367 Data Sheet
Signal/Connection Descriptions Signal Groupings
Table DSP56367 Functional Signal Groupings (Continued)
Functional Group Number Signals Detailed Description
Note:
Port external memory interface port, including external address bus, data bus, control signals. Port signals GPIO port signals which multiplexed with HDI08 signals. Port signals GPIO port signals which multiplexed with ESAI signals. Port signals GPIO port signals which multiplexed with signals. Port signals GPIO port signals which multiplexed with ESAI_1 signals.
DSP56367 Data Sheet
Signal/Connection Descriptions Signal Groupings
PORT ADDRESS
A0-A17 VCCA GNDA
DSP56367
OnCEON-CHIP EMULATION/ JTAG PORT
PORT DATA
D0-D23 VCCD GNDD
PARALLEL HOST PORT (HDI08) Port
HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH
PORT CONTROL
AA0-AA2/RAS0-RAS2 VCCC GNDC
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
Port
[PC4] HCKT [PC5] SCKR [PC0] [PC1] HCKR [PC2] SDO0[PC11] SDO0_1[PE11] SDO1[PC10] SDO1_1[PE10] SDO2/SDI3[PC9] SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]
INTERRUPT MODE CONTROL
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
CLOCK
EXTAL PINIT/NMI PCAP VCCP GNDP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
Port
T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS GNDS
QUIET POWER
VCCQH VCCQL GNDQ
SPDIF TRANSMITTER (DAX)
[PD1] [PD0]
Port
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
TIMER
TIO0 [TIO0]
Figure Signals Identified Functional Group
DSP56367 Data Sheet
Signal/Connection Descriptions Power
POWER
Table Power Inputs
Power Name VCCP Description Power-VCCP dedicated use. voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Core (Low) Power-VCCQL isolated power internal processing logic. This input must tied externally other VCCQL power pins VCCP power only. with other power pins. user must provide adequate external decoupling capacitors. There four VCCQL inputs. Quiet External (High) Power-VCCQH quiet power source lines. This input must tied externally other chip power inputs.The user must provide adequate decoupling capacitors. There three VCCQH inputs. Address Power-VCCA isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There three VCCA inputs. Data Power-VCCD isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power-VCCC isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. Host Power-VCCH isolated power HDI08 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH input. SHI, ESAI, ESAI_1, Timer Power -VCCS isolated power SHI, ESAI, ESAI_1, Timer. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCS inputs.
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
GROUND
Table Grounds
Ground Name GNDP Description Ground-GNDP ground dedicated use. connection should provided with extremely low-impedance path ground. should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Quiet Ground-GNDQ isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections.
GNDQ
DSP56367 Data Sheet
Signal/Connection Descriptions Clock
Table Grounds
Ground Name GNDA Description Address Ground-GNDA isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground-GNDD isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground-GNDC isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDC connections. Host Ground-GNDh isolated ground HD08 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connection. SHI, ESAI, ESAI_1, Timer Ground-GNDS isolated ground SHI, ESAI, ESAI_1, Timer. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDD
GNDC
GNDH
GNDS
CLOCK
Table Clock Signals
Signal Name Type State during Reset Input Signal Description
EXTAL
Input
External Clock Input-An external clock source must connected EXTAL order supply clock internal clock generator PLL. Capacitor-PCAP input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal CCP. used, PCAP tied VCC, GND, left floating. Initial/Nonmaskable Interrupt-During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET assertion during normal instruction processing, PINIT/NMI Schmitt-trigger input negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized internal system clock.
PCAP
Input
Input
PINIT/NMI
Input
Input
EXTERNAL MEMORY EXPANSION PORT (PORT
When DSP56367 enters low-power standby mode (stop wait), releases mastership tri-states relevant port signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, CAS.
MOTOROLA DSP56367 Data Sheet
Signal/Connection Descriptions External Address
EXTERNAL ADDRESS
Table External Address Signals
Signal Name Type State during Reset Tri-stated Signal Description
A0-A17
Output
Address Bus-When master, A0-A17 active-high outputs that specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
EXTERNAL DATA
Table External Data Signals
Signal Name D0-D23 Type Input/Output State during Reset Tri-stated Signal Description Data Bus-When master, D0-D23 active-high, bidirectional input/outputs that provide bidirectional data external program data memory accesses. Otherwise, D0-D23 tri-stated.
EXTERNAL CONTROL
Table External Control Signals
Signal Name Type State during Reset Tri-stated Signal Description
AA0-AA2/ RAS0-RAS
Output
Address Attribute Address Strobe-When defined these signals used chip selects additional address lines. When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity. Column Address Strobe- When master, active-low output used DRAM strobe column address. Otherwise, mastership enable (BME) DRAM control register cleared, signal tri-stated. Read Enable-When master, active-low output that asserted read external memory data (D0-D23). Otherwise, tri-stated. Write Enable-When master, active-low output that asserted write external memory data (D0-D23). Otherwise, tri-stated.
Output
Tri-stated
Output
Tri-stated
Output
Tri-stated
DSP56367 Data Sheet
Signal/Connection Descriptions External Control
Table External Control Signals (Continued)
Signal Name Type State during Reset Ignored Input Signal Description
Input
Transfer Acknowledge-If master there external activity, master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous internal system clock. number wait states determined input control register (BCR), whichever longer. used minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion, otherwise improper operation result. operate synchronously asynchronously, depending setting operating mode register (OMR). functionality used while performing DRAM type accesses, otherwise improper operation result. Request-BR active-low output, never tri-stated. asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independent whether DSP56367 master slave. "parking" allows deasserted even though DSP56367 master. (See description "parking" signal description.) request hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. only affected requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state. Grant-BG active-low input. asserted external arbitration circuit when DSP56367 becomes next master. When asserted, DSP56367 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. proper operation, asynchronous arbitration enable (ABE) register must set.
Output
Output (deasserted)
Input
Ignored Input
Input/ Output
Input
Busy-BB bidirectional active-low input/output. indicates that active. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity regardless whether asserted deasserted. This called "bus parking" allows current master reuse without rearbitration until another device requires bus. deassertion done "active pull-up" method (i.e., driven high then released held high external pull-up resistor). proper operation, asynchronous arbitration enable (ABE) register must set. requires external pull-up resistor.
DSP56367 Data Sheet
Signal/Connection Descriptions Interrupt Mode Control
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
Table Interrupt Mode Control
Signal Name Type State during Reset Input Signal Description
MODA/IRQA
Input
Mode Select A/External Interrupt Request A-MODA/IRQA active-low Schmitt-trigger input, internally synchronized clock. MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. processor stop standby state MODA/IRQA pulled GND, processor will exit stop state. This input 3.3V tolerant. Mode Select B/External Interrupt Request B-MODB/IRQB active-low Schmitt-trigger input, internally synchronized clock. MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input 3.3V tolerant. Mode Select C/External Interrupt Request C-MODC/IRQC active-low Schmitt-trigger input, internally synchronized clock. MODC/IRQC selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input 3.3V tolerant. Mode Select D/External Interrupt Request D-MODD/IRQD active-low Schmitt-trigger input, internally synchronized clock. MODD/IRQD selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input 3.3V tolerant. Reset-RESET active-low, Schmitt-trigger input. When asserted, chip placed Reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted during power stable EXTAL signal must supplied while RESET being asserted. This input 3.3V tolerant.
MODB/IRQB
Input
Input
MODC/IRQC
Input
Input
MODD/IRQD
Input
Input
RESET
Input
Input
DSP56367 Data Sheet
Signal/Connection Descriptions Parallel Host Interface (HDI08)
PARALLEL HOST INTERFACE (HDI08)
HDI08 provides fast, 8-bit, parallel data port that connected directly host bus. HDI08 supports variety standard buses directly connected number industry standard microcomputers, microprocessors, DSPs, hardware.
DSP56367 Data Sheet
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table Host Interface
Signal Name Type State during Reset Signal Description
H0-H7
Input/ output
Host Data-When HDI08 programmed interface nonmultiplexed host function selected, these signals lines bidirectional, tri-state data bus. Host Address/Data-When HDI08 programmed interface multiplexed host function selected, these signals lines address/data bidirectional, multiplexed, tri-state bus. GPIO disconnected Port 0-7-When HDI08 configured GPIO, these signals individually programmable input, output, internally disconnected. default state after reset these signals GPIO disconnected. These inputs 3.3V tolerant.
HAD0-HAD7
Input/ output
PB0-PB7
Input, output, disconnected
Input
GPIO disconnected
Host Address Input 0-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address input bus. Host Address Strobe-When HDI08 programmed interface multiplexed host function selected, this signal host address strobe (HAS) Schmitt-trigger input. polarity address strobe programmable, configured active-low (HAS) following reset. Port 8-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
HAS/HAS
Input
Input, output, disconnected
Input
GPIO disconnected
Host Address Input 1-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address (HA1) input bus. Host Address 8-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA8) input bus.
Input
Input, output, disconnected
Port 9-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
1-10
DSP56367 Data Sheet
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset GPIO disconnected Signal Description
Input
Host Address Input 2-When HDI08 programmed interface non-multiplexed host function selected, this signal line host address (HA2) input bus. Host Address 9-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA9) input bus. Port 10-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
Input
PB10
Input, Output, Disconnected
Input
GPIO disconnected
Host Read/Write-When HDI08 programmed interface single-data-strobe host function selected, this signal Host Read/Write (HRW) input. Host Read Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host read data strobe (HRD) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HRD) after reset. Port 11-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
HRD/
Input
PB11
Input, Output, Disconnected
HDS/
Input
GPIO disconnected
Host Data Strobe-When HDI08 programmed interface single-data-strobe host function selected, this signal host data strobe (HDS) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HDS) following reset. Host Write Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host write data strobe (HWR) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HWR) following reset. Port 12-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
HWR/
Input
PB12
Input, output, disconnected
DSP56367 Data Sheet
1-11
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset GPIO disconnected Signal Description
Input
Host Chip Select-When HDI08 programmed interface nonmultiplexed host function selected, this signal host chip select (HCS) input. polarity chip select programmable, configured active-low (HCS) after reset. Host Address 10-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA10) input bus. Port 13-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
HA10
Input
PB13
Input, output, disconnected
HOREQ/HOREQ
Output
GPIO disconnected
Host Request-When HDI08 programmed interface single host request host function selected, this signal host request (HOREQ) output. polarity host request programmable, configured active-low (HOREQ) following reset. host request programmed driven open-drain output. Transmit Host Request-When HDI08 programmed interface double host request host function selected, this signal transmit host request (HTRQ) output. polarity host request programmable, configured active-low (HTRQ) following reset. host request programmed driven open-drain output. Port 14-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
HTRQ/ HTRQ
Output
PB14
Input, output, disconnected
HACK/ HACK
Input
GPIO disconnected
Host Acknowledge-When HDI08 programmed interface single host request host function selected, this signal host acknowledge (HACK) Schmitt-trigger input. polarity host acknowledge programmable, configured active-low (HACK) after reset. Receive Host Request-When HDI08 programmed interface double host request host function selected, this signal receive host request (HRRQ) output. polarity host request programmable, configured active-low (HRRQ) after reset. host request programmed driven open-drain output. Port 15-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected.
HRRQ/ HRRQ
Output
PB15
Input, output, disconnected
default state after reset this signal GPIO disconnected. This input 3.3V tolerant.
1-12
DSP56367 Data Sheet
Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
five signals that configured allow operate either mode.
Table Serial Host Interface Signals
Signal Name Signal Type State during Reset Tri-stated Signal Description
Input output
Serial Clock-The signal output when configured master Schmitt-trigger input when configured slave. When configured master, signal derived from internal clock generator. When configured slave, signal input, clock signal from external master synchronizes data transfer. signal ignored defined slave slave select (SS) signal asserted. both master slave devices, data shifted edge signal sampled opposite edge where data stable. Edge polarity determined transfer protocol. Serial Clock-SCL carries clock transactions mode. Schmitt-trigger input when configured slave open-drain output when configured master. should connected through pull-up resistor. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input 3.3V tolerant.
Input output
MISO
Input output
Tri-stated
Master-In-Slave-Out-When configured master, MISO master data input line. MISO signal used conjunction with MOSI signal transmitting receiving serial data. This signal Schmitt-trigger input when configured Master mode, output when configured Slave mode, tri-stated configured Slave mode when deasserted. external pull-up resistor required operation. Data Acknowledge-In mode, Schmitt-trigger input when receiving open-drain output when transmitting. should connected through pull-up resistor. carries data transactions. data must stable during high period SCL. data only allowed change when low. When free, high. line only allowed change during time high case start stop events. high-to-low transition line while high unique situation, defined start event. low-to-high transition while high unique situation defined stop event. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input 3.3V tolerant.
Input open-drain output
DSP56367 Data Sheet
1-13
Signal/Connection Descriptions Serial Host Interface
Table Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Tri-stated Signal Description
MOSI
Input output
Master-Out-Slave-In-When configured master, MOSI master data output line. MOSI signal used conjunction with MISO signal transmitting receiving serial data. MOSI slave data input line when configured slave. This signal Schmitt-trigger input when configured Slave mode. Slave Address 0-This signal uses Schmitt-trigger input when configured mode. When configured slave mode, signal used form slave device address. ignored when configured master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input 3.3V tolerant.
Input
Input
Tri-stated
Slave Select-This signal active Schmitt-trigger input when configured mode. When configured Slave mode, this signal used enable slave transfer. When configured master mode, this signal should kept deasserted (pulled high). asserted while configured master, error condition flagged. deasserted, ignores clocks keeps MISO output signal high-impedance state. Slave Address 2-This signal uses Schmitt-trigger input when configured mode. When configured Slave mode, signal used form slave device address. ignored master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input 3.3V tolerant.
Input
HREQ
Input Output
Tri-stated
Host Request-This signal active Schmitt-trigger input when configured master mode active output when configured slave mode. When configured slave mode, HREQ asserted indicate that ready next data word transfer deasserted first clock pulse data word transfer. When configured master mode, HREQ input. When asserted external slave device, will trigger start data word transfer master. After finishing data word transfer, master will await next assertion HREQ proceed next transfer. This signal tri-stated during hardware, software, personal reset, when HREQ1-HREQ0 bits HCSR cleared. There need external pull-up this state. This input 3.3V tolerant.
1-14
DSP56367 Data Sheet
Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table Enhanced Serial Audio Interface Signals
Signal Name HCKR Signal Type Input output State during Reset GPIO disconnected Signal Description High Frequency Clock Receiver-When programmed input, this signal provides high frequency clock source ESAI receiver alternate core clock. When programmed output, this signal serve high-frequency sample clock (e.g., external digital analog converters [DACs]) additional system clock. Port 2-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. HCKT Input output GPIO disconnected High Frequency Clock Transmitter-When programmed input, this signal provides high frequency clock source ESAI transmitter alternate core clock. When programmed output, this signal serve high frequency sample clock (e.g., external DACs) additional system clock. Port 5-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. Input output GPIO disconnected Frame Sync Receiver-This receiver frame sync input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Input, output, disconnected Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. Input output GPIO disconnected Frame Sync Transmitter-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant.
Input, output, disconnected
Input, output, disconnected
Input, output, disconnected
DSP56367 Data Sheet
1-15
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table Enhanced Serial Audio Interface Signals (Continued)
Signal Name SCKR Signal Type Input output State during Reset GPIO disconnected Signal Description Receiver Serial Clock-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Input, output, disconnected Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. SCKT Input output GPIO disconnected Transmitter Serial Clock-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. SDO5 SDI0 Output Input Input, output, disconnected GPIO disconnected Serial Data Output 5-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant. SDO4 SDI1 Output Input Input, output, disconnected GPIO disconnected Serial Data Output 4-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant.
Input, output, disconnected
1-16
DSP56367 Data Sheet
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO3/SD O3_1 SDI2/SDI PC8/PE8 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 3-When programmed transmitter, SDO3 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Serial Data Input 2-When programmed receiver, SDI2 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input Port 8-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input 3.3V tolerant. SDO2/SD O2_1 SDI3/SDI PC9/PE9 Output GPIO disconnected Serial Data Output 2-When programmed transmitter, SDO2 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Serial Data Input 3-When programmed receiver, SDI3 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input Port 9-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input 3.3V tolerant. SDO1/SD O1_1 PC10/PE1 Output GPIO disconnected Serial Data Output 1-SDO1 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Port 10-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input 3.3V tolerant. SDO0/SD O0_1 PC11/PE1 Output GPIO disconnected Serial Data Output 0-SDO0 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Port 11-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input 3.3V tolerant.
Input
Input, output, disconnected
Input
Input, output, disconnected
Input, output, disconnected
Input, output, disconnected
DSP56367 Data Sheet
1-17
Signal/Connection Descriptions Enhanced Serial Audio Interface_1
ENHANCED SERIAL AUDIO INTERFACE_1
Table Enhanced Serial Audio Interface_1 Signals
Signal Name FSR_1 Signal Type Input output State during Reset GPIO disconnected Signal Description Frame Sync Receiver_1-This receiver frame sync input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Input, output, disconnected Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate 3.3V. FST_1 Input output GPIO disconnected Frame Sync Transmitter_1-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate 3.3V. SCKR_1 Input output GPIO disconnected Receiver Serial Clock_1-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Input, output, disconnected Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate 3.3V.
Input, output, disconnected
1-18
DSP56367 Data Sheet
Signal/Connection Descriptions SPDIF Transmitter Digital Audio Interface
Table Enhanced Serial Audio Interface_1 Signals
Signal Name SCKT_1 Signal Type Input output State during Reset GPIO disconnected Signal Description Transmitter Serial Clock_1-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate 3.3V. SDO5_1 SDI0_1 Output Input Input, output, disconnected GPIO disconnected Serial Data Output 5_1-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0_1-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate 3.3V. SDO4_1 SDI1_1 Output Input Input, output, disconnected GPIO disconnected Serial Data Output 4_1-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1_1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input 3.3V tolerant.
Input, output, disconnected
SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE
Table Digital Audio Interface (DAX) Signals
Signal Name Type State During Reset Signal Description
Input
GPIO Disconnected Audio Clock Input-This clock input. When programmed external clock, this input supplies clock. external clock frequency must 256, 384, times audio sampling frequency (256 respectively). Port 0-When configured GPIO, this signal individually programmable input, output, internally disconnected.
Input, output, disconnected
default state after reset GPIO disconnected. This input 3.3V tolerant.
DSP56367 Data Sheet
1-19
Signal/Connection Descriptions Timer
Table Digital Audio Interface (DAX) Signals (Continued)
Signal Name Type State During Reset Signal Description
Output
GPIO Disconnected Digital Audio Data Output-This signal audio non-audio output form AES/EBU, CP340 IEC958 data biphase mark format. Port 1-When configured GPIO, this signal individually programmable input, output, internally disconnected.
Input, output, disconnected
default state after reset GPIO disconnected. This input 3.3V tolerant.
TIMER
Table Timer Signal
Signal Name Type State during Reset Input Signal Description
TIO0
Input Output
Timer Schmitt-Trigger Input/Output-When timer functions external event counter measurement mode, TIO0 used input. When timer functions watchdog, timer, pulse modulation mode, TIO0 used output. default mode after reset GPIO input. This changed output configured timer input/output through timer control/status register (TCSR0). TIO0 being used, recommended either define GPIO output immediately beginning operation leave defined GPIO input connected through pull-up resistor order ensure stable logic level this input. This input 3.3V tolerant.
JTAG/OnCE INTERFACE
Table JTAG/OnCE Interface
Signal Name Signal Type State during Reset Input Signal Description
Input
Test Clock-TCK test clock input signal used synchronize JTAG test logic. internal pull-up resistor. This input 3.3V tolerant.
1-20
DSP56367 Data Sheet
Signal/Connection Descriptions
Table JTAG/OnCE Interface (Continued)
Signal Name Signal Type State during Reset Input Signal Description
Input
Test Data Input-TDI test data serial input signal used test instructions data. sampled rising edge internal pull-up resistor. This input 3.3V tolerant.
Output
Tri-stated
Test Data Output-TDO test data serial output signal used test instructions data. tri-statable actively driven shift-IR shift-DR controller states. changes falling edge TCK. Test Mode Select-TMS input signal used sequence test controller's state machine. sampled rising edge internal pull-up resistor. This input 3.3V tolerant.
Input
Input
DSP56367 Data Sheet
1-21
Signal/Connection Descriptions
1-22
DSP56367 Data Sheet
SECTION SPECIFICATIONS
INTRODUCTION
DSP56367 high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs outputs. Note: This document contains information product. Specifications information herein subject change without notice.
Finalized specifications published after further characterization device qualifications completed.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs pulled appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor
Note:
calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum"
DSP56367 Data Sheet
Specifications Maximum Ratings
value another specification; adding maximum minimum represents condition that never exist.
Table Maximum Ratings
Rating1 Supply Voltage Symbol VCCQL, VCCP VCCQH, VCCA, VCCD, VCCC, VCCH, VCCS, "3.3V tolerant" input voltages Current drain excluding Operating temperature range3 Storage temperature Note: TSTG Value1, Unit
-0.3 -0.3
+125
VCCP, VCCQL ±5%, other Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. Temperatures below -0°C qualified consumer applications.
DSP56367 Data Sheet
Specifications Thermal Characteristics
THERMAL CHARACTERISTICS
Table Thermal Characteristics
Characteristic Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Natural Convection, Thermal characterization parameter4 Note: Symbol TQFP Value 45.0 10.0 Unit
°C/W °C/W °C/W
Junction temperature function size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance. SEMI G38-87 JEDEC JESD51-2 with single layer board horizontal. Thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2. When Greek letters available, thermal characterization parameter written Psi-JT.
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics5
Characteristics Supply voltages Core (VCCQL) PLL(VCCP) Supply voltages VCCQH VCCA VCCD VCCC VCCH VCCS Input high voltage D(0:23), ESAI_1 (except
SDO4_1)
Symbol
1.71
1.89
Unit
3.14
3.46
VIHP VCCQH VCCQH both VIHP VCCQH both VIHP VCCQH
MOD1/IRQ1, RESET, PINIT/NMI SDO4_1)/SHI(SPI mode) SHI(I2C mode)
VIHP
VCCQH
EXTAL
VIHX
DSP56367 Data Sheet
Specifications Electrical Characteristics
Table Electrical Characteristics5 (Continued)
Characteristics Input voltage D(0:23), ESAI_1(except
SDO4_1)
Symbol
Unit
VILP
-0.3 -0.3
MOD1/IRQ1, RESET, PINIT/NMI SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL
VILP VILX ITSI
-0.3 -0.3
VCCQH
Input leakage current High impedance (off-state) input current Output high voltage6
Output voltage6 Internal supply current2 internal clock 150MHz ICCI Normal mode Wait mode Stop mode3 ICCW ICCS
58.0
supply current Input capacitance Note:
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins Power Consumption Considerations section provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (i.e., allowed float). Measurements based synthetic intensive benchmarks. power consumption numbers this specification measured results this benchmark. This reflects typical applications. Typical internal supply current measured with VCCQL 1.8V, VCC(other) 3.3V 25°C. Maximum internal supply current measured with VCCQL 1.89V, VCC(other) 3.46V 95°C. order obtain these results, inputs, which disconnected Stop mode, must terminated (i.e., allowed float). Periodically sampled 100% tested VCCQL -40°C +95°C, other -40°C +95°C, This characteristic does apply PCAP.
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL. timing specifications, which referenced device input signal, measured production with respect point respective input signal's transition. DSP56367 output levels
DSP56367 Data Sheet
Specifications Internal Clocks
measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
INTERNAL CLOCKS
Table Internal Clocks
Expression1, Characteristics Symbol Internal operation frequency with enabled Internal operation frequency with disabled Internal clock high period With disabled With enabled With enabled 0.49 DF/MF 0.47 DF/MF 0.51 DF/MF 0.53 DF/MF MF)/ (PDF Ef/2
Internal clock period With disabled With enabled With enabled ICYC 0.49 DF/MF 0.47 DF/MF 0.51 DF/MF 0.53 DF/MF
DF/MF
Internal clock cycle time with enabled Internal clock cycle time with disabled Instruction cycle time Note:
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor internal clock cycle Refer DSP56300 Family
Manual detailed discussion PLL.
DSP56367 Data Sheet
Specifications External Clock Operation
EXTERNAL CLOCK OPERATION
DSP56367 system clock externally supplied square wave voltage source connected EXTAL(Figure
VIHC EXTAL VILC Midpoint
Note:
midpoint (VIHC VILC).
Figure External Clock Timing
Table Clock Operation
Characteristics Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle4) With enabled (42.5%-57.5% duty cycle4) Symbol 150.0
3.11 2.83 3.11 2.83
157.0 157.0 273.1 8.53
EXTAL input low1, With disabled (46.7%-53.3% duty cycle4) With enabled (42.5%-57.5% duty cycle4) time2
EXTAL cycle With disabled With enabled
Instruction cycle time ICYC With disabled With enabled
ICYC
13.33 6.67
Note:
Measured input transition maximum value enabled given minimum maximum maximum value enabled given minimum maximum indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correct operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
DSP56367 Data Sheet
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table Characteristics
Characteristics frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Note: 580) 780) 1470 Unit
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: 680)-120, 1100,
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table Reset, Stop, Mode Select, Interrupt Timing
Characteristics Delay from RESET assertion pins reset value3 Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled Power Internal oscillator During STOP, XTAL disabled During STOP, XTAL enabled During normal operation Expression 26.0 Unit
1000 75000 75000
333.4
16.7 16.7
Delay from asynchronous RESET deassertion first external address output (internal reset deassertion) Minimum Maximum 3.25 20.25 23.7 145.0
reset setup time from RESET Maximum
reset deassert delay time Minimum Maximum 3.25 20.25 22.7 30.0 140.0
Mode select setup time
DSP56367 Data Sheet
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table Reset, Stop, Mode Select, Interrupt Timing
Characteristics Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Expression Unit
4.25 7.25
30.3 50.3 71.7
Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution Delay from address output valid caused first interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1,7,8
3.75) 10.94
Note
Delay from assertion interrupt request deassertion level sensitive fast interrupts1,7,8
3.25) 10.94
Note
Delay from assertion interrupt request deassertion level sensitive fast interrupts1, DRAM 3.5) 10.94 Note
SRAM SRAM SRAM
1.75 2.75
Note Note Note
Synchronous setup time from IRQs assertion CLKOUT trans.
Synch. delay time from CLKOUT trans2 first external address valid caused first inst fetch Minimum Maximum 9.25 24.75 62.7 170.0
Duration IRQA assertion recover from Stop state
DSP56367 Data Sheet
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table Reset, Stop, Mode Select, Interrupt Timing
Characteristics Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR (128 PLC/2) (23.75 +/0.5) Expression Unit
active during Stop (PCTL (Implies Stop Delay)
(8.25 0.5)
51.7
58.3
Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay) (128 PLC/2) (20.5 +/0.5)
36.7
Interrupt Requests Rate HDI08, ESAI, ESAI_1, SHI, DAX, Timer IRQ, (edge trigger) (level trigger)
12TC 12TC
80.0 53.0 53.0 80.0
Requests Rate Data read from HDI08, ESAI, ESAI_1, SHI, Data write HDI08, ESAI, ESAI_1, SHI, Timer IRQ, (edge trigger)
40.0
46.7 13.3
20.0
DSP56367 Data Sheet
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table Reset, Stop, Mode Select, Interrupt Timing
Characteristics Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid Expression 4.25 30.3 Unit
Note:
When using fast interrupts IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using external clock (PCTL stabilization delay required recovery time will defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs: stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (i.e., 4096/150 27.3 µs). During stabilization period, will constant, their width vary, timing vary well.
Periodically sampled 100% tested RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock VCCQH VCC= 1.8V -40°C 95°C, number wait states (measured clock cycles, number TC). expression compute maximum value.
RESET
Pins Reset Value
A0-A17
First Fetch
AA0460
Figure Reset Timing
2-10
DSP56367 Data Sheet
Specifications Reset, Stop, Mode Select, Interrupt Timing A0-A17
First Interrupt Instruction Execution/Fetch
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
General Purpose IRQA, IRQB, IRQC, IRQD, General Purpose
Figure External Fast Interrupt Timing
IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD,
AA0463
Figure External Interrupt Timing (Negative Edge-Triggered)
DSP56367 Data Sheet
2-11
Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET
MODA, MODB, MODC, MODD, PINIT
IRQA, IRQB, IRQD,
AA0465
Figure Operating Mode Select Timing
IRQA
First Instruction Fetch
AA0466
A0-A17
Figure Recovery from Stop State Using IRQA Interrupt Service
IRQA A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure Recovery from Stop State Using IRQA Interrupt Service
2-12
DSP56367 Data Sheet
Specifications Reset, Stop, Mode Select, Interrupt Timing
A0-A17
Source Address
IRQA, IRQB, IRQC, IRQD, First Interrupt Instruction Execution
AA1104
Figure External Memory Access (DMA Source) Timing
DSP56367 Data Sheet
2-13
Specifications External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table SRAM Read Write Accesses
Characteristics Symbol Expression1 Address valid assertion pulse width tRC, 0.75 1.25 assertion pulse width 0.5) 22.7 Unit
69.3
Address valid assertion
19.3
deassertion address valid
1.25 2.25 0.75) 0.25)
11.0
Address valid input data valid
tAA,
13.3
assertion input data valid
10.0
deassertion data valid (data hold time) Address valid deassertion2
tOHZ 0.75) 0.25)
14.3
Data valid deassertion (data setup time)
(tDW)
2-14
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table SRAM Read Write Accesses (Continued)
Characteristics Symbol Expression1 Data hold time from deassertion 1.25 2.25 0.25 -0.25 0.25 1.25 2.25 Previous deassertion data active (write) 1.25 2.25 3.25 deassertion time 1.75 2.75 deassertion time Address valid assertion assertion pulse width 0.25) -4.0 Unit
13.0
assertion data active
-2.0
-5.4
deassertion data high impedance
15.2
11.0
17.7
14.3
12.7
19.3
11.0
DSP56367 Data Sheet
2-15
Specifications External Memory Expansion Port (Port
Table SRAM Read Write Accesses (Continued)
Characteristics Symbol Expression1 deassertion address valid 1.25 2.25 Note: setup before deassertion3 hold after deassertion 0.25 Unit
13.0
number wait states specified BCR. value given minimum given category. (For example, category timing specified wait states.) wait states minimum otherwise. Timings 100, guaranteed design, tested. case negation: timing relative deassertion edge were remain active
A0-A17 AA0-AA2 D0-D23 Data
AA0468
Figure SRAM Read Access
2-16
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port A0-A17 AA0-AA2 D0-D23 Data
Figure SRAM Write Access
DRAM Timing
selection guides provided Figure Figure should used primary selection only. Final selection should based timing provided following tables. example, selection guide suggests that wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (e.g., MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance.
DSP56367 Data Sheet
2-17
Specifications External Memory Expansion Port (Port DRAM Type (tRAC Note: This figure should primary selection. exact detailed timings following tables.
Chip Frequency (MHz)
Wait States Wait States
Wait States Wait States
AA047
Figure DRAM Page Mode Wait States Selection Guide
Table DRAM Page Mode Timings, Three Wait States
Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) tCAC tOFF 1.25 20.0 Unit
12.5
13.0 23.0
2-18
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Three Wait States (Continued)
Characteristics Symbol Expression Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] applicable BRW[1:0] BRW[1:0] tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH 0.75 0.25 tRSH tRHCP tCAS tCRP 21.0 41.0 16.0 Unit
4.75 6.75 1.25 0.75 2.25 3.75 3.25 1.25
41.5 61.5 11.0 21.0 36.0 18.3 30.5 33.2 28.2 21.0 31.0
18.0
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
DSP56367 Data Sheet
2-19
Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Three Wait States (Continued)
Characteristics Symbol Expression Note: Unit
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56367. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
Table DRAM Page Mode Timings, Four Wait States1,
Characteristics Symbol Expression
Unit
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses
50.0
2.75 3.75
45.0
21.8 31.8
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1-0] 01-Not applicable BRW[1-0] BRW[1-0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion
tCAC tOFF tRSH tRHCP tCAS tCRP
31.0 56.0 21.0
5.25 7.25 tASC tCAH tRAL tRCS 1.25
46.5 66.5 16.0 31.0 46.0
2-20
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Four Wait States1, (Continued)
Characteristics Symbol Expression4 Note: deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance tRCH tWCH tRWL tCWL tWCS tROH 0.75 0.25 1.25 3.25 4.75 3.75 1.25 3.25 28.3 40.5 43.2 33.2 31.0 41.0 Unit
26.8
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56367. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). expressions used calculate maximum minimum value listed, appropriate. BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
DSP56367 Data Sheet
2-21
Specifications External Memory Expansion Port (Port
A0-A17
Column Address Column Address
Last Column Address
D0-D23
Data Data Data AA0473
Figure DRAM Page Mode Write Accesses
2-22
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
A0-A17
Column Address
Column Address
Last Column Address
D0-D23
Data Data Data AA0474
Figure DRAM Page Mode Read Accesses
DSP56367 Data Sheet
2-23
Specifications External Memory Expansion Port (Port DRAM Type (tRAC
Note:This figure should primary selection. exact detailed timings following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
AA0475
Figure DRAM Out-of-Page Wait States Selection Guide
Table DRAM Out-of-Page Refresh Timings, Four Wait States
MHz4 Characteristics3 Symbol Expression Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion tRAC tCAC tOFF tRAS tRSH 1.75 3.25 1.75 2.75 1.25 250.0 83.5 158.5 83.5 130.0 55.0 67.5 166.7 54.3 104.3 54.3 84.2 34.2 42.5 MHz4 Unit
2-24
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Four Wait States (Continued)
MHz4 Characteristics3 Symbol Expression assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 2.75 1.25 1.25 2.25 1.75 1.75 1.25 0.25 1.75 3.25 0.75 0.25 4.75 4.25 2.25 1.75 3.25 1.25 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 83.5 158.5 96.0 71.2 33.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 37.2 77.0 64.5 192.5 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 54.3 104.3 62.7 46.2 21.3 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 24.7 52.0 43.7 125.8 MHz4 Unit
DSP56367 Data Sheet
2-25
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Four Wait States (Continued)
MHz4 Characteristics3 Symbol Expression Note: deassertion data high impedance 0.25 12.5 MHz4 Unit
number wait states page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (Figure 14).
2-26
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Eleven Wait States
Characteristics4 Symbol Expression3 Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 4.25 1.75 0.75 5.25 7.75 1.75 0.25 11.5 11.75 6.25 3.75 120.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 48.5 73.5 56.0 26.0 13.5 45.8 70.8 110.5 113.2 55.5 30.5 38.0 29.0 21.5 Unit
DSP56367 Data Sheet
2-27
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Eleven Wait States (Continued)
Characteristics4 Symbol Expression3 assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid tCWL tDHR tWCS tCSR tRPC tROH 10.25 5.75 5.25 7.75 2.75 11.5 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0 0.75 0.25 93.0 Unit
Note:
deassertion data valid4 assertion data active deassertion data high impedance
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56367. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table DRAM Out-of-Page Refresh Timings, Fifteen Wait States
Characteristics Symbol Expression3 Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width tRAC tCAC tOFF tRAS 8.25 4.75 6.25 9.75 160.0 58.5 93.5 76.8 41.8 49.3 Unit
2-28
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics Symbol Expression3 assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25 2.75 0.75 6.25 9.75 1.75 0.25 15.5 15.75 14.25 8.75 6.25 9.75 4.75 15.5 58.5 78.5 43.5 33.0 25.5 73.5 56.5 58.5 23.5 58.5 93.5 66.0 46.2 13.8 55.8 90.8 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 37.0 29.5 134.3 deassertion data valid5 assertion data active Unit
DSP56367 Data Sheet
2-29
Specifications External Memory Expansion Port (Port
Table DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics Symbol Expression3 Note: deassertion data high impedance 0.25 Unit
number wait states out-of-page access specified DCR. refresh period specified DCR. expression used compute maximum minimum value listed both expression includes Either tRCH tRRH must satisfied read cycles. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
2-30
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port A0-A17
Address Column Address
Data AA0476
D0-D23
Figure DRAM Out-of-Page Read Access
DSP56367 Data Sheet
2-31
Specifications External Memory Expansion Port (Port A0-A17 Address D0-D23 Data
AA0477
Column Address
Figure DRAM Out-of-Page Write Access
2-32
DSP56367 Data Sheet
Specifications External Memory Expansion Port (Port
AA0478
Figure DRAM Refresh Access
DSP56367 Data Sheet
2-33
Specifications External Memory Expansion Port (Port
Arbitration Timings
Table Asynchronous Arbitration Timing
Characteristics Expression
assertion window from input negation. Delay from assertion assertion
21.7
Note:
18.3
register must enter Asynchronous Arbitration mode Asynchronous Arbitration mode active, none timings Table required. order guarantee timings 250, 251, recommended assert inputs different 56300 devices same bus) overlap manner shown Figure
Figure Asynchronous Arbitration Timing
250+251
Figure Asynchronous Arbitration Timing
2-34
DSP56367 Data Sheet
Specifications Parallel Host Interface (HDI08) Timing
Background explanation Asynchronous Arbitration: asynchronous arbitration enabled internal synchronization circuits inputs. These synchronization circuits delay from external signal until exposed internal logic. result this delay, 56300 part assume mastership assert some time after negated. This reason timing 250. Once asserted, there synchronization delay from assertion time this assertion exposed other 56300 components which potential masters same bus. input asserted before that time, situation asserted, negated, cause another 56300 component assume mastership same time. Therefore some non-overlap period between input active another input active required. Timing ensures that such situation avoided.
PARALLEL HOST INTERFACE (HDI08) TIMING
Table Host Interface (HDI08) Timing
Characteristics3
Expression
Unit
Read data strobe assertion width HACK read assertion width
16.7
Read data strobe deassertion width HACK read deassertion width
Read data strobe deassertion width after "Last Data Register"
23.3
reads between consecutive CVR, ICR,
reads
13.2
HACK deassertion width after "Last Data Register" reads Write data strobe assertion width HACK write assertion width
Write data strobe deassertion width8 HACK write deassertion width after ICR, "Last Data Register" writes after writes, after TXH:TXM writes (with HBE=0), after TXL:TXM writes (with HBE=1)
23.3
16.5
assertion width deassertion data strobe assertion
Host data input setup time before write data strobe deassertion Host data input setup time before HACK write deassertion
DSP56367 Data Sheet
2-35
Specifications Parallel Host Interface (HDI08) Timing
Table Host Interface (HDI08) Timing (Continued)
Characteristics3
Expression
Unit
Host data input hold time after write data strobe deassertion Host data input hold time after HACK write deassertion Read data strobe assertion output data active from high impedance HACK read assertion output data active from high impedance
Read data strobe assertion output data valid HACK read assertion output data valid
24.2
Read data strobe deassertion output data high impedance HACK read deassertion output data high impedance Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion assertion read data strobe deassertion
+9.9
16.7
19.1
assertion write data strobe deassertion assertion output data valid hold time after data strobe deassertion
Address (AD7-AD0) setup time before deassertion (HMUX=1) Address (AD7-AD0) hold time after deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion Read Write
A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion
Delay from read data strobe deassertion host request assertion "Last Data Register" read
Delay from write data strobe deassertion host request assertion "Last Data Register" write
13.4
Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD
19.1
2-36
DSP56367 Data Sheet
Specifications Parallel Host Interface (HDI08) Timing
Table Host Interface (HDI08) Timing (Continued)
Characteristics3
Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD open drain Host Request)
Expression
300.0
Unit
19.1 19.1 32.5 29.2 20.2
Delay from HACK deassertion HOREQ assertion "Last Data Register" read
"Last Data Register" write other cases
Delay from HACK assertion HOREQ deassertion HROD Delay from HACK assertion HOREQ deassertion "Last Data Register" read write HROD open drain Host Request
300.0
Note:
Host Port Usage Considerations DSP56367 User's Manual. timing diagrams below, controls pins drawn active low. polarity programmable. -40°C +95°C, read data strobe dual data strobe mode single data strobe mode. "last data register" register address which last location read written data transfers. This timing applicable only read from "last data register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HOREQ signal. This timing applicable only consecutive reads from these registers executed. write data strobe dual data strobe mode single data strobe mode. data strobe host read (HRD) host write (HWR) dual data strobe mode host data strobe (HDS) single data strobe mode. host request HOREQ single host request mode HRRQ HTRQ double host request mode. this calculation, host request signal pulled resistor open-drain mode.
DSP56367 Data Sheet
2-37
Specifications Parallel Host Interface (HDI08) Timing
HACK HD7-HD0
HOREQ
AA1105
Figure Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2
HRD, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0484
Figure Read Timing Diagram, Non-Multiplexed
2-38
DSP56367 Data Sheet
Specifications Parallel Host Interface (HDI08) Timing HA0-HA2
HWR, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0485
Figure Write Timing Diagram, Non-Multiplexed
DSP56367 Data Sheet
2-39
Specifications Parallel Host Interface (HDI08) Timing HA8-HA10
HRD, HAD0-HAD7 Address HOREQ, HRRQ, HTRQ
AA0486
Data
Figure Read Timing Diagram, Multiplexed
2-40
DSP56367 Data Sheet
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HWR, HAD0-HAD7 Address Data HOREQ, HRRQ, HTRQ
AA0487
Figure Write Timing Diagram, Multiplexed
HOREQ (Output) HACK (Input) TXH/M/L Write H0-H7 (Input) Data Valid
Figure Host Write Timing Diagram
DSP56367 Data Sheet
2-41
Specifications Parallel Host Interface (HDI08) Timing
HOREQ (Output)
HACK (Input) H0-H7 (Output)
Read
Data Valid
Figure Host Read Timing Diagram
2-42
DSP56367 Data Sheet
Specifications Serial Host Interface Protocol Timing
SERIAL HOST INTERFACE PROTOCOL TIMING
Table Serial Host Interface Protocol Timing
Characteristics1 Tolerable spike width clock data Mode Filter Mode Bypassed Narrow Wide Minimum serial clock cycle tSPICC(min) Master Bypassed Narrow Wide Serial clock high period Master Bypassed Narrow Wide Slave Bypassed Narrow Wide Serial clock period Master Bypassed Narrow Wide Slave Bypassed Narrow Wide Serial clock rise/fall time Master Slave assertion first edge CPHA Slave Bypassed Narrow Wide Expression3 86.2 192.2 263.2 126.5 28.8 118.8 205.8 126.5 28.8 118.8 205.8 38.5 2000 Unit
CPHA
Slave
Bypassed Narrow Wide
DSP56367 Data Sheet
2-43
Specifications Serial Host Interface Protocol Timing
Table Serial Host Interface Protocol Timing (Continued)
Characteristics1 Last edge asserted Mode Slave Filter Mode Bypassed Narrow Wide Data input valid edge (data input set-up time) Master/ Slave Bypassed Narrow Wide last sampling edge data input valid Master/ Slave Bypassed Narrow Wide assertion data active deassertion data high impedance2 edge data valid (data delay time) Slave Slave Master/ Slave Bypassed Narrow Wide edge data valid (data hold time) Master/ Slave Bypassed Narrow Wide assertion data valid (CPHA First sampling edge HREQ output deassertion Slave Expression3 MAX{(20-TC), MAX{(40-TC), TC+5 TC+55 TC+106 TC+33 13.3 33.3 26.8 46.8 66.8 11.7 61.7 112.7 46.4 136.4 223.4 39.7 Unit
Slave
Bypassed Narrow Wide
46.8 96.8 152.8 46.8
46.8 136.8 233.8
Last sampling edge HREQ output deasserted (CPHA
Slave
Bypassed Narrow Wide
deassertion HREQ output deasserted (CPHA deassertion pulse width (CPHA
Slave
Slave
TC+6
12.7
2-44
DSP56367 Data Sheet
Specifications Serial Host Interface Protocol Timing
Table Serial Host Interface Protocol Timing (Continued)
Characteristics1 HREQ assertion first edge Mode Master Filter Mode Bypassed Expression3 tSPICC 97.8 Unit
Narrow
160.8
Wide
196.8
HREQ deassertion last sampling edge (HREQ set-up time) (CPHA First edge HREQ asserted (HREQ hold time)
Master
Master
Note:
-40°C +95°C, Periodically sampled, 100% tested timing values calculated based simulation data 150MHz. Tester restrictions limit testing lower clock frequencies.
DSP56367 Data Sheet
2-45
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid
Valid
MOSI (Output) HREQ (Input)
AA0271
Figure Master Timing (CPHA
2-46
DSP56367 Data Sheet
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure Master Timing (CPHA
DSP56367 Data Sheet
2-47
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input) HREQ (Output)
AA0273 Valid Valid
Figure Slave Timing (CPHA
2-48
DSP56367 Data Sheet
Specifications Serial Host Interface (SHI) Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input) HREQ (Output)
AA0274 Valid Valid
Figure Slave Timing (CPHA
SERIAL HOST INTERFACE (SHI) PROTOCOL TIMING
Table Protocol Timing
Standard I2C* Characteristics1,2,3 Tolerable spike width Filters bypassed Narrow filters enabled Wide filters enabled clock frequency clock cycle free time FSCL TSCL TBUF Symbol/ Expression Standard4,6 Fast-Mode55,6 Unit
DSP56367 Data Sheet
2-49
Specifications Serial Host Interface (SHI) Protocol Timing
Table Protocol Timing (Continued)
Standard I2C* Characteristics1,2,3 Start condition set-up time Start condition hold time period high period rise time fall time Data set-up time Data hold time clock frequency Filters bypassed Narrow filters enabled Wide filters enabled data valid Stop condition setup time HREQ deassertion last edge (HREQ set-up time) First sampling edge HREQ output deassertion TVD;DAT TSU;STO tSU;RQI TNG;RQO Symbol/ Expression TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT FDSP 10.6 11.8 13.1 28.5 39.7 61.0 Standard4,6 1000 Fast-Mode55,6 Unit
Filters bypassed Narrow filters enabled Wide filters enabled
Last edge HREQ output deasserted Filters bypassed Narrow filters enabled Wide filters enabled
TAS;RQO TI2CCP tHO;RQI TAS;RQI
HREQ assertion first edge Filters bypassed Narrow filters enabled Wide filters enabled
4327 4282 4238
Note:
First edge HREQ asserted (HREQ hold time.)
-40°C +95°C, Pull-up resistor: (min) kOhm Capacitive load: (max) recommended enable wide filters when operating Standard Mode. recommended enable narrow filters when operating Fast Mode. timing values derived from frequencies exceeding MHz.
2-50
DSP56367 Data Sheet
Specifications Serial Host Interface (SHI) Protocol Timing
Programming Serial Clock
programmed serial clock cycle, specified value HDM[7:0] bits HCKR (SHI clock control register).
expression
I2CCP (HDM[7:0] HRS)
where prescaler rate select bit. When cleared, fixed divide-by-eight prescaler operational. When set, prescaler bypassed. HDM[7:0] divider modulus select bits. divide ratio from (HDM[7:0] $FF) selected.
mode, user select value programmed serial clock cycle from
HDM[7:0]
4096 HDM[7:0]
programmed serial clock cycle rise time (TR), filters selected should chosen order achieve desired serial clock cycle (TSCL), shown Table
Table Serial Clock Cycle (TSCL) Generated Master
Filters bypassed Narrow filters enabled Wide filters enabled
TI2CCP 45ns TI2CCP 135ns TI2CCP 223ns
EXAMPLE: clock frequency (i.e. 10ns), operating standard mode environment (FSCL (i.e. TSCL 10µs), 1000ns), with wide filters enabled:
TI2CCP 10µs 223ns 1000ns 8752ns
Choosing gives
HDM[7:0] 8752ns 10ns 53.7
Thus HDM[7:0] value should programmed (=54).
DSP56367 Data Sheet
2-51
Specifications Serial Host Interface (SHI) Protocol Timing
resulting will
I2CCP (HDM[7:0] I2CCP [10ns I2CCP [10ns 8640ns
Stop
Start
Stop
HREQ
AA0275
Figure Timing
2-52
DSP56367 Data Sheet
Specifications Enhanced Serial Audio Interface Timing
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table Enhanced Serial Audio Interface Timing
Characteristics1, Clock cycle5 Symbol tSSICC Expression3 TXC:max[3*tc; t454] Clock high period internal clock external clock 10.0 10.0 26.8 20.1 26.5 Condition4 Unit
10.0
Clock period internal clock external clock
10.0 19.0 23.0 23.0 19.0
37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0
rising edge (bl) high
rising edge (bl)
rising edge (wr) high6
rising edge (wr) low6
rising edge (wl) high
rising edge (wl)
Data setup time before (SCK synchronous mode) falling edge Data hold time after falling edge input (bl, high before falling edge
input (wl) high before falling edge input hold time after falling edge Flags input setup before falling edge
DSP56367 Data Sheet
2-53
Specifications Enhanced Serial Audio Interface Timing
Table Enhanced Serial Audio Interface Timing (Continued)
Characteristics1, Flags input hold time after falling edge rising edge (bl) high Symbol Expression3 21.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 26.5 21.0 31.0 16.0 34.0 20.0 27.0 Condition4 Unit
rising edge (bl)
rising edge (wr) high6
rising edge (wr) low6
rising edge (wl) high
rising edge (wl)
rising edge data enable from high impedance rising edge transmitter drive enable assertion rising edge data valid
21.0
rising edge data high impedance7
rising edge transmitter drive enable deassertion7
input (bl, setup time before falling edge6
input (wl) data enable from high impedance input (wl) transmitter drive enable assertion input (wl) setup time before falling edge input hold time after falling edge Flag output valid after rising edge
31.0
21.0 40.0
32.0 18.0
HCKR/HCKT clock cycle
2-54
DSP56367 Data Sheet
Specifications Enhanced Serial Audio Interface Timing
Table Enhanced Serial Audio Interface Timing (Continued)
Note: Characteristics1, HCKT input rising edge output HCKR input rising edge output Symbol Expression3 27.5 27.5 Condition4 Unit
-40°C +95°C, internal clock external clock internal clock, asynchronous mode (asynchronous implies that different clocks) internal clock, synchronous mode (synchronous implies that same clock) length word length word length relative TXC(SCKT pin) transmit clock RXC(SCKR pin) receive clock FST(FST pin) transmit frame sync FSR(FSR pin) receive frame sync HCKT(HCKT pin) transmit high frequency clock HCKR(HCKR pin) receive high frequency clock internal clock, external clock cycle defined Icyc ESAI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same length frame sync signal), until before last clock first word frame. Periodically sampled 100% tested timing values calculated based simulation data 150MHz. Tester restrictions limit ESAI testing lower clock frequencies. ESAI_1 specs match those ESAI_0.
DSP56367 Data Sheet
2-55
Specifications Enhanced Serial Audio Interface Timing
(Input/ Output)
(Bit)
(Word)
First Last
Data
Transmitter Drive Enable
(Bit) (Word)
Note
Flags Note: network mode, output flag transitions occur start each time slot within frame. normal mode, output flag state asserted entire frame period.
AA0490
Figure ESAI Transmitter Timing
2-56
DSP56367 Data Sheet
Specifications Enhanced Serial Audio Interface Timing (Input/Output) (Bit) (Word) Data (Bit) (Word) Flags
AA0491
First
Last
Figure ESAI Receiver Timing
DSP56367 Data Sheet
2-57
Specifications Enhanced Serial Audio Interface Timing
HCKT
SCKT(output)
Figure ESAI HCKT Timing
HCKR
SCKR (output)
Figure ESAI HCKR Timing
2-58
DSP56367 Data Sheet
Specifications Digital Audio Transmitter Timing
DIGITAL AUDIO TRANSMITTER TIMING
Table Digital Audio Transmitter Timing
Characteristic Expression
frequency (see note) period high duration duration rising edge valid 13.4
Unit
10.0
Note:
order assure proper operation DAX, frequency should less than DSP56367 internal clock frequency. example, DSP56367 running internally, frequency should less than MHz.
AA1280
Figure Digital Audio Transmitter Timing
TIMER TIMING
Table Timer Timing
Characteristics Expression
15.4 15.4
High
DSP56367 Data Sheet
2-59
Specifications Timer Timing
Table Timer Timing (Continued)
Characteristics Expression
Note:
0.09 -40°C +95°C,
AA0492
Figure Timer Event Input Restrictions
2-60
DSP56367 Data Sheet
Specifications GPIO Timing
GPIO TIMING
Table GPIO Timing
Characteristics1 EXTAL edge GPIO valid (GPIO delay time) EXTAL edge GPIO valid (GPIO hold time) GPIO valid EXTAL edge (GPIO set-up time) EXTAL edge GPIO valid (GPIO hold time) Fetch EXTAL edge before GPIO change GPIO rise time GPIO fall time 0.09 -40°C +95°C, Valid only when enabled with multiplication factor equal one. 6.75 TC-1.8 Expression
4902 4942 Note:
10.2 43.4
32.8
EXTAL (Input) GPIO (Output) GPIO (Input) Valid
A0-A17 Fetch instruction MOVE X0,X:(R0); contains value GPIO contains address GPIO data register. GPIO (Output)
Figure GPIO Timing
DSP56367 Data Sheet
2-61
Specifications JTAG Timing
JTAG TIMING
Table JTAG Timing
frequencies Characteristics Note: frequency operation (1/(TC maximum MHz) cycle time Crystal mode clock pulse width measured rise fall times Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance 45.0 20.0 24.0 25.0 22.0 40.0 40.0 44.0 44.0 Unit
0.09 -40°C +95°C, timings apply OnCE module data transfers because uses JTAG port interface.
(Input)
AA0496
Figure Test Clock Input Timing Diagram
2-62
DSP56367 Data Sheet
Specifications JTAG Timing
(Input)
Data Inputs Data Outputs Data Outputs Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
AA0497
Figure Boundary Scan (JTAG) Timing Diagram
(Input) (Input)
Input Data Valid
(Output) (Output) (Output)
Output Data Valid
Output Data Valid
AA0498
Figure Test Access Port Timing Diagram
DSP56367 Data Sheet
2-63
Specifications JTAG Timing
2-64
DSP56367 Data Sheet
SECTION PACKAGING
PIN-OUT PACKAGE INFORMATION
This section provides information about available package this product, including diagrams package pinouts tables describing signals described Section allocated package. DSP56367 available 144-pin LQFP package. Table 1and Table show pin/name assignments packages.
LQFP Package Description
view 144-pin LQFP package shown Figure with pin-outs. package drawing shown Figure
DSP56367 Data Sheet
Packaging Pin-out Package Information
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
MISO/SDA MOSI/HA0 SDO4_1/SDI1_1 MODA/IRQA# MODB/IRQB# MODCIRQC# MODD/IRQD# GNDD VCCD GNDQ VCCQL GNDD VCCD GNDD VCCD
GNDD VCCD GNDA VCCQH VCCQL GNDQ GNDA VCCA GNDA VCCA GNDA VCCA
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# VCCC GNDC
Figure 144-pin package
DSP56367 Data Sheet
Packaging Pin-out Package Information
Table Signal Identification Name
Signal Name
Signal Name
Signal Name
GNDS GNDS HA8/HA1
Signal Name
SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/ SDO2_1/SDI3_1 SDO3/SDI2/ SDO3_1/SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TIO0 VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD VCCD VCCH VCCQH VCCQH VCCQH VCCQL
CAS#
EXTAL FSR_1 FST_1 GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD
HA9/HA2 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HA0 HCKR HCKT HCS/HA10 HDS/HWR HOREQ/HTRQ HREQ# HRW/HRD MODA/IRQA# MODB/IRQB# MODC/IRQC# MODD/IRQD# MISO/SDA MOSI/HA0 PCAP PINIT/NMI#
DSP56367 Data Sheet
Packaging Pin-out Package Information
Table Signal Identification Name (Continued)
Signal Name
Signal Name
GNDD GNDH GNDP GNDQ GNDQ GNDQ GNDQ
Signal Name
RESET# SCK/SCL SCKR SCKR_1 SCKT SCKT_1
Signal Name
VCCQL VCCQL VCCQL VCCP VCCS VCCS
DSP56367 Data Sheet
Packaging Pin-out Package Information
Table
Signal Identification Number
Signal Name
VCCA GNDA VCCA GNDA VCCA GNDA GNDQ VCCQL VCCQH GNDA VCCD GNDD
Signal Name
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/ SDI3_1 SDO3/SDI2/SDO3_1/ SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
Signal Name
Signal Name
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# VCCC GNDC
VCCD GNDD VCCD GNDD VCCQL GNDQ VCCD GNDD MODD/IRQD# MODC/IRQC# MODB/IRQB# MODA/IRQA# SDO4_1/SDI1_1 MOSI/HA0 MISO/SDA
DSP56367 Data Sheet
Packaging Pin-out Package Information
LQFP Package Mechanical Drawing
DSP56367 Data Sheet
Packaging Pin-out Package Information
Figure DSP56367 144-pin LQFP Package
Figure DSP56367 144-pin LQFP Package
DSP56367 Data Sheet
Packaging Pin-out Package Information
Figure DSP56367 144-pin LQFP Package
DSP56367 Data Sheet
Packaging Ordering Drawings
ORDERING DRAWINGS
detailed package drawing available Motorola page package 918-03 search.
DSP56367 Data Sheet
Packaging Ordering Drawings
3-10
DSP56367 Data Sheet
SECTION DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
estimation chip junction temperature, obtained from following equation:
Where:
ambient temperature RqJA package junction-to-ambient thermal resistance °C/W power dissipation package
Historically, thermal resistance been expressed junction-to-case thermal resistance case-to-ambient thermal resistance.
Where:
package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W
device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement printed circuit board (PCB), otherwise change thermal dissipation capability area surrounding device PCB. This model most useful ceramic packages with heat sinks; some heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through PCB, analysis device thermal performance need additional modeling capability system level thermal simulation tool. thermal performance plastic packages more dependent temperature which package mounted. Again, estimations obtained from satisfactorily answer whether thermal performance adequate, system level model appropriate. complicating factor existence three common ways determining junction-to-case thermal resistance plastic packages.
DSP56367 Data Sheet
Design Considerations Electrical Design Considerations
minimize temperature variation across surface, thermal resistance measured from junction outside surface package (case) closest chip mounting area when that surface proper heat sink. define value approximately equal junction-to-board thermal resistance, thermal resistance measured from junction where leads attached case. temperature package case (TT) determined thermocouple, thermal resistance computed using value obtained equation TT)/PD.
noted above, junction-to-case thermal resistances quoted this data sheet determined using first definition. From practical standpoint, that value also suitable determining junction temperature from case thermocouple reading forced convection environments. natural convection, using junction-to-case thermal resistance estimate junction temperature from thermocouple reading case package will estimate junction temperature slightly hotter than actual temperature. Hence, thermal metric, thermal characterization parameter been defined TT)/PD. This value gives better estimate junction temperature natural convection when using surface temperature package. Remember that surface temperature readings packages subject significant errors caused inadequate attachment sensor surface errors caused heat loss sensor. recommended technique attach 40-gauge thermocouple wire bead center package with thermally conductive epoxy.
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor ohm.
following list recommendations assure correct operation:
DSP56367 Data Sheet
Design Considerations Power Consumption Considerations
Provide low-impedance path from board power supply each from board ground each pin. least 0.01-0.1 bypass capacitors positioned close possible four sides package connect power source GND. Ensure that capacitor leads associated printed circuit traces that connect chip pins less than (0.5 inch) capacitor lead. least four-layer with inner layers GND. Because output signals have fast rise fall times, trace lengths should minimal. This recommendation particularly applies address data buses well IRQA, IRQB, IRQD, pins. Maximum trace lengths order inches) recommended. Consider device loads well parasitic capacitance traces when calculating capacitance. This especially critical systems with higher capacitive loads that could create higher transient currents circuits. inputs must terminated (i.e., allowed float) using CMOS levels, except three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care minimize noise levels VCCP GNDP pins. multiple DSP56367 devices same board, check cross-talk excessive spikes supplies synchronous operation devices. RESET must asserted when chip powered stable EXTAL signal must supplied before deassertion RESET. power-up, ensure that voltage difference between tolerant pins chip never exceeds voltage.
POWER CONSUMPTION CONSIDERATIONS
Power dissipation issue portable applications. Some factors which affect current consumption described this section. Most current consumed CMOS devices alternating current (ac), which charging discharging capacitances pins internal nodes. Current consumption described following formula:
where
node/pin capacitance voltage swing frequency node/pin toggle
DSP56367 Data Sheet
Design Considerations Power Consumption Considerations
Table Power Consumption Example
Port address loaded with capacitance, operating with clock, toggling maximum possible rate MHz), current consumption
8.25mA
maximum internal current (ICCImax) value reflects typical possible switching internal buses best-case operation conditions, which necessarily real application case. typical internal current (ICCItyp) value reflects average switching internal buses typical operating conditions. applications that require very current consumption, following: when accessing external memory. Minimize external memory accesses internal memory accesses. Minimize number pins that switching. Minimize capacitive load pins. Connect unused inputs pull-up pull-down resistors. Disable unused peripherals.
evaluate power consumption current MIPS measurement methodology minimize specific board effects (i.e., compensate measured board current caused DSP). benchmark power consumption test algorithm listed Appendix page test algorithm, specific test current measurements, following equation derive current MIPS value.
MIPS typF2 typF1
where
ItypF2 ItypF1
current current high frequency (any specified operating frequency) frequency (any specified operating frequency lower than
Note:
should significantly less than example, could could MHz. degree difference between determines amount precision with which current rating determined application.
DSP56367 Data Sheet
Design Considerations Performance Issues
PERFORMANCE ISSUES
following explanations should considered general observations expected behavior. There testing that verifies these exact numbers. These observations were measured limited number parts were verified over entire temperature voltage ranges.
Input (EXTAL) Jitter Requirements
allowed jitter frequency EXTAL 0.5%. rate change frequency EXTAL slow (i.e., does jump between minimum maximum values cycle) frequency jitter fast (i.e., does stay extreme value long time), then allowed jitter phase frequency jitter performance results only valid input jitter less than prescribed values.
DSP56367 Data Sheet
Design Considerations Performance Issues
DSP56367 Data Sheet
APPENDIX POWER CONSUMPTION BENCHMARK
following benchmark program permits evaluation power usage test situation. enables PLL, disables external clock, uses repeated multiply-accumulate instructions with synthetic application data emulate intensive sustained operation.
CHECKS Typical Power Consumption
page 200,55,0,0,0 nolist I_VEC START INT_PROG INT_XDAT INT_YDAT $000000 $8000 $100 Interrupt vectors program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list movep #$0123FF,x:M_BCR; BCR: Area (SRAM) Default: (SRAM) movep #$0d0000,x:M_PCTL XTAL disable enable CLKOUT disable Load program move #INT_PROG,r0 move #PROG_START,r1 move p:(r1)+,x0 move x0,p:(r0)+ PLOAD_LOOP Load X-data move #INT_XDAT,r0 P:START
DSP56367 Data Sheet
Power Consumption Benchmark
move move move XLOAD_LOOP Load Y-data move move move move YLOAD_LOOP PROG_START move move move move move move move move bset move PROG_END
#XDAT_START,r1 p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr #60,_end x0,y0,a x1,y1,a x0,y0,a x1,y1,a b1,x:$ff
x:(r0)+,x1 x:(r0)+,x0 x:(r0)+,x1
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
_end
XDAT_START
$262EB9
DSP56367 Data Sheet
Power Consumption Benchmark
$86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A
DSP56367 Data Sheet
Power Consumption Benchmark
XDAT_END YDAT_START
$EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540
$5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4
DSP56367 Data Sheet
Power Consumption Benchmark
YDAT_END
$87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
DSP56367 Data Sheet
Power Consumption Benchmark
DSP56367 Data Sheet
APPENDIX IBIS MODEL
[IBIS ver] [File name] 56367.ibs [File Rev] [Date] 29/6/2000 [Component] 56367 [Manufacturer] Motorola [Package] |variable R_pkg L_pkg 2.5nH C_pkg 1.3pF
1.1nH 1.2pF
4.3nH 1.4pF
[Pin]signal_name model_name ip5b_io ip5b_io hreq_ ip5b_io sdo0 ip5b_io sdo1 ip5b_io sdoi23 ip5b_io sdoi32 ip5b_io svcc power sgnd sdoi41 ip5b_io sdoi50 ip5b_io ip5b_io ip5b_io sckt ip5b_io sckr ip5b_io hsckt ip5b_io hsckr ip5b_io qvccl power qvcch power hp12 ip5b_io hp11 ip5b_io hp15 ip5b_io hp14 ip5b_io svcc power sgnd ip5b_io ip5b_io ip5b_io hp13 ip5b_io hp10 ip5b_io
DSP56367 Data Sheet
IBIS Model
svcc sgnd ires_ pvcc pcap pgnd sdo5 qvcch fst_1 cas_ sck_1 qgnd cxtldis_ qvccl cvcc cgnd fsr_1 sckr1 nmi_ cvcc cgnd eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 avcc agnd eab6 eab7 eab8
ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io power ip5b_io ip5b_io ip5b_io ip5b_io ip5b_i power power ipbw_io power ipbw_io icbc_o icbc_o ipbw_io iexlh_i power power ipbw_io ipbw_io ipbw_i icbc_o icbc_o icbc_o power icbc_o icbc_o icbc_o icbc_o icbc_o ic
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