L64777 chip implements modulator that digital video broadcasting (DVB)

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L64777 chip implements modulator that digital video broadcasting (DVB)

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L64777 Modulator
L64777 chip implements modulator that digital video broadcasting (DVB)-compliant, described document 429. input MPEG-2 system layer-compliant transport stream either parallel byte-wide serial format. chip contains digital signal processing functions, digital-to-analog converters, sampling clock circuitry that generates quadrature amplitude modulation (QAM)modulated output signal baseband. Users configure device means serial interface. Figure shows block diagram typical CATV transmitter using L64777 Modulator. Figure
Video Source
CATV Transmitter Block Diagram with L64777
MPEG-2 Transport Decoder Modulator Mixer Power Amplifier Source CATV
Satellite Receiver Antenna
Modulator
Mixer Power Amplifier Source
CATV
Introduction
L64777 chip design based existing Logic L64767 device includes following major enhancements:
internal digital-to-analog converters generate in-phase quadrature baseband signals.
June 2000
Copyright 2000 Logic Corporation. rights reserved.
on-chip voltage-controlled oscillator improves symbol rate support most frequently used application ranges. serial interface replaces eight-bit microprocessor interface. digital numerically controlled oscillator (NCO) interpolation mode support operation with L64724 device.
modulator intended follow either MPEG transport stream source (for example, transport multiplexer) satellite receiver, such Logic L64724 (see Figure processes MPEG-2 system-compliant frames input. program sync word block length, chip reinsert sync information. device handles MPEG-specific transport-packet error indication (TEI) internally. Figure L64777 Operating Environment
Analog Modulated Components
MPEG transport MPEG Transport Stream (Digital) QPSK Satellite Receiver Transmission Network L64777 Modulator
Mixer
Cable Network
Features Benefits
following partial list features benefits L64777.
standard 429-compliant modulation operation Highly integrated global synchronization clock control On-chip support symbol rates Msymbols/s Digital interpolation mode support operation with L64724 Four-fold Nyquist filter oversampling Maskable interrupts error conditions Individual module bypass configuration modes baseband outputs both digital analog formats
L64777 Modulator
I2C-compatible serial interface control, setup, monitoring various chip parameters User-controllable input synchronization schemes 128, modes Reed-Solomon encoder Frame sync byte reinsertion Input jitter handling Reed-Solomon insertion 128-word circular FIFO buffer IEEE 1149.1 JTAG interface testing Mbytes/s parallel data input Mbits/s serial data input 11.25 Mbaud operation mode operation Easy interface most input sources ambient operation without special cooling devices Unconstrained serial mode allow modulation non-MPEG data stream
Architectural Overview
L64777 implements modulator processing chain defined 429. This processing chain illustrated Figure Figure 429-Compliant Modulation Operation
Energy Dispersal (204,188) Encoder Convol. Interleaver Byte m-tuple conversion Differential Encoder Mapping Square Root Nyquist Filter
Figure block diagram L64777 architecture. input clock drives only input synchronizing stage. OCLK, which four times symbol rate, base residual processing.
L64777 Modulator
numerically controlled oscillator (NCO) module allows L64777 interface with Logic L64724. this case, chip must receive L64724 PCLK clock; thus, byte_clock output from L64724 must applied ICLK. This assumes PCLK generated byte clock. mapping supports 128, QAM. input device MPEG-2 compliant transport stream; output consists baseband signals
L64777 Modulator
Figure
PCLK divided ICLK NCO* freq compare Interpolator*
Data Path
Data Sync Error flag Reinsertion Energy Dispersal (204,188) Encoder Convol. Interleaver Byte m-tuple Diff. Encoder Mapping Square Root Nyquist Filter
ICLK
Input Sync Stage
Circular Buffer FIFO Word
L64777 Modulator
Global Control Synchronization Start/Stop Signals Generation OCLK OCLK SCAN chain JTAG Test RAMbist Serial Microprocessor Interface
Symbol Clock Generation (incl. Phase Freq. Comp.)
Only used Mode
Modes
Connecting L64777 satellite receiver Logic satellite decoder chipset requires circuits lock input output clocks. modes achieve this:
Mode uses phase/frequency detector dividers L64777 accept external VCO. Mode connects PCLK output L64724 L64734 L64777 PCLK clock input, connects byte clock output ICLK input L64777. This also called Numerically Controlled Oscillator (NCO) mode operation. This mode dedicated connection L64724.
Mode Figure shows phase frequency detection external voltage-controlled oscillator (VCO) loop. Choose between frequency phase detection through microprocessor interface. Figure Phase Frequency Detection with External
FREQ_PHASE_COMP (From Microprocessor)
Phase Detect Load Value Frequency Detect CNT_I
current PLL_CS
CNT_O
Load Value
ICLK
OCLK From
Prescalers (CNT_I) divider (CNT_O) feedback loop generate internal operating clock (OCLK). Program 15-bit prescalers through microprocessor interface, selecting values CNT_I CNT_O that minimize CNT_O reach required ratio.
L64777 Modulator
Mode Mode PCLK input provides external clock. L64777 uses internal lock transport byte clock, provided ICLK. chip generates OCLK internally. Select PCLK least twice frequency internal OCLK. Consecutive sync blocks have length between them. Thus, L64777 convert input block block with insertion, long size 128-byte circular input buffer sufficient insert gaps cope with possible jitter. encoder with 16-parity insertion, L64777 selects size circular input buffer with sufficient margin. When operating public synchronous networks (such synchronous digital hierarchy, SDH, plesiochronous digital hierarchy, PDH), system designer must consider possible jitter input network. design L64777 permits short-term deviations input-to-output frequency bytes before FIFO overrun condition occurs. This sufficient operations networks. Anetworks, must prebuffer input data continuous frame rate chip input. high input jitter occurs over Awithout prebuffer, whole regulation input-to-output frame rate fails. must design size prebuffer according maximum jitter expected over asynchronous transfer mode (ATM) network.
following subsections describe input output L64777. Input Modulator accepts serial input data maximum clock frequency ICLK pin. Byte-Parallel Input mode (Parallel mode), maximum frequency ICLK MHz. Output Signals L64777 outputs components signal separate analog output interfaces. output interface contains internal 10-bit digital-to-analog converters (see Figure
L64777 Modulator
Figure
Analog Output Interface Diagram
VDDX1 AVDD1/COMP1
Filter Output 10-Bit
Differential Output QAM_I, QAM_In AVSS1 Functional Test (Test mode selected using mode pins) VREF1 VREF2 VDDX2 AVDD2/COMP2
10-Bit Filter Output
Differential Output QAM_Q, QAM_Qn
AVSS2
On-Chip
Off-Chip
differential outputs terminate externally (the external components must provide termination both differential lines, achieves maximum linearity differential mode). L64777 component outputs available 10-bit digital format. related clock depends mode: OCLK used Mode PCLK used Mode output format programmed either two's complement, sign magnitude representation. analog Q-modulated output signals sampling rate OCLK, which four times symbol rate. input digital-to-analog conversion available also digital format DIG_I DIG_Q pins.
L64777 Modulator
Control Interface
external uses L64777 serial control interface control setup programmable parameters chip. This interface slave type only, connected same serial Logic L64724.
Serial Microprocessor Interface
bidirectional microprocessor interface allows write confidence read-back internal registers. interaction during operation required with microprocessor, registers must configured after RESET guarantee proper operation device. default setup that requires microprocessor download built QAM.
Input Synchronization
L64777 transport interface reads data stream from transport source, identifies position synchronization bytes, strips invalid data. transport interface operate either Parallel Serial mode. L64777 synchronize transport interface ways. both modes, works synchronously with ICLK reads signals, including input data, raising edge ICLK.
external synchronization mode, transport interface specifies position external sync byte asserting FSTARTIN HIGH during sync byte input. serial mode, interface must assert signal HIGH during first (MSB) input stream. internal synchronization mode, L64777 does require block start indication finds position programmed sync byte automatically.
L64777 Modulator
Sync Acquisition Phase sync acquisition phase, number sync detections required sync loss programmable from designation number track steps. After error-free consecutive detections sync byte correct locations, L64777 declares synchronization; mismatch occurs, goes back search state. Validating detection sync word three times ensures probability false alarm equal (2-8)3 6*10-8. Validating detection sync word five times insures probability false alarm equal (2-8)5 9*10-13. Sync Tracking Phase sync tracking phase checks detection correct location (i.e., every bytes). mismatches tolerated, last mismatch L64777 declares loss-of-sync goes back state look synchronization.
FIFO Clock Conversion
L64777 uses dual-ported implement circular buffer FIFO function. circular buffer write pointer driven ICLK read pointer driven Symbol clock, OCLK/4. device does prevent collisions pointers; rather, PLL-VCO follow-up time proper initial setup pointer distance must guarantee this. FIFO initialization, L64777 loads user-programmable pointer distance cycles (the FIFO delay value Register Group into read address pointer (after each microprocessor delay register access) sets write address pointer zero (see Figure After this initialization, both pointers free, OCLK ICLK frequency relationship determines read write pointers advance. allow outside watching asynchronous pointers, alarm comparator indicates when both pointers equal. Because both counters Gray Code counters which changes occur only bit) spikes glitches asynchronous signals minimized.
L64777 Modulator
Figure
FIFO Pointer Concept
Read Pointer
Circular Buffer Words
Zero
When specifying microprocessor download value read pointer initialization, must Gray Code. write pointer also Gray Code counter-driven; initializes zero when read counter loaded. Properly programmed delay values Gray Code guarantee that read pointer directly opposite write pointer most time; this increases system immunity against frequency swings, which might occur during phases unstable input signal. Smaller distances also reduce system delay.
Sync/EF Reinsertion Unit
following subsections describe Sync/EF modes, error flag insertion, scrambler. Sync Insertion Mode Sync/EF unit inserts sync words that mode programmed. Sync insertion useful work against errors sync bytes, even sync already inserted stream. bitstream contains sync bytes that device uses synchronization, regenerated sync bytes conceal single errors synchronization pattern. Error Flag Insertion next processing task error flag handling MPEG-2 transport packets. ERRORIN indicates decoder error first byte frame, L64777 sets TRANSPORT_ERROR_INDICATOR MPEG-2 packet. This second byte packet. there error indication, L64777 passes TRANSPORT_ERROR_INDICATOR transparently.
L64777 Modulator
Energy Dispersal (Scrambler) Unit function Scrambler specified serial domain Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems. energy dispersal module (scrambler) operates Parallel mode based algorithm serial domain. scrambler block consists major modules: generate pseudo-random binary sequence (PRBS) that modifies incoming data stream, other control module that properly aligns data with PRBS.
Reed-Solomon Encoder
Reed-Solomon (RS) error correction codes systematic operate bytes rather than single-bit data streams. codes expressed convention numbers, first indicating total code word length (N), second indicating number message bytes (K). difference between these numbers number check bytes. error-correcting power code related number redundant check symbols code words. general, code with check symbols code word correct byte errors code word. Higher redundancy allows more errors corrected. Forward Error Correction (FEC) requires encoder that appends redundant check information message before transmission. bytes with indeterminate number bits referred symbols. message symbols following redundant check symbols make code words. check symbols redundant because they derived from message appended message. Check symbols also referred "redundant check bytes," sometimes "correction bytes." large number check symbols allows decoder correct large number transmission errors. redundant check symbols message allow decoder receiving transmission line detect transmission errors reconstruct original message content.
L64777 Modulator
After generating code word, encoder transmits decoder. decoder compares bitstream message data encoding check bytes detect transmission errors. L64777 reconstruct original message precisely from check symbols, long code word more than byte errors, where number redundant check bytes. Error Handling Correction error occurs when transmitted received vice versa. byte error occurs when more bits byte have errors. example, byte with only error counted byte error, byte with errors (all bits inverted) also counted byte error. long code word more than byte errors, decoder corrects errors. achieve encoding lowest possible gate count power consumption, check byte parameters encoder L64777 fixed according standard. When encoder switched off, data feeds through without check-word insertion internal delay clock cycles.
Convolutional Interleaver
convolutional interleaver rearranges ordering sequence symbols deterministic manner. periodic interleaver following characteristics:
minimum separation interleaver output symbols symbols that separated less than symbols interleaver input. burst errors inserted channel results single errors deinterleaver output.
scheme also referred convolutional interleaver/ deinterleaver (based Forney approach). L64777 interleaver performs periodic interleaving with fixed parameters: desired interleaving depth, defined
L64777 Modulator
values interleaver L64777 are: 204, switch interleaver. fully transparent with intrinsic delay three clock cycles. main modules configured RAM-based delay lines implement proper delay individual data bytes, controller handle generate strobes needed subsequent modules data path.
Bytes M-tuples Converter
This unit cuts down bytes slices bits. programming parameter, mSize, must order oldest byte first. Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems detailed specification. When cutting six-bit symbols, cuts three bytes into four symbols. case four-bit symbols trivial (eight bits split into sets four bits each).
Differential Encoder mapping
This block performs differential encoding mapping QAM, specified Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems, baseline document, extensions. mapping taken from document 1190. encoder performs differential encoding most significant bits each symbol.
Square Root Nyquist Filter
This pulse-shaper module implements programmable square-root raised cosine filtering function with default roll-off factor. precision internal Nyquist filter computations, width output data bus, sufficient modulations 256. filter operates four times oversampling rate. Each branches filter, realized polyphase structures. Each filter consists four filter branches, which compute 1-phase filter results symbol rate. Thus, L64777 Nyquist filter
L64777 Modulator
module generates desired pulse shape combining outputs four identical filter branches oversampling factor four, filter executes above sequence four times symbol rate mode).
Global Control Module
L64777 interface supports serial parallel input modes input interface. global control generates clocking input output interfaces; also controls data path. contains necessary logic chain processing units together. global control manages output data stream that continuous gaps between symbols), assuming that incoming data rate constant average). achieve this, must derive output clock OCLK from input transport stream rate. module consists independent clock dividers ICLK OCLK. dividers 15-bit binary counters that have count sequence length that programmable. default values written external microprocessor are: OCLK divider ICLK divider QAM.
Interpolator
Mode interpolator retimes output samples that Nyquist filter calculated. interpolator clocked with PCLK generates output samples PCLK sampling grid. interpolator takes required retiming information from NCO. PCLK least twice frequency original OCLK obtained formula Modes square root raised cosine filter also compensates sin(x)/x frequency characteristic digital-to-analog converter with faster sampling grid.
Serial Microprocessor Interface
external microprocessor controls mode operation, QAM. also controls mode input synchronization (that whether lock synchronization sync bytes input pulses).
L64777 Modulator
microprocessor interface downloads filter coefficients delay value proper FIFO initialization. microprocessor interface uses I2C-compatible serial control protocol. interface slave-only master serial bus. base address component composed fixed five-bit address selectable bits, which through SB_BASE[1:0].
Test Unit
L64777 supports:
Full scan test BIST RAMs JTAG boundary scan Digital-to-analog conversion test tests
Signals
Figure shows L64777 interface signals their respective groupings. Within each category, signals described alphabetical order signal mnemonic.
L64777 Modulator
Figure
Logic Symbol L64777
Serial Microprocessor Interface SB_BASE[1:0]
INT_n
DIN[7:0] DVALIDIN ERRORIN MPEG FSTARTIN ICLK SCLK SSTARTIN L64777 Modulator
AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 IREF1 IREF2 QAM_I QAM_IN QAM_Q QAM_QN VDDX_I VDDX_Q VREF_I VREF_Q DIG_I[9:0] DIG_Q[9:0] FIFOALARM FIRSTOUT FSTARTOUT SYNCOK TESTPINS[11:0]
Analog
Status Information Test
OCLK
PLL_MODE[1:0]
RESET_n
PCLK
Control Signals
External Signals
L64777 Modulator
PLL_OUT_CS
MPEG Transport Stream Multiplexer Signals DIN[7:0] Modulator Parallel/Serial Data Input Serial data enters L64777 DIN[0]; parallel data enters DIN[7:0]. modulator samples DIN[7:0] positive edge ICLK. DIN[7:0] input accepts data with number invalid bits between. modulator disregards invalid bits bytes does take them into input FIFO. Clock Enable Input Input When DVALIDIN active (HIGH), L64777 accepts data from DIN[7:0] continuous basis. When DVALIDIN LOW, data input internal FIFO internal data processing stop, encoder does accept input from DIN[7:0] pins. DVALIDIN functions independently modulator. Error Detection Flag Input ERRORIN asserted flag uncorrectable errors. L64777 checks ERRORIN status first frame; then, required (HIGH error bit), copies value that MPEG error-indication bit. External Sync Input Input FSTARTIN asserted mark beginning MPEG transport packet hardwired signal. incoming bitstream contains unique sync words, this pulse must applied L64777. L64777 forces synchronization with FSTARTIN pulses into chip; does flywheel-stabilize synchronization sync word detection mode. sync insertion mode, L64777 regenerates DVB-defined sync information inserts into Modulator. Modulator Input Clock Input ICLK positive-edge-triggered clock. L64777 clocks DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN SSTARTIN rising edge ICLK. ICLK either byte clock clock, depending control register (Register setup parallel/serial mode.
DVALIDIN
ERRORIN
FSTARTIN
ICLK
L64777 Modulator
SCLK
Modulator Symbol Clock Output Output SCLK clock output synchronous internally processed symbols bytes; identical OCLK/4. L64777 uses SCLK determine phase Nyquist filter output. rising edge SCLK followed Phase falling edge transition Phase Phase 4-fold oversampling mode. Sync Sequence Start Input SSTARTIN asserted mark beginning new, fully reset sequence hardwired signal. L64777 evaluates SSTARTIN negative slope restarts internal sequences next Block/Frame start following negative SSTARTIN slope. SSTARTIN applied, internal sequences free after reset.
SSTARTIN
Status Information Signals DIG_I[9:0] Digital Component Output This port provides modulator I-component output digital format. Depending mode, either OCLK PCLK related clock. Digital Component Output This port provides modulator Q-component output digital format. Depending mode, either OCLK PCLK related clock. FIFO Collision Detected Output this alarm occurs, FIFO control detected equal pointers read write access. detected collision most probably indicates unlocked external PLL-VCO circuitry. L64777 synchronizes this signal with SCLK-driven flip-flops output. First Block Sequence Output FIRSTOUT occurs together with FSTARTOUT indicates head sync block that just-reset sequences, controlled SSTARTIN. FIRSTOUT acceptance SSTARTIN negative slope delayed internal processing modules.
DIG_Q[9:0]
FIFOALARM
FIRSTOUT
FSTARTOUT Frame Start Output Output FSTARTOUT asserted during first symbol every sync frame. width FSTARTOUT reflects
L64777 Modulator
number bytes that parameter inserts. one-cycle width indicates inserted gaps; width means inserted bytes Reed-Solomon gap. FSTARTOUT applied only sync word detection mode. FSTARTIN pulses force synchronization, FSTARTOUT constantly LOW. SYNCOK SYNC Detection/Phase Monitoring Output internal sync mode, this indicates undisturbed synchronization status when HIGH. This signal asserted when number track steps required synchronization fulfilled. FSTARTIN pulses force synchronization, SYNCOK constantly LOW.
Test Signals FTMODE[2:0] Functional Test These must tied IDDTN[3] NT_OUT[4] Test Mode IDDTN production test pin. Nand Tree Output NT_OUT production test pin. Input Input Output
SCAN_ENABLE[5] Scan Enable This enables scan chain shift. TNn[11]
Input
Test Output Enable Input switches 3-state buffers high-impedance mode testing. Test Reset Reset JTAG unit. Test Mode Select selects JTAG unit test mode. Test Data Output JTAG unit data output. Test Data Input JTAG unit data input. Test Mode Clock JTAG test mode clock. Input Input Output Input Input
TRSTn[10] TMS[9] TDO[8] TDI[7] TCK[6]
L64777 Modulator
Control Signals OCLK Encoder Out/Processing Clock Bidirectional OCLK positive-edge-triggered clock. L64777 internally processes data based fraction OCLK (for example: scrambler, interleaver, Reed-Solomon encoder) references data outputs FSTARTOUT) OCLK. Input
PLL_MODE[1:0] Select Mode select mode: 0b00 0b01 external usage 0b11 usage. RESET_n
Reset Input This resets internal data paths. Reset timing asynchronous device clocks. Reset affects configuration registers filter coefficients, which must downloaded again after reset.
External Signals PCLK Processing Clock: Mode Input PCLK output L64724 provides this clock, which drives digital signal processing interpolation NCO. When using Mode leave this open.
PLL_OUT_CS Current Source 3-State Output This charge pump external pass control frequency. comparator frequency- phase-sensitive. normally 3-state level drives positive negative current, required. Depending configuration, current source inverted. Analog Signals AVDD1 Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998).
L64777 Modulator
AVDD2
Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Compensation Output: Comp. Analog Output usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Compensation Output: Comp. Analog Output usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Current: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Current: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Symbol Modulation Analog Output QAM_I positive differential analog in-phase output signal modulator. Symbol Modulation Inverted Analog Output QAM_IN corresponding inverted differential part QAM_I. Symbol Modulation Analog Output QAM_Q positive differential analog quadrature output signal modulator.
AVSS1
AVSS2
COMP1
COMP2
IREF1
IREF2
QAM_I
QAM_IN
QAM_Q
L64777 Modulator
QAM_QN
Inverted Differential QAM_Q Analog Output QAM_QN corresponding inverted differential part QAM_Q. Isolated Power: Digital-to-Analog Converter, Channel Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Isolated Power: Digital-to-Analalog Converter, Channel Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Voltage Input: Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Voltage Input: Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998).
VDDX_I
VDDX_Q
VREF_I
VREF_Q
Serial Microprocessor Interface Signals INT_n Interrupt Request Output L64777 asserts INT_n when interrupt enabled interrupt condition occurs. INT_n open drain output that requires external pull-up resistor operation. Serial Base Address Input external microprocessor must apply these signals static signals device because they determine LSBs serial base address. Serial Clock Line conjunction with SDA, controls microprocessor interface. Input
SB_BASE[1:0]
L64777 Modulator
Serial Data Access Bidirectional conjunction with SCL, controls microprocessor interface.
Specifications
This section provides information about electrical ratings, pins, packaging L64777.
AC/DC Specifications
following subsections list electrical requirements, provide timing characteristics, show timing diagrams, list timing values L64777 decoder. Electrical Ratings tables this section specify electrical requirements L64777 decoder. Table provides L64777 absolute maximum electrical temperature ratings. Table provides L64777 recommended operating conditions. Table lists characteristics L64777. Table
Symbol TSTG
L64777 Absolute Maximum Ratings
Parameter Supply LVTTL Input Voltage Compatible Inputs Input Current Storage Temperature Range (Plastic) Operating Junction Temperature Range Limits -0.3 -1.0 -1.0 +150 +125 Unit
L64777 Modulator
Table
Symbol
L64777 Recommended Operating Conditions
Parameter Supply Ambient Temperature Limits Unit
3.14 3.45
When studying values Table note that L64777 follows Logic G10®-p process, which characterized 0.35-micron gate length. Table L64777 Characteristics
Condition1 3.14 Max, VOUT Max, Max, Max, ICLK MHz, MODE PCLK 3.45 Units
Symbol Parameter Supply Voltage Input Voltage Input Voltage HIGH Output Voltage HIGH Output Voltage Current 3-State Leakage w/Pulldown Input Current Leakage Input Current Leakage w/Pullup Input Current Leakage w/Pulldown Quiescent Supply Current Dynamic Supply Current
Specified ambient temperature over specified range.
L64777 Modulator
Timing Diagrams L64777 Figure illustrates input timing. Figure Input Timing
ICLK Inputs
Figure illustrates reset timing L64777. Figure L64777 RESET Timing Diagram
RESET
Figure illustrates 3-state delay timing L64777 bus. Figure
DATA
L64777 3-State Delay Timing
Note:
Complete timings during design phase.
numbers column Table refer timing parameters preceding figures. parameters this table apply output load
L64777 Modulator
Table
L64777 Preliminary Timing Parameters
Parameter tCYCLE tPWH tPWL tI_CYCLE tI_PWH tI_PWL tI_S tI_H tRWH Description Clock Cycle OCLK Clock Pulse Width HIGH OCLK Clock Pulse Width OCLK Clock Cycle ICLK Clock Pulse Width HIGH ICLK Clock Pulse Width ICLK Input Setup Time ICLK Input Hold ICLK Reset Pulse Width HIGH Wake-up Time after RESET (used initialization during microprocessor configuration access) 18.5 1280 Unit ICLK cycles with DVALIDIN HIGH OCLK cycles
2560 tTDLY Delay from
Descriptions Lists
following subsections provide descriptions electrical pins, well numerical alphabetic listings L64777 pins. L64777 Electrical Descriptions Table summarizes electrical properties pins L64777. table provides signal types both output input pins, drive capacity outputs.
L64777 Modulator
Table
L64777 Description Summary
Drive (mA) Active HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW/ HIGH
Mnemonic AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 DIG_I[9:0] DIG_Q[9:0] DIN[7:0] DVALIDIN ERRORIN FIFOALARM FIRSTOUT FSTARTIN FSTARTOUT FTMODE[2:0] ICLK IDDTN INT_n
Description Supply Supply Analog Supply Supply Compensation Output Compensation Output Digital Output Digital Output Data Input Data Enable Input Error Flag Input FIFO Alarm Output Beginning Sequence Frame Start Input Frame Start Output
Type Analog Input Analog Input Analog Input Analog Input Analog Output Analog Output Output Output Input Input Input Output Output Input Output
Functional Test Mode Input w/Pulldown Ground Input Clock Test Interrupt Request Analog Input Input w/Pullup Open Drain, Driving
L64777 Modulator
Table
L64777 Description Summary (Cont.)
Drive (mA) Active HIGH LOW/ HIGH HIGH HIGH 3-state HIGH HIGH HIGH LOW/ HIGH Opendrain
Mnemonic IREF1 IREF2 NT_OUT OCLK PCLK PLL_MODE[1:0] PLL_OUT_CS QAM_I QAM_In QAM_Q QAM_QN RESET_n SB_BASE[1:0] SCAN_ENABLE SCLK
Description Reference Current Input Reference Current Input Nand Tree Clock Output External Clock Input Clock Input Mode Select Mode Current Source Positive Output Channel Negative Output Channel Positive Output Channel Negative Output Channel Chip Reset Serial Base Address Selector Scan Enable Serial Control Line
Type Analog Input Analog Input Output Bidirectional input Input w/Pulldown 3-state Current Source Analog Output Analog Output Analog Output Analog Output Input Input w/Pulldown Input w/Pulldown Input V-tolerant)
Symbol Clock Output Output Serial Data Access Bidirectional V-tolerant)
L64777 Modulator
Table
L64777 Description Summary (Cont.)
Drive (mA) Active HIGH HIGH HIGH HIGH HIGH
Mnemonic SSTARTIN SYNCOK TRSTn VDDX_I VDDX_Q VREF_I VREF_Q
Description
Type
Sequence Start Input Input Sync Detection Flag JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select 3-State Mode JTAG Test Reset Supply Digital Part Supply Digital Part Voltage Reference Voltage Reference Output Input w/Pulldown Input w/Pulldown Output Input w/Pulldown Input w/Pullup Input w/Pulldown Analog Input Analog Input Analog Analog
Also compatible.
L64777 Modulator
Lists L64777
Table
Signal QAM_I QAM_IN AVDD1 IREF1 COMP1 VREF_I AVSS VDDX_I VDDX_Q AVSS2 VREF_Q COMP2 IREF2 AVDD2 QAM_QN QAM_Q PLL_OUT_CS
L64777 Numerical List
Signal PLL_MODE.0 PLL_MODE.1 IDDTN RESET_N DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 OCLK Signal TRSTN INT_N FIFOALARM FIRSTOUT SYNCOK FSTARTOUT DIN.7 DIN.6 DIN.5 DIN.4 ICLK DIN.3 DIN.2 DIN.1 DIN.0 DVALIDIN ERRORIN FSTARTIN SSTARTIN Signal NT_OUT SCAN_ENABLE FTMODE.0 FTMODE.1 FTMODE.2 SB_BASE.0 SB+BASE.1 PCLK SCLK DIG_I.0 DIG_I.1 DIG_I.2 DIG_I.3 DIG_I.4 DIG_I.5 DIG_I.6 DIG_I.7 DIG_I.8 DIG_I.9
pins connected.
L64777 Modulator
Table
Signal AVDD1 AVDD2 AVSS AVSS2 COMP1 COMP2 DIG_I.0 DIG_I.1 DIG_I.2 DIG_I.3 DIG_I.4 DIG_I.5 DIG_I.6 DIG_I.7 DIG_I.8 DIG_I.9 DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 DIN.0 DIN.1 DIN.2 DIN.3
L64777 Alphabetical List
Signal DIN.4 DIN.5 DIN.6 DIN.7 DVALIDIN ERRORIN FIFOALARM FIRSTOUT FSTARTIN FSTARTOUT FTMODE.0 FTMODE.1 FTMODE.2 ICLK IDDTN INT_N IREF1 IREF2 NT_OUT OCLK PCLK PLL_MODE.0 Signal PLL_MODE.1 PLL_OUT_CS QAM_I QAM_IN QAM_Q QAM_QN RESET_N SB+BASE.1 SB_BASE.0 SCAN_ENABLE SCLK SSTARTIN SYNCOK TRSTN Signal VDDX_I VDDX_Q VREF_I VREF_Q
pins connected.
L64777 Modulator
Package Pinout
Figure Package 120-Pin PQFP Pinout
DIG_I.9 DIG_I.8 DIG_I.7 DIG_I.6 DIG_I.5 DIG_I.4 DIG_I.3 DIG_I.2 DIG_I.1 DIG_I.0 SCLK PCLK SB_BASE.1 SB_BASE.0 FTMODE.2 FTMODE.1 FTMODE.0 SCAN_ENABLE NT_OUT
PLL_MODE.0 PLL_MODE.1 IDDTN RESET_N DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 OCLK
QAM_I QAM_IN AVDD1 IREF1 COMP1 VREF_I AVSS1 VDDX_I VDDX_Q AVSS2 VREF_Q COMP2 IREF2 AVDD2 QAM_QN QAM_Q PLL_OUT_CS
View L64777
SSTARTIN FSTARTIN ERRORIN DVALIDIN DIN.0 DIN.1 DIN.2 DIN.3 ICLK DIN.4 DIN.5 DIN.6 DIN.7 FSTARTOUT SYNCOK FIRSTOUT FIFOALARM INT_N TRSTN
L64777 Modulator
Figure provides mechanical drawing 120-pin PQFP L64777. Figure 120-pin PQFP (PE) Mechanical Drawing
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64777 Modulator
Figure
120-pin PQFP (PE) Mechanical Drawing (Cont.)
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64777 Modulator
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L64777 chip implements modulator that digital video broadcasting (DVB)

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