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28F256J3, 28F128J3, 28F640J3, 28F320J3 x8 / x16

Order Number: 290667-015 January 2004

Intel StrataFlash® Memory (J3)
28F256J3, 28F128J3, 28F640J3, 28F320J3 (x8 / x16)
Datasheet
Product Features
Order Number: 290667-015 January 2004
Datasheet
Contents
Device Description ............................................................8
Device Operations ............................................................15
Read Operations .............................................................19
Programming Operations ......................................................22
Erase Operations .............................................................24
Security Modes ..............................................................26
Datasheet
Contents
Special Modes............................................................... 30 8.1 8.2 Set Read Configuration Register Command ................................... 30 Status (STS) ............................................................ 30 Power-Up / Down Characteristics............................................. 32 Power Supply Decoupling.................................................. 32 Reset Characteristics..................................................... 32 Absolute Maximum Ratings ................................................ 33 Operating Conditions ..................................................... 34 DC Current Characteristics................................................. 35 DC Voltage Characteristics................................................. 36 Read Operations......................................................... 37 Write Operations......................................................... 41 Block Erase, Program, and Lock-Bit Configuration Performance.................... 42 Reset Operation......................................................... 44 AC Test Conditions....................................................... 44 Capacitance............................................................ 45
Power and Reset............................................................. 32 9.1 9.2 9.3 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6
10.0 Electrical Specifications ....................................................... 33
11.0 AC Characteristics ........................................................... 37
Appendix A Common Flash Interface.................................................46 Appendix B Flow Charts ...........................................................53 Appendix C Mechanical Information .................................................62 Appendix D Design Considerations ..................................................65 Appendix E Additional Information ..................................................67 Appendix F Ordering Information ....................................................68
Datasheet
Contents
Revision History
Date of Revision 07 / 07 / 99 08 / 03 / 99 09 / 07 / 99 Version -001 -002 -003 Original Version A0-A2 indicated on block diagram Changed Minimum Block Erase time, IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I / O operation Corrected Ordering Information, Valid Combinations entries 12 / 16 / 99 -004 Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2 / 3 to VCCQ1 / 2 03 / 16 / 00 -005 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of 0.45 V Removed VOH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion 06 / 26 / 00 -006 Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7 not 2-7 Updated Table 16 bit 2 definition from R to PSS 2 / 15 / 01 -007 Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics-Read-Only Operations (1, 2) Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC Characteristics-Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
Description
Revised Section 7.0, Ordering Information
Datasheet
Contents
Date of Revision
Version
Description Added Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit) Added Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for -40 °C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to 2.2 V Removed Note #4, Section 6.4 and Section 6.6 Minor text edits Added notes under lead descriptions for VF BGA Package Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits Added nomenclature for J3C (0.18 µm) devices. Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added "TE" package designator for J3C TSOP package. Revised Asynchronous Page Read description. Revised Write-to-Buffer flow chart. Updated timing waveforms. Added 256-Mbit J3C pinout. Added 256Mbit device timings, device ID, and CFI information. Also corrected VLKO specification.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Introduction
Document Purpose
This document contains information pertaining to the Intel StrataFlash® Memory (J3) device. The purpose of this document is to facilitate the use of this product and describe the features, operations, and specifications of this device.
Nomenclature
Block: Clear: CUI: MLC: OTP: PLR: PR: PRD Program: RFU: Set: SR: SRD: VPEN: VPEN: WSM: XSR:
Conventions
0x: 0b: k (noun): M (noun): Nibble Byte: Word: Kword: Kb: KB: Mb: MB: Brackets: Hexadecimal prefix Binary prefix 1, 000 1, 000, 000 4 bits 8 bits 16 bits 1, 024 words 1, 024 bits 1, 024 bytes 1, 048, 576 bits 1, 048, 576 bytes Square brackets () will be used to designate group membership or to define a group of signals with similar function (i.e. A21:1, SR4, 1 and D15:0). 7
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Device Description
Product Overview
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Ballout Diagrams
Intel StrataFlash® memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball VF BGA package is available on 32 and 64 Mbit devices. Figure 1, Figure 2, and Figure 3 show the pinouts.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 1. Intel StrataFlash® Memory Easy BGA Ballout (32 / 64 / 128 / 256 Mbit)
1 A A1 B A2 C A3 D A4 E D8 F BYTE# D0 G A23 128M H CE2# RFU VCC VSS D13 VSS Easy BGA Top View- Ball side down D7 A24 256M A24 D7 256M VSS D13 VSS VCC RFU CE2# Easy BGA Bottom View- Ball side up A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23 128M H D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE# G D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8 F A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4 E A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3 D VSS A9 CEO# A14 RFU A19 CE1# CE1# A19 RFU A14 CEO# A9 VSS A2 C A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1 B 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A
NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC). 3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).
Figure 2. Intel StrataFlash® Memory 56-Lead TSOP (32 / 64 / 128 / 256 Mbit)
3 Volt Intel StrataFlash Memory 28F160S3 NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 28F320J5 NC CE1 A21 A20 A19 A18 A17 A16 VCC(4) A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 32 / 64 / 128M A22(1) CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 Volt Intel StrataFlash Memory 32 / 64 / 128M A24(3) WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23(2) CE2 28F320J5 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC(4) DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 28F160S3 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
3 Volt Intel StrataFlash® Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
Highlights pinout changes
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 3. Intel StrataFlash® Memory VF BGA Ballout (32 and 64 Mbit)
VCCQ F
VF BGA 6x8 Top View - Ball Side Down
VF BGA 6x8 Bottom View - Ball Side Up
NOTES: 1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded. 2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC). 3. STS not supported in this package. 4. x8 not supported in this package.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Signal Descriptions
Table 1 lists the active signals used and provides a description of each. Table 1.
Symbol A0
Signal Descriptions (Sheet 1 of 2)
AMAX:1
INPUT
INPUT / OUTPUT
D15:8
INPUT / OUTPUT
CE0, CE1, CE2
INPUT
OE# WE#
INPUT INPUT
OPEN DRAIN OUTPUT
BYTE#
INPUT
POWER
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 1.
Symbol GND NC RFU
Signal Descriptions (Sheet 2 of 2)
Type SUPPLY Name and Function GROUND: Do not float any ground signals. NO CONNECT: Lead is not internally connected it may be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device functionality and enhancement.
Block Diagram
Figure 4. 3 Volt Intel StrataFlash® Memory Block Diagram
D15:0
Output Buffer
Input Buffer
Query Output Latch / Multiplexer Write Buffer Identifier Register Status Register
I / O Logic Data Register CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Command User Interface
Multiplexer Data Comparator
Y-Decoder AMAX:MIN Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program / Erase Voltage Switch
STS VPEN
Address Latch Address Counter
X-Decoder
VCC GND
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Memory Map
Figure 5. Intel StrataFlash® Memory (J3) Memory Map
AMAX:MIN
1FFFFFF 1FE0000
AMAX:MIN
FFFFFF
128-Kbyte Block
257 FF0000
64-Kword Block
0FFFFFF
7FFFFF
128-Kbyte Block
0FE0000
127 7F0000
64-Kword Block
07FFFFF 07E0000
3FFFFF
128-Kbyte Block
63 3F0000
64-Kword Block
128-Kbyte Block
31 1F0000
64-Kword Block
03E0000
003FFFF 0020000 001FFFF 0000000
128-Kbyte Block 128-Kbyte Block
01FFFF 1 010000 00FFFF 0 000000
64-Kword Block 64-Kword Block
Byte-Wide (x8) Mode
Word Wide (x16) Mode
32-Mbit
Datasheet
64-Mbit
03FFFFF
1FFFFF
128-Mbit
256-Mbit
28F256J3, 28F128J3, 28F640J3, 28F320J3
Device Operations
Bus Operations
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Table 2.
Mode Read Array Output Disable Standby
Bus Operations
Reset / Power-Down Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM on) Write
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 3.
Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: For single-chip applications, CE2 and CE1 can be connected to VIL.
Bus Read Operation
To perform a bus read operation, CEx (refer to Table 3 on page 16) and OE# must be asserted. CEx is the device-select control when active, it enables the flash memory device. OE# is the dataoutput control when active, the addressed flash memory data is driven onto the I / O bus. For all read states, WE# and RP# must be de-asserted. See Section 11.1, "Read Operations" on page 37. Refer to Section 4.0, "Read Operations" on page 19 for details on reading from the flash array, and refer to Section 8.0, "Special Modes" on page 30 for details regarding all other available read states.
Bus Write Operation
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output signals D15:0 are placed in a high-impedance state.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Standby
CE0, CE1, and CE2 can disable the device (see Table 3 on page 16) and place it in standby mode. This manipulation of CEx substantially reduces device power consumption. D15:0 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
Reset / Power-Down
RP# at VIL initiates the reset / power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0x80. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel® Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
Device Commands
When the VPEN voltage VPENLK, only read operations from the Status Register, CFI, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4, "Command Bus-Cycle Definitions" on page 17 defines these commands.
Table 4.
Command
Command Bus-Cycle Definitions (Sheet 1 of 2)
Oper(3) Read Array Read Identifier Codes Read Query SCS / BCS SCS / BCS SCS 1 2 2 Write Write Write
Addr(4) X X X
Data(5, 6) 0xFF 0X90 0x98
Oper(3)
Addr(4)
Data(5, 6) 1
Read Read
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 4.
Command
Command Bus-Cycle Definitions (Sheet 2 of 2)
Data(5, 6) 0x70 0x50 0xE8 0x40 or 0x10 0x20 0xB0 0xD0 0xB8 0x60 0x60 0xC0
Oper(3) Read
Addr(4) X
Data(5, 6) SRD 1, 8 1
Write Write Write
N PD 0xD0
Write Write Write Write
CC 0x01 0xD0 PD
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Read Operations
Read Array
Upon initial device power-up and after exit from reset / power-down mode, the device defaults to read array mode. The read configuration register defaults to asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. If the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPEN voltage.
Asynchronous Page-Mode Read
Asynchronous Page Mode is the default read mode on power-up or reset. In asynchronous page mode, array data is sensed four words (eight bytes) at a time and is loaded into a page buffer. After the initial access delay, the first word out of the page buffer corresponds to the initial address. Address bits A2:1 determine which word is output from the page buffer for a x16 bus width, and A2:0 determine which word is output from the page buffer for a x8 bus width. Subsequent reads from the device come from the page buffer. These reads are output on D15:0 for a x16 bus width and D7:0 for a x8 bus width after a minimum delay as long as A2:0 are the only address bits that change. Data can be read from the page buffer multiple times, and in any order. If address bits AMAX:3 change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer. Asynchronous Page Mode is the default read mode on power-up or reset. To perform a page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used to access register information, but only one word is loaded into the page buffer during register access.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Read Identifier Codes
The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See Section 3.2, "Device Commands" on page 17 for details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read mode. To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPEN voltage. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read
Table 5.
Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit 256-Mbit Block Lock Configuration · Block Is Unlocked · Block Is Locked · Reserved for Future Use Address(1) 00000 00001 00001 00001 00001
X0002
Data (00) 89 (00) 16 (00) 17 (00) 18 (00) 1D
Read Status Register
The Status Register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read only after the specified time W12 (see Table 16, "Write Operations" on page 41). After writing this command, all subsequent read operations output data from the Status Register until another valid command is written. Page-mode reads are not supported in this read mode. The Status Register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 3, "Chip Enable Truth Table" on page 16). OE# must toggle to VIH or the device must be disabled before further reads to update the Status Register latch. The Read Status Register command functions independently of the VPEN voltage. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR7 is valid until the Write State Machine completes or suspends the operation. Device I / O signals D6:0 and D15:8 are placed in a high-impedance state. When the operation completes or suspends (check SR7), all contents of the Status Register are valid when read.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 6.
Status Register Definitions
ESS bit 6 ECLBS bit 5 PSLBS bit 4 VPENS bit 3 PSS bit2 DPS bit 1 R bit 0
Yes Yes Yes
If both SR5 and SR4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
SR3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences.
SR1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read Identifier Codes command to determine block lock-bit status. SR0 is reserved for future use and should be masked when polling the Status Register.
Table 7.
eXtended Status Register Definitions
Reserved bits 6-0
Status Register Bits
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Read Query / CFI
The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any information from the query register, execute the Read Query Register command. See Section 3.2, "Device Commands" on page 17 for details on issuing the CFI Query command. Refer to Appendix A, "Query Structure Overview" on page 47 for a detailed explanation of the CFI register. Information contained in this register can only be accessed by executing a single-word read.
Programming Operations
The device supports two different programming methods: word programming, and write-buffer programming. Successful programming requires the addressed block to be unlocked. An attempt to program a locked block will result in the operation aborting, and SR1 and SR4 being set, indicating a programming error. The following sections describe device programming in detail.
Byte / Word Program
Byte / Word program is executed by a two-cycle command sequence. Byte / Word program setup (standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs SRD when read (see Figure 16, "Byte / Word Program Flowchart" on page 55). The CPU can detect the completion of the program event by analyzing the STS signal or SR7. When program is complete, SR4 should be checked. If a program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in Read Status Register mode until it receives another command. Reliable byte / word programming can only occur when VCC and VPEN are valid. If a byte / word program is attempted while VPEN VPENLK, SR4 and SR3 will be set. Successful byte / word programs require that the corresponding block lock-bit be cleared. If a byte / word program is attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set.
Write to Buffer
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Program Suspend
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Program Resume
To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend / resume of two nested routines. See Figure 17, "Program Suspend / Resume Flowchart" on page 56).
Erase Operations
Flash erasing is performed on a block basis therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level one. To determine the status of a block erase, poll the Status Register and analyze the bits. This following section describes block erase operations in detail.
Block Erase
Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs SRD when read after the Block Erase Suspend command is written. Polling SR7 then SR6 can determine when the block erase operation has been suspended (both will be set). In default mode, STS will also transition to VOH. Specification tWHRH defines the block erase suspend latency.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, SR7 will return to "0" and STS output (in default mode) will transition to VOL. However, SR6 will remain "1" to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. SR6 and SR7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs SRD when read (see Figure 19, "Block Erase Suspend / Resume Flowchart" on page 58). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
Erase Resume
To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume the program operations first. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend / resume of two nested routines. See Figure 18, "Block Erase Flowchart" on page 57.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Security Modes
This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail.
Set Block Lock-Bit
A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read (see Figure 20 on page 59). The CPU can detect the completion of the set lock-bit event by analyzing the STS signal output or SR7. When the set lock-bit operation is complete, SR4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in SR4 and SR5 being set. Also, reliable operations occur only when VCC and VPEN are valid. With VPEN VPENLK, lock-bit contents are protected against alteration.
Clear Block Lock-Bits
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lockbits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs Status Register data when read (see Figure 21 on page 60). The CPU can detect completion of the clear block lock-bits event by analyzing the STS signal output or SR7. When the operation is complete, SR5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until another command is issued. This two-step sequence of setup followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR4 and SR5 being set. Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN VPENLK, SR3 and SR5 will be set.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.
Protection Register Program
The Intel StrataFlash® memory (J3) includes a 128-bit Protection Register that can be used to increase the security of a system design. For example, the number contained in the PR can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming.
Reading the Protection Register
The Protection Register is read in the identification read mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 8 or Table 9 retrieve the specified information. To return to read array mode, write the Read Array command (0xFF).
Programming the Protection Register
Protection Register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Table 8 or Table 9. See Figure 22, "Protection Register Programming Flowchart" on page 61 Any attempt to address Protection Program commands outside the defined PR address space will result in a Status Register error (SR4 will be set). Attempting to program a locked PR segment will result in a Status Register error (SR4 and SR1 will be set).
Locking the Protection Register
The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "0xFFFD" to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a Status Register error (SR4 and SR1 will be set). PR lockout state is not reversible.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 6. Protection Register Memory Map
Word Address
A24:1: 256 Mbit A23:1: 128 Mbit
A22:1: 64 Mbit A21:1: 32 Mbit
64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80
128-Bit Protection Register 0 64-bit Segment (Factory-Programmed)
NOTE: A0 is not used in x16 mode when accessing the protection register map (See Table 8 for x16 addressing). For x8 mode A0 is used (See Table 9 for x8 addressing).
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 8.
Word-Wide Protection Register Addressing
Table 9.
Byte-Wide Protection Register Addressing
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Array Protection
The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program operation, poll the Status Register and analyze the bits.
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to configure the STS signal.
Set Read Configuration Register Command
Status (STS)
The Status (STS) signal can be configured to different states using the Configuration command. Once the STS signal has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY / BY# operation where RY / BY# low indicates that the WSM is busy. RY / BY# high indicates that the state machine is ready for a new operation or suspended. Table 10, "STS Configuration Coding Definitions" on page 31 displays the possible STS configurations. To reconfigure the Status (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with the Configuration command resets the STS signal to the default RY / BY# level mode. The possible configurations and their usage are described in Table 10, "STS Configuration Coding Definitions" on page 31. The Configuration command may only be given when the device is not busy or suspended. Check SR7 for device status. An invalid configuration code will result in both SR4 and SR5 being set. When configured in one of the pulse modes, the STS signal pulses low with a typical pulse width of 250 ns.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 10. STS Configuration Coding Definitions
D7 D6 D5 D4 D3 D2 D1 Pulse on Program Complete (1) Notes
D0 Pulse on Erase Complete (1)
Reserved
NOTES: 1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns. 2. An invalid configuration code will result in both SR4 and SR5 being set.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Power and Reset
This section provides an overview of some system level considerations in regards to the flash device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations.
Power-Up / Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down VCC and VCCQ together. It is also recommended to power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly before VCC.
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each VCC / VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance.
Reset Characteristics
By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 11, "AC Waveform for Reset Operation" on page 44 for detailed information regarding reset timings.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Electrical Specifications
Absolute Maximum Ratings
This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute maximum ratings are shown in Table 11.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 11. Absolute Maximum Ratings
Parameter Temperature under Bias Extended Storage Temperature Voltage On Any signal Output Short Circuit Current Maximum Rating -40 °C to +85 °C -65 °C to +125 °C -2.0 V to +5.0 V(1) 100 mA(2)
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Symbol TA VCC VCCQ
Operating Conditions
Parameter Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 V) VCCQ Supply Voltage (2.7 V-3.6 V) Min -40 2.70 2.70 Max +85 3.60 3.60 Unit °C V V Test Condition Ambient Temperature
Table 12. Temperature and VCC Operating Conditions
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
DC Current Characteristics
Table 13. DC Current Characteristics
50 ICCS VCC Standby Current 0.71 ICCD VCC Power-Down Current 50
15 ICCR VCC Page Mode Read Current 24
ICCE ICCWS ICCES
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
DC Voltage Characteristics
Table 14. DC Voltage Characteristics
Output High Voltage
VPENLK VPENH VLKO
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
AC Characteristics
Read Operations
Table 15. Read Operations (Sheet 1 of 2)
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 15. Read Operations (Sheet 2 of 2)
OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low Page Address Access Time OE# to Array Output Delay 0
tOH tELFL / tELFH tFLQV / tFHQV tFLQZ tEHEL tAPA tGLQV
R11 R12 R13 R14 R15 R16
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3).
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 7. Single Word Asynchronous Read Waveform
R1 R2 Address A R3 CEx E R9 OE# G WE# W R4 R16 R7 R6 Data D / Q R11 BYTE#F R5 RP# P
R12 R13
NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3). 2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e.: Status Register reads, query reads, or device identifier reads).
Figure 8. Page Mode Read Waveform
R1 R2 AMAX:3 A A2:1 A R3 CEx E R4 OE# G WE# W R8 R10 R9 2 3 4 00 01 10 11
R6 R7 D15:0 Q R5 RP# P 1
R10 R15
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3).
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Write Operations
Table 16. Write Operations
Versions # W1 W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15 Symbol tPHWL (tPHEL) tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL Parameter RP# High Recovery to WE# (CEX) Going Low CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High 0 Valid for All Speeds Min 1 0 70 50 55 0 0 0 30 0 35 500 Max µs ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 5 1, 2, 5 1, 2, 1, 2, 1, 2, 1, 2, 6 1, 2, 3 1, 2, 7 1, 2, 8 1, 2, 3, 8, 9 Unit Notes
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3).
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Block Erase, Program, and Lock-Bit Configuration Performance
Table 17. Configuration Performance
# W16 W16 tWHQV3 tEHQV3 Sym Parameter Write Buffer Byte Program Time (Time to Program 32 bytes / 16 words) Byte Program Time (Using Word / Byte Program Command) Block Program Time (Using Write to Buffer Command) W16 W16 W16 W16 W16 tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read Typ 218 210 0.8 1.0 64 0.5 25 26 Max(8) 654 630 2.4 5.0 75 / 85 0.70 / 1.4 75 / 90 35 / 40 Unit µs µs sec sec µs sec µs µs Notes 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4, 9 1, 2, 3, 4, 10 1, 2, 3, 9 1, 2, 3, 9
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 9. Asynchronous Write Waveform
W5 ADDRESS A W6 CEx (WE#) E (W) W2 WE# (CEx) W (E) OE# G W4 DATA D / Q D W13 STSR W1 RP# P W11 VPEN V W7 W3 W9 W8
Figure 10. Asynchronous Write to Read Waveform
W5 Address A W6 CE# E W2 WE# W W12 OE# G W4 Data D / Q W1 RST# / RP# P W11 VPEN V D W7 W3 W8
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Reset Operation
Figure 11. AC Waveform for Reset Operation
STS (R)
VIH VIL
RP# (P)
VIH VIL
NOTE: STS is shown in its default mode (RY / BY#).
Table 18. Reset Specifications
# P1 Sym tPLPH tPHRH Parameter RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Min 35 Max Unit µs Notes 1, 2
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY / BY# mode) or RP# going high until outputs are valid.
AC Test Conditions
VCCQ Input 0.0 V CCQ / 2 Test Points VCCQ / 2 Output
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 13. Transient Equivalent Testing Load Circuit
Capacitance
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix A Common Flash Interface
The Common Flash Interface(CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forwardand backward-compatible software support for the specified flash device families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8 / x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
Query Structure Output
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 19. Summary of Query Structure Output as a Function of Device and Mode
Device Type / Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset x16 device x16 mode x16 device x8 mode 10h 10: 11: 12: Hex Code 0051 0052 0059 N / A(1) ASCII Value "Q" "R" "Y" Query data with byte addressing Hex Offset 20: 21: 22: 20: 21: 22: Hex Code 51 00 52 51 51 52 ASCII Value "Q" "Null" "R" "Q" "Q" "R"
Table 20. Example of Query Structure Output of a x16- and x8-Capable Device
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 21. Query Structure
Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Device Code Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm Description Manufacturer Code Notes 1 1 1, 2 1 1 1 1 1, 3
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program / erase operations.
Table 22. Block Status Register
Offset (BA+2)h
Length 1
Address BA+2: BA+2:
Value -00 or -01 (bit 0): 0 or 1
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 23. CFI Identification (Sheet 1 of 2)
Offset Length Description Add. 10 11: 12: 13: 14: 15: 16: 17: Hex Code -51 -52 -59 -01 -00 -31 -00 -00 Value "Q" "R" "Y"
10h 13h 15h 17h
Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 23. CFI Identification (Sheet 2 of 2)
Offset Length Description 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. 18: 19: 1A: Hex Code -00 -00 -00 Value
System Interface Information
The following device information can optimize system interface software.
Table 24. System Interface Information
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
1E: 1F: 20: 21: 22: 23: 24: 25: 26:
-00 -08 -08 -0A -00 -04 -04 -04 -00
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 25. Device Geometry Definition (Sheet 1 of 2)
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 25. Device Geometry Definition (Sheet 2 of 2)
2D: 2E: 2F: 30:
Device Geometry Definition
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 32 Mbit -16 -02 -00 -05 -00 -01 -1F -00 -00 -02 64 Mbit -17 -02 -00 -05 -00 -01 -3F -00 -00 -02 128 Mbit -18 -02 -00 -05 -00 -01 -7F -00 -00 -02 256Mbit -19 -02 -00 -05 -00 -01 -FF -00 -00 -02
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information.
Table 26. Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 26. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
(P+5)h (P+6)h (P+7)h (P+8)h
No Yes Yes Yes(1) No No Yes Yes No
(P+9)h
(P+A)h (P+B)h
Yes No 3.3 V
(P+C)h
(P+D)h
NOTE: 1. Future devices may not support the described "Legacy Lock / Unlock" function. Thus bit 3 would have a value of "0."
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 27. Protection Register Information
80h 00h 8bytes 8bytes
(P+F)h (P+10)h (P+11)h (P+12)h
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Table 28. Burst Read Information
(P+14)h
(P+15)h NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix B Flow Charts
Figure 14. Write to Buffer Flowchart
Start
Setup - Write 0xE8 - Block Address
Check Buffer Status - Perform read operation - Read Ready Status on signal SR7
Confirm - Write 0xD0 - Block address
Read Status Register (SR)
Yes Full Status Register Check (if desired)
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 15. Status Register Flowchart
Start
Data Cycle - Read Status Register SR7:0
- Set / Reset by WSM
Erase Suspend See Suspend / Resume Flowchart
Program Suspend See Suspend / Resume Flowchart
Error Command Sequence
No Error Erase Failure
Error Program Failure
- Set by WSM - Reset by user - See Clear Status Register Command
Error Block Locked
Datasheet
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 16. Byte / Word Program Flowchart
Start
Bus Operation Write Write
Command Setup Byte / Word Program Byte / Word Program
Write 40H, Address Write Data and Address Read Status Register 0
Read (Note 1) Standby
1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode.
1 Device Protect Error
Standby
Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register c