Commercial Express 87C52 80C52 80C32 87C54 80C54 87C58 80C58 Tabl
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8XC52 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express 87C52 80C52 80C32 87C54 80C54 87C58 80C58
Table Proliferation Options
High Performance CHMOS EPROM Operations Three 16-Bit Timer Counters Programmable Clock Down Timer Counter Three Level Program Lock System On-Chip Program Memory Bytes On-Chip Data Improved Quick Pulse Programming Algorithm Boolean Processor Programmable Lines
Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition CMOS Compatible Logic Levels External Program Memory Space External Data Memory Space Microcontroller Compatible Instruction Power Saving Idle Power Down Modes ONCE (On-Circuit Emulation) Mode Four-Level Interrupt Priority Extended Temperature Range Except Offering
MEMORY ORGANIZATION
Device 80C52 80C54 80C58 EPROM Version 87C52 87C54 87C58 ROMless Version 80C32 80C32 80C32 EPROM Bytes Bytes
These devices address Kbytes external program data memory Intel 8XC52 8XC54 8XC58 single-chip control-oriented microcontroller which fabricated Intel's reliable CHMOS III-E technology Being member family controllers 8XC52 8XC54 8XC58 uses same powerful instruction same architecture pin-for-pin compatible with existing family products 8XC52 8XC54 8XC58 enhanced version 87C51 80C51BH 80C31BH added features make even more powerful microcontroller applications that require clock output down counting capabilities such motor control also more versatile serial channel that facilitates multi-processor communications Throughout this document 8XC5X will refer 8XC52 80C32 8XC54 8XC58 unless information applies specific device
Other brands names property their respective owners Information this document provided connection with Intel products Intel assumes liability whatsoever including infringement patent copyright sale Intel products except provided Intel's Terms Conditions Sale such products Intel retains right make changes these specifications time without notice Microcomputer Products have minor variations this specification known errata
COPYRIGHT
INTEL CORPORATION 1996
March 1996
Order Number 272336-004
8XC52
Table Proliferations Options Standard 80C32 80C52 87C52 80C54 87C54 80C58 87C58
NOTES
272336
Figure 8XC5X Block Diagram
8XC52
PROCESS INFORMATION
This device manufactured P629 CHMOS III-E process Additional process reliability information available Intel® Quality System Handbook.
PACKAGES
Part 8XC5X 87C5X 8XC5X 8XC5X Prefix Package Type 40-Pin Plastic (OTP) 40-Pin CERDIP (EPROM) 44-Pin PLCC (OTP) 44-Pin (OTP)
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PLCC
272336
272336
connect reserved pins
Figure Connections
8XC52
pins that externally pulled will source current (IIL data sheet) because internal pullups Port emits high-order address byte during fetches from external Program Memory during accesses external Data Memory that 16-bit addresses (MOVX DPTR) this application uses strong internal pullups when emitting During accesses external Data Memory that 8-bit addresses (MOVX Port emits contents Special Function Register Some Port pins receive high-order address bits during EPROM programming program verification Port Port 8-bit bidirectional port with internal pullups Port output buffers drive inputs Port pins that have written them pulled high internal pullups that state used inputs inputs Port pins that externally pulled will source current (IIL data sheet) because pullups Port also serves functions various special features 8051 Family listed below Port Alternate Function (serial input port) (serial output port) INT0 (external interrupt INT1 (external interrupt (Timer external input) (Timer external input) (external data memory write strobe) (external data memory read strobe)
DESCRIPTIONS
Supply voltage Circuit ground VSS1 Secondary ground (not DIP) Provided reduce ground bounce improve power supply by-passing NOTE This substitute (pin (Connection necessary proper operation Port Port 8-bit open drain bidirectional port output port each sink several inputs Port pins that have written them float that state used high-impedance inputs Port also multiplexed low-order address data during accesses external Program Data Memory this application uses strong internal pullups when emitting source sink several inputs Port also receives code bytes during EPROM programming outputs code bytes during program verification External pullup resistors required during program verification Port Port 8-bit bidirectional port with internal pullups Port output buffers drive inputs Port pins that have written them pulled high internal pullups that state used inputs inputs Port pins that externally pulled will source current (IIL data sheet) because internal pullups addition Port serves functions following special features 8XC5X Port Alternate Function (External Count Input Timer Counter Clock-Out T2EX (Timer Counter Capture Reload Trigger Direction Control)
Reset input high this machine cycles while oscillator running resets device port pins will driven their reset condition when minimum VIHI voltage applied whether oscillator running internal pulldown resistor permits power-on reset with only capacitor connected Address Latch Enable output pulse latching byte address during accesses external memory This (ALE PROG) also program pulse input during EPROM programming 87C5X normal operation emitted constant rate oscillator frequency used external timing clocking purposes Note however that pulse skipped during each access external Data Memory
Port receives low-order address bytes during EPROM programming verifying Port Port 8-bit bidirectional port with internal pullups Port output buffers drive inputs Port pins that have written them pulled high internal pullups that state used inputs inputs Port
8XC52
desired operation disabled setting location With this weakly pulled high However disable feature will suspended during MOVX MOVC instruction idle mode power down mode mode disable feature will terminated reset When disable feature suspended terminated will longer pulled weakly Setting ALE-disable affect microcontroller external execution mode Throughout remainder this data sheet will refer signal coming PROG will referred PROG PSEN Program Store Enable read strobe external Program Memory When 8XC5X executing code from external Program Memory PSEN activated twice each machine cycle except that PSEN activations skipped during each access external Data Memory External Access enable must strapped order enable device fetch code from external Program Memory locations 0000H 0FFFFH Note however that Lock bits programmed will internally latched reset should strapped internal program executions This also receives programming supply voltage (VPP) during EPROM programming XTAL1 Input inverting oscillator amplifier XTAL2 Output from inverting oscillator amplifier
272336
Crystals Ceramic Resonators contact resonator manufacturer
Figure Oscillator Connections drive device from external clock source XTAL1 should driven while XTAL2 floats shown Figure There requirements duty cycle external clock signal since input internal clocking circuitry through divide-by-two flip-flop minimum maximum high times specified data sheet must observed external oscillator encounter much load XTAL1 when starts This interaction between amplifier feedback capacitance Once external signal meets specifications capacitance will exceed
272336
Figure External Clock Drive Configuration
IDLE MODE
user's software invoke Idle Mode When microcontroller this mode power consumption reduced Special Function Registers onboard retain their values during Idle processor stops executing instructions Idle Mode will exited chip reset enabled interrupt occurs
OSCILLATOR CHARACTERISTICS
XTAL1 XTAL2 input output respectively inverting amplifier which configured on-chip oscillator shown Figure Either quartz crystal ceramic resonator used More detailed information concerning on-chip oscillator available Application Note AP-155 ``Oscillators Microcontrollers'' Order 230659
8XC52
Table Status External Pins during Idle Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External PSEN PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
POWER DOWN MODE
save even more power Power Down mode invoked software this mode oscillator stopped instruction that invoked Power Down last instruction executed on-chip Special Function Registers retain their values until Power Down mode terminated 8XC5X either hardware reset external interrupt cause exit from Power Down Reset redefines SFRs does change onchip external interrupt allows both SFRs on-chip retain their values properly terminate Power Down reset external interrupt should executed before restored normal operating level must held active long enough oscillator restart stabilize (normally less than With external interrupt INT0 INT1 must enabled configured level-sensitive Holding restarts oscillator bringing back high completes exit Once interrupt serviced next instruction executed after RETI will following instruction that device into Power Down
When idle mode terminated hardware
reset device normally resumes program execution from where left machine cycles before internal reset algorithm takes control On-chip hardware inhibits access internal this event access port pins inhibited eliminate possibility unexpected write when Idle terminated reset instruction following that invokes Idle should that writes port external memory
ONCE MODE
ONCE (``On-Circuit Emulation'') Mode facilitates testing debugging systems using 8XC5X without 8XC5X having removed from circuit ONCE Mode invoked Pull while device reset PSEN high Hold deactivated While device ONCE Mode Port pins float other port pins PSEN weakly pulled high oscillator circuit remains active While 8XC5X this mode emulator test used drive circuit Normal operation restored when normal reset applied
DESIGN CONSIDERATION
window D87C5X must covered
opaque label Otherwise characteristics device functionally impaired
NOTE more detailed information reduced power modes refer current Embedded Microcontrollers Processors Handbook Volume (Order 270645) Application Note AP-252 (Embedded Applications Handbook Order 270648) ``Designing with 80C51BH
8XC52
optional burn-in dynamic minimum time hours with following guidelines MIL-STD-883 Method 1015 Package types EXPRESS versions identified one- two-letter prefix part number prefixes listed Table extended temperature range option this data sheet specifies parameters which deviate from their commercial temperature range limits NOTE Intel offers Express Temperature specifications 8XC5X speed options except
8XC5X EXPRESS
Intel EXPRESS system offers enhancements operational specifications family microcontrollers These EXPRESS products designed meet needs those applications whose operating requirements exceed commercial standards EXPRESS program includes commercial standard temperature range with burn-in extended temperature range with without burn-in With commercial standard temperature range operational characteristics guaranteed over temperature range With extended temperature range option operational characteristics guaranteed over range
Table Prefix Identification Prefix Package Type Plastic Cerdip PLCC Plastic Cerdip PLCC Plastic Cerdip PLCC Temperature Range Commercial Commercial Commercial Commercial Extended Extended Extended Extended Extended Extended Extended Extended Burn-In
NOTE Contact distributor local sales office match EXPRESS prefix with proper device EXAMPLES P80C52 indicates 80C52 plastic package specified commercial temperature range without burn-in TD80C52 indicates 80C52 Cerdip package specified extended temperature range without burn-in
8XC52
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias Storage Temperature Voltage Voltage Other
NOTICE This data sheet contains preliminary information products production specifications subject change without notice Verify with your local Intel Sales office that have latest data sheet before finalizing design
Power Dissipation (based PACKAGE heat transfer limitations device power consumption)
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
OPERATING CONDITIONS
Symbol Description Ambient Temperature Under Bias Commercial Express Supply Voltage 8XC5X-33 Oscillator Frequency 8XC5X 8XC5X-1 8XC5X-2 8XC5X-24 8XC5X-33
Units
fOSC
CHARACTERISTICS
Symbol VIL1 VIH1 Parameter Input Voltage Input Voltage Input High Voltage (Except XTAL1 RST) Input High Voltage (XTAL1 RST)
(Over Operating Conditions) parameter values apply devices unless otherwise indicated
(Note
Unit
Test Conditions
Output Voltage (Note (Ports
(Note (Note (Note (Note (Note (Note
VOL1
Output Voltage (Note (Port PSEN)
Output High Voltage (Ports PSEN)
8XC52
CHARACTERISTICS
Symbol VOH1
(Over Operating Conditions) (Continued) parameter values apply devices unless otherwise indicated Parameter Output High Voltage (Port External Mode) Logical Input Current (Ports Input leakage Current (Port Logical Transition Current (Ports Commercial Express Pulldown Resistor Capacitance Power Supply Current Active Mode (Figure (8XC5X-33) Idle Mode (Figure (8XC5X-33) Power Down Mode 8XC5X-33
(Note
Unit
Test Conditions
RRST
(Note
NOTES Capacitive loading Ports cause noise pulses above superimposed VOLs Ports noise external capacitance discharging into Port Port pins when these pins change from applications where capacitive loading exceeds noise pulses these signals exceed desirable qualify other signals with Schmitt Triggers CMOS-level input logic Capacitive loading Ports cause PSEN drop below specification when address lines stabilizing Figures test conditions Minimum Power Down Typicals based limited number samples guaranteed values listed room temperature Under steady state (non-transient) conditions must externally limited follows 10mA Maximum port Maximum 8-bit port Port Ports Maximum total output pins exceeds test condition exceed related specification Pins guaranteed sink current greater than listed test conditions
8XC52
272336
NOTE while below
Figure 8XC52 Frequency
272336 other pins disconnected TCLCH TCHCL
Figure Test Condition Active Mode
8XC52
272336 other pins disconnected TCLCH TCHCL other pins disconnected
272336
Figure Test Condition Idle Mode
Figure Test Condition Power Down Mode
272336
Figure Clock Signal Waveform Tests Active Idle Modes TCLCH TCHCL
8XC52
Logic level PSEN Output Data signal Time Valid signal longer valid logic level Float example TAVLL Time from Address Valid TLLPL Time from PSEN
EXPLANATION SYMBOLS
Each timing symbol characters first character always (stands time) other characters depending their positions stand name signal logical status that signal following list characters what they stand Address Clock Input Data Logic level HIGH Instruction (program memory contents)
CHARACTERISTICS
(Over Operating Conditions Load Capacitance Port PROG PSEN Load Capacitance Other Outputs
EXTERNAL MEMORY CHARACTERISTICS
parameter values apply devices unless otherwise indicated this table 8XC5X refers 8XC5X 8XC5X-1 8XC5X-2 Oscillator Symbol Parameter TCLCL Variable Units
TCLCL Oscillator Frequency 8XC5X 8XC5X-1 8XC5X-2 8XC5X-24 8XC5X-33 TLHLL TAVLL Pulse Width Address Valid 8XC5X 8XC5X-24 8XC5X-33 Address Hold After 8XC5X 8XC5X-33 Valid Instruction 8XC5X 8XC5X-24 8XC5X-33
TCLCL TCLCL TCLCL
TLLAX
TCLCL TCLCL
TLLIV
TCLCL TCLCL TCLCL
8XC52
EXTERNAL MEMORY CHARACTERISTICS (Continued) parameter values apply devices unless otherwise indicated
Oscillator Symbol Parameter TLLPL PSEN 8XC5X 8XC5X-33 PSEN Pulse Width PSEN Valid Instruction 8XC5X 8XC5X-24 8XC5X-33 Input Instruction Hold After PSEN Input Instruction Float After PSEN 8XC5X 8XC5X-24 8XC5X-33 Address Valid Instruction 8XC5X 8XC5X-33 PSEN Address Float Pulse Width Pulse Width Variable Units
TCLCL TCLCL TCLCL
TPLPH TPLIV
TCLCL TCLCL TCLCL
TPXIX
TPXIZ
TCLCL TCLCL TCLCL
TAVIV
TCLCL TCLCL
TPLAZ
TRLRH TWLWH
TCLCL TCLCL
8XC52
EXTERNAL MEMORY CHARACTERISTICS (Continued) parameter values apply devices unless otherwise indicated
Oscillator Symbol Parameter Variable Units
TRLDV Valid Data 8XC5X 8XC5X-24 8XC5X-33 Data Hold After Data Float After 8XC5X 8XC5X-33 Valid Data 8XC5X 8XC5X-24 Address Valid Data 8XC5X 8XC5X-24 Address 8XC5X 8XC5X-24 8XC5X-33
TCLCL TCLCL TCLCL
TRHDX TRHDZ
TCLCL TCLCL
TLLDV
TCLCL TCLCL
TAVDV
TCLCL
TCLCL TCLCL TCLCL
TLLWL TAVWL
TCLCL TCLCL TCLCL
8XC52
EXTERNAL MEMORY CHARACTERISTICS (Continued) parameter values apply devices unless otherwise indicated
Oscillator Symbol Parameter TQVWX Data Valid Transition 8XC5X 8XC5X-24 Data Hold After 8XC5X 8XC5X-24 8XC5X-33 Data Valid High 8XC5X 8XC5X-24 Address Float High High 8XC5X 8XC5X-24 8XC5X-33 Variable Units
TCLCL TCLCL
TWHQX
TCLCL TCLCL TCLCL
TQVWH
TCLCL TCLCL
TRLAZ TWHLH
TCLCL TCLCL TCLCL
TCLCL TCLCL TCLCL
8XC52
EXTERNAL PROGRAM MEMORY READ CYCLE
272336
EXTERNAL DATA MEMORY READ CYCLE
272336
EXTERNAL DATA MEMORY WRITE CYCLE
272336
8XC52
SERIAL PORT TIMING SHIFT REGISTER MODE Test Conditions
Symbol
Over Operating Conditions Load Capacitance
Oscillator
Parameter
TCLCL
Variable
Units
TXLXL
Serial Port Clock Cycle Time Output Data Setup Clock Rising Edge Output Data Hold after Clock Rising Edge 8XC5X 8XC5X-24 Input Data Hold After Clock Rising Edge Clock Rising Edge Input Data Valid
TQVXH
TCLCL
TXHQX
TCLCL TCLCL
TXHDX
TXHDV
TCLCL
SHIFT REGISTER MODE TIMING WAVEFORMS
272336
8XC52
EXTERNAL CLOCK DRIVE
Symbol TCLCL Parameter Oscillator Frequency 8XC5X 8XC5X-1 8XC5X-2 8XC5X-24 8XC5X-33 High Time 8XC5X-24 Time 8XC5X-24 Rise Time 8XC5X-24 8XC5X-33 Fall Time 8XC5X-24 8XC5X-33 TOSC TOSC TOSC TOSC Units
TCHCX TCLCX TCLCH
TCHCL
EXTERNAL CLOCK DRIVE WAVEFORM
272336
TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272336 Inputs during testing driven Logic ``1'' Logic ``0'' Timing measurements made Logic ``1'' Logic ``0''
272336 timing purposes port longer floating when change from load voltage occurs begins float when change from loaded level occurs
8XC52
PROGRAMMING EPROM
part must running with oscillator address EPROM location programmed applied address lines while code byte programmed that location applied data lines Control program signals must held levels indicated Table Normally held logic high until just before PROG pulsed raised PROG pulsed then returned high (also refer timing diagrams) NOTES
DEFINITION TERMS
ADDRESS LINES respectively DATA LINES CONTROL SIGNALS PSEN PROGRAM SIGNALS PROG
Exceeding maximum amount
time could damage device permanently source must well regulated free glitches Table EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address Program Lock Bits Read Signature Byte PSEN PROG
8XC52
272336
Table proper input these pins
Figure Programming EPROM
PROGRAMMING ALGORITHM
Refer Table Figures address data control signals program 87C5X following sequence must exercised Input valid address address lines Input appropriate data byte data lines Activate correct combination control signals Raise from Pulse PROG times EPROM array times encryption table lock bits
Repeat through changing address data entire array until object file reached
PROGRAM VERIFProgram verify done after each byte block bytes programmed either case complete verify programmed array will ensure reliable programming 87C5X lock bits cannot directly verified Verification lock bits done observing that their features enabled
272336
Figure Programming Signal's Waveforms
8XC52
Erasing EPROM also erases encryption array program lock bits returning part full functionality
EPROM Lock System
program lock system when programmed protects onboard program against software piracy 80C5X one-level program lock system 64-byte encryption table line Table program protection desired user submits encryption table with their code both lock-bit encryption array programmed factory encryption array available without lock lock programmed user must submit encryption table 87C5X 3-level program lock system 64-byte encryption array Since this EPROM device locations user-programmable Table
Reading Signature Bytes
8XC5X signature bytes locations read these bytes follow procedure EPROM verify activate control lines provided Table Read Signature Byte Location Device 80C52 87C52 Contents
Encryption Array
Within EPROM array bytes Encryption Array that initially unprogrammed (all 1's) Every time that byte addressed during verify address lines used select byte Encryption Array This byte then exclusive-NOR'ed (XNOR) with code byte creating Encryption Verify byte algorithm with array unprogrammed state (all 1's) will return code original unmodified form programming Encryption Array refer Table (Programming EPROM) When using encryption array important factor needs considered code byte value 0FFH verifying byte will produce encryption byte value large block bytes) code left unprogrammed verification routine will display contents encryption array this reason unused code bytes should programmed with some value other than 0FFH them same value This will ensure maximum program protection
80C54 87C54 80C58 87C58
Erasure Characteristics (Windowed Packages Only)
Erasure EPROM begins occur when chip exposed light with wavelength shorter than approximately Angstroms Since sunlight fluorescent lighting have wavelengths this range exposure these light sources over extended time (about week sunlight years roomlevel fluorescent lighting) could cause inadvertent erasure application subjects device this type exposure suggested that opaque label placed over window recommended erasure procedure exposure ultraviolet light 2537 Angstroms) integrated dose least W-sec Exposing EPROM ultraviolet lamp rating minutes distance about inch should sufficient Erasure leaves EPROM Cells state
Program Lock Bits
87C5X programmable lock bits that when programmed according Table will provide different levels protection on-chip code data
8XC52
Table Program Lock Bits Features Program Lock Bits Protection Type Program Lock features enabled (Code verify will still encrypted Encryption Array programmed MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory sampled latched Reset further programming EPROM disabled Same also verify disabled Same also external execution disabled
NOTE other combination lock bits defined
EPROM PROGRAMMING VERIFICATION CHARACTERISTICS
Symbol TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup PROG Address Hold after PROG Data Setup PROG Data Hold after PROG (Enable) High Setup PROG Hold after PROG PROG Width Address Data Valid ENABLE Data Valid Data Float after ENABLE PROG High PROG 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL Units
8XC52
EPROM PROGRAMMING VERIFICATION WAVEFORMS
272336
pulses EPROM array pulses encryption table lock bits
Thermal Impedance
thermal impedance data approximate static conditions power dissipation Values will change depending operating conditions applications Intel Packaging Handbook (Order Number 240800) description Intel's thermal impedance test methodology Package Device
following differences exist between this datasheet (272336-003) previous version (272336-002) Removed 8XC5X-3 8XC5X-20 from data sheet Included 8XC5X-24 8XC5X-33 devices Removed statement ``The 80C32 standard 80C52 standard have from section DESIGN CONSIDERATION following differences exist between this datasheet (272336-002) previous version (272336-001) Removed 8XC5X-L from data sheet Included features available 80C32-Standard 80C52-Standard devices This 8XC5X datasheet (272336-001) replaces following datasheets 87C52 80C52 80C32 87C52 80C52 80C32 EXPRESS 87C52-20 80C52-20 80C32-20 87C54 80C54 87C54 80C54 EXPRESS 87C54-20 80C54-20 87C54 80C58 87C58 80C58 EXPRESS 87C58-20 80C58-20 270757-003 270868-002 272272-001 270816-004 270901-001 270941-003 270900-003 270902-001 272029-002
DATA SHEET REVISION HISTORData sheets changed device information becomes available Verify with your local Intel sales office that have latest version before finalizing design ordering devices
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