1024-Mbit Family Device Architecture Flash density: 128-, 256-Mbi
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Intel Wireless Memory System (LV18/LV30 SCSP)
1024-Mbit Family
Device Architecture Flash density: 128-, 256-Mbit Bottom flash parameter configuration Device Voltage Core: (Typ) I/O: VCCQ (Typ) Device Common Performance Buffered EFP: Byte (Typ) Buffer Program: Byte (Typ) Concurrent Program: 4.5-Mbit second (4-dies) Device Common Architecture Asymmetrical blocking structure 16-KWord parameter blocks (Top Bottom); 64-KWord main blocks Zero-latency block locking Absolute write protection with block lock down using F-WP# Device Packaging balls active ball matrix) device balls active ball matrix) device. Area: Height:
Code Segment Flash Performance initial access async page read sync reads (tCHQV) Data Segment Flash Performance initial access async page read Code Segment Flash Architecture Hardware Read-While-Write/Erase Multiple 8-Mbit 16-Mbit Partition Sizes 2-Kbit One-Time Programmable (OTP) protection register Data Segment Flash Architecture Software Read-While-Write/Erase Single Partition Size Flash Software FDI, PSM, Common Flash Interface (CFI) Basic/Extended Command Quality Reliability Extended Temp: Minimum flash block erase cycle 0.13 VIII flash technology
Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP) family offers variety high performance code segment large embedded data segment combination flash dies common package footprints ballouts 0.13 ETOXVIII flash technology. code segment flash features low-power operations with flexible multi-partitions, dual operation Read-While-Write/Erase, asynchronous synchronous reads MHz. data segment flash features low-power operations optimized cost sensitive large asynchronous embedded data application. device integrates code segment flash dies data segment flash dies compatible with other LQ/LVQ LX/LVX SCSP family ballout packages.
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
253854-001 October 2003
INFORMATION THIS DOCUMENT PROVIDED CONNECTION WITH INTEL® PRODUCTS. LICENSE, EXPRESS IMPLIED, ESTOPPEL OTHERWISE, INTELLECTUAL PROPERTY RIGHTS GRANTED THIS DOCUMENT. EXCEPT PROVIDED INTEL'S TERMS CONDITIONS SALE SUCH PRODUCTS, INTEL ASSUMES LIABILITY WHATSOEVER, INTEL DISCLAIMS EXPRESS IMPLIED WARRANTY, RELATING SALE AND/OR INTEL PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit Family contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2003. *Other names brands claimed property others.
Contents
Contents
Introduction.7 Nomenclature Acronyms Conventions.9 Device Description Two-Die UT-SCSP Three-Die UT-SCSP Signal Descriptions Absolute Maximum Ratings Operating Conditions Current Characteristics Voltage Characteristics.21 Test Conditions.23 Capacitance Read Specifications Write Specifications Program Erase Characteristics Power-Up Down.36 Reset Power Supply Decoupling.38 Automatic Power Saving (APS) Operations 9.1.1 Reads 9.1.2 Writes.40 9.1.3 Output Disable 9.1.4 Standby.41 9.1.5 Reset Flash Device Commands.41 Command Definitions Asynchronous Page-Mode Read
Functional Overview Package Information
Ballout Signal Descriptions Maximum Ratings Operating Conditions.18
Electrical Specifications
Characteristics
Power Reset Specifications
Design Guide: Operation Overview
10.1
10.0 Read Operation
Contents
10.2 10.3 10.4 10.5 10.6 10.7
Synchronous Burst-Mode Read (Code Segment) 10.2.1 Burst Suspend Read Array Command (0xFF) Read Status Register Command (0x70). Clear Status Register Command (0x50). Read Flash Device Identifier Command (0x90). Query Command (0x98)
11.0 Program Operation. 11.1 11.2 11.3 11.4 11.5 Word Program Setup Command (0x40) 11.1.1 Factory Word Programming. Buffered Program Setup Command (0xE8). Buffered Program Confirm Command (0xD0) Buffered Setup Command (0xE8). Buffered Confirm Command (0xD0) 11.5.1 Buffered Setup Phase. 11.5.2 Buffered Program/Verify Phase 11.5.3 Buffered Exit Phase Program Protection. Block Erase Setup Command (0x20) Block Erase Confirm Command (0xD0). Erase Suspend Command (0xB0) Program Suspend Command (0xB0). Program Resume Command (0xD0) Erase Resume Command (0xD0). Block Locking During Erase Suspend 14.1.1 F-WP# Lock-Down Control Lock Block Setup Command (0x60) Unlock Block Command (0xD0). Lock-Down Block Command (0x2F) Reading Protection Registers Program Protection Register Setup Command (0xC0). 15.2.1 Locking Protection Registers
11.6 12.1 12.2 13.1 13.2 13.3 13.4 14.1 14.2 14.3 14.4 15.1 15.2
12.0 Erase Operation.
13.0 Suspend Resume Operations
14.0 Block Locking Unlocking Operations
15.0 Protection Register Operation
16.0 Configuration Operation 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Read Mode Bit- RCR[15] Latency Count RCR[13:11] WAIT Polarity RCR[10]. 16.3.1 WAIT Signal Function Data Hold RCR[9]. WAIT Delay RCR[8] Burst Sequence RCR[7] Clock Edge RCR[6]
Contents
16.8 16.9 16.10 16.11
Burst Wrap RCR[3].73 Burst Length RCR[2:0] Read Configuration Register Command (0x60) Write Read Configuration Register Command (0x03)
17.0 Dual Operation Considerations.74 17.1 17.2 17.3 17.4 17.5 17.6 17.7 Product Configurations Memory Partitioning Product segment unique features.77 Memory Consecutive Back-to-Back Cycle Operations Read during Buffered Program Operation Simultaneous Operation Restrictions Simultaneous Operation Details
Appendix Write State Machine (WSM) Code Segment (TBD). Appendix Write State Machine (WSM) Data Segment (TBD). Appendix Flowcharts. Appendix Common Flash Interface (CFI) Code Segment. Appendix Common Flash Interface (CFI) Data Segment Appendix Additional Information. Appendix Ordering Information.
Contents
Revision History
Date 10/03 Revision -001 Initial release. Description
1024-Mbit Family
Introduction
This document provides preliminary information about Intel StrataFlash® wireless memory system (LV18/LV30 SCSP), 1024-Mbit family. This document describes only high performance code large embedded data segments flash features, operations, specifications within subsystem.
Nomenclature
Volt Core: Volt I/O: Asserted: Deasserted: High-Z: Low-Z: Non-Array Reads: Program: Write: Block: Parameter block: Main block: parameter: (core) voltage range VCCQ (Input/Output) voltage range Signal with logical voltage level VIL, enabled. Signal with logical voltage level VIH, disabled. High Impedance. Driven Flash reads which return flash Device Identifier, Query, Protection Register Status Register information. operation Write data flash array. cycle operation inputs flash die, which command data sent flash array. Group cells, bits, bytes words within flash memory array that erased with erase instruction. 16-Kword flash array block. 64-Kword flash array block. Previously referred top-boot device, device with flash parameter partition located highest physical address memory processor system boot Previously referred bottom-boot device, device with flash parameter partition located lowest physical address memory processor system boot group flash blocks that shares common status register read state. flash partition containing parameter main blocks. flash partition containing only main blocks. Individual physical flash used stacked chip scale package memory device.
Bottom parameter:
Partition: Parameter partition: Main partition: Die:
1024-Mbit Family
Segment:
section stacked chip scale package memory device divided different operating characteristics. stacked memory device have three segments: flash code segment, flash data segment, xRAM segment. segment that contains flash memory dies optimized high performance code data reads. Each features multi-partitions synchronous read-while-write burst read-while-erase capability. segment contains flash memory dies optimized large embedded data storage. Each feature single-partition asynchronous read, write, erase operations. segment contains three xRAM memory dies. xRAM segment could include SRAM, PSRAM LPSDRAM. stacked memory integration concept made multiple memory dies arranged Code, Data, xRAM segments. specific stacked flash xRAM memory density configuration combination within memory system product family.
Code segment:
Data segment:
xRAM segment: (Memory) System: Device:
Acronyms
Buffered EFP: CUI: OTP: PLR: RCR: RFU: WSM: APS: CFI: technology: RWE: RWW: Buffered Enhanced Factory Programming Command User Interface One-Time Programmable Protection Lock Register Protection Register Read Configuration Register Reserved Future (all unused active signals package ballout) Status Register Write State Machine Automatic Power Savings Command Flash Interface Multi-Level-Cell technology Read-While-Erase Read-While-Write
1024-Mbit Family
Conventions
VCC: VCC: Set: Clear: SR[4]: D[15:0]: F1-CE#: Signal voltage connection Signal voltage level Logical Logical zero Hexadecimal number prefix. Binary number prefix. Denotes individual flash status register bit, this case status register SR[7:0]. Denotes group similarly named signals, such data bus. Denotes element signal group membership, this case address Denotes Chip Enable flash where denote flash specific signal suffix "CE#" root signal name flash die. Other notation includes: denote SRAM, denote PSRAM, denote LPSDRAM, denote common type signal names. Denotes global power signal stacked device, common memory dies within stacked memory device. Binary unit, valid range Eight bits, valid range [0x00 0xFF] bytes sixteen bits, valid range [0x0000 0xFFFF] 1024 bits 1024 bytes (8,192 bits) 1024 words (16,384 bits) 1,048,576 bits 1,048,576 bytes (8,388,608 bits) 1,073,741,824 bits
VSS: bit: byte: word: Kbit: KByte: Kword: Mbit: MByte: Gbit:
1024-Mbit Family
Functional Overview
This section provides overview features capabilities LV18/LV30 SCSP family 16-bit configuration. intent this document provide information describing high performance code large embedded data segments flash features, operations, specifications within memory system. xRAM segment details described following datasheets:
Intel Wireless Memory System (LV18/LV30 SCSP); 768-Mbit Family with
Asynchronous Static (document number 253852).
Intel Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit Family with
Dynamic (document number 253853).
Device Description
Intel StrataFlash® wireless memory system (LV18/LV30 SCSP) family incorporates Intel fourth generation Multi-Level Cell (MLC) 0.13 ETOXVIII process technology provide power, high performance code execution large embedded data solution. SCSP device comprised stacked high performance code segment flash dies, large embedded data segment dies cost-sensitive data storage, xRAM segment dies. high performance code segment multi-partition, synchronous burst-mode Read-WhileWrite (RWW) Read-While-Erase (RWE) Intel StrataFlash® wireless memory die. large embedded data segment single partition, asynchronous Intel StrataFlash® wireless memory optimized cost-sensitive large embedded data storage applications. family available common device package footprints ballouts: QUAD+ Performance, seamless upgrades through Gigabit densities. QUAD+ ballout supports flash-only flash PSRAM and/or SRAM stacked memory combinations within device family. QUAD+ ballout ball pitch, 8x10 active ball matrix supporting memory system x16-bit bus. Figure "LVQ device family block diagram" page stacked device block diagram. Performance ballout supports flash-only, flash Synchronous PSRAM, flash LPSDRAM stacked memory combinations within device family. Performance ballout ball pitch, 9x12 active ball matrix supporting memory system with 100+ x16-bit bus.
1024-Mbit Family
Figure device family block diagram
Family
Code Segment F1-CE# F-WE# F[2:1]-OE# F-RST# F3-CE#
Flash (128- 256-Mbit)
Data Segment
Flash (128- 256-Mbit)
F2-CE# F-VCC F-VPP
Optional Flash (128- 256-Mbit)
Optional Flash (128- 256-Mbit)
F3-CE#
F-WP# ADV# WAIT S-CS1# S-CS2 P[2:1]-CS# R-OE# R-WE#
128Mbit PSRAM 128-Mbit PSRAM 8-Mbit SRAM
VCCQ A[MAX:MIN] D[15:0] xRAM Segment S-VCC P-VCC R-UB# R-LB# P-MODE P-CRE
NOTE: Optional Flash either code data die.
Note:
block diagram family development will available soon. family volt flash core device (F-VCC) with common 1.8-volt 3.0-volt (VCCQ) options. SCSP device available with least code segment flash data segment flash die. SCSP device maximum flash dies code segment flash dies data segment. Table "1024-Mbit Family Matrix (Flash only)" page available combinations. Designed low-voltage systems, SCSP device supports flash read operations with F-VCC volt, erase program operations with F-VPP 1.8- 9.0-volt. Buffered Enhanced Factory Programming (Buffered EFP) provides fastest flash array programming performance throughput. With F-VPP volt, F-VCC F-VPP tied together simple, ultra-lowpower design. addition voltage flexibility, dedicated F-VPP connection provides complete data protection when F-VPP VPPLK. SCSP device provides data security through individual zero-latency flash block lock capability. Each flash block unlocked, locked, locked-down hardware and/or software control. Individualized F-CE# control allows user manage which flash enabled, furthering flexibility power management while controlling data integrity segment with F-WP#.
1024-Mbit Family
Note:
Individualized flash Write Protect (F-WP#[2:1]) each segment available only products. Flash Write Protect (F-WP#) shared between code data segments products. addition, product with Performance ballout global signal flash xRAM dies within stacked device. products with QUAD+ ballout, F[2:1]OE# common within stacked device
Table
Family
1024-Mbit Family Matrix (Flash only)
Voltage 256L18 256V18 256V18 256V30 256V30 256V30 256V18 256V18 256V30 256V30 8x11x1.2 8x11x1.2 8x11x1.2 11x11x1.4 11x11x1.4 UT-SCSP UT-SCSP UT-SCSP UT-SCSP Code segment flash 256L18 Data segment flash 256V18 Package Size 8x11x1.2 Package Type Notes
256L30 256L30 256L30 256L30 NOTES: Available bottom parameter configuration. Refer Table Flash Code Data Stacked Configuration" page parameter configuration specifics. Combination using Intel® Ultra-Thin Stacked Chip Scale Package. off-line programmer, programmer socket required with Intel® UT-SCSP package socket contact technology change. 256L18 256L18
1024-Mbit Family
Package Information
family available various combinations Intel® Ultra-Thin Stacked Chip Scale Package (Intel® UT-SCSP).
Two-Die UT-SCSP
Figure Mechanical Specifications Two-Die Intel® UT-SCSP (8x11
Index Mark
View Ball Down
Bottom View Ball
Draw scale.
Dimensions ckage Height Ball Height ckage Body Thickne Ball (Lead) Width ckage Body Length ckage Body Width Pitch Ball (Lead) Count ating Plane Coplanarity Corne Ball Distance Along Corne Ball Distance Along
Symbol
0.200 0.325 10.900 7.900
Millimete 1.200 0.860 0.375 11.000 8.000 0.800 1.200 1.100
Notes
0.0079
Inches
0.0472
0.425 11.100 8.100
0.0128 0.4291 0.3110
0.0339 0.0148 0.4331 0.3150 0.0315 0.0472 0.0433
0.0167 0.4370 0.3189
1.100 1.000
0.100 1.300 1.200
0.0433 0.0394
0.0039 0.0512 0.0472
1024-Mbit Family
Three-Die UT-SCSP
Figure Mechanical Specifications Three-Die Intel® UT-SCSP (8x11
Index Mark
View Ball Down
Bottom View Ball
Draw scale.
Note:DimensionsA1, A2,andb arepreliminary
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along Symbol 0.117 0.300 10.900 7.900 0.910 0.350 11.00 8.00 0.80 1.200 1.100 0.400 11.100 8.100 Millimeters 1.20 Notes 0.0046 0.0118 0.4291 0.3110 0.0358 0.0138 0.4331 0.3150 0.0315 0.0472 0.0433 0.0157 0.4370 0.3189 Inches 0.0472
1.100 1.000
0.100 1.300 1.200
0.0433 0.0394
0.0039 0.0512 0.0472
Note:
package information four-die UT-SCSP device will available soon.
1024-Mbit Family
Ballout Signal Descriptions
1024-Mbit family devices available common ballouts: QUAD+ Performance, shown Figure "QUAD+ Signal Ballout Device Family. Note: ballout development will available soon.
Figure QUAD+ Signal Ballout Device Family
F1-VCC F2-VCC
R-LB# S-CS2
F-VPP, F-VPEN R-WE# P1-CS#
F-WP# ADV#
R-UB# F-RST# F-WE#
WAIT F2-CE#
R-OE# F2-OE#
S-CS1# F1-OE# VCCQ
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE
VCCQ F1-VCC
View Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific
1024-Mbit Family
Signal Descriptions
Table describes individual flash active signals used 1024-Mbit Family.
Table
Symbol
Signal Descriptions (Sheet
Type ADDRESS: Global device signals. Address inputs memory dies during read write operations data bus. device family: Flash address range: 128-Mbit: A[22:0]; 256-Mbit: A[23:0]; where A[0] AMIN lowest-order address bit. device family: Flash address range: 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; where A[1] AMIN lowest-order address bit. A[0] ball populated Performance ballout. Unused High-order addresses reserved future device densities. DATA INPUT/OUTPUT: Global device signals. Input/ Output Inputs data commands during write cycles, outputs data during read cycles. Data signals float when device outputs deselected. Data internally latched during writes flash device. DEVICE ADDRESS VALID: Low-true input. During synchronous flash read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. asynchronous flash read operations, addresses latched rising edge ADV#, continuously flow-through when ADV# kept asserted. CHIP ENABLE: Flash specific signal. Low-true input. F[4:1]-CE# selects associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, sense amplifiers active. When deasserted, associated flash deselected, power reduced standby levels, data WAIT outputs placed high-Z state. Name Function Notes
A[MAX:MIN]
Input
D[15:0]
ADV#
Input
F[4:1]-CE#
Input
devices: F1-CE# selects code segment flash F2-CE# selects data segment flash F3-CE# selects flash code data option. (There flash #4). devices: F1-CE# selects code segment flash F2-CE# selects data segment flash F[4:3]-CE# select flash flash code data option respectively. CLOCK: Synchronizes flash with memory clock synchronous read mode increments internal address generator.
CLK, F-CLK
Input
During synchronous flash read operations, addresses latched next valid edge with ADV# low. used only within device family. F-CLK used only within device family. OUTPUT ENABLE: Low-true input. F[2:1]-OE# enables flash output buffers. F[2:1]-OE# high disables flash output buffers, places selected flash outputs WAIT High-Z.
OE#, F-OE# F[2:1] Input
devices, F1-OE# controls outputs flash F2-OE# controls outputs flash flash F2-OE# available stacked combinations with three flash stacked combinations with only flash die. devices, global signal. RESET: Flash specific signal. Low-true input.
F-RST#
Input
F-RST# initializes flash internal circuitry disables flash operations. F-RST# high enables flash operation. Exit from reset places flash dies asynchronous read array mode.
1024-Mbit Family
Table
Symbol
Signal Descriptions (Sheet
Type Name Function DEVICE WAIT: Seletable high-true low-true output. Notes
WAIT
Output
During synchronous-burst reads (array non-array), WAIT-asserted indicates invalid read data. During asynchronous-page reads writes, WAIT deasserted. Wait High-Z whenever F-CE# deasserted. WRITE ENABLE: Low-true input. F-WE# controls write operations selected flash die. Address data latched rising edge F-WE#. WRITE PROTECT: Low-true input. F-WP# controls lock-down protection mechanism selected flash die. When low, FWP# enables lock-down mechanism where locked down blocks cannot unlocked with software commands. When high, F-WP# disables lock-down mechanism, allowing locked down blocks unlocked with software commands. devices, F-WP# shared between code data segment flash dies. devices, F-WP#1 controls code segment flash while F-WP#2 controls subsequent code data segment flash dies. ERASE/ PROGRAM VOLTAGE LEVEL: Valid F-VPP voltage this ball enables flash program/erase operations. Flash memory array contents cannot altered when F-VPP VPPLK. Erase program operations invalid F-VPP voltages should attempted. FLASH CORE VOLTAGE Flash core source voltage. Write operations flash array inhibited when VLKO. Operations invalid voltages should attempted.
F-WE#
Input
F-WP#, F-WP#[2:1]
Input
F-VPP
Power
F-VCC
Power
devices, F1-VCC supplies power core logic flash F2-VCC supplies power core logic flash flash F2-VCC available stacked combinations with three flash dies, stacked combinations with only flash die. devices, F-VCC supplies power flash cores. OUTPUT VOLTAGE: Supply power device input output buffers. GROUND: Connect system ground. float connection. USE: connect other signal, power supply; must left floating. RESERVED FUTURE USE: Reserved future device functionality/ enhancements. Contact Intel regarding balls designated RFU.
VCCQ
Power Power
1024-Mbit Family
Warning: Table
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Absolute Maximum Ratings
Parameter Case Temperature under bias Storage temperature Voltage signal (except VCC, VPP) voltage voltage VCCQ voltage (for Volt option) VCCQ voltage (for Volt option) Output short circuit current Maximum Rating -25°C +85°C -65°C +125°C -0.5V +3.8V -0.2V +10V -0.2V +2.5V -0.2V +2.5V -0.2V +3.8V 1,2,3 Notes
NOTES: Voltages shown specified with respect VSS. Minimum voltage -0.5 input/output signals -0.2 VCC, VCCQ, VPP. During transitions, this level undershoot -2.0 periods Maximum voltage +0.5 which, during transitions, overshoot periods Maximum voltage input/output signals VCCQ VCCQ +0.5 which, during transitions, overshoot VCCQ +2.0 periods Maximum voltage overshoot +10.0 periods Program/erase voltage typically V-1.95 Additionally, applied hours maximum total, blocks 1000 cycles maximum. program/erase voltage reduce block cycling capability. Output shorted more than second. more than output shorted time.
1024-Mbit Family
Operating Conditions
Operating conditions flash-only, SCSP combination shown Table "Operating Conditions" page
Warning: Table
Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability. Operating Conditions
Symbol VCCQ VCCQ VPPL VPPH tPPH Block Erase Cycles Operating Temperature Supply Voltage Volt Supply Voltage option Volt Supply Voltage option Voltage Supply (Logic Level) Factory word programming Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks VPPH VPPH VPPH 100,000 1000 2500 Cycles Parameter Hours Units Notes
NOTES: VCCQ operation range flash only stacked 1.7V 2.0V. VCCQ 2.0V limitation xRAM (SRAM, PSRAM, LPSDRAM) VCCQ specification limit 1.7V 2.0V. typical operation, program voltage VPPL. connected 8.50 1000 cycles main blocks, 2500 cycles parameter blocks.
1024-Mbit Family
Electrical Specifications
Current Characteristics
current characteristics shown Table individual code data segment flash dies within SCSP device. SCSP device total current additive each flash die.
Table
Current Characteristics (Sheet
VCCQ Parameter VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCMax VCCQ VCCQMax F-CE# VCCQ F-RST# VCCQ (for ICCS) F-RST# (for ICCD) F-WP# VCCQ VCCQ F-CE# VSSQ F-RST# VCCQ inputs rail rail (VCCQ VSSQ). Asynchronous Single-Word 5MHz CLK) Page-Mode Read CLK) Synchronous Burst Read 40MHz, 4-Word Read Burst length=4 Burst length=8 Burst length=16 Burst length Continuous Burst length=4 Burst length=8 Burst length=16 Burst Length Continuous F-CE# Inputs: Unit Test Conditions Notes
Input Load Current Output Leakage Current
D[15:0], WAIT Mbit
ICCS ICCD
Standby, Power Down Mbit
Mbit ICCAPS
Mbit
ICCR
Average Read Current
Synchronous Burst Read f=54MHz, LC=4, 1.8V f=52MHz, LC=4, 3.0V
1024-Mbit Family
Table
Current Characteristics (Sheet
VCCQ Parameter 0.05 0.10 0.10 0.05 0.05 0.10 0.05 0.10 VPPH, program progress VPPL, erase progress VPPH, erase progress VPPL, program/erase progress VPPH, program/erase progress F-CE# VCCQ; suspend progress VPPL, suspend progress VPPL, program progress 1,3,4, 1,3,5, 1,6,3 Unit Test Conditions Notes
ICCW, ICCE
Program Current, Erase Current
ICCWS, Program Suspend Current, Mbit ICCES IPPS,
IPPES
Erase Suspend Current Standby Current, Erase Suspend Current Read
Mbit
IPPWS, Program Suspend Current, IPPR
IPPW
Program Current
IPPE
Erase Current
NOTES: currents unless noted. Typical values typical VCC, +25°C. ICCS average current measured over time interval after F-CE# deasserted. Sampled, 100% tested. read program current read program currents. read erase current read erase currents. ICCES specified with device deselected. device read while erase suspend, current ICCES plus ICCR ICCW, ICCE measured over typical times specified Section 7.5, "Program Erase Characteristics" page
Voltage Characteristics
Table
Voltage Characteristics (Sheet
VCCQ Parameter VCCQ VCCQ -0.1 VCCQ -0.1 VCCQ -0.4 VCCQ VCCMIN VCCQ VCCQMIN VCCMIN VCCQ VCCQMIN -100 2.0V Unit VCCQ -0.4 Test Condition Notes
Input Voltage Input High Voltage
Output Voltage
VPPLK
Output High Voltage Lock-Out Voltage
1024-Mbit Family
Table
VLKO VLKOQ
Voltage Characteristics (Sheet
VCCQ Parameter 2.0V Unit Test Condition Notes
Lock Voltage VCCQ Lock Voltage
NOTES: undershoot -0.4V overshoot VCCQ+0.4V durations less. VPPLK inhibits erase program operations. VPPL VPPH outside their valid ranges.
1024-Mbit Family
Characteristics
Test Conditions
Figure Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
NOTE: test inputs driven VCCQ Logic Logic "0." Input/output timing begins/ends VCCQ/2. Input rise fall times (10% 90%) Worst case speed occurs VCCMin.
Figure Transient Equivalent Testing Load Circuit (TBD)
NOTES: following table component values. Test configuration component value worst case speed conditions. includes capacitance.
Table
Device Loading Specification
Test Configuration Standard Test (pF)
Figure Clock Input Waveform
R201
R202 R203
CLKINPUT
1024-Mbit Family
Table
Capacitance
Capacitance
Symbol COUT Parameter1 Input Capacitance Output Capacitance Input Capacitance Unit Condition VOUT
NOTES: +25°C, MHz. Sampled, 100% tested.
Read Specifications
Table Table show read specifications each code segment data segment flash die, respectively.
Table
Read Specifications (Code Segment Flash) (Sheet
1.7V 2.0V 1.7V 2.0V 1.8V 2.0V 1.8V 2.0V 1.7V 2.0V 2.7V 3.3V 1.8V 2.0V 2.7V 3.3V Units Notes
Symbol
Parameter1
VCCQ
Asynchronous Specifications
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ tGLTV tGLTX tGHTZ Read cycle time Address output valid F-CE# output valid output valid F-RST# high output valid F-CE# output Low-Z output Low-Z F-CE# high output high-Z high output high-Z Output hold from first occurring address, F-CE#, change F-CE# pulse width high F-CE# WAIT valid F-CE# high WAIT high-Z WAIT valid WAIT low-Z high WAIT high-Z 1,2,3
Latching Specifications
1024-Mbit Family
Table
Read Specifications (Code Segment Flash) (Sheet
Address setup ADV# high F-CE# ADV# high ADV# output valid ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access RST# high ADV# high
R101 tAVVH R102 tELVH R103 tVLQV R104 tVLVH R105 tVHVL R106 tVHAX R108 tAPA R111 tPHVH
Clock Specifications
R200 fCLK R201 tCLK R202 tCH/CL R203 tFCLK/ RCLK frequency period high/low time fall/rise time 18.5 19.2
Synchronous Specifications
R301 tAVCH/L R302 tVLCH/L R303 tELCH/L R304 tCHQV tCLQV Address setup ADV# setup F-CE# setup output valid Output hold from Address hold from WAIT valid Valid ADV# Setup WAIT Hold from 1,4,5
R305 tCHQX R306 tCHAX R307 tCHTV R311 tCHVL R312 tCHTX
NOTES: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. delayed tELQV tGLQV after F-CE#'s falling edge without impact tELQV. Sampled, 100% tested. Address hold synchronous-burst mode read tCHAX tVHAX, whichever timing specification satisfied first. Applies only subsequent synchronous reads.
1024-Mbit Family
Table Read Specifications (Data Segment Flash)
VCCQ Symbol Parameter1 1.7V 3.0V Unit Notes
Asynchronous Specifications
tAVAV tAVQV tFLQV tGLQV tPHQV tFLQX tGLQX tFHQZ tGHQZ tEHEL tELTV tEHTZ tGLTV tGLTX tGHTZ Read cycle time Address output valid F-CE# output valid output valid F-RST# high output valid F-CE# output low-Z output low-Z F-CE# high output high-Z high output high-Z Output hold from first occurring address, F-CE#, change F-CE# pulse width high F-CE# WAIT valid F-CE# high WAIT high-Z WAIT high-Z WAIT low-Z high WAIT high-Z 1,2,3
Latching Specifications
R101 tAVVH R102 tELVH R103 tVLQV R104 tVLVH R105 tVHVL R106 tVHAX R108 tAPA Address setup ADV# high F-CE# ADV# high ADV# output valid ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access
NOTES: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. delayed tELQV tGLQV after F-CE#'s falling edge without impact tELQV. Sampled, 100% tested.
1024-Mbit Family
Figure Asynchronous Single-Word Read with ADV#
Address ADV# WAIT Data [D/Q] RST#
NOTE: WAIT shown configured low-true.
Figure Asynchronous Single-Word Read with ADV# Latch
Address A[1:0][A] R101 R105 ADV# WAIT Data [D/Q] R106
NOTE: WAIT shown configured low-true.
1024-Mbit Family
Figure Asynchronous Page-Mode Read Timing
A[Max:2] A[1:0] R106 R101 R105 ADV# WAIT DATA [D/Q] R108 R108 R108
NOTE: WAIT shown configured low-true.
Figure Synchronous Single-Word Array-Read Timing (Code Segment Only)
Latency Count R301 Address R101 R105 R104 ADV# R303 R102 WAIT R304 Data [D/Q] R305 R307 R312 R106 R306
NOTES: WAIT driven assertion during synchronous array non-array read, configured assert either during data cycle before valid data. This diagram illustrates case which n-word burst initiated flash memory array terminated deassertion after first word burst.
1024-Mbit Family
Figure WAIT EOWL Timing (Code Segment Only)
R301 R302 R306 R101 Address R106 R105 ADV# R303 R102 WAIT R304 Data [D/Q] R305 R305 R305 R305 R307 R304 R304 R304
NOTES: EOWL Word Line; delay incurred when burst access crosses 16-word boundary starting address 4-word boundary aligned. WAIT asserted (RCR[10]=0) during synchronous array read, configured assert either during data cycle before valid data.
Figure Synchronous Burst-Mode Four-Word Read Timing (Code Segment Only)
Latency Coun R301 R302 R306 R101 Addres R106 R105 ADV# R303 R102 R304 Data [D/Q] R307
R304 R305
NOTES: Section 16.2, "Latency Count RCR[13:11]" page describes insert clock cycles during initial access. WAIT asserted (RCR[10]=0) during synchronous array read, configured assert either during data cycle before valid data.
1024-Mbit Family
Figure Burst Suspend Timing (Code Segment Only)
Latency Count R304 R305 Note Address R106 R101 R105 ADV# WAIT DATA [D/Q] R304 R304
(Burst Suspend)
R305 R305
NOTES: stopped either high state.
1024-Mbit Family
Write Specifications
Table shows write timing specifications each code data segment flash die.
Table Write Specifications
Nbr. Symbol tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL tWHQV Parameter F-RST# high recovery F-CE# setup write pulse width Data setup high Address setup high F-CE# hold from high Data hold from high Address hold from high pulse width high setup high hold from Status read F-WP# hold from Status read F-WP# setup high high high read valid 1,2,3 1,2,3,7 tAVQV+35 1,2,9 1,2,3,6,10 1,2,5 1,2,4 Units Notes
Write Asynchronous Read Specifications tWHAV high Address valid 1,2,3,6,8
Write Synchronous Read Specifications tWHCH/L tWHVH tVHWL tCHWL high Clock valid high ADV# high ADV# high Clock high 1,2,3,11 1,2,3,6,10
NOTES: Write timing characteristics during erase suspend same write-only operations. write operation terminated with either F-CE# WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from F-CE# (whichever occurs last) F-CE# high (whichever occurs first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from F-CE# high (whichever occurs first) F-CE# (whichever occurs last). Hence, tWHWL tEHEL tWHEL tEHWL). tWHVH tWHCH/L must when transition from write cycle synchronous burst read. F-WP# should valid level until erase program success determined. This specification only applicable when transitional from write cycle asynchronous read. spec synchronous read. When issuing Read Status operation following program erase write cycle, 20ns. 10.If write operation results block lock status change, 10ns subsequent read cycle reflect this change. 11.These specs required only when device synchronous mode clock active during address setup phase.
1024-Mbit Family
Figure Write Write Timing
Address Data [D/Q] RST#/
Figure Asynchronous Read Write Timing
Address Data [D/Q] RST#
1024-Mbit Family
Figure Write Asynchronous Read Timing
Address
Data [D/Q]
Figure Synchronous Read Write Timing
Latency Count R306 R301 R302 R101 Addres R105 R106 R102 ADV# R303 R304 Data [D/Q] R305 R307 R104
NOTE: WAIT shown asserted (RCR[10]=0) during write operation.
1024-Mbit Family
Figure Write Synchronous Read Timing
R302 R301 Address R104 ADV# WAIT R304 Data [D/Q] RST# R305 R304 R307 R303 R106 R306
NOTE: WAIT shown asserted (RCR[10]=0) during write operation.
Program Erase Characteristics
Table shows program erase timings each code data segment flash die.
Table Program Erase Timing (Sheet
VPPL Nbr. Symbol Parameter VPPH Units Notes
Word Programming W200 tPROG/W Program Time Single word Single cell Write-Buffer Programming W200 W201 tPROG/W tPROG/
Single word Program Time Buffer (32Words)
Buffered
W400 W401
tBuffered
EFP/W
Single word Program Buffered Setup
tBuffered
EFP/Setup
Erasing Suspending
1024-Mbit Family
Table Program Erase Timing (Sheet
VPPL Nbr. Symbol Parameter W500 W501 W600 W601 tERS/PB tERS/MB tSUSP/P tSUSP/E Suspen Latency Erase Time 16-Kword Parameter 64-Kword Main Program suspend Erase suspend VPPH Units Notes
NOTES: Typical values measured nominal voltages. Performance numbers valid speed versions. Excludes system overhead. Sampled, 100% tested. Averaged over entire device.
1024-Mbit Family
Power Reset Specifications
Power-Up Down
Power supply sequencing required VCC, VCCQ, connected same supply. VCCQ and/or connected supply, then should ramp before VCCQ VPP. Inputs should driven D[15:0] before supply voltage ramps MIN. Power supply transitions should only occur when F-RST# low. This protects device from accidental programming erasure during power transitions.
Reset
Asserting F-RST# during system reset important with automated program/erase devices because systems typically expect read from flash memory when coming reset. reset occurs without flash memory reset, proper initialization occur. This because flash memory providing status information, instead array data expected. Connect F-RST# same low-true reset signal used initialization. Also, because device disabled when F-RST# asserted, ignores control inputs during power-up/down. Invalid conditions masked, providing level memory protection. VCC-LKO. Because both System designers should guard against spurious writes when F-CE# must asserted write operation, deasserting either signal inhibits writes device. Command User Interface (CUI) architecture provides additional protection because alteration memory contents only occur after successful completion two-step command sequence (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43). Note: Asserting F-RST# resets segments SCSP device.
Table Reset Timing
Nbr. Symbol tPLPH Parameter F-RST# pulse width Unit Notes 1,2,3,4
1024-Mbit Family
Table Reset Timing
Nbr. Symbol tPLRH tVCCPH Parameter F-RST# device reset during erase F-RST# device reset during program Power valid F-RST# deasserted (high) 1,3,4,7 1,4,5,6 Unit Notes
NOTES: These specifications valid device versions (packages speeds). device reset tPLPH tPLPH MIN, this guaranteed. applicable F-RST# tied Vcc. Sampled, 100% tested. F-RST# tied supply, device will ready until tVCCPH after min. F-RST# tied supply/signal with VCCQ voltage levels, F-RST# input voltage must exceed until MIN. Reset completes within tPLPH F-RST# asserted while erase program operation executing.
1024-Mbit Family
Figure Reset Operation Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
RESET
Power Supply Decoupling
SCSP memory device requires careful power supply decoupling. Some basic power supply current considerations include standby active current levels transient peaks that produced when F-CE# asserted deasserted. When device accessed, many internal conditions change. Circuits within device enable charge-pumps, internal logic states change high speed. these internal activities produce transient signals. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control correct decoupling capacitor selection suppress transient voltage peaks. SCSP device draws power from VCC, VPP, VCCQ, each power connection should have ceramic coupling capacitor. High-frequency, inherently low-inductance capacitors should placed close possible package leads. Additionally, every eight dies used system, electrolytic capacitor should placed between power ground close devices. bulk capacitor meant overcome voltage droop caused trace inductance.
Automatic Power Saving (APS)
Automatic Power Saving (APS) provides power operation during read's active state. ICCAPS average current measured over time interval, after F-CE# deasserted. During APS, average SCSP device current measured across each segment flash over same time interval after following events:
There internal sense activity. F-CE# asserted. address lines quiescent, VIH. driven during APS.
1024-Mbit Family
Design Guide: Operation Overview
This section provides overview device operations. system provides control insystem read, program, erase operations device system bus. on-chip Write State Machine (WSM) manages block-erase word-program algorithms. Flash device commands written Command User Interface (CUI) control flash memory device operations. does occupy addressable memory location; mechanism through which flash device controlled. Note: Each flash within 1024-Mbit family shares basic asynchronous read write operations unless otherwise specified.
Operations
With F-CE# F-RST# high, SCSP flash dies enabled normal operations. flash internally decodes upper address inputs determine accessed partition block. asynchronous mode, addresses latched when ADV# transition from VIH, continuously flows through ADV# held low. Code segment flash die, synchronous-burst mode reads, addresses latched rising edge ADV# next valid edge when ADV# low. Table "Example Code Data Segment Operations" summarizes operations voltage levels that must applied individual flash each mode.
Table Example Code Data Segment Operations
F-RST# F1-CE# F2-CE# Device D[15:0] F-WE# F-VPP Mode Notes 1,2,3,4 1,2,3,4 1,2,3,4 2,3,4,5 ADV# WAIT
Sync Array Read Flash (code) Enabled Sync Non-Array Read Async Read
VPP1 VPP2
Driven Driven Deasserted
Flash code outputs Flash code outputs Flash code outputsS Flash code inputs Flash1 High-Z Flash1 High-Z Flash1 High-Z
Write Output Disable Standby Reset
Deasserted High-Z High-Z High-Z
1024-Mbit Family
Table Example Code Data Segment Operations
F-RST# F1-CE# F2-CE# Device D[15:0] F-WE# F-VPP Mode Notes 2,3,4,6 2,3,4,5 ADV# WAIT
Flash (data) Enabled
Async Read
VPP1 VPP2
Deasserted
Flash data outputs Flash data inputs Flash2 High-Z Flash2 High-Z Flash2 High-Z
Write Output Disable Standby Reset
Deasserted High-Z High-Z High-Z
NOTES: WAIT driven during sync burst read when F-CE# asserted. WAIT High-Z F-CE# deasserted. either flash dies, should never asserted simultaneously. means means VIH.while inputs VPP1, VPP2 VPPLK VPP. Flash query status register accesses D[7:0] only. other reads D[15:0]. Refer Table "Command Cycles" page valid during flash writes. Data segment flash only operates asynchronous mode, ignored WAIT deasserted.
9.1.1
Reads
controls data-outputs. perform read operation, F-RST# must deasserted while F-CE# asserted. When F-CE# asserted, addressed flash memory data driven onto memory bus. Section 10.0, "Read Operation" page details read commands, Section 16.0, "Configuration Operation" page details configuring code data segment flash read modes. Section 7.0, Characteristics" page signal-timing details.
9.1.2
Writes
controls data-inputs. perform write operation, F-RST# deasserted while FCE# asserted. write operations asynchronous. During write operation, addresses latched rising edge ADV#, WE#, F-CE#, whichever occurs first. Data latched rising edge F-CE#, whichever occurs first. case two-cycle write operations, address latched second cycle, operation applies that address. Table "Command Cycles" page shows cycle sequence each supported commands, while Table "Command Codes Definitions" page describes each command. Section 7.0, Characteristics" page signal-timing details. Note: Write operations with invalid and/or voltages produce spurious results should attempted.
9.1.3
Output Disable
When F-CE# deasserted, flash outputs D[15:0] disabled placed High-Z state.
1024-Mbit Family
9.1.4
Standby
When F-CE# deasserted, flash deselected placed standby, substantially reducing power consumption. standby, data outputs placed High-Z, independent level placed OE#. Standby current (ICCS) average current measured over time interval, after F-CE# deasserted (See Section 6.1, Current Characteristics" page details). When flash device deselected after valid program erase operation started, flash continues consume active power until program erase operation completed.
9.1.5
Reset
After initial power-up reset, SCSP flash dies defaults asynchronous Read Array mode, Status Registers default 0x80. blocks locked state. Read Configuration Register bits reverts their default states. Section 16.0, "Configuration Operation" page Figure "Block Locking State Diagram" page details. Asserting F-RST# de-energizes internal circuits, places output drivers High-Z. When F-RST# asserted, flash shuts down operation progress, process which takes minimum amount time (tPLRH) complete. (See Section 8.2, "Reset" page details.) Note: F-RST# asserted during program erase operation, operation terminated memory contents aborted location (for program) block location (for erase) longer valid. Because data have been only partially written erased, memory content should treated invalid. Upon return from reset, minimum reset delay (tVCCH) required before performing initial read write operations. When normal operation restored, user must reconfigure WAIT Read Configuration Register (RCR[10]) data segment flash match code segment flash WAIT (RCR[10]) setting. This operation prevents contention that result because WAIT signals shared between code data segment flash dies. Note: important user assert F-RST# when system reset. When system comes reset, system processor attempt read from flash memory system boot device. processor reset occurs with flash memory reset, improper processor initialization occur because flash memory providing status information rather than array data. FRST# should controlled same low-true reset signal that resets system processor memory controller.
Flash Device Commands
Flash device operations initiated writing specific flash commands Command User Interface (CUI). Table "Command Codes Definitions" page Flash operations initiated writing specific flash commands CUI, shown Table Program Erase commands modify flash array data.
1024-Mbit Family
Table Command Cycles (Sheet
Oper Command Read Array Read Device Identifier Read Query Read Status Register Clear Status Register Word Program Program (Write) Buffered Program3 Buffered Enhanced Factory Program (Buffered EFP)4 Block Erase Program/Erase Suspend Cycles First Cycle Oper Write Write Write Write Write Write Write Write Addr1 Data2 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 Write Write Write 0xD0 Write 0xD0 Read Read Read PBA+IA PnA+QA Second Cycle Oper Addr1 Data2 Third Cycle Oper Addr1 Data2
Block Suspend Erase Locking/ Unlocking Resume
Write Write
0x20 0xB0
Write
0xD0
Program/Erase Resume
Write
0xD0
Lock Block Unlock Block
Write Write
0x60 0x60
Write Write
0x01 0xD0
Lock-down Block
Write
0x60
Write
0x2F
1024-Mbit Family
Table Command Cycles (Sheet
Oper
Configuration Protection Register (Code Segment Only)
Command Program Protection Register5
Cycles
First Cycle Oper Write Addr1 Data2 0xC0
Second Cycle Oper Write Addr1 Data2
Third Cycle Oper Addr1 Data2
Program Lock Register5
Write
0xC0
Write
Program Configuration Register
Write
0x60
Write
0x03
NOTES: First command cycle address should same operation's target address. Partition Base Address. (Note: Data segment flash access block address) Address within Partition.(Note: Data segment flash access block address) Identification code Address offset. Query Address offset. Address within block. Word Address memory location written. Protection Register Address. Lock Register Address. valid address within flash. Identifier Data. Query data D[15:0]. Status Register Data. Word Data. Word count data loaded into buffer. Protection Register Sata. Lock Register Data. Read Configuration Register Data presented A[15:0]. A[MAX:16] bits must zeros. Section "Status Register Description" page second cycle buffered Program command number words count loaded into buffer. This followed 32-words data.Then confirm command (0xD0) issued, triggering array program operation. confirm command (0xD0) followed buffer data. Protection Register bits only accessible with code segment flash. Attempts program PR[16:0] will result SR[4,1] error.
Command Definitions
Flash operations selected writing specific commands CUI. Valid commands accepted described Table "Command Codes Definitions". commands have been specified form byte, accepted lower byte 16-bit data bus. upper byte ignored CUI. Note: Code segment flash dies accessed partition address location, while data segment flash dies accessed block address location.
1024-Mbit Family
Table Command Codes Definitions (Sheet
Operation Command Code 0xFF Flash Mode Read Array Read Status Register Description Place addressed partition block Read Array mode. Array data output D[15:0]. Place addressed partition block Read Status Register mode. partition block enter this mode after program erase command issued. Status Register data output D[7:0]. Places addressed partition block Read Device Identifier mode. Subsequent reads from addresses within partition block output manufacturer/device codes, Configuration Register data, Block Lock status, Protection Register data D[15:0]. Place addressed partition block Read Query mode. Subsequent reads from partition block addresses output Common Flash Interface (CFI) information D[7:0]. only Status Register error bits. Clear Status Register command used clear Status Register error bits. First cycle two-cycle programming command; prepares write operation. second write cycle, address data latched executes programming algorithm addressed location. 0x40 Word Program Setup During program operations, partition responds only Read Status Register Program Suspend commands. F-CE# must assert deassert update Status Register asynchronous read. Read Array command must issued read array data after programming finished. Note: code segment flash, F-CE# ADV# must assert deassert update Status Register data synchronous non-array read. 0x10 Program (Write) Alternate Word Program Setup Buffered Program Setup Equivalent Word Program Setup command, 0x40. First cycle two-cycle buffered program command; prepares flash receive variable number bytes buffer size 32-Words. second cycle contains number bytes transferred. second cycle two-cycle buffered program command, confirm command issued after filling data into buffer. confirm command instructs perform buffered program algorithm, writing data from buffer flash memory array. First cycle two-cycle Buffered Enhanced Factory Programming (Buffered EFP) command; initiates Buffered EFP. then waits Buffered Confirm command (0xD0) that initiates Buffered algorithm. other commands ignored when Buffered mode begins. second cycle two-cycle Buffered command. confirm command enable latch address data, prepares flash Buffered mode.
0x70
Read
0x90
Read Device Identifier
0x98
Read Query Clear Status Register
0x50
0xE8
0xD0
Buffered Program Confirm Buffered Enhanced Factory Programming Setup Buffered Confirm
0x80
0xD0
1024-Mbit Family
Table Command Codes Definitions (Sheet
Operation Command Code Flash Mode Description First cycle two-cycle erase command; prepares blockerase operation. performs erase algorithm block addressed Erase Confirm command. second command Erase Confirm (0xD0) command, sets Status Register bits SR[4] SR[5], place addressed partition block status register mode. first command Block Erase Setup (0x20), latches address data, erases addressed block. During blockerase operations, partition block responds only Status Register Erase Suspend commands. F-CE# must assert deassert update Status Register asynchronous read. Note: code segment flash, F-CE# ADV# must assert deassert update Status Register data synchronous non-array read. This command issued flash address initiates suspend currently-executing program block erase operation. Status Register indicates successful suspend operation setting either SR[2] (program suspended) SR[6] (erase suspended), along with SR[7] (ready). Write State Machine remains suspend mode regardless control signal states (except F-RST# asserted). This command issued flash address resumes suspended program block-erase operation. First cycle two-cycle lock block command; prepares block lock configuration changes. second command Block Lock (0x01), Block Unlock (0xD0), Block Lock-Down (0x2F), sets Status Register bits SR[4] SR[5], indicating command sequence error. previous command Block Lock Setup (0x60), addressed block locked. previous command Block Lock Setup (0x60), addressed block unlocked. addressed block lock-down state, Unlock Block (0xD0) command effect. previous command Block Lock Setup (0x60), addressed block locked down. First cycle two-cycle program protection register command; prepares code segment flash Protection Register Lock Register program operation. second cycle latches register address data, starts programming algorithm. Note: F-CE# must assert deassert update Status Register. Read Array command must issued read array data after programming finished. First cycle two-cycle Read Configuration Register command; prepares flash read configuration. Read Configuration Register command (0x03) second command, sets Status Register bits SR[4] SR[5], indicating command sequence error. previous command Read Configuration Register Setup (0x60), latches address writes A[15:0] Read Configuration Register. Following configured Read Configuration Register command, subsequent read operations access array data.
0x20
Block Erase Setup
Erase Block Erase Confirm
0xD0
0xB0 Suspend Resume 0xD0
Program Erase Suspend
Suspend Resume
0x60
Lock Block Setup
Block Locking/ Unlocking
0x01
Lock Block
0xD0
Unlock Block
0x2F
Lock-Down Block
Protection Register1
0xC0
Program Protection Register Setup
0x60 Configuration 0x03
Read Configuration Register Setup Read Configuration Register
NOTES: Protection Register bits only accessible with code segment flash. Attempts program data segment flash PR[16:0] will result SR[4,1] error.
1024-Mbit Family
10.0
Read Operation
code segment supports read modes: asynchronous page-mode read synchronous burstmode read. Asynchronous page-mode read default read mode after power-up reset. Read Configuration Register bits must configured enable synchronous burst reads (See Section 16.0, "Configuration Operation" page details). Note: data segment supports only asynchronous page-mode read. Only WAIT polarity RCR[10] must equal code segment RCR[10] setting. Each partition block flash four output states: Read Array, Read Status, Read Identifier, Read Query. Upon power-up after reset, blocks within flash segments default Read Array. change partition block read state, appropriate read command must written selected flash (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43.)
10.1
Asynchronous Page-Mode Read
Following device power-up reset, asynchronous page-mode read flash default read mode blocks across segments Read Array. However, perform array reads after other flash operation such program, erase, query, Device operation, Read Array command must issued order read from flash memory array. Note: After code segment flash synchronous burst-mode read operation, asynchronous page-mode read only performed when Read Configuration Register RCR[15] set. (See Section 16.0, "Configuration Operation" page perform asynchronous page-mode read, address driven onto A[MAX:MIN] F-CE# ADV# asserted. ADV# deasserted latch address, held throughout read cycle. ignored during asynchronous page-mode reads. asynchronous page-mode read, four data words "sensed" simultaneously from flash memory array loaded into internal page buffer. buffered word corresponding initial address A[MAX:MIN] driven onto D[15:0] after initial access delay. Address bits A[MAX:MIN+2] select 4-word group. Address bits A[MIN+1:MIN] determine which word 4-word group output from data buffer given time. long address bits A[MAX:MIN+2] change, same buffered data read from page-buffer multiple times order. A[MAX:MIN+2] address bits change time F-CE# toggled, flash will detect this load four data words into internal page buffer. Note: designs that will only operate code data segment flash asynchronous page-mode read, should tied valid level, WAIT signal floated, ADV# must tied ground. Array data driven onto D[15:0] after initial access time tAVQV delay. (See Section 7.0, Characteristics" page 23).
Note:
code data segments share same WAIT pins. Validity this depends selected segment command issued. WAIT deasserted during asynchronous page-mode reads.
1024-Mbit Family
10.2
Synchronous Burst-Mode Read (Code Segment)
Synchronous Burst-Mode Read code segment-only operation. Before synchronous burstmode read operation performed, appropriate Read Configuration Register bits (RCR[15:0]) must synchronous read. synchronous burst-mode read performed array non-array reads with configurable burst lengths 4-word, 8-word, 16-word, continuous word. Sychronous burst-mode read operation only valid code segment flash. Read Configuration Register bits RCR[15:0] must before synchronous burst operation performed. Table "Read Configuration Register Description" page details). synchronous-burst mode read output groups 16-, continuous-words. perform synchronous burst-mode read, initial address driven onto A[MAX:MIN] FCE# ADV# asserted. (Ensure that F-RST# already deasserted). There methods latching address: ADV# must asserted then deasserted latch address. ADV# remain asserted throughout burst access, which case address latched next valid edge while ADV# asserted. burst read operation starts after ADV# asserted F-CE# asserted, whichever last. During synchronous array non-array read modes, first word output from data buffer next valid edge after initial access latency delay (see Section 16.2, "Latency Count RCR[13:11]" page 68). Subsequent data output valid edges following tCHQV delay. Synchronous burst-mode reads only step through data once, only sequential manner, starting from address latched beginning burst cycle (see Section 7.0, Characteristics" page timing details). However, synchronous non-array reads, same word data will output successive clock edges until configured burst length read. During synchronous burst-mode read operations, WAIT driven with respect being asserted. WAIT indicates invalid data when asserted, valid data when deasserted after Latency Count delay.
10.2.1
Burst Suspend
Burst Suspend feature flash reduce eliminate initial access latency incurred when system software needs suspend burst sequence that progress order retrieve data from another non-flash device same system bus. system processor resume burst sequence within cycle maximum benefits non-cache systems.
Note:
Burst Suspend feature only used with code segment flash device family. device family does support Burst Suspend because global control signal memory dies within 1024-Mbit devices. burst access suspended during initial access latency (before data received) after data output. When burst access suspended, internal array sensing continues previously latched internal data retained. burst sequence suspended resumed without limit long operating conditions met. Burst Suspend occurs when F-CE# asserted, current address been latched (either rising edge ADV# valid edge), deasserted, halted (CLK VIL). ADV# other flash signals needs maintained static. WAIT High-Z while deasserted. resume burst access, reasserted restarted. next valid edge resumes burst sequence.
1024-Mbit Family
Within code segment flash, F-CE# gates WAIT signal. Therefore, during Burst Suspend, WAIT placed high-Z state when F-CE# deasserted. WAIT deasserted when re-asserted. Figure "Burst Suspend Timing (Code Segment Only)" page following sections describe detail read non-array read: Status Register, Register register states. This section will also discuss simultaneous flash operations between SCSP code data segment.
10.3
Read Array Command (0xFF)
Read Array command places addressed partition block Read Array mode. Array data output D[15:0]. perform read operation, F-RST# must deasserted while FCE# asserted. When F-CE# asserted, addressed flash memory data driven onto memory bus.
10.4
Read Status Register Command (0x70)
This command non-array read command. status code segment flash partition block determined reading Status Register (SR) from address target partition block. status data segment flash determined reading from address within flash address range. read issue Read Status Register command within desired partition block address, data output D[7:0]. data also made available automatically following Word Program, Block Erase, Block Lock command sequence. Read from partition block address after these command sequences outputs flash status until another valid command issued flash partition block address (e.g. Read Array command). read asynchronous page-mode synchronous single word burst-mode. data output D[7:0], while 0x00 output D[15:8]. falling edge F-CE# (whichever occurs first) updates latches contents. Note: code segment flash, Read Status Register command does affect read state other partitions. data segment flash, Read Status Register command sets read state entire flash because single partition die. perform other operation with data segment flash after Read Status Register command, Clear Status Register command must issued.
1024-Mbit Family
SR[7] provides status each accessed flash die. SR[0] indicates whether addressed location some other partition block (for code segment flash) actively programming erasing. SR[6:1] bits present status error information about program, erase, suspend, VPP, block-locked operations. Table Status Register Description
Status Register (SR) Write Status Erase Suspend Status Name Write Status (DWS) Erase Suspend Status (ESS) Erase Status (ES) Program Status (PS) Status (VPPS) Program Suspend Status (PSS) Block-Locked Status (BLS) Erase Status Program Status Status VPPS Program Suspend Status Description busy; program erase cycle progress; SR[0] valid. ready; SR[6:1] valid. Erase suspend effect. Erase suspend effect. Erase successful. Erase fail program sequence error when with SR[4,7]. Program successful. Program fail program sequence error when with SR[5,7] within acceptable limits during program erase operation. VPPLK during program erase operation. Program suspend effect. Program suspend effect. Block locked during program erase. Block locked during program erase; operation aborted. current partition busy Buffered prog/verify done Another partition busy Buffered program busy Partition Write Status (PWS) Note: Table partition status interpretation details Table Buffered status interpretation details. Default Value 0x80 BlockLocked Status Partition Status
Table Status Register bits Description Partition Status
(SR.7) (SR.0) Description addressed partition performing Program/Erase operation. other partition active partition other than currently addressed performing Program/Erase operation. Program/Erase operation progress partition. Erase Program suspend bits, SR[6, indicate whether other partitions suspended Reserved
Note: only applies code segment flash operations
1024-Mbit Family Table Status Register bits Description Buffered Mode Status
(SR.7) (SR.0) Description Buffer available loading subsequent data during Buffered operation Buffer available loading. Buffered currently being programmed Buffer available loading initial data Buffered operation Reserved
Note: only applies code segment flash operations
Note:
Always clear avoid ambiguity when issuing commands during Erase Suspend. example command sequence error occurs during erase-suspend state, contains command sequence error status (SR[7,5,4] set). When erase operation resumes finishes, possible errors during erase operation cannot detected been cleared because still contains previous error status.
10.5
Clear Status Register Command (0x50)
This command non-array read command. Clear Status Register command clears Status Register (SR), leaving partition block read states unchanged. functions independently VPP. Write State Machine (WSM) sets clears SR[7, sets bits SR[5:3, without clearing them. should cleared before starting command sequence avoid ambiguity. device reset also clears
10.6
Read Flash Device Identifier Command (0x90)
This command non-array read command. Read Flash Device Identifier Command command instructs addressed partition block output manufacturer code, identifier code, block-lock status, protection register (code segment only), Read Configuration Register data when that partition block addresses read. Section "Command Cycles" page details issuing Read Device Identifier command. Table "Device Identifier Information" page Table "Device Identifier Code" page show address offsets data values each flash die.
Table Device Identifier Information (Sheet
Item Manufacturer Code Code Block Lock Configuration: Block Unlocked Block Locked Block Locked-Down Block Locked-Down Read Configuration Register Lock Register 0x05 0x80 0x02 Address 0x00 0x01 0089h (see Table "Device Identifier Code" page Lock Bit: Read Configuration Register Data Protection Register Lock Bits Data Notes
1024-Mbit Family
Table Device Identifier Information (Sheet
Item 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 128-bit User-Programmable Protection Registers Address 0x81-0x84 0x85-0x88 0x89 0x8A-0x109 Data Factory Protection Register Data User Protection Register Data Protection Register Lock Bits User Protection Register Data Notes
NOTES: Partition Base Address code segment flash. Data segment flash 0x00. Block Base Address. Protection Register feature only applies Code Segment flash dies.
Table Device Identifier Code
Device Flash Dies Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Code: 128-Mbit Code: 256-Mbit Device (Hex) 880C 880D 880F Bottom 8810 8812 8813 8815 Bottom 8816 8818 8819 881B Bottom 881C 881E 881F 8821 Bottom 8822 Parameter Partition Configuration
10.7
Query Command (0x98)
This command non-array read command. Query command instructs device output Common Flash Interface (CFI) data when partition block addresses read. Table "Command Cycles" page details issuing Query command. Appendix "Common Flash Interface (CFI) Code Segment" page shows information address offsets within database. Issuing Query command partition block that programming erasing places that partition block outputs Query state, while partition block continues program erase background. Query command subject read restrictions dependent parameter partition block availability, described Table "Simultaneous Operation Restrictions" page
1024-Mbit Family
11.0
Program Operation
flash segments support three programming methods: word programming, buffered programming, Buffered Enhanced Factory Programming (Buffered EFP). Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page liste various programming commands issued flash. Successful programming requires addressed block unlocked. block locked down, F-WP# must deasserted issue block unlock commands (setup confirm) before attempting program block. Attempting program locked block causes program error terminates operation. Section 14.0, "Block Locking Unlocking Operations" page details locking unlocking blocks. Figure "Status Register Description" page details each segment flash status. Programming flash memory array changes state from logical logical (0). Memory array bits that logical changed logical only erasing block (see Section 12.0, "Erase Operation" page 58).
11.1
Word Program Setup Command (0x40)
Word programming operations initiated writing Word Program Setup command device. This followed second write flash device with address data programmed. partition block address accessed during both write cycles outputs Status Register data when read. partition block address accessed during second cycle (the data cycle) program command sequence location where data written. Figure "Word Program Flowchart" page Programming occur only partition block time; other partitions blocks must read state erase suspend. VPPLK, within specified VPPL Min/Max values (nominally Note: Since data segment flash single partition dies, word programming starts targeted block address. During programming, Write State Machine (WSM) executes sequence internally-timed events that program desired data bits addressed location, verifies that bits sufficiently programmed. Status Register examined programming progress errors reading address within partition block that being programmed. addressed partition block remains Status Register state until another command written that partition block. Issuing Status Register command another partition block address sets that partition block Status Register state, allowing programming progress monitored that partition block address. Note: determine status word-program during operation, poll status register analyze SR[7:0] data bits. flash standby mode during program operation, flash will continue program word until operation complete; flash will then enter standby mode.
1024-Mbit Family
Status Register SR[7] indicates programming status while sequence executes. Commands that issued programming partition during programming Program Suspend, Read Status Register, Read Device Identifier, Query, Read Array. F-CE# must assert deassert update Status Register contents. When programming finished, Status Register bits SR[4,3,1] indicate result program operation. Status Register SR[4] will there programming failure. SR[3] set, could perform word programming operation because outside acceptable limits. SR[1] set, operation attempted program locked block, causing operation abort. Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow completed program operation. This especially important when simultaneous operations between code data segment flash. Section 17.0, "Dual Operation Considerations" page additional details.
11.1.1
Factory Word Programming
Factory word programming similar word programming that uses same commands programming algorithms. However, factory word programming enhances programming performance with elevated VPPH. This enable faster programming times during manufacturing processes. Factory word programming intended extended use. Section 5.2, "Operating Conditions" page limitations when VPPH. Both code data segments support factory programming with VPPH.
Note:
When VPPL, flash draws programming current from supply. driven logic signal, VPPL VPPL program flash. When VPPH, flash draws programming current from supply. Figure "Example Supply Connections" page shows examples device power supply configurations.
11.2
Buffered Program Setup Command (0xE8)
perform buffered programming, Buffered Program command, 0xE8, issued along with block address (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43). Status Register information updated, reflects availability buffer. SR[7] indicates availability buffer loading data. SR[7] set, buffer available; set, buffer available. retry, issue Buffered Programming setup command again, re-check SR7. When SR[7] set, buffer available. Figure "Buffered Programming Flowchart" page Each flash code data segment features 32-word buffer enable optimum programming performance. buffered programming, data first written on-chip buffer. Then buffered data programmed into flash memory array buffer-size increments. This improve system programming performance significantly over non-buffered programming. Next, word count written flash buffered address. This tells flash many data words will written buffer, maximum size buffer (32-words).
1024-Mbit Family
next write, flash start address given along with first data written flash memory array. Subsequent write cycles provide additional flash address data. data addresses must within start address plus word count. Optimum programming performance lower power usage obtained aligning starting address 32-word boundary, where A[4:0] 0x00. Note: misaligned buffered programming starting address will double total program time.
11.3
Buffered Program Confirm Command (0xD0)
After last data written buffer, Buffered Program confirm command issued. Write State Machine begins copy buffered contents into flash memory array. command other than Buffered Program confirm command written flash, command sequence error will occur Status Register bits SR[4,5,7] will set. error occurs while writing array, flash will stop programming, Status Register SR[4] SR[7] will set, indicating programming failure. When Buffered Programming completed, additional buffered writes initiated issuing another Buffered Program setup command repeating buffered program sequence. Anytime SR[4] SR[5] set, flash will accept Buffered Program commands. attempt made program past block boundary using Buffered Program command, flash will abort operation. This will generate command sequence error, Status Register bits SR[4] SR[5] will set. Buffered Programming attempted while VPPLK, Status Register bits SR[4:3] set. errors detected that have Status Register bits, Status Register should cleared using Clear Status Register command.
11.4
Buffered Setup Command (0xE8)
Each code data segment flash also features Buffered Enhanced Factory Programing (Buffered EFP) which further improves Multi-Level Cell (MLC) flash programming time beat-ratesensitive manufacturing environments. This enhanced algorithm eliminates traditional elements that drive overhead off-board on-board, off-line in-line, manual automated programmer systems. Buffered consists three phases: Setup, Program/Verify, Exit (see Figure "Buffered Flowchart" page 89). Buffered different than non-buffered mode; incorporates buffer spread program performance across data words. Additionally, verification occurs same phase programming, inherent requirement technology accurately program correct state. two-cycle command sequence programs entire block data. This enhancement eliminates three write cycles buffer; commands word count each data words. Host programmer cycles fill flash buffer. This followed status check SR[0] determine when data from that buffer completed programming into sequential flash memory array locations. Following buffer-to-flash programming sequence, increments internal addressing automatically select next 32-word array boundary.
1024-Mbit Family
Buffered saves programming equipment address-bus setup overhead. With proper continuity testing, programming equipment rely internal verification ensure device programmed properly. This capability eliminates external post-program verification associated overhead. Buffered Requirements Considerations shown Table
Table Buffered Requirements Considerations
Description Case temperature: 25°C, ±5°C within specified operating range. 1.95 driven VPPH. Elevated Requirements Target block unlocked before issuing Buffered Setup Confirm commands. first-word address (WA0) block programmed must held constant from setup phase through data streaming into target block, until transition exit phase desired. must align with start array buffer boundary. optimum performance, cycling must limited below erase cycles block Considerations Buffered programs block time; buffer data must fall within single block. Buffered cannot suspended. Programming flash memory array occur only when buffer full. Notes
NOTES: Word buffer boundaries array determined A[4:0] (0x00 through 0x1F). alignment start point A[4:0] 0x00. Some degradation performance occur this limit exceeded, internal algorithm continues work properly. internal address counter increments beyond block's maximum address, addressing wraps around beginning block. number words less than remaining locations must filled with 0xFFFF.
11.5
Buffered Confirm Command (0xD0)
Buffered consists three phases: Setup, Program/Verify, Exit (see Figure "Buffered Flowchart" page 89).
11.5.1
Buffered Setup Phase
After receiving Buffered Setup Confirm command sequence, Status Register SR[7] (Ready) cleared, indicating that busy with Buffered algorithm startup. delay before checking SR[7] required allow enough time perform setups checks (Block-Lock status, level, etc.). error detected, SR[4] Buffered operation terminates. block found locked, SR[1] also set. SR[3] error occurred incorrect level.
Note:
Reading from flash after issuing Buffered Setup Confirm command sequence outputs Status Register data. issue Status Register command; will interpreted data loaded into buffer. However, permissible read from another flash within SCSP device undergoing Buffered EFPBuffered EFP.
1024-Mbit Family
11.5.2
Buffered Program/Verify Phase
After Buffered setup phase completed, host programming system must check SR[7,0] determine availability buffer data streaming. SR[7] cleared indicates device busy Buffered program/verify phase activated. SR[0] cleared indicates buffer available. basic sequences repeat this phase: loading buffer, followed programming buffer data array. Buffered EFP, count value loading buffer always maximum buffer size 32-Words. During this buffer-loading sequence, data stored sequential buffer locations starting address 0x00. Programming buffer contents flash memory array starts soon buffer full. number words less than remaining buffer word locations must filled with 0xFFFF.
Caution:
buffer must completely filled programming occur. Supplying address outside current block's range during buffer-fill sequence causes operation lock-up Buffered algorithm exit immediately. data previously loaded into buffer during fill cycle programmed into array. starting address data entry must buffer-size aligned; not, Buffered algorithm will aborted program fail (SR[4]) flag will set. Data words from buffer directed sequential memory locations flash memory array; programming continues from where previous buffer sequence ended. host programming system must poll SR[0] determine when buffer program sequence completes. SR[0] cleared indicates that buffer data been transferred flash array; SR[0] indicates that buffer available next fill cycle. host system check full status errors time, only necessary block basis after Buffered exits. host programming system continues Buffered algorithm providing next group data words written buffer. Alternatively, host programming system terminate this phase changing block address address outside current block's range. Program/Verify phase concludes when programmer writes different block address; data supplied must 0xFFFF. Upon Program/Verify phase completion, device enters Buffered Exit phase.
11.5.3
Buffered Exit Phase
When SR[7] set, device returned normal operating conditions. full status check should performed this time ensure entire block programmed successfully. After Buffered exit, valid command issued flash.
11.6
Program Protection
When VIL, absolute hardware write protection provided flash blocks both code data segments. VPPLK, programming operations halt SR[3] indicating VPP-level error. Block lock registers affected voltage level VPP; they still programmed read, even VPPLK.
1024-Mbit Family
Figure Example Supply Connections
PROT#
Factory Word Programming with VPPH Complete Write/Erase Protection when VPPLK VPPH
Voltage Programming Only Logic Control Device Protection
Voltage Factory Word Programming
Voltage Programming Only Full Device Protection Unavailable
1024-Mbit Family
12.0
Erase Operation
Erasing flash performed block basis. entire block erased each time erase command sequence issued, block time. When block erased, bits within that block read logical one's. following sections describe block erase operations detail.
12.1
Block Erase Setup Command (0x20)
Block erase two-cycle command operation. Erase initiated issuing Erase Setup command block address erased (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43). Next, Erase Confirm command issued block address erased.
12.2
Block Erase Confirm Command (0xD0)
After block erase operation initiated writing Block Erase Setup command address block erased, Block Erase Confirm command written address block erased. (See Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43). Erase operation occur only partition block time; other partitions blocks must read state. possible have both code data segment flash perform erase operation issuing successive erase command sequences each segment asserting either FCE# sequence. flash placed standby (F-CE# deasserted) during erase operation, flash completes erase operation before entering standby. VPPLK block must unlocked (see Figure "Block Erase Flowchart" page 90). During block erase, Write State Machine (WSM) performs sequence internally-timed events that conditions, erases, verifies bits within block. Erasing flash memory array changes logical zero logical one. Memory array bits that ones changed zeros only programming block (see Section 11.0, "Program Operation" page 52). Status Register examined block erase progress errors reading address within partition block that being erased. partition block remains Read Status Register state until another command written that partition block. Issuing Status Register command another partition block address sets that partition block Status Register state, allowing erase progress monitored that address location. SR[0] determines whether addressed partition block another partition block erasing within same flash. SR[0] indicates another partition blockis erasing SR[0] indicates addressed partition block erasing. Status Register SR[7] upon erase completion. Status Register SR[7] determines block erase status while sequence performing. When erase operation finished, Status Register SR[5] indicates whether erase failure occurred. SR[3] indicates could perform erase operation because outside acceptable limits. SR[1] indicates erase operation attempted erase locked block, causing operation abort. F-CE# must deassert, then assert update Status Register contents.
1024-Mbit Family
Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow once block erase operation completed.
13.0
Note:
Suspend Resume Operations
When VIL, absolute hardware erase protection provided device blocks. VPPLK, erase operations halt SR[3] indicating VPP-level error.
13.1
Erase Suspend Command (0xB0)
Issuing Erase Suspend command while erase progress suspends block erase operation. This allows data accessed from memory location other than being erased. Erase Suspend command issued segment flash address within block. block erase operation suspended perform word buffer program operation, read operation within block except block that erase-suspended (see Figure "Program Suspend/ Resume Flowchart" page 87). When block erase operation executing, issuing Erase Suspend command requests suspend erase algorithm several predetermined points. partition block that suspended continues output Status Register data after Erase Suspend command issued. Block erase suspended when Status Register bits SR[7:6] set. Suspend latency specified Section 7.5, "Program Erase Characteristics" page read data from blocks within suspended partition block (other than erase-suspended block), Read Array command must issued that partition block first. During Erase Suspend, Program command issued block other than erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, Query, Erase Resume valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, Block Lock-Down valid commands during Erase Suspend. Note: both segments executing erase operation, Erase Suspend command applies device segment with F-CE# asserted. both F-CE#'s asserted, erase operations both device segments suspended. During erase suspend, deasserting F-CE# places selected segment flash standby, reducing active current. must remain valid level, F-WP# must remain unchanged while erase suspend. F-RST# asserted, both code data segments reset.
13.2
Program Suspend Command (0xB0)
program suspend command pauses programming operation. suspend command issued flash address. suspend command allows data accessed from memory location other than from being programmed from block being erased. partition address corresponding suspend command address affected.
1024-Mbit Family
program operation suspended perform read-only. However, Erase operation suspended perform either program read operation. program command nested within suspended Erase suspended read another address location. (see Figure "Program Suspend/Resume Flowchart" page 87). When programming operation started, issuing suspend command requests suspend programming algorithm predetermined points. partition address that suspended continues output Status Register data after program suspend command issued. program operation suspended when Status Register bits SR[7,2] set. Suspend latency (tSUSP/P) specified Section 7.5, "Program Erase Characteristics" page read data from blocks within suspended partition block, other than erase-suspended block, Read Array command written that partition address. Read Array, Status Register, Device Identifier, Query, Read Configuration Register, Enhanced Configuration Register, Program Resume valid commands during program suspend. During program suspend, deasserting F-CE# places flash standby which reduces supply current placing flash standby. must remain programming level, F-WP# must remain unchanged while program suspend mode. F-RST# asserted, both code data segments reset.
13.3
Program Resume Command (0xD0)
Resume command instructs device continue programming, automatically clears Status Register bits SR[7,2]. This command written partition block segment. When read partition block that programming, flash outputs data that corresponds that partition last state. error bits set, Status Register should cleared before issuing next instruction. F-RST# must remain deasserted (see Figure "Program Suspend/Resume Flowchart" page 87).
13.4
Erase Resume Command (0xD0)
Erase Resume command instructs corresponding segment continue erasing, automatically clears status register bits SR[7:6]. This command written partition block. When read partition block that erasing, flash outputs data corresponding partition block last state. status register error bits set, Status Register should cleared before issuing next instruction. F-RST# must remain deasserted (see Figure "Program Suspend/Resume Flowchart" page 87).
1024-Mbit Family
14.0
Block Locking Unlocking Operations
1024-Mbit family features security modes used protect information stored code data segment memory arrays. following sections describe each security mode detail. Individual instant block locking used protect data flash memory array. blocks power locked state protect array data from being altered during power transitions. block locked unlocked with latency. Locked blocks cannot programmed erased; they only read. Refer Figure "Command Cycles" page block lock command cycles, Table block lock state diagram. Software-controlled security implemented using Block Lock Block Unlock commands. Hardware-controlled security implemented using Block Lock-Down command along with asserting F-WP# inhibit program erase operations. Figure "Block Locking State Diagram provides overview block lock security management.
14.1
Block Locking During Erase Suspend
Block locking changes made during erase suspend (but during program suspend) using standard locking command sequences unlock, lock, lock-down block. This useful when another block needs updated while erase operation suspended. change block locking during erase operation, first issue Erase Suspend command, then check status register SR[7:6] until indicates that erase operation suspended. Next issue desired confirmed lock command sequence target block, lock state target block will changed. After completing block lock, read, program operations, resume erase operation with Erase Resume command block locked locked-down during erase suspend same block, locking status bits will change immediately. But, when resumed, erase operation will complete. Note: Nested lock program commands during erase suspend return ambiguous status register results. Configuration Setup command (0x60) followed invalid command produces lock command status register error (SR[5:4] this error occurs during erase suspend, SR[5:4] remain logical after erase resumes. When erase completes, previous locking command error hides status register's erase errors. similar situation occurs program operation error nested within erase suspend. Appendix "Write State Machine (WSM) Code Segment (TBD)" page which shows valid commands during erase suspend. Lock Block Setup command followed command other than Lock Block, Unlock Block, Lock-Down Block produces command sequence error sets Status Register bits SR[4] SR[5]. command sequence error occurs during erase suspend, SR[4] SR[5] remains set, even after erase operation resumed. Unless Status Register cleared using Clear
Caution:
1024-Mbit Family
Status Register command before resuming erase operation, possible erase errors masked command sequence error.
14.1.1
F-WP# Lock-Down Control
lock-down status particular block, F-WP# signal then enabled master lock/unlock override that particular block. When F-WP# asserted, blocks that have lock-down status automatically into lock-down state cannot unlocked with Unlock Block command. Once F-WP# deasserted, block reverts back locked state; only then unlocked software.
Figure Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
Notes:
[a,b,c] represents [WP#, D0]. Don't Care. indicates block Lock-down status. `0', Lock-down been issued this block. `1', Lock-down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
14.2
Lock Block Setup Command (0x60)
lock unlocked block, cycle command sequence required. First issue Lock Block Setup command. next command must Lock Block command issued desired block's address (See Figure "Block Lock Operations Flowchart" page 92).
1024-Mbit Family
Note:
Read Configuration Register command issued after Lock Block Setup command, flash configures Read Configuration Register instead. Block lock unlock operations affected voltage level VPP. block lock register bits modified read even VPPLK.
14.3
Unlock Block Command (0xD0)
Locked blocks unlocked issuing two-cycle Unlocked block commands. Unlocked blocks read, programmed, erased. Unlocked blocks always return locked state when device reset powered down.
14.4
Lock-Down Block Command (0x2F)
Lock-Down Block command adds additional level security flash. Issuing LockDown Block command sets lock-down status locks block. Lock-Down Block command used block's current state either locked unlocked. Once this set, F-WP# enabled hardware lock control that particular block. block locked-down F-WP# deasserted, user must issue Unlock Block command allow program erase operations that block. Note: Only device reset power-down clear lock-down status bit.
1024-Mbit Family
15.0
Protection Register Operation
Protection Register Operations applies only code segment. SCSP device, only code segment flash contains Protection Registers, PR[16:0]. code segment contains flash dies, each will have 2176-bits Protection Registers. However, code segment only flash die, then single flash will have 2176-bits Protection Registers. Protection Registers sub-divided into sixteen 128-bit increments, which used implement system security measures and/or device identification. Each user accessible Protection Register individually locked. PR[0] comprised 64-bit (8-words) components. lower 64-bit component preprogrammed factory with unique 64-bit number. other 64-bit component, well PR[16:1] users programmable registers. programmed single word increments. locked prevent additional programming (see Figure "Protection Register Map" page 65). Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot erased; that they cannot re-programmed from logical zero logical (1). Each accessed multiple times program individual bits, long register remains unlocked register programmed data stream logical available. Each associated Lock Register bit. When Lock Register programmed, associated only read; longer programmed. Additionally, because Lock Register bits themselves OTP, when programmed, Lock Register bits cannot erased.
15.1
Reading Protection Registers
Protection Registers read from within partition address space. read data, first issue Read Device Identifier command partition address place that partition Read Device Identifier state (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43). Next, perform read operation that partition base address plus address offset corresponding register read. Table "Device Identifier Information" page shows address offsets Protection Registers Lock Registers. Register data read word time. Note: program erase operation occurs partition while reading Protection Register another partition, certain restrictions apply. Table "Simultaneous Operation Restrictions" page details.
1024-Mbit Family
Figure Protection Register
0x109 PR16
(User-Programmable)
0x102 0x91
(User-Programmable)
0x8A Lock Register 0x89
0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 Lock Register 0x80
15.2
Program Protection Register Setup Command (0xC0)
program Protection Registers, first issue Program Protection Register command parameter partition base address plus offset desired Protection Register (see Section "Command Cycles" page 42). Next, write desired Protection Register data same Protection Register address (see Figure "Protection Register Map" page 65). device programs register data word time (see Figure "Protection Register Programming Flowchart" page 93). Issuing program Protection Register command outside Protection Register's address space causes program error (SR[4] set). Attempting program locked Protection Register causes program error (SR[4] set) lock error (SR[1] set).
1024-Mbit Family
15.2.1
Locking Protection Registers
Each Protection Register locked programming respective lock Lock Register. lock Protection Register, program corresponding Lock Register issuing Program Lock Register command, followed desired Lock Register data. Lock Register pre-programmed Intel with unique identification numbers. Lock Register programmed user lock user-programmable, 64-bit region first 128-bit PR[0] section. remaining bits Lock Register used cannot changed user. Lock Register controls locking PR[16:1]. Each bits Lock Register correspond each upper sixteen 128-bit PRs. Once locked, cannot unlocked.
1024-Mbit Family
16.0
Configuration Operation
Read Configuration Register (RCR) used configure code segment flash (synchronous asynchronous) data segment flash (asynchronous) read modes. modify settings, Read Configuration Register command (see Section 9.2, "Flash Device Commands" page Section 9.3, "Command Definitions" page 43).
Caution:
data segment flash die, only Read Configuration Register (RCR[10]) changed user. other Read Configuration Register bits (RCR[15:11, 9:0]) default settings should changed. Changes default settings will cause flash indeterminate state. reset flash will required re-start normal operation. RCR[15:0] contents examined using Device Identifier command, then reading from <partition base block address> 0x05 (See Section 10.6, "Read Flash Device Identifier Command (0x90)" page 50). Read Configuration Register bits shown Table following sections describe each RCR[15:0] bits.
Table Read Configuration Register Description (Sheet
Read Configuration Register (RCR) Read Mode Latency Count LC[2:0] WAIT Polarity Data Hold WAIT Delay Burst Edge Default Value 0xFFFF Burst Wrap Burst Length BL[2:0]
Name Read Mode (RM) Reserved Synchronous burst-mode read
Description Asynchronous page-mode read (default) Reserved bits should cleared =Code =Code =Code
13:11
Latency Count (LC[2:0])
=Code Code Code (default) (Other settings reserved) =WAIT signal active =WAIT signal active high (default) Note: user must data segment flash RCR[10] equal code segment flash RCR[10] prior normal operation.
Wait Polarity (WP)
Data Hold (DH) Wait Delay (WD) Burst Sequence (BS)
=Data held 1-clock data cycle =Data held 2-clock data cycle (default) =WAIT deasserted with valid data =WAIT deasserted data cycle before valid data (default) =Reserved =Linear (default)
1024-Mbit Family
Table Read Configuration Register Description (Sheet
Clock Edge (CE) Reserved Burst Wrap (BW) Falling edge Rising edge (default) Reserved bits should cleared =Wrap; Burst accesses wrap within burst length BL[2:0] Wrap; Burst accesses wrap within burst length (default) =4-word burst =8-word burst =16-word burst =Continuous-word burst (default) (Other settings reserved)
Burst Length (BL[2:0])
16.1
Read Mode Bit- RCR[15]
Read Mode (RM) selects synchronous burst-mode asynchronous page-mode operation data segment flash. When set, asynchronous page-mode read selected (default). When cleared, synchronous-burst mode read selected.
16.2
Latency Count RCR[13:11]
Latency Count bits, LC[2:0], flash count many clock cycles must elapse from first valid clock edge after ADV# asserted, from rising edge ADV#, until first data word driven onto D[15:0]. input clock frequency used determine this value. Figure shows data output latency different settings LC[2:0]. Refer Table Frequency Support tAVQV tCHQV 85ns 14ns" page Latency Code Settings Note: During synchronous-burst mode read, Latency Count setting Code results zero WAIT state. However, Latency Count setting code causes WAIT state after every four words, regardless whether 16-word boundary crossed. (Note that Latency Count setting code causes WAIT states Latency Count setting code causes three WAIT states.) RCR[9] set, indicating data hold clocks, this WAIT condition does occur because enough clocks elapse during each burst cycle eliminate subsequent WAIT states.
1024-Mbit Family
Figure First-Access Latency Count
Valid Address
Address
ADV# Code (Reserved) Code
DQ15 [D/Q] DQ15 [D/Q] DQ15 [D/Q] DQ15 [D/Q] DQ15 [D/Q] DQ15 [D/Q]
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Code
Valid Output
Table Frequency Support tAVQV tCHQV 85ns 14ns
Latency Count Settings Frequency Support (MHz)
Figure Example Latency Count Setting Using LC=3
tData
ADV# A[MAX:0]
Code Address
D[15:0]
High-Z
Data
R103
1024-Mbit Family
16.3
WAIT Polarity RCR[10]
WAIT Polarity (WP), RCR[10] determines asserted level (VOH VOL) WAIT. When set, WAIT high-true signal (default). When cleared, WAIT low-true signal. WAIT changes state valid clock edges during active cycles (F-CE# asserted, F-RST# deasserted).
Caution:
user require configure data segment flash RCR[10] same configuration setting code segment flash valid operation. Configuring code data segment RCR[10] differently result contention during read operation.
16.3.1
WAIT Signal Function
WAIT signal indicates when data valid invalid with code segment flash operating synchronous-burst mode read (RCR[15]=0). WAIT active synchronous array read synchronous non-array read with code segment flash. WAIT signal deasserted only when data valid bus. When device operating synchronous non-array read mode, such read status, read read query, WAIT signal also "de-asserted" when data valid bus. When device operating asynchronous page mode, asynchronous single word read mode, write operations, WAIT de-asserted state determined RCR[10]. Figure "Asynchronous Single-Word Read with ADV# Latch, Figure "Asynchronous PageMode Read Timing" page
Note:
Refer Table WAIT state specific operational modes.
Table WAIT Summary Table
CONDITION WAIT
F-CE# F-CE# Synchronous Array Reads Synchronous Non-Array Reads Asynchronous Reads Write operations
High-Z Driven High-Z Driven Driven Driven Deasserted Deasserted
NOTE: Active: WAIT asserted until completed data becomes valid, then deasserts.
1024-Mbit Family
16.4
Data Hold RCR[9]
code segment burst read operations, Data Hold (DH) determines whether data output remains valid D[15:0] clock cycles. When set, output data held clocks (default). When cleared, output data held clock (see Figure 26). processor's data setup time flash memory's clock-to-data output delay should considered when determining whether hold output data clocks. Note: Here possible method determining Data Hold configuration: device clock data hold subsequent reads, following condition must satisfied: tCHQV (ns) tDATA (ns) Period (ns) tDATA Data Clock (defined CPU) example, with clock frequency MHz, clock period 18.5 Assumption, tCHQV tDATA applying these values formula yields 18.5 equation satisfied data will available every clock period with data hold setting clock. tCHQV (ns) tDATA (ns) Period (ns), then data hold setting clock periods must used.
Figure Data Hold Timing
Data Hold Data Hold
Valid Output Valid Output Valid Output
D[15:0]
D[15:0]
Valid Output
Valid Output
16.5
WAIT Delay RCR[8]
WAIT Delay (WD) controls WAIT assertion-delay behavior during synchronous burst reads. WAIT asserted either during data cycle before invalid data output D[15:0]. When set, WAIT asserted data cycle before invalid data (default). When clear, WAIT asserted during invalid data.
1024-Mbit Family
16.6
Burst Sequence RCR[7]
Burst Sequence (BS) selects linear-burst sequence (default). Table Shows synchronous burst sequence burst lengths, well effect Burst Wrap (BW) setting, RCR[3].
Table Burst Sequence Word Ordering
Burst Addressing Sequence (DEC) Start Addr. (DEC)
Burst Wrap (RCR[3])
4-Word Burst (BL[2:0] 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
8-Word Burst (BL[2:0] 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-Word Burst (BL[2:0] 0b011) 0-1-2-3-4.14-15 1-2-3-4-5.15-0 2-3-4-5-6.0-1 3-4-5-6-7.1-2 4-5-6-7-8.2-3 5-6-7-8-9.3-4 6-7-8-9-10.4-5 7-8-9-10-11.5-6
Continuous Burst (BL[2:0] 0b111) 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13.
14-15-0-1-2.12-13 15-0-1-2-3.13-14
14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-.
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-1112 6-7-8-9-10-11-1213 7-8-9-10-11-1213-14
0-1-2-3-4.14-15 1-2-3-4-5.15-16 2-3-4-5-6.16-17 3-4-5-6-7.17-18 4-5-6-7-8.18-19 5-6-7-8-9.19-20 6-7-8-9-10.20-21 7-8-9-10-11.21-22
0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13.
14-15-16-1718.28-29 15-16-17-1819.29-30
14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-.
16.7
Clock Edge RCR[6]
Clock Edge selects either rising (default) falling clock edge CLK. This clock edge used start burst cycle count output synchronous data assert/deassert WAIT.
1024-Mbit Family
16.8
Burst Wrap RCR[3]
Burst Wrap (BW) determines whether 4-word, 8-word, 16-word burst length accesses wrap within selected word-length boundaries cross word-length boundaries. When set, burst wrapping does occur (default). When cleared, burst wrapping occurs. When performing synchronous burst reads with wrap), output delay occur when burst sequence crosses first 16-word boundary. burst sequence start address 4word aligned, then delay occurs. start address 4-word boundary, worst case output delay clock cycle less than first access Latency Count. This delay take place only once, does occur burst sequence does cross first 16-word boundary. WAIT informs system this delay when occurs.
16.9
Burst Length RCR[2:0]
Burst Length (BL) bits RCR[2:0] select linear burst length synchronous burst reads flash memory array. burst lengths 4-word, 8-word, 16-word, continuous-word. Continuous-burst accesses linear only, wrap within word length boundaries Table "Burst Sequence Word Ordering" page When burst cycle begins, code segment flash outputs synchronous burst data until reaches available accessible contiguous address space.
16.10
Read Configuration Register Command (0x60)
Read Configuration Register command first cycle two-cycle command prepare flash read configuration. Read Configuration Register command (0x03) second command, sets Status Register bits SR[4] SR[5], indicating command sequence error.
16.11
Write Read Configuration Register Command (0x03)
previous command Read Configuration Register Setup (0x60), latches address writes A[15:0] Read Configuration Register. Following configured Read Configuration Register command, subsequent read operations access array data.
1024-Mbit Family
17.0
Dual Operation Considerations
multi-partition architecture code segment allows programming erasing occur partition block while reading code execution occurs from another partition block. addition, SCSP device configuration enables reading from code segment while programming erasing within data segment; conversely possible read from data segment while programming erasing code segment. Simultaneous program erase allowed within same partition.
17.1
Product Configurations Memory Partitioning
LV18/LV30 SCSP family consist least code data die. minimum density option 384-Mbit: 256-Mbit code 128-Mbit data, 128-Mbit code 256-Mbit data. default, first flash first code segment flash die, fast, eXecute-In-Place (XIP) solution ideal instruction fetch application. This portion user-selected parameter configuration option (Top Bottom) either 128-Mbit flash 256-Mbit flash die, each containing parameter partition several main partitions. 128-Mbit memory array divided into sixteen 8-Mbit partitions. Each density contains parameter partition fifteen main partitions. 8-Mbit bottom parameter partition contains four 16-Kword blocks seven 64-Kword blocks. remaining fifteen 8-Mbit main partitions each contain eight 64-Kword blocks. 256-Mbit memory array divided into sixteen 16-Mbit partitions. Each device contains parameter partition fifteen main partitions. 16-Mbit bottom parameter partition contains four 16-Kword blocks fifteen 64-Kword blocks.
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