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Intel® 848P Chipset

Intel® 82848P Memory Controller Hub (MCH)

Intel® 848P Chipset
Datasheet
Intel® 82848P Memory Controller Hub (MCH)
August 2003
Document Number: 253575-001
Contents
1 Introduction ........................................................13
Signal Description ..................................................21
Register Description ................................................39
Contents
System Address Map.............................................. 113
Functional Description ............................................ 121
Contents
Thermal Management ............................................133 5.5.1 External Thermal Sensor Interface Overview..................133 5.5.2 External Thermal Sensor Usage Model ......................134 Clocking.......................................................135 Absolute Maximum Ratings........................................137 Thermal Characteristics ..........................................137 Power Characteristics ............................................138 Signal Groups..................................................138 DC Parameters.................................................140 MCH Ballout ...................................................145 MCH Package Information ........................................156 XOR Test Mode Initialization.......................................159 XOR Chain Definition ............................................161
Electrical Characteristics ..........................................137
Ballout and Package Information ..................................145
Testability .........................................................159
Contents
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Intel® 848P Chipset System Block Diagram ............................ 16 Intel® 82848P MCH Interface Block Diagram ........................... 22 Intel® 848P Chipset System Clock and Reset Requirements ............... 35 Full and Warm Reset Waveforms .................................... 37 Conceptual Intel® 848P Chipset Platform PCI Configuration Diagram ........ 41 Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping ....................................................... 43 Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping ....................................................... 44 PAM Register Attributes........................................... 59 Memory System Address Map ..................................... 114 Detailed Memory System Address Map.............................. 114 Platform External Sensor ......................................... 134 Intel® 848P Chipset System Clocking Block Diagram.................... 135 Intel® 82848P MCH Ballout Diagram (Top View-Left Side) .............. 146 Intel® 82848P MCH Ballout Diagram (Top View-Right Side)............. 147 Intel® 82848P MCH Package Dimensions (Top and Side Views)........... 156 Intel® 82848P MCH Package Dimensions (Bottom View) ................ 157 XOR Toggling of HCLKP and HCLKN ............................... 159 XOR Testing Chains Tested Sequentially............................. 160
Contents
Tables
Contents
Revision History
Revision -001 · Initial Release Description Date August 2003
Contents
Intel® 82848P MCH Features
Communication Streaming Architecture (CSA) Interface Support - Gigabit Ethernet (GbE) communication devices supported on the CSA interface (e.g., Intel® 82547EI GbE controller) - 8-bit Hub Interface 1.5 electrical / transfer protocol - 266 MB / s point-to-point connection - 1.5 V operation Hub Interface (HI) Support - Hub Interface 1.5 - 266 MB / s point-to-point connection to the ICH5 - 66 MHz base clock - 1.5 V operation AGP Interface Support - Single AGP device - AGP 3.0 with 4X / 8X AGP data transfers and 4X / 8X fast writes, respectively - 32-bit 4X / 8X data transfers and 4X / 8X fast writes - Peak BW of 2 GB / s. - 0.8 V and 1.5 V AGP signalling levels no 3.3 V support - AGP 2.0 1X / 4X AGP data transfers and 4X fast writes - 32-deep AGP request queue MCH Package - 37.5 mm x 37.5 mm Flip Chip Ball Grid Array (FC-BGA) package - 932 solder balls
Contents
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Introduction
This Memory Controller Hub (MCH) datasheet is for the Intel® 82848P MCH. The 82848P MCH is part of the Intel® 848P chipset. Each chipset contains two main components: Memory Controller Hub (MCH) for the host bridge and I / O Controller Hub for the I / O subsystem. The MCH provides the processor interface, system memory interface, CSA interface, AGP interface, and hub interface in an 848P chipset desktop platform. The 848P chipset uses either the Intel® 82801EB ICH5 or Intel® 82801ER ICH5R for the I / O Controller Hub.
Table 1.
Terminology
This section provides the definitions of some of the terms used in this document. General Terminology (Sheet 1 of 2)
Terminology Description Accelerated Graphics Port. In this document AGP refers to the AGP / PCI interface that is in the MCH. The MCH AGP interface supports only 0.8 V / 1.5 V AGP 2.0 / AGP 3.0 compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and 8X (533 MHz) transfers. MCH does NOT support any 3.3 V devices. For AGP 2.0 PIPE# and SBA addressing cycles and their associated data phases are generally referred to as AGP transactions. FRAME# cycles are generally referred to as AGP / PCI transactions. DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank, which is the only type the MCH supports. Each bank acts somewhat like a separate DRAM, opening and closing pages independently, allowing different pages to be open in each. Most commands to a DRAM target a specific bank, but some commands (i.e., Precharge All) are targeted at all banks. Multiple banks allows higher performance by interleaving the banks and reducing page miss cycles. In the MCH a DRAM channel is the set of signals that connect to one set of DRAM DIMMs. The MCH internal base logic. The Column address selects one DRAM location, or the starting location of a burst, from within the open page on a read or write command. Terminology often used to describe a DIMM that contains two DRAM rows. Generally a Double-Sided DIMM contains two rows, with the exception noted above. This terminology is not used within this document. Double Data Rate SDRAM. DDR describes the type of DRAMs that transfers two data items per clock on each pin. This is the only type of DRAM supported by the MCH. A Full MCH Reset is defined in this document when RSTIN# is asserted. Graphics Aperture Re-map Table. GART is a table in memory containing the page re-map information used during AGP aperture address translations. The Memory Controller Hub component that contains the processor interface, DRAM controller, CSA interface, and AGP interface. It communicates with the I / O controller hub (ICH5) over proprietary interconnects called HI. Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries. Hub Interface. HI is the proprietary Hub interconnect that connects the MCH to the ICH5. In this document HI cycles originating from or destined for the primary PCI interface on the ICH5 are generally referred to as HI / PCI or simply HI cycles.
Channel Chipset Core Column Address Double-Sided DIMM DDR Full Reset GART
Intel® 82848P MCH Datasheet
Introduction
Table 1.
General Terminology (Sheet 2 of 2)
Terminology Host Intel® ICH5 Description This term is used synonymously with processor. Fifth generation IO Controller Hub component that contains additional functionality compared to the Intel® ICH4. The physical PCI bus that is driven directly by the ICH5 component. Communication between PCI and the MCH occurs over HI. Note that even though the Primary PCI bus is referred to as PCI it is not PCI Bus 0 from a configuration standpoint. Processor Front Side Bus. A group of DRAM chips that fill out the data bus width of the system and are accessed in parallel by each DRAM command. The Row address is presented to the DRAMs during an Activate command and indicates which page to open within the specified bank (the bank number is also presented). Processor-to-MCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The Enhanced Mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting of source synchronous transfers for address and data, and FSB interrupt delivery. The Intel® Pentium® 4 processor implements a subset of the enhanced mode. Terminology often used to describe a DIMM that contains one DRAM row. Usually one row fits on a single side of the DIMM allowing the backside to be empty. Single Data Rate SDRAM. Synchronous Dynamic Random Access Memory. The physical PCI interface that is a subset of the AGP bus driven directly by the MCH. It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at 1.5 V (not 3.3 V or 5 V). Stub Series Terminated Logic for 2.6 Volts (DDR)
Primary PCI FSB Row Row Address
Scalable Bus
Related Documents
Document1 Intel® 848P Chipset Platform Design Guide Intel® 848P Chipset Thermal Design Guide Intel 848P Chipset Customer Reference Board Schematics Intel 82801EB I / O Controller Hub 5 (ICH5) and Intel 82801ER I / O Controller Hub 5R (ICH5R) Datasheet Intel® Pentium® 4 Processors with 512-KB L2 Cache on 0.13 Micron Process Datasheet JEDEC Double Data Rate (DDR) SDRAM Specification Intel® PC SDRAM Specification
Accelerated Graphics Port Interface Specification, Revision 2.0
NOTES: 1. For additional related documents, refer to the Intel® 848PChipset Platform Design Guide. 2. Contact your Intel Field Sales Representative.
Intel® 82848P MCH Datasheet
Introduction
Intel® 848P Chipset System Overview
Intel® 82848P MCH Datasheet
Introduction
Figure 1. Intel® 848P Chipset System Block Diagram
Processor 400 / 533 / 800 MHz FSB
Intel® 848P Chipset System Memory DDR
2.1 GB / s AGP 8x / 4x Intel® 82848P MCH CSA Interface Gigabit Ethernet 266 MB / s 2.1 GB / s up to 3.2 GB / s 266 MB / s HI 1.5 USB 2.0 8 ports, 480 Mb / s
Power Management Clock Generation
2 Serial ATA Ports 150 MB / s
2 ATA 100 Ports
Flash BIOS
LPC Interface
Sys Blk 875P 1
Intel® 82848P MCH Datasheet
Introduction
Intel® 82848P MCH Overview
Host Interface
Intel® 82848P MCH Datasheet
Introduction
System Memory Interface
Supports one 64-bit wide DDR data channel Available bandwidth up to 3.2 GB / s (DDR400). Support for non ECC. Supports 128-Mb, 256-Mb, 512-Mb DDR technologies Supports only x8, x16, DDR devices with four banks Registered DIMMs not supported Supports opportunistic refresh SPD (Serial Presence Detect) scheme for DIMM detection support Suspend-to-RAM support using CKE Supports configurations defined in the JEDEC DDR1 DIMM specification only Up to 2.0 GB of DDR Supports up to two DDR DIMMs, single-sided and / or double-sided Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs Supports up to 16 simultaneous open pages Does not support mixed-mode / uneven double-sided DDR DIMMs
Hub Interface
Communications Streaming Architecture (CSA) Interface
The CSA interface connects the MCH with a Gigabit Ethernet (GbE) controller. The MCH supports only HI 1.5 over the interface that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The CSA interface runs at 266 MT / s (with 66 MHz base clock) and uses 1.5 V signaling.
Intel® 82848P MCH Datasheet
Introduction
AGP 8X Interface
Clock Ratios
Table 2 lists the supported system memory clock ratios. AGP, CSA, and HI run at 66 MHz common clock and asynchronous to the chipset core. There is no required skew or ratio between FSB / chipset core and 66 MHz system clocks.
Table 2.
System Memory Clock Ratios
Host Clock DRAM Clock Ratios DRAM Data Rate DRAM Type Peak Bandwidth
100 MHz 133 MHz 200 MHz 133 MHz 200 MHz) 200 MHz
133 MHz 133 MHz 133 MHz 166 MHz 160 MHz 200 MHz
DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM
Intel® 82848P MCH Datasheet
Introduction
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Intel® 82848P MCH Datasheet
Signal Description
This chapter provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O I / O s / t / s Input pin Output pin Bi-directional Input / Output pin Sustained Tri-state. This pin is driven to its inactive state prior to tri-stating.
The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I / O Specification for complete details. The MCH integrates AGTL+ termination resistors, and supports VTT from1.15 V to 1.55 V (not including guard banding). AGP interface signals. These signals are compatible with AGP 2.0 1.5 V signaling and AGP 3.0 0.8 V swing signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. Hub Interface 1.5 compatible signals Low Voltage TTL 3.3 V compatible signals Stub Series Terminated Logic 2.6 V compatible signals.
2.6 VGPIO 2.6 V buffers used for misc GPIO signals 3.3 VGPIO 3.3 V buffers used for DAC / DCC signals CMOS CMOS buffers.
Host Interface signals that perform multiple transfers per clock cycle may be marked as either "4X" (for signals that are "quad-pumped") or 2X (for signals that are "double-pumped"). Note that the processor address and data bus signals are logically inverted signals. In other words, the actual values are inverted from what appears on the processor bus. This has been taken into account in the 848P chipset and the address and data bus signals are inverted inside the MCH host bridge. All processor control signals follow normal convention. A 0 indicates an active low level (low voltage) if the signal name is followed by # symbol a 1 indicates an active high level (high voltage) if the signal has no # suffix.
Intel® 82848P MCH Datasheet
Signal Description
Figure 2. Intel® 82848P MCH Interface Block Diagram
Processor Sy stem Bus Interf ace
AGP Interf ace
Sy stem Memory DDR Voltage Ref ernce, RCOMP, VSWING, and Power
Hub Interf ace
CSA Interf ace
Clocks, Reset, & Test
Intel® 82848P MCH Datasheet
Signal Description
Host Interface Signals
BPRI#
O AGTL+
BREQ0#
O AGTL+
BSEL1:0
I CMOS
CPURST#
O AGTL+
DBSY# DEFER#
I / O AGTL+ O AGTL+
DINV3:0#
DINVx#
Data Bits
DINV3# DINV2# DINV1# DINV0#
HD63:48# HD47:32# HD31:16# HD15:0#
NOTE: This signal is called DBI3:0 in the Intel processor specification.
DRDY#
Data Ready: This signal is asserted for each cycle that data is transferred.
Intel® 82848P MCH Datasheet
Signal Description
Signal Name
Description Host Address Bus: HA31:3# connect to the processor address bus. During processor cycles the HA31:3# are inputs. The MCH drives HA31:3# during snoop cycles on behalf of HI and AGP / Secondary PCI initiators. HA31:3# are transferred at 2X rate. Note that the address is inverted on the processor bus. NOTE: The MCH drives the HA7# signal, which is then sampled by the processor and the MCH on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. Host Address Strobe: HADSTB1:0# are source synchronous strobes used to transfer HA31:3# and HREQ4:0# at the 2X transfer rate. Strobe Address Bits HADSTB0# A16:3#, REQ4:0# HADSTB1# A31:17# Host Data: These signals are connected to the processor data bus. Data on HD63:0# is transferred at a 4X rate. Note that the data signals may be inverted on the processor bus, depending on the DINV3:0 signals. Differential Host Data Strobes: These signals are differential source synchronous strobes used to transfer HD63:0# and DINV3:0# at the 4X transfer rate.
HA31:3#
HADSTB1:0#
HD63:0#
HDSTBP3:0# HDSTBN3:0#
Strobe
Data Bits
HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0#
HD63:48#, DINV3# HD47:32#, DINV2# HD31:16#, DINV1# HD15:0#, DINV0#
I / O AGTL+ I / O AGTL+ I AGTL+
Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. HIT# is also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. HITM# is also driven in conjunction with HIT# to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic (i.e., no HI or AGP / PCI snoopable access to system memory are allowed when HLOCK# is asserted by the processor). Host Request Command: These signals define the attributes of the request. HREQ4:0# are transferred at 2X rate. They are asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type.
HITM#
HLOCK#
HREQ4:0#
The transactions supported by the MCH Host Bridge are defined in the Chapter 5.
Intel® 82848P MCH Datasheet
Signal Description
Signal Name
HTRDY# PROCHOT#
O AGTL+ I / 0 AGTL+
RS2:0#
Idle state Retry response Deferred response Reserved (not driven by MCH) Hard Failure (not driven by MCH) No data response Implicit Writeback Normal data response
The following is the list of processor bus interface signals that are not supported by the MCH.
Signal Name Not Supported Function Not Supported Thus, MCH Does Not Support
AP1:0# DP3:0# HA35:32 RSP# IERR# BINIT# MCERR#
Address bus parity Data parity Upper address bits Response (RS) parity Processor Internal Error Bus Initialization Signal Machine Check Error
Parity protection on address bus Data parity errors on host interface Only supports a 4-GB system address space Response parity errors on host interface Responding to processor internal error Reset of the Host Bus state machines. Signaling or recognition of Machine Check Error
Intel® 82848P MCH Datasheet
Signal Description
Memory Interface
DDR DRAM Interface
Intel® 82848P MCH Datasheet
Signal Description
Hub Interface
Signal Name Type Description Packet Data: HI10:0 are the data signals used for HI read and write operations. Packet Strobe: HISTRS is one of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: HISTRF is one of two differential strobe signals used to transmit or receive packet data over HI.
HI10:0 HISTRS HISTRF
CSA Interface
Signal Name Type Description Packet Data: CI10:0 are data signals used for CI read and write operations. Packet Strobe: CISTRS is one of two differential strobe signals used to transmit or receive packet data over CI. Packet Strobe Complement: CISTRF is one of two differential strobe signals used to transmit or receive packet data over CI.
CI10:0 CISTRS CISTRF
Intel® 82848P MCH Datasheet
Signal Description
AGP Interface Signals
AGP Addressing Signals
Signal Name Type Description Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master enqueues one request each rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new requests are enqueued across the GAD bus.
Sideband Address: This bus provides an additional bus to pass address and command to the MCH from the AGP master.
GSBA7:0 (2.0) GSBA7:0# (3.0)
NOTE: In AGP 2.0 signaling mode, when sideband addressing is disabled, these signals are isolated. When sideband addressing is enabled, internal pull-ups are enabled to prevent indeterminate values on them in cases where the Graphics Card may not have its GSBA7:0 output drivers enabled yet.
NOTES: 3. The previous table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When GPIPE# is used to queue addresses the master is not allowed to queue addresses using the SB bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset. 4. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 5. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
Intel® 82848P MCH Datasheet
Signal Description
AGP Flow Control Signals
Signal Name Type Description Read Buffer Full: This signal indicates if the master is ready to accept previously requested low priority read data. When GRBF(#) is asserted, the MCH is not allowed to return low priority read data to the AGP master on the first block. GRBF(#) is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data, it is not required to implement this signal. Write Buffer Full: This signal indicates if the master is ready to accept fast write data from the MCH. When GWBF(#) is asserted, the MCH is not allowed to drive fast write data to the AGP master. GWBF(#) is only sampled at the beginning of a cycle.
GRBF# (2.0) GRBF (3.0)
GWBF# (2.0) GWBF (3.0)
If the AGP master is always ready to accept fast write data, it is not required to implement this signal.
NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
AGP Status Signals
Signal Name Type Description Status: These signals provide information from the arbiter to an AGP Master on what it may do. GST2:0 only have meaning to the master when its GGNT(#) is asserted. When GGNT(#) is deasserted, these signals have no meaning and must be ignored. GST2:0 are always an output from the MCH and an input to the master. Encoding Meaning 000 Previously requested low priority read data (Async read for AGP 3.0 signaling mode) is being returned to the master. 001 Previously requested high priority read data is being returned to the master. Reserved in AGP 3.0 signaling mode. 010 The master is to provide low priority write data (Async write for AGP 3.0 signaling mode) for a previously queued write command. 011 The master is to provide high priority write data for a previously queued write command. Reserved in AGP 3.0 signaling mode. 100 Reserved. 101 Reserved. 110 Reserved. 111 The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting GPIPE# (4X signaling mode) or start a PCI transaction by asserting GFRAME(#).
GST2:0 (2.0) GST2:0 (3.0)
Intel® 82848P MCH Datasheet
Signal Description
AGP Strobes
GADSTB0 (2.0) GADSTBF0 (3.0)
GADSTB0# (2.0) GADSTBS0 (3.0)
GADSTB1 (2.0) GADSTBF1 (3.0)
GADSTB1# (2.0) GADSTBS1 (3.0)
GSBSTB (2.0) GSBSTBF (3.0)
GSBSTB# (2.0) GSBSTBS (3.0)
NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
Intel® 82848P MCH Datasheet
Signal Description
PCI Signals-AGP Semantics
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using PCI protocol, these signals completely preserve PCI 2.1 semantics. The exact roles of all PCI signals during AGP transactions are defined in the following table.
GFRAME# (2.0) GFRAME (3.0)
GIRDY# (2.0) GIRDY (3.0)
GTRDY# (2.0) GTRDY (3.0)
GSTOP# (2.0) GSTOP (3.0) GDEVSEL# (2.0) GDEVSEL (3.0) GREQ# (2.0) GREQ (3.0) GGNT# (2.0) GGNT (3.0)
GAD31:0
GC / BE3:0# (2.0) GC# / BE3:0 (3.0)
GPAR (2.0) GPAR (3.0)
Intel® 82848P MCH Datasheet
Signal Description
Signal Name
Description Dynamic Bus Inversion LO: (AGP 3.0 only) This bit that goes along with GAD15:0 to indicate whether GAD15:0 must be inverted on the receiving end.
NOTES: 1. Note that PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic. 2. LOCK# signal is not supported on the AGP interface (even for PCI operations). 3. (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing) 4. (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing)
PCI Pins during PCI Transactions on AGP Interface
PCI signals described in a previous table behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP interface.
Test Signals
Intel® 82848P MCH Datasheet
Signal Description
Clocks, Reset, and Miscellaneous
Signal Name Type Description Differential Host Clock In: These pins receive a low voltage differential host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the host clock domain 0.7 V. 66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP / PCI and HI clock domains. Note that this clock input is required to be 3.3 V tolerant. Reset In: When asserted, this signal asynchronously resets the MCH logic. This signal is connected to the PCIRST# output of the ICH5. All AGP / PCI output and bi-directional signals will also tri-state compliant to PCI Revision 2.0 and 2.1 specifications. This input should have a Schmitt trigger to avoid spurious resets. Note that this input needs to be 3.3 V tolerant. Power OK: When asserted, PWROK is an indication to the MCH that the core power and GCLKIN have been stable for at least 10 µs. External Thermal Sensor Input: This is an open-drain signal indicating an OverTemp condition in the platform. This signal should remains asserted for as long as the Over-temp Condition exists. This input pin can be programmed to activate hardware management of memory reads and writes and / or trigger software interrupts.
HCLKP HCLKN
I CMOS I LVTTL (3.3 V) I LVTTL (3.3 V) I LVTTL (3.3 V) I LVTTL (3.3 V)
GCLKIN
RSTIN#
PWROK
EXTTS#
Intel® 82848P MCH Datasheet
Signal Description
RCOMP, VREF, VSWING
HDVREF HDRCOMP HDSWING
SMXRCOMPVOL SMXRCOMPVOH SMXRCOMP
SMYRCOMPVOL SMYRCOMPVOH SMYRCOMP GVREF GVSWING
NOTE: Refer to the Intel® 848P Chipset Platform Design Guide for platform design information.
Intel® 82848P MCH Datasheet
Signal Description
Power and Ground Signals
MCH Sequencing Requirements
Power Plane and Sequencing Requirements:
· Clock Valid Timing. · GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK. · HCLKN / HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#.
Figure 3. Intel® 848P Chipset System Clock and Reset Requirements
POWER
~100 ms
PWROK
RSTIN#
10 us min GCLKIN valid
10 us min HCLKN / HCLKP valid
Intel® 82848P MCH Datasheet
Signal Description
The MCH uses the rising edge of PWROK to latch strap values. During S3, when power is not valid, the MCH requires that PWROK de-assert and then re-assert when power is valid so that it can properly re-latch the straps.
Signals Used As Straps
Functional Straps
Signal Name Strap Name Description
The value on HA7# is sampled by all processor bus agents, including the MCH, on the de-asserting edge of CPURST#. FSB IOQ Depth
NOTE: For HA7#, the minimum setup time is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs.
NOTE: 1. All straps, have internal 8 k pull-ups (HA7# has GTL pull-up) enabled during their sampling window. Therefore, a strap that is not connected or not driven by external logic will be sampled high.
Strap Input Signals
BSEL1:0
I CMOS
Intel® 82848P MCH Datasheet
Signal Description
Full and Warm Reset States
Figure 4. Full and Warm Reset Waveforms
Intel® ICH5 Power
ICH5 PWROK In 1 ms min ICH5 PCIRST# Out MCH RSTIN# In 1 ms MCH CPURST# Out
Write to CF9h
MCH Power
MCH PWROK In
MCH Reset State
Unknown
Full Reset Warm Reset
Running
Warm Reset
Running
All register bits assume their default values during full reset. PCIRST# resets all internal flops and state machines (except for a few configuration register bits). A full reset occurs when PCIRST# (MCH RSTIN#) is asserted and PWROK is deasserted. A warm reset occurs when PCIRST# (MCH RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states.
Reset State RSTIN# PWROK
Full Reset Warm Reset Does Not Occur Normal Operation
Intel® 82848P MCH Datasheet
Signal Description
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Intel® 82848P MCH Datasheet
Register Description
The MCH contains two sets of software accessible registers, accessed via the host processor I / O address space:
· Control registers I / O mapped into the processor I / O space that controls access to PCI and AGP
configuration space.
· Internal configuration registers residing within the MCH are partitioned into three logical
Register Terminology
Term Description Read Only. If a register is read only, writes to this register have no effect. Read / Write. A register with this attribute can be read and written. Read / Write / Lock. A register with this attribute can be read, written, and Locked. Read / Write Clear. A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read / Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
Reserved Bits
Intel® 82848P MCH Datasheet
Register Description
Description
Reserved Registers
In addition to reserved bits within a register, the MCH contains address locations in the configuration space of the Host-HI Bridge entity that are marked either "Reserved" or "Intel Reserved". The MCH responds to accesses to Reserved address locations by completing the host cycle. When a Reserved register location is read, a zero value is returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved registers have no effect on the MCH. Caution: Registers that are marked as "Intel Reserved" must not be modified by system software. Writes to "Intel Reserved" registers may cause system failure. Reads to "Intel Reserved" registers may return a non-zero value. Upon a reset, the MCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the MCH registers accordingly.
Default Value upon a Reset
Overview of the Platform Configuration Structure
· Device 0: Host-HI Bridge / DRAM Controller. Logically this appears as a PCI device residing
on PCI bus 0. Physically Device 0 contains the standard PCI registers, DRAM registers, the Graphics Aperture controller, configuration for HI, and other MCH specific registers.
· Device 1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing
on PCI bus 0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP / PCI configuration registers (including the AGP I / O and memory address mapping).
· Device 3: CSA Port. Appears as a virtual PCI-CSA (PCI-to-PCI) bridge device. · Device 6: Function 0: Overflow Device. The purpose of this device is to provide additional
configuration register space for Device 0.
Intel® 82848P MCH Datasheet
Register Description
Table 3 shows the Device # assignment for the various internal MCH devices. Table 3. Internal MCH Device Assignment
MCH Function Bus 0, Device #
DRAM Controller / 8-bit HI Controller Host-to-AGP Bridge (virtual PCI-to-PCI) Intergrated GBE (CSA) Overflow
Device 0 Device 1 Device 3 Device 6
Logically, the ICH5 appears as multiple PCI devices within a single physical component also residing on PCI bus 0. One of the ICH5 devices is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI 0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus 0 does not exist and the hub interface and the internal devices in the MCH and ICH5 logically constitute PCI Bus 0 to configuration software.
Figure 5. Conceptual Intel® 848P Chipset Platform PCI Configuration Diagram
Processor
Host-AGP Bus 0 Device 1 CSA Bus 0 Device 3
PCI Configuration Window I / O Space
DRAM Control / Hub Interface Bus 0 Device 0, 6 Hub Interface
Hub Interface
Intel® ICH5
LPC Bus 0 Device Fcn 0
Hub Interface - PCI Bridge PBus 0 Fcn 0
Intel® 82848P MCH Datasheet
Register Description
Routing Configuration Accesses
Standard PCI Bus Configuration Mechanism
PCI Bus 0 Configuration Mechanism
Primary PCI and Downstream Configuration Mechanism
Intel® 82848P MCH Datasheet
Register Description
Figure 6. Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping
31 1 Reserved 24 23 Bus Number 16 15 14 11 10 8 7 Register Number 2 1 x 0 x Device Number Function #
24 23 IDSEL
8 7 Register Number
Function #
AGP GAD31:0 Address AGP / PCI1 Type 0 Configuration Cycle
Table 4.
Configuration Address Decoding
Config Address AD15:11 AGP GAD31:16 IDSEL Config Address AD15:11 AGP GAD31:16 IDSEL
01000 01001 01010 01011 01100 01101 01110 01111 1xxxx
Intel® 82848P MCH Datasheet
Register Description
Function Number
Reg. Index
PCI Address AD31:0 31
Bus Number 16 15
Device Number
Function Number
Reg. Index 2 1
I / O Mapped Registers
Intel® 82848P MCH Datasheet
Register Description
I / O Address: Default Value: Access: Size: 0CF8h Accessed as a DWord 00000000h R / W 32 bits
Bit Descriptions Configuration Enable (CFGE).
Reserved.
Intel® 82848P MCH Datasheet
Register Description
I / O Address: Default Value: Access: Size: 0CFCh 00000000h R / W 32 bits
Intel® 82848P MCH Datasheet
Register Description
DRAM Controller / Host-Hub Interface Device Registers (Device 0)
DRAM Controller / Host-Hub Interface Device Register Address Map (Device 0) (Sheet 1 of 2)
Address Offset Register Symbol Register Name Default Value Access
Table 5.
00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0C 0Dh 0Eh 0Fh 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-50h 51h 52h 53h 54-5Fh 60h 61-89h 90h 91h 92h 93h 94h 95h 96h 97h 98-9Ch
VID DID PCICMD PCISTS RID - SUBC BCC - MLT HDR - APBASE - SVID SID - CAPPTR - AGPM - CSABCONT - FPLLCONT - PAM0 PAM1 PAM2 PAM3 PAM4 PAM5 PAM6 FDHC -
Vendor Identification Device Identification PCI Command PCI Status Revision Identification Intel Reserved Sub-Class Code Base Class Code Intel Reserved Master Latency Timer Header Type Intel Reserved Aperture Base Configuration Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved AGP Miscellaneous Config Intel Reserved CSA Basic Control R Intel Reserved FPLL Clock Control Intel Reserved Programmable Attribute Map 0 Programmable Attribute Map 1 Programmable Attribute Map 2 Programmable Attribute Map 3 Programmable Attribute Map 4 Programmable Attribute Map 5 Programmable Attribute Map 6 Fixed DRAM Hole Control Intel Reserved
8086h 2570h 0006h 0090h see register description - 00h 06h - 00h 00h - 00000008h - 0000h 0000h - E4h - 00h - 00h - 00h - 00h 00h 00h 00h 00h 00h 00h 00h -
Intel® 82848P MCH Datasheet
Register Description
Table 5.
DRAM Controller / Host-Hub Interface Device Register Address Map (Device 0) (Sheet 2 of 2)
Address Offset Register Symbol Register Name Default Value Access
9Dh 9Eh 9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B4h B5-B7h B8-BBh BCh BDh BE-C3h C4-C5h C6-C7h C8-C9h CA-CEh CF-DDh DE-DFh E0-E3h E4-E8h E9-FFh
SMRAM ESMRAMC - ACAPID AGPSTAT AGPCMD - AGPCTRL APSIZE - ATTBASE AMTT LPTT - TOUD MCHCFG ERRSTS ERRCMD - SKPD - CAPREG -
System Management RAM Control Extended System Management RAM Control Intel Reserved AGP Capability Identifier AGP Status AGP Command Intel Reserved AGP Control Aperture Size Intel Reserved Aperture Translation Table AGP MTT Control Register AGP Low Priority Transaction Timer Intel Reserved Top of Used DRAM MCH Configuration Error Status Register Error Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved
Intel® 82848P MCH Datasheet
Register Description
VID-Vendor Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 00-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identifies any PCI device.
Bit Descriptions Vendor Identification (VID)-RO. This register field contains the PCI standard identification for Intel, 8086h.
DID-Device Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 02-03h 2570h RO 16 bits
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI device.
Bit Descriptions Device Identification Number (DID)-RO. This is a 16-bit value assigned to the MCH Host-HI Bridge Function 0.
Intel® 82848P MCH Datasheet
Register Description
PCICMD-PCI Command Register (Device 0)
Address Offset: Default Value: Access: Size: 04-05h 0006h RO, R / W 16 bits
Bit Descriptions
Reserved
Fast Back-to-Back Enable (FB2B)-RO. Hardwired to 0. This bit controls whether or not the master can do fast back-to-back write. Since Device 0 is strictly a target this bit is not implemented. SERR Enable (SERRE)-R / W. This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have a SERR signal. The MCH communicates the SERR condition by sending a SERR message over HI to the ICH5.
Address / Data Stepping Enable (ADSTEP)-RO. Hardwired to 0. Parity Error Enable (PERRE)-RO. Hardwired to 0. PERR# is not implemented by MCH. VGA Palette Snoop Enable (VGASNOOP)-RO. Hardwired to 0. Memory Write and Invalidate Enable (MWIE)-RO. Hardwired to 0. The MCH will never issue memory write and invalidate commands. Special Cycle Enable (SCE)-RO. Hardwired to 0. Bus Master Enable (BME)-RO. Hardwired to 1. MCH is always enabled as a master on HI. Memory Access Enable (MAE)-RO. Hardwired to 1. The MCH always allows access to main memory. I / O Access Enable (IOAE)-RO. Hardwired to 0.
Intel® 82848P MCH Datasheet
Register Description
PCISTS-PCI Status Register (Device 0)
Address Offset: Default Value: Access: Size: 06-07h 0090h RO, R / WC 16 bits
Reserved
Capability List (CLIST)-RO. Hardwired to 1 to indicate to the configuration software that this device / function implements a list of new capabilities. A list of new capabilit