Intel® 82848P Memory Controller (MCH) Document Number: 253575-001
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Intel® 848P Chipset
Intel® 82848P Memory Controller (MCH)
Document Number: 253575-001
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Contents
Contents
Introduction
Terminology.13 Related Documents.14 Intel® 848P Chipset System Overview.15 Intel® 82848P Overview.17 1.4.1 Host Interface 1.4.2 System Memory Interface 1.4.3 Interface.18 1.4.4 Communications Streaming Architecture (CSA) Interface 1.4.5 Interface Clock Ratios Host Interface Signals Memory Interface 2.2.1 DRAM Interface Interface.27 Interface Interface Signals 2.5.1 Addressing Signals 2.5.2 Flow Control Signals 2.5.3 Status Signals 2.5.4 Strobes 2.5.5 Signals-AGP Semantics 2.5.5.1 Pins during Transactions Interface.32 Test Signals.32 Clocks, Reset, Miscellaneous RCOMP, VREF, VSWING.34 Power Ground Signals Sequencing Requirements.35 Signals Used Straps.36 2.11.1 Functional Straps 2.11.2 Strap Input Signals 2.11.3 Full Warm Reset States Register Terminology Overview Platform Configuration Structure Routing Configuration Accesses 3.3.1 Standard Configuration Mechanism 3.3.2 Configuration Mechanism 3.3.3 Primary Downstream Configuration Mechanism 3.3.4 AGP/PCI_B Configuration Mechanism Mapped Registers 3.4.1 CONFIG_ADDRESS-Configuration Address Register 3.4.2 CONFIG_DATA-Configuration Data Register
Signal Description
2.10 2.11
Register Description
Contents
DRAM Controller/Host-Hub Interface Device Registers (Device 3.5.1 VID-Vendor Identification Register (Device 3.5.2 DID-Device Identification Register (Device 3.5.3 PCICMD-PCI Command Register (Device 3.5.4 PCISTS-PCI Status Register (Device 3.5.5 RID-Revision Identification Register (Device 3.5.6 SUBC-Sub-Class Code Register (Device 3.5.7 BCC-Base Class Code Register (Device 3.5.8 MLT-Master Latency Timer Register (Device 3.5.9 HDR-Header Type Register (Device 3.5.10 APBASE-Aperture Base Configuration Register (Device 3.5.11 SVID-Subsystem Vendor Identification Register (Device 3.5.12 SID-Subsystem Identification Register (Device 3.5.13 CAPPTR-Capabilities Pointer Register (Device 3.5.14 AGPM-AGP Miscellaneous Configuration Register (Device 3.5.15 CSABCONT-CSA Basic Control Register (Device 3.5.16 FPLLCONT-Front Side Clock Control Register (Device 3.5.17 PAM[0:6]-Programmable Attribute Registers. 3.5.18 FDHC-Fixed Memory (ISA) Hole Control Register (Device 3.5.19 SMRAM-System Management Control Register (Device 3.5.20 ESMRAMC-Extended System Management Control (Device 3.5.21 ACAPID-AGP Capability Identifier Register (Device 3.5.22 AGPSTAT-AGP Status Register (Device 3.5.23 AGPCMD-AGP Command Register (Device 3.5.24 AGPCTRL-AGP Control Register (Device 3.5.25 APSIZE-Aperture Size Register (Device 3.5.26 ATTBASE-Aperture Translation Table Register (Device 3.5.27 AMTT-AGP Control Register (Device 3.5.28 LPTT-AGP Priority Transaction Timer Register (Device 3.5.29 TOUD-Top Used DRAM Register (Device 3.5.30 MCHCFG-MCH Configuration Register (Device 3.5.31 ERRSTS-Error Status Register (Device 3.5.32 ERRCMD-Error Command Register (Device 3.5.33 SKPD-Scratchpad Data Register (Device 3.5.34 CAPREG-Capability Identification Register (Device PCI-to-AGP Bridge Registers (Device 3.6.1 VID1-Vendor Identification Register (Device 3.6.2 DID1-Device Identification Register (Device 3.6.3 PCICMD1-PCI Command Register (Device 3.6.4 PCISTS1-PCI Status Register (Device 3.6.5 RID1-Revision Identification Register (Device 3.6.6 SUBC1-Sub-Class Code Register (Device 3.6.7 BCC1-Base Class Code Register (Device 3.6.8 MLT1-Master Latency Timer Register (Device 3.6.9 HDR1-Header Type Register (Device
Contents
PBUSN1-Primary Number Register (Device SBUSN1-Secondary Number Register (Device SUBUSN1-Subordinate Number Register (Device 1).81 SMLT1-Secondary Master Latency Timer Register (Device 3.6.14 IOBASE1-I/O Base Address Register (Device 3.6.15 IOLIMIT1-I/O Limit Address Register (Device 3.6.16 SSTS1-Secondary Status Register (Device 3.6.17 MBASE1-Memory Base Address Register (Device 3.6.18 MLIMIT1-Memory Limit Address Register (Device 3.6.19 PMBASE1-Prefetchable Memory Base Address Register (Device 3.6.20 PMLIMIT1-Prefetchable Memory Limit Address Register (Device 3.6.21 BCTRL1-Bridge Control Register (Device 3.6.22 ERRCMD1-Error Command Register (Device 1).88 PCI-to-CSA Bridge Registers (Device 3).89 3.7.1 VID3-Vendor Identification Register (Device 3.7.2 DID3-Device Identification Register (Device 3).90 3.7.3 PCICMD3-PCI Command Register (Device 3.7.4 PCISTS3-PCI Status Register (Device 3.7.5 RID3-Revision Identification Register (Device 3.7.6 SUBC3-Class Code Register (Device 3.7.7 BCC3-Base Class Code Register (Device 3).93 3.7.8 MLT3-Master Latency Timer Register (Device 3.7.9 HDR3-Header Type Register (Device 3.7.10 PBUSN3-Primary Number Register (Device 3.7.11 SBUSN3-Secondary Number Register (Device 3.7.12 SMLT3-Secondary Master Latency Timer Register (Device 3.7.13 IOBASE3-I/O Base Address Register (Device 3.7.14 IOLIMIT3-I/O Limit Address Register (Device 3.7.15 SSTS3-Secondary Status Register (Device 3.7.16 MBASE3-Memory Base Address Register (Device 3.7.17 MLIMIT3-Memory Limit Address Register (Device 3.7.18 PMBASE3-Prefetchable Memory Base Address Register (Device 3.7.19 PMLIMIT3-Prefetchable Memory Limit Address Register (Device 3.7.20 BCTRL3-Bridge Control Register (Device .100 3.7.21 ERRCMD3-Error Command Register Registers (Device 3).101 3.7.22 CSACNTRL-CSA Control Registers (Device .101 Overflow Configuration Registers (Device .102 3.8.1 VID6-Vendor Identification Register (Device .102 3.8.2 DID6-Device Identification Register (Device 6).103 3.8.3 PCICMD6-PCI Command Register (Device .103 3.8.4 PCISTS6-PCI Status Register (Device .104 3.8.5 RID6-Revision Identification Register (Device .104 3.8.6 SUBC6-Sub-Class Code Register (Device .105 3.8.7 BCC6-Base Class Code Register (Device 6).105 3.8.8 HDR6-Header Type Register (Device .105
3.6.10 3.6.11 3.6.12 3.6.13
Contents
BAR6-Memory Delays Base Address Register (Device SVID6-Subsystem Vendor Identification Register (Device 3.8.11 SID6-Subsystem Identification Register (Device Device Memory-Mapped Register Space. 3.9.1 DRB[0:7]-DRAM Boundary Register (Device MMR). 3.9.2 DRA- DRAM Attribute Register (Device MMR). 3.9.3 DRT-DRAM Timing Register (Device MMR). 3.9.4 DRC-DRAM Controller Mode Register (Device MMR) System Memory Address Ranges. Compatibility Area Extended Memory Area 4.3.1 15-MB-16-MB Window 4.3.2 Pre-Allocated Memory. Memory Address Ranges Processor Front Side (FSB) 5.1.1 Overview 5.1.2 Dynamic Inversion. 5.1.3 Interrupt Overview 5.1.4 Upstream Interrupt Messages System Memory Controller. 5.2.1 DRAM Technologies Organization 5.2.2 Memory Operating Mode. 5.2.2.1 Dynamic Addressing Mode. 5.2.2.2 Linear Mode. 5.2.3 Memory Address Translation Decoding 5.2.4 Memory Organization Configuration. 5.2.5 Configuration Mechanism DIMMS 5.2.5.1 Memory Detection Initialization. 5.2.5.2 SMBus Configuration Access Serial Presence Detect Ports 5.2.5.3 Memory Register Programming. 5.2.6 Memory Thermal Management 5.2.6.1 Determining When Thermal Manage. Accelerated Graphics Port (AGP) 5.3.1 Support 5.3.2 Selecting between 2.0. 5.3.3 Downshift Data Rate) Mode 5.3.3.1 Mechanism Detecting 2.0, 3.0. 5.3.4 Target Operations. 5.3.5 Transaction Ordering 5.3.6 Support PCI-66 Devices. 5.3.7 Protocol 5.3.7.1 Fast Writes 5.3.7.2 Semantic Transactions Power Management 5.4.1 Supported ACPI States
3.8.9 3.8.10
System Address Map.
Functional Description
Contents
Thermal Management .133 5.5.1 External Thermal Sensor Interface Overview.133 5.5.2 External Thermal Sensor Usage Model .134 Clocking.135 Absolute Maximum Ratings.137 Thermal Characteristics .137 Power Characteristics .138 Signal Groups.138 Parameters.140 Ballout .145 Package Information .156 Test Mode Initialization.159 Chain Definition .161
Electrical Characteristics .137
Ballout Package Information .145
Testability .159
Contents
Figures
Intel® 848P Chipset System Block Diagram Intel® 82848P Interface Block Diagram Intel® 848P Chipset System Clock Reset Requirements Full Warm Reset Waveforms Conceptual Intel® 848P Chipset Platform Configuration Diagram Configuration Mechanism Type Configuration Address Address Mapping Configuration Mechanism Type Configuration Address Address Mapping Register Attributes. Memory System Address Detailed Memory System Address Map. Platform External Sensor Intel® 848P Chipset System Clocking Block Diagram. Intel® 82848P Ballout Diagram (Top View-Left Side) Intel® 82848P Ballout Diagram (Top View-Right Side). Intel® 82848P Package Dimensions (Top Side Views). Intel® 82848P Package Dimensions (Bottom View) Toggling HCLKP HCLKN Testing Chains Tested Sequentially.
Contents
Tables
General Terminology.13 System Memory Clock Ratios Internal Device Assignment Configuration Address Decoding.43 DRAM Controller/Host-Hub Interface Device Register Address (Device Register Attributes PCI-to-Virtual Bridge Configuration Register Address (Device VGAEN MDAP Field Definitions.87 PCI-to-CSA Bridge Configuration Register Address (Device 3).89 VGAEN MDAP Definitions.100 Overflow Device Configuration Register Address (Device 6).102 Device Memory-Mapped Register Address Map.107 Memory Segments Their Attributes.115 Pre-Allocated Memory.117 System Memory Capacity .123 DRAM Address Translation (Single-Channel Mode) (Non-Dynamic Mode).124 DRAM Address Translation (Single-Channel Mode) (Dynamic Mode) .125 Supported DIMM Configurations .125 Data Bytes DIMM Used Programming DRAM Registers .126 Support Matrix .128 Downshift Mode Parameters .129 Strap Values Selecting 3.0.130 Commands Compared .130 Supported Data Rates.131 Absolute Maximum Ratings.137 Power Characteristics .138 Signal Groups.139 Operating Characteristics.140 Characteristics .142 Ballout Signal Name.148 Chain Outputs.161 Chain Inputs) Output Pins: TESTP17, TESTP4 .162 Chain Inputs) Output Pins: TESTP18, TESTP5 .163 Chain Inputs) Output Pins: TESTP19, TESTP6 .163 Chain Inputs) Output Pins: TESTP20, TESTP7 .164 Chain Inputs) Output Pins: TESTP21, TESTP8 .164 Chain Inputs) Output Pins: TESTP22, TESTP9 .165 Chain Inputs) Output Pins: TESTP23, TESTP10 .165 Chain Inputs) Output Pins: TESTP24, TESTP11 .166 Chain Inputs) Output Pins: HTRDY#, BPRI# .166 Chain Inputs) Output Pins: RS2#, DEFER# .167 Excluded Pins.168
Contents
Revision History
Revision -001 Initial Release Description Date
Contents
Intel® 82848P Features
Host Interface Support Intel® Pentium® processors with 512-KB cache 0.13 micron process processor code named Prescott 1.55 ranges 64-bit frequencies (100 clock), (133 clock), (200 clock). Maximum theoretical GB/s. Dynamic Inversion data 32-bit addressing access memory space 12-deep Order Queue AGTL+ On-die Termination (ODT) Hyper-Threading Technology System Memory Controller Support Single-channel bits wide) memory interface Symmetric asymmetric memory upgrade 128-Mb, 256-Mb, 512-Mb technologies implemented devices four bank devices Non-ECC, un-buffered DIMMS only Maximum DIMMs, with each DIMM having rows 2-GB system memory open pages 4-KB 32-KB page sizes Opportunistic refresh Suspend-to-RAM support using (Serial Presence Detect) Scheme DIMM Detection (Double Data Rate type Maximum DIMMs, single-sided and/or double-sided DDR266, DDR333, DDR400 DIMM modules channel operation MHz, MHz, with Peak GB/s, GB/s, GB/s, respectively Burst length bytes access, respectively) SSTL_2 signaling
Communication Streaming Architecture (CSA) Interface Support Gigabit Ethernet (GbE) communication devices supported interface (e.g., Intel® 82547EI controller) 8-bit Interface electrical/transfer protocol MB/s point-to-point connection operation Interface (HI) Support Interface MB/s point-to-point connection ICH5 base clock operation Interface Support Single device with data transfers fast writes, respectively 32-bit 4X/8X data transfers 4X/8X fast writes Peak GB/s. signalling levels; support 1X/4X data transfers fast writes 32-deep request queue Package 37.5 37.5 Flip Chip Ball Grid Array (FC-BGA) package solder balls
Contents
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Introduction
Introduction
This Memory Controller (MCH) datasheet Intel® 82848P MCH. 82848P part Intel® 848P chipset. Each chipset contains main components: Memory Controller (MCH) host bridge Controller subsystem. provides processor interface, system memory interface, interface, interface, interface 848P chipset desktop platform. 848P chipset uses either Intel® 82801EB ICH5 Intel® 82801ER ICH5R Controller Hub.
Table
Terminology
This section provides definitions some terms used this document. General Terminology (Sheet
Terminology Description Accelerated Graphics Port. this document refers AGP/PCI interface that MCH. interface supports only V/1.5 2.0/AGP compliant devices using MHz), MHz), (266 MHz), (533 MHz) transfers. does support devices. PIPE# addressing cycles their associated data phases generally referred transactions. FRAME# cycles generally referred AGP/PCI transactions. DRAM chips divided into multiple banks internally. Commodity parts bank, which only type supports. Each bank acts somewhat like separate DRAM, opening closing pages independently, allowing different pages open each. Most commands DRAM target specific bank, some commands (i.e., Precharge All) targeted banks. Multiple banks allows higher performance interleaving banks reducing page miss cycles. DRAM channel signals that connect DRAM DIMMs. internal base logic. Column address selects DRAM location, starting location burst, from within open page read write command. Terminology often used describe DIMM that contains DRAM rows. Generally Double-Sided DIMM contains rows, with exception noted above. This terminology used within this document. Double Data Rate SDRAM. describes type DRAMs that transfers data items clock each pin. This only type DRAM supported MCH. Full Reset defined this document when RSTIN# asserted. Graphics Aperture Re-map Table. GART table memory containing page re-map information used during aperture address translations. Memory Controller component that contains processor interface, DRAM controller, interface, interface. communicates with controller (ICH5) over proprietary interconnects called Graphics Translation Look-aside Buffer. cache used store frequently used GART entries. Interface. proprietary interconnect that connects ICH5. this document cycles originating from destined primary interface ICH5 generally referred HI/PCI simply cycles.
Bank
Channel Chipset Core Column Address Double-Sided DIMM Full Reset GART
GTLB
Intel® 82848P
Introduction
Table
General Terminology (Sheet
Terminology Host Intel® ICH5 Description This term used synonymously with processor. Fifth generation Controller component that contains additional functionality compared Intel® ICH4. physical that driven directly ICH5 component. Communication between occurs over Note that even though Primary referred from configuration standpoint. Processor Front Side Bus. group DRAM chips that fill data width system accessed parallel each DRAM command. address presented DRAMs during Activate command indicates which page open within specified bank (the bank number also presented). Processor-to-MCH interface. compatible mode Scalable Bus. Enhanced Mode Scalable plus enhancements primarily consisting source synchronous transfers address data, interrupt delivery. Intel® Pentium® processor implements subset enhanced mode. Terminology often used describe DIMM that contains DRAM row. Usually fits single side DIMM allowing backside empty. Single Data Rate SDRAM. Synchronous Dynamic Random Access Memory. physical interface that subset driven directly MCH. supports subset 32-bit, compliant components, only (not Stub Series Terminated Logic Volts (DDR)
Primary Address
Scalable
Single-Sided DIMM SDRAM Secondary SSTL_2
Related Documents
Document1 Intel® 848P Chipset Platform Design Guide Intel® 848P Chipset Thermal Design Guide Intel 848P Chipset Customer Reference Board Schematics Intel 82801EB Controller (ICH5) Intel 82801ER Controller (ICH5R) Datasheet Intel® Pentium® Processors with 512-KB Cache 0.13 Micron Process Datasheet JEDEC Double Data Rate (DDR) SDRAM Specification Intel® SDRAM Specification
Document Number/ Location chipsets/designex/ Note Note chipsets/datashts/252516.htm pentium4/datashts/298643.htm www.jedec.org http://developer.intel.com/ technology/memory/pcsdram/spec/ index.htm agp/agp_index.htm
Accelerated Graphics Port Interface Specification, Revision
NOTES: additional related documents, refer Intel® 848PChipset Platform Design Guide. Contact your Intel Field Sales Representative.
Intel® 82848P
Introduction
Intel® 848P Chipset System Overview
Figure shows example block diagram 848P chipset-based platform. 848P chipset designed desktop system based Pentium processor with 512-KB cache 0.13 micron process 478-pin package processor code named Prescott. processor interface supports Pentium processor subset Extended Mode Scalable Protocol. 848P chipset-based platform, many functions integrated onto ICH5. 848P chipset platform supports external graphics device AGP. MCH's interface supports 1x/4x/8x data transfers 4x/8x fast writes, defined Accelerated Graphics Port Interface Specification, Revision 3.0. provides Communications Streaming Architecture (CSA) Interface that connects Gigabit Ethernet (GbE) controller. 848P chipset platforms support system memory. 848P chipset, memory 266/333/400 Double Data Rate (DDR) memory components. Available bandwidth GB/s using DDR400. 82801EB ICH5 integrates Ultra controller, Serial host controllers, EHCI host controller, four UHCI host controllers supporting eight external ports, interface controller, flash BIOS interface controller, interface controller, digital controller, integrated controller, controller interface communication with MCH. ICH5 component provides data buffering interface arbitration required ensure that system interfaces operate efficiently provide bandwidth necessary enable system obtain peak performance. 82801ER ICH5R elevates Serial storage performance next level with Intel® RAID Technology. ACPI compliant ICH5 platform support Full-on, Stop Grant, Suspend RAM, Suspend Disk, Soft-Off power management states. Through integrated functions, ICH5 also supports Alert Standard Format remote management.
Intel® 82848P
Introduction
Figure Intel® 848P Chipset System Block Diagram
Processor 400/533/800
Intel® 848P Chipset System Memory
GB/s 8x/4x Intel® 82848P Interface Gigabit Ethernet MB/s GB/s GB/s MB/s ports, Mb/s
Power Management Clock Generation
GPIO Intel® 82801EB ICH5 Intel® 82801ER ICH5R Connect/ASF System Management (TCO) SMBus 2.0/I2C Masters CODEC support
Serial Ports MB/s
Ports
Flash BIOS
Interface
875P
Intel® 82848P
Introduction
Intel® 82848P Overview
82848P Memory Controller (MCH) provides host bridge interfaces 848P chipset based platform. contains advanced desktop power management logic. MCH's role system manage flow information between five interfaces: processor front side (FSB), memory attached DRAM controller, port, Interface, interface. This includes arbitrating between five interfaces when each initiates operation. While doing must support data coherency snooping must perform address translation access Aperture memory. increase system performance, incorporates several queues write cache.
1.4.1
Host Interface
single Pentium processor with 512-KB cache 0.13 micron process 478-pin package. processor interface supports Intel® Pentium® processor subset extended mode Scalable Protocol. supports frequencies 400/533/800 (100 MHz, MHz, HCLK, respectively) using scalable VCC_CPU. supports 32-bit host addressing, decoding processor's memory address space. Host-initiated cycles decoded AGP/PCI_B, Interface, configuration space. Host-initiated memory cycles decoded AGP/PCI_B, Interface system DDR. memory accesses from host interface that graphics aperture translated using address translation table. AGP/PCI_B device accesses non-cacheable system memory snooped host bus. Memory accesses initiated from AGP/PCI_B using semantics from interface system DRAM will snooped host bus.
Intel® 82848P
Introduction
1.4.2
System Memory Interface
integrates system memory controller with two, 64-bit wide interfaces. Only Double Data Rate (DDR) DRAM memory supported; consequently, buffers support only SSTL_2 signal interfaces. memory controller interface fully configurable through control registers.
System Memory Interface
Supports 64-bit wide data channel Available bandwidth GB/s (DDR400). Support ECC. Supports 128-Mb, 256-Mb, 512-Mb technologies Supports only x16, devices with four banks Registered DIMMs supported Supports opportunistic refresh (Serial Presence Detect) scheme DIMM detection support Suspend-to-RAM support using Supports configurations defined JEDEC DDR1 DIMM specification only Supports DIMMs, single-sided and/or double-sided Supports DDR266, DDR333, DDR400 unregistered non-ECC DIMMs Supports simultaneous open pages Does support mixed-mode uneven double-sided DIMMs
1.4.3
Interface
Interface connects ICH5. Virtually communication between ICH5 occurs over interface. supports only 1.5, which uses protocol with electrical characteristics. interface runs MT/s (with base clock) uses signaling. Acceses between interface AGP/PCI_B limited interface originated memory writes AGP.
1.4.4
Communications Streaming Architecture (CSA) Interface
interface connects with Gigabit Ethernet (GbE) controller. supports only over interface that uses protocol with electrical characteristics. interface runs MT/s (with base clock) uses signaling.
Intel® 82848P
Introduction
1.4.5
Interface
single component connector (not both) supported MCH's interface. Support includes electrical characteristics. Support single PCI-66 device limited subset supported specification. external graphics device requirement. PCI_B buffers operate only mode supports connector. AGP/PCI_B interface supports signaling fast writes. semantic cycles system snooped host bus. semantic cycles system snooped host bus. supports PIPE# SBA[7:0] address mechanisms, both simultaneously. Either PIPE# SBA[7:0] mechanism must selected during system initialization. contains deep request queue. Highpriority accesses supported.
Clock Ratios
Table lists supported system memory clock ratios. AGP, CSA, common clock asynchronous chipset core. There required skew ratio between FSB/chipset core system clocks.
Table
System Memory Clock Ratios
Host Clock DRAM Clock Ratios DRAM Data Rate DRAM Type Peak Bandwidth
MHz)
MT/s MT/s MT/s MT/s MT/s MT/s
DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM
GB/s GB/s GB/s GB/s GB/s GB/s
Intel® 82848P
Introduction
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Intel® 82848P
Signal Description
Signal Description
This chapter provides detailed description signals. signals arranged functional groups according their associated interface. symbol signal name indicates that active, asserted state occurs when signal voltage level. When present after signal name signal asserted when high voltage level. following notations used describe signal type: s/t/s Input Output Bi-directional Input/Output Sustained Tri-state. This driven inactive state prior tri-stating.
signal description also includes type buffer used particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer AGTL+ Specification complete details. integrates AGTL+ termination resistors, supports from1.15 1.55 (not including guard banding). interface signals. These signals compatible with signaling swing signaling Environment Specifications. buffers tolerant. Interface compatible signals Voltage compatible signals Stub Series Terminated Logic compatible signals.
HI15 LVTTL SSTL_2
VGPIO buffers used misc GPIO signals VGPIO buffers used DAC/DCC signals CMOS CMOS buffers.
Host Interface signals that perform multiple transfers clock cycle marked either "4X" (for signals that "quad-pumped") (for signals that "double-pumped"). Note that processor address data signals logically inverted signals. other words, actual values inverted from what appears processor bus. This been taken into account 848P chipset address data signals inverted inside host bridge. processor control signals follow normal convention. indicates active level (low voltage) signal name followed symbol; indicates active high level (high voltage) signal suffix.
Intel® 82848P
Signal Description
Figure Intel® 82848P Interface Block Diagram
HA[31:3]# HD[63:0]# ADS# BNR# BPRI# DBSY DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY RS[2:0]# CPURST# BREQ0# DINV[3:0]# HADSTB[1:0]# HDSTBP[3:0]#, HDSTBN[3:0]# BSEL[1:0] PROCHOT# SCS_A[3:0]# SMAA_A[12:0], SMAB_A[5:1] SBA_A[1:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDQS_A[7:0] SCKE_A[3:0] SCMDCLK_A[5:0], SCMDCLK_A[5:0]# HI[10:0] HISTRS HISTRF CI[10:0] CISTRS CISTRF HCLKP, HCLKN GCLKIN TESTP[29:4,1:0] TESTP[3:2] RSTIN# PWROK EXTTS# GSBA[7:0] GPIPE# GST[2:0] GRBF# GWBF# GADSTB[1:0], GADSTB[1:0]# GSBSTB, GSBSTB# GFRAME# GIRDY GTRDY GSTOP# GDEVSEL# GREQ# GGNT# GAD[31:0] GC/BE[3:0]# GPAR GSBA[7:0]# DBI_HI GST[2:0] GRBF GWBF GADSTBF[1:0], GADSTBS[1:0] GSBSTBF, GSBSTBS GFRAME GIRDY GTRDY GSTOP GDEVSEL GREQ GGNT GAD[31:0] GC#/BE[3:0] GPAR/ADD_DETECT DBI_LO (3.0only
Processor stem Interf
Interf
stem Memory Voltage ernce, RCOMP, VSWING, Power
Interf
Interf
Clocks, Reset, Test
HDVREF HDRCOMP HDSWING SMVREF_A, SMVREF_B SMXRCOMPVOL, RCOMPVOL SMXRCOMPVOH, RCOMPVOH SMXRCOMP, RCOMP GVREF GVSWING GRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING VCCA_AGP VCC_AGP VCCA_FSB VCCA_DPLL VCC_DAC VCCA_DAC VSSA_DAC VCC_DDR VCCA_DDR
875P
Intel® 82848P
Signal Description
Host Interface Signals
Signal Name Type Description Address Strobe: processor owner asserts ADS# indicate first cycles request phase. assert this signal snoop cycles interrupt messages. Block Next Request: This signal used block current request owner from issuing requests. This signal used dynamically control processor pipeline depth. Priority Agent Request: only Priority Agent processor bus. asserts this signal obtain ownership address bus. This signal priority over symmetric requests will cause current symmetric owner stop issuing transactions unless HLOCK# signal asserted. Request pulls processor BREQ0# signal during CPURST#. signal sampled processor active-to-inactive transition CPURST#. minimum setup time this signal HCLKs. minimum hold time clocks maximum hold time HCLKs. BREQ0# should terminated high (Pulled after hold time requirement been satisfied. NOTE: This signal called BR0# Intel processor specification. Core Frequency (FSBFREQ) Select Strap: This strap latched rising edge PWROK. These pins default internal pull-up resistor. Core frequency MHz, frequency Core frequency MHz, frequency Core frequency MHz, frequency Reserved Reset: CPURST# output from MCH. asserts CPURST# while RSTIN# (PCIRST# from Intel® ICH5) asserted approximately after RSTIN# deasserted. CPURST# allows processors begin execution known state. Note that ICH5 must provide processor frequency select strap setup hold times around CPURST#. This requires strict synchronization between CPURST# deassertion ICH5 driving straps. Data Busy: This signal used data owner hold data transfers requiring more than cycle. Defer: DEFER# indicates that will terminate transaction currently being snooped with either deferred response with retry response. Dynamic Inversion: These signals driven along with HD[63:0]# signals. They indicate associated signals inverted. DINV[3:0]# asserted such that number data bits driven electrically (low voltage) within corresponding 16-bit group never exceeds
ADS#
AGTL+ AGTL+
BNR#
BPRI#
AGTL+
BREQ0#
AGTL+
BSEL[1:0]
CMOS
CPURST#
AGTL+
DBSY# DEFER#
AGTL+ AGTL+
DINV[3:0]#
AGTL+
DINV[x]#
Data Bits
DINV3# DINV2# DINV1# DINV0#
HD[63:48]# HD[47:32]# HD[31:16]# HD[15:0]#
NOTE: This signal called DBI[3:0] Intel processor specification.
DRDY#
AGTL+
Data Ready: This signal asserted each cycle that data transferred.
Intel® 82848P
Signal Description
Signal Name
Type
Description Host Address Bus: HA[31:3]# connect processor address bus. During processor cycles HA[31:3]# inputs. drives HA[31:3]# during snoop cycles behalf AGP/Secondary initiators. HA[31:3]# transferred rate. Note that address inverted processor bus. NOTE: drives HA7# signal, which then sampled processor active-to-inactive transition CPURST#. minimum setup time this signal HCLKs. minimum hold time clocks maximum hold time HCLKs. Host Address Strobe: HADSTB[1:0]# source synchronous strobes used transfer HA[31:3]# HREQ[4:0]# transfer rate. Strobe Address Bits HADSTB0# A[16:3]#, REQ[4:0]# HADSTB1# A[31:17]# Host Data: These signals connected processor data bus. Data HD[63:0]# transferred rate. Note that data signals inverted processor bus, depending DINV[3:0] signals. Differential Host Data Strobes: These signals differential source synchronous strobes used transfer HD[63:0]# DINV[3:0]# transfer rate.
HA[31:3]#
AGTL+
HADSTB[1:0]#
AGTL+
HD[63:0]#
AGTL+
HDSTBP[3:0]# HDSTBN[3:0]#
AGTL+
Strobe
Data Bits
HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0#
HD[63:48]#, DINV3# HD[47:32]#, DINV2# HD[31:16]#, DINV1# HD[15:0]#, DINV0#
HIT#
AGTL+ AGTL+ AGTL+
Hit: This signal indicates that caching agent holds unmodified version requested line. HIT# also driven conjunction with HITM# target extend snoop window. Modified: This signal indicates that caching agent holds modified version requested line that this agent assumes responsibility providing line. HITM# also driven conjunction with HIT# extend snoop window. Host Lock: processor cycles sampled with assertion HLOCK# ADS#, until negation HLOCK# must atomic (i.e., AGP/PCI snoopable access system memory allowed when HLOCK# asserted processor). Host Request Command: These signals define attributes request. HREQ[4:0]# transferred rate. They asserted requesting agent during both halves Request Phase. first half signals define transaction type level detail that sufficient begin snoop request. second half signals carry additional information define complete transaction type.
HITM#
HLOCK#
HREQ[4:0]#
AGTL+
transactions supported Host Bridge defined Chapter
Intel® 82848P
Signal Description
Signal Name
Type
Description Host Target Ready: This signal indicates that target processor transaction able enter data transfer phase. Processor Hot: This signal informs chipset when processor Tj>thermal Monitor trip point. Response Signals: These signals indicate type response according following: Encoding Response Type
HTRDY# PROCHOT#
AGTL+ AGTL+
RS[2:0]#
AGTL+
Idle state Retry response Deferred response Reserved (not driven MCH) Hard Failure (not driven MCH) data response Implicit Writeback Normal data response
following list processor interface signals that supported MCH.
Signal Name Supported Function Supported Thus, Does Support
AP[1:0]# DP[3:0]# HA[35:32] RSP# IERR# BINIT# MCERR#
Address parity Data parity Upper address bits Response (RS) parity Processor Internal Error Initialization Signal Machine Check Error
Parity protection address Data parity errors host interface Only supports 4-GB system address space Response parity errors host interface Responding processor internal error Reset Host state machines. Signaling recognition Machine Check Error
Intel® 82848P
Signal Description
2.2.1
Memory Interface
DRAM Interface
Signal Name Type Description Differential Clock: SCMDCLK_Ax SCMDCLK_Ax# pairs differential clock outputs. crossing positive edge SCMDCLK_Ax negative edge SCMDCLK_Ax# used sample address control signals DRAM. There three pairs each DIMM. Complementary Differential Clock: These complementary Differential Clock signals. Chip Select: These signals select particular DRAM components during active state. There SCS_A# each DRAM row, toggled positive edge SCMDCLK_Ax. Memory Address: These signals used provide multiplexed column address DRAM. Memory Address Copies: SMAB_A[5:1] identical SMAA_A[5:1] used reduce loading Selective (clock-per-command). Bank Select (Bank Address): These signals define which banks selected within each DRAM row. Bank select memory address signals combine address every possible location within DRAM device. Address Strobe: SRAS_A# used with SCAS_A# SWE_A# (along with SCS_A#) define DRAM commands. Column Address Strobe: SCAS_A# used with SRAS_A# SWE_A# (along with SCS_A#) define DRAM commands. Write Enable: SWE_A# used with SCAS_A# SRAS_A# (along with SCS_A#) define DRAM commands. Data Lines: SDQ_A[63:0] interface DRAM data bus. Data Strobes: Data strobes used capturing data. During writes, SDQS_A[7:0] centered data. During reads, SDQS_A[7:0] edge aligned with data. following list matches data strobe with data bytes. Data Strobes Data Bytes
SCMDCLK_A[5:0]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
SCMDCLK_A[5:0]#
SCS_A[3:0]# SMAA_A[12:0] SMAB_A[5:1] TESTP[29:25]
SBA_A[1:0]
SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0]
SDQS_A[7:0]
SSTL_2
SDQS_A7 SDQS_A6 SDQS_A5 SDQS_A4 SDQS_A3 SDQS_A2 SDQS_A1 SDQS_A0
SDQ_A[63:56] SDQ_A[55:48] SDQ_A[47:40] SDQ_A[39:32] SDQ_A[31:24] SDQ_A[23:16] SDQ_A[15:8] SDQ_A[7:0]
SCKE_A[3:0]
SSTL_2
Clock Enable: SCKE_A[3:0] used initialize DRAM during power-up place DRAM rows into self-refresh during Suspend-to-RAM. SCKE_A[3:0] also used dynamically power down inactive DRAM rows. There SCKE_Ax DRAM row, toggled positive edge SCMDCLK_Ax.
Intel® 82848P
Signal Description
Interface
Signal Name Type Description Packet Data: HI[10:0] data signals used read write operations. Packet Strobe: HISTRS differential strobe signals used transmit receive packet data over Packet Strobe Complement: HISTRF differential strobe signals used transmit receive packet data over
HI[10:0] HISTRS HISTRF
HI15 HI15 HI15
Interface
Signal Name Type Description Packet Data: CI[10:0] data signals used read write operations. Packet Strobe: CISTRS differential strobe signals used transmit receive packet data over Packet Strobe Complement: CISTRF differential strobe signals used transmit receive packet data over
CI[10:0] CISTRS CISTRF
HI15 HI15 HI15
Intel® 82848P
Signal Description
2.5.1
Interface Signals
Addressing Signals
Signal Name Type Description Pipelined Read: This signal asserted current master indicate full width address queued target. master enqueues request each rising clock edge while GPIPE# asserted. When GPIPE# deasserted, requests enqueued across bus.
GPIPE# (2.0) DBI_HI (3.0)
GPIPE# used signaling modes, permitted specification. When operating signaling mode, GPIPE# signal used DBI_HI. GPIPE# sustained tri-state signal from master (graphics controller) input MCH. signaling mode this signal Dynamic Inversion Dynamic Inversion This signal goes along with GAD[31:16] indicate whether GAD[31:16] must inverted receiving end. DBI_HI GAD[31:16] inverted receiver DBI_HI GAD[31:16] inverted receiver must invert before use. GADSTBF1 GADSTBS1 strobes used with DBI_HI. data rate mode dynamic inversion disabled while transmitting (data never inverted DBI_HI driven low); dynamic inversion enabled when receiving data. data rate, dynamic inversion enabled when transmitting receiving data.
Sideband Address: This provides additional pass address command from master.
GSBA[7:0] (2.0) GSBA[7:0]# (3.0)
NOTE: signaling mode, when sideband addressing disabled, these signals isolated. When sideband addressing enabled, internal pull-ups enabled prevent indeterminate values them cases where Graphics Card have GSBA[7:0] output drivers enabled yet.
NOTES: previous table contains mechanisms queue requests master. Note that master only mechanism. When GPIPE# used queue addresses master allowed queue addresses using bus. example, during configuration time, master indicates that either mechanism, configuration software will indicate which mechanism master will use. Once this choice been made, master will continue mechanism selected until master reset (and reprogrammed) other mode. This change modes dynamic mechanism rather static decision when device first being configured after reset. term (2.0) following signal name indicates function signaling mode (1.5 swing). term (3.0) following signal name indicates function signaling mode (0.8 swing).
Intel® 82848P
Signal Description
2.5.2
Flow Control Signals
Signal Name Type Description Read Buffer Full: This signal indicates master ready accept previously requested priority read data. When GRBF(#) asserted, allowed return priority read data master first block. GRBF(#) only sampled beginning cycle. master always ready accept return read data, required implement this signal. Write Buffer Full: This signal indicates master ready accept fast write data from MCH. When GWBF(#) asserted, allowed drive fast write data master. GWBF(#) only sampled beginning cycle.
GRBF# (2.0) GRBF (3.0)
GWBF# (2.0) GWBF (3.0)
master always ready accept fast write data, required implement this signal.
NOTE: term (2.0) following signal name indicates function signaling mode (1.5 swing). term (3.0) following signal name indicates function signaling mode (0.8 swing).
2.5.3
Status Signals
Signal Name Type Description Status: These signals provide information from arbiter Master what GST[2:0] only have meaning master when GGNT(#) asserted. When GGNT(#) deasserted, these signals have meaning must ignored. GST[2:0] always output from input master. Encoding Meaning Previously requested priority read data (Async read signaling mode) being returned master. Previously requested high priority read data being returned master. Reserved signaling mode. master provide priority write data (Async write signaling mode) previously queued write command. master provide high priority write data previously queued write command. Reserved signaling mode. Reserved. Reserved. Reserved. master been given permission start transaction. master queue requests asserting GPIPE# signaling mode) start transaction asserting GFRAME(#).
GST[2:0] (2.0) GST[2:0] (3.0)
Intel® 82848P
Signal Description
2.5.4
Strobes
Signal Name Type Description Strobe-0: GADSTB0 provides timing clocked data GAD[15:0] GC/BE[1:0]# signaling mode. agent that providing data drives this signal. Strobe First-0: signaling mode GADSTBF0 strobes first numbered data items with low-to-high transition. used with GAD[15:0] GC#/BE[1:0]. Strobe-0 Complement: GADSTB0# differential complement GADSTB0 signal. used provide timing clocked data signaling mode. Strobe Second-0: signaling mode GADSTBS0 strobes second even numbered data items with low-to-high transition. Strobe-1: GADSTB1 provides timing clocked data GAD[31:16] GC/BE[3:2]# signaling mode. agent that providing data drives this signal. Strobe First-1: signaling mode GADSTBF1 strobes first numbered data items with low-to-high transition. used with GAD[31:16], GC#/BE[3:2], DBI_HI, DBI_LO. Strobe-1 Complement: GADSTB1 differential complement GADSTB1 signal. used provide timing clocked data signaling mode. STrobe Second-1: signaling mode GADSTBS1 strobes second even numbered data items with low-to-high transition. Sideband Strobe: GSBSTB provides timing clocked data GSBA[7:0] signaling mode. driven master after system been configured clocked sideband address delivery. Sideband Strobe First: signaling mode GSBSTBF strobes first numbered data items with low-to-high transition. Sideband Strobe Complement: GSBSTB# differential complement GSBSTB signal. used provide timing clocked data signaling mode. Sideband Strobe Second: signaling mode GSBSTBS strobes second even numbered data items with low-to-high transition.
GADSTB0 (2.0) GADSTBF0 (3.0)
(s/t/s)
GADSTB0# (2.0) GADSTBS0 (3.0)
(s/t/s)
GADSTB1 (2.0) GADSTBF1 (3.0)
(s/t/s)
GADSTB1# (2.0) GADSTBS1 (3.0)
(s/t/s)
GSBSTB (2.0) GSBSTBF (3.0)
GSBSTB# (2.0) GSBSTBS (3.0)
NOTE: term (2.0) following signal name indicates function signaling mode (1.5 swing). term (3.0) following signal name indicates function signaling mode (0.8 swing).
Intel® 82848P
Signal Description
2.5.5
Signals-AGP Semantics
signals redefined when used transactions carried using protocol extension. transactions interface carried using protocol, these signals completely preserve semantics. exact roles signals during transactions defined following table.
Signal Name Type Description GFRAME(#): This signal driven current master indicate beginning duration standard protocol ("frame based") transaction during fast writes. used, must inactive during transactions. GIRDY (#): This signal used both GFRAME(#) based transactions. During transactions, indicates compliant master ready provide write data current transaction. Once GIRDY(#) asserted write operation, master allowed insert wait states. assertion GIRDY(#) reads indicates that master ready transfer subsequent block clocks) read data. master never allowed insert wait state during initial data transfer (first clocks) read transaction. However, insert wait states after each clock block transferred. NOTE: There GFRAME(#) GIRDY(#) relationship transactions. GTRDY(#): This signal used both GFRAME(#) based transactions. During transactions, indicates compliant target ready provide read data entire transaction (when transfer size less than equal clocks) ready transfer initial subsequent block clocks) data when transfer size greater than clocks. target allowed insert wait states after each block clocks) transferred both read write transactions. GSTOP (#): This signal used during GFRAME(#) based transactions target request that master stop current transaction. used during transactions. Device Select: During GFRAME based accesses, GDEVSEL(#) driven active target indicate that responding access. used during transactions. Request: This signal output from device. Used request access initiate (GFRAME(#)) AGP(GPIPE(#)) request. required initiate request Grant: This signal output from either granting device initiate GFRAME(#) GPIPE(#) access response GREQ(#) active) indicate that data transferred previously enqueued transaction. GST[2:0] indicates purpose grant. Address/Data: These signals provide address GFRAME(#) GPIPE(#) transactions, data transactions. They operate data rate GFRAME(#) based cycles, operate specified channel rate (1X, data phases fast write data phases. Command/Byte Enables: These signals provide command during address phase GFRAME(#) GPIPE(#) transaction, byte enables during data phases. Byte enables used read data reads. These signals operate same data rate GAD[31:0] signals given time. Parity: GPAR used transactions used during GFRAME(#) based transactions defined specification. GPAR used during fast writes. This signal contains internal pull-up.
GFRAME# (2.0) GFRAME (3.0)
s/t/s
GIRDY# (2.0) GIRDY (3.0)
s/t/s
GTRDY# (2.0) GTRDY (3.0)
s/t/s
GSTOP# (2.0) GSTOP (3.0) GDEVSEL# (2.0) GDEVSEL (3.0) GREQ# (2.0) GREQ (3.0) GGNT# (2.0) GGNT (3.0)
s/t/s s/t/s
GAD[31:0]
GC/BE[3:0]# (2.0) GC#/BE[3:0] (3.0)
GPAR (2.0) GPAR (3.0)
Intel® 82848P
Signal Description
Signal Name
Type
Description Dynamic Inversion (AGP only) This that goes along with GAD[15:0] indicate whether GAD[15:0] must inverted receiving end.
DBI_LO (3.0 only)
DBI_LO= GAD[15:0] inverted receiver DBI_LO= GAD[15:0] inverted receiver must invert before use. GADSTBF1 GADSTBS1 strobes used with DBI_LO. Dynamic inversion used signaling mode only.
NOTES: Note that PCIRST# from ICH5 connected RSTIN# used reset interface logic within MCH. agent will also typically PCIRST# provided ICH5 input reset internal logic. LOCK# signal supported interface (even operations). (2.0) following signal name indicates function signaling mode (1.5 swing) (3.0) following signal name indicates function signaling mode (0.8 swing)
2.5.5.1
Pins during Transactions Interface
signals described previous table behave according specifications when used perform transactions interface.
Test Signals
Signal Name Type Description Test Point: This signal used testing should routed testing left connect. Test Point: TESTP[29:25] used testing multiplexed with system memory channel signals SMAB_A[5:1]. Intel® 848P Chipset Platform Design Guide details. Test Point: These signals used testing left connects. Test Point: TESTP[16:12] used testing should routed testing left connects Test Point: These signals used testing left connects. Test Point: This signal used testing should routed testing left connect.
TESTP[139:30] TESTP[29:25] SMAB_A[5:1] TESTP[24:17] TESTP[16:12] TESTP[11:4] TESTP[3:0]
Test Point SSTL_2 SSTL_2 SSTL_2 SSTL_2 GPIO
Intel® 82848P
Signal Description
Clocks, Reset, Miscellaneous
Signal Name Type Description Differential Host Clock These pins receive voltage differential host clock from external clock synthesizer. This clock used logic that host clock domain Clock In:. This receives clock from clock synthesizer. This clock used AGP/PCI clock domains. Note that this clock input required tolerant. Reset When asserted, this signal asynchronously resets logic. This signal connected PCIRST# output ICH5. AGP/PCI output bi-directional signals will also tri-state compliant Revision specifications. This input should have Schmitt trigger avoid spurious resets. Note that this input needs tolerant. Power When asserted, PWROK indication that core power GCLKIN have been stable least External Thermal Sensor Input: This open-drain signal indicating OverTemp condition platform. This signal should remains asserted long Over-temp Condition exists. This input programmed activate hardware management memory reads writes and/or trigger software interrupts.
HCLKP HCLKN
CMOS LVTTL (3.3 LVTTL (3.3 LVTTL (3.3 LVTTL (3.3
GCLKIN
RSTIN#
PWROK
EXTTS#
Intel® 82848P
Signal Description
RCOMP, VREF, VSWING
Signal Name Type Description Host Data Reference Voltage: This signal reference voltage input data signals Host AGTL+ interface. Host RCOMP: This signal used calibrate Host AGTL+ buffers. Host Voltage Swing: These signals provide reference voltage used RCOMP circuit. Memory Reference Voltage: This signal reference voltage input system memory interface. This signal tied internally SMVREF_B. Thus, only these signals needs SMVREF other should decoupled. Memory RCOMP: This signal used Calibrate VOL. Memory RCOMP: This signal used Calibrate VOH. Memory RCOMP: This signal used calibrate memory buffers. Memory Reference Voltage: This signal reference voltage input System Memory Interface. This signal tied internally SMVREF_A. Thus only these signals needs SMVREF other should decoupled. Memory RCOMP: This signal used Calibrate VOL. Memory RCOMP: This signal used Calibrate VOH. Memory RCOMP: This signal used calibrate memory buffers. Reference: reference voltage buffers 0.75 Voltage Swing: This signal provides reference voltage GRCOMP mode. Compensation AGP: This signal used calibrate buffers. This signal should connected ground through pull-up resistor VDDQ Reference: This signal reference voltage input interface. Compensation This signal used calibrate buffers. Voltage Swing: This signal provides reference voltage used HI_RCOMP circuit. Reference: This signal reference voltage input interface. Compensation CSA: This signal used calibrate buffers. Voltage Swing: This signal provides reference voltage used CI_RCOMP circuit.
HDVREF HDRCOMP HDSWING
CMOS
SMVREF_A
SMXRCOMPVOL SMXRCOMPVOH SMXRCOMP
CMOS
SMVREF_B
SMYRCOMPVOL SMYRCOMPVOH SMYRCOMP GVREF GVSWING
CMOS CMOS CMOS CMOS
GRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING
NOTE: Refer Intel® 848P Chipset Platform Design Guide platform design information.
Intel® 82848P
Signal Description
Power Ground Signals
Signal Name Description Supply: This core. Supply Power: This analog supply. AGP: This value either supports both electrical characteristics. Analog Host PLL: This supply requires special filtering. Refer Intel® 848P Chipset Platform Design Guide details. Supply: supply range V-1.55 Analog Display PLL: This supply requires special filtering. Refer Intel® 848P Chipset Platform Design Guide details. Supply: This supply required MCH. Analog VCC: This analog supply. Refer Intel® 848P Chipset Platform Design Guide supply requirements. Analog VSS: This supply should directly motherboard ground. System Memory: VCC_DDR DDR. Analog System Memory: This signal supply DDR. supply requires special filtering. Refer Intel® 848P Chipset Platform Design Guide details.
VCCA_AGP VCC_AGP VCCA_FSB VCCA_DPLL VCC_DAC VCCA_DAC VSSA_DAC VCC_DDR VCCA_DDR
2.10
Sequencing Requirements
Power Plane Sequencing Requirements:
Clock Valid Timing. GCLKIN must valid least prior rising edge PWROK. HCLKN/HCLKP must valid least prior rising edge RSTIN#.
Figure Intel® 848P Chipset System Clock Reset Requirements
POWER
~100
PWROK
RSTIN#
GCLKIN valid
HCLKN/HCLKP valid
Intel® 82848P
Signal Description
uses rising edge PWROK latch strap values. During when power valid, requires that PWROK de-assert then re-assert when power valid that properly re-latch straps.
2.11
2.11.1
Signals Used Straps
Functional Straps
Signal Name Strap Name Description
value HA7# sampled processor agents, including MCH, de-asserting edge CPURST#. Depth
NOTE: HA7#, minimum setup time HCLKs. minimum hold time clocks maximum hold time HCLKs.
HA7#
latched value determines maximum depth supported processor bus. (low voltage) depth (high voltage) depth maximum This strap selects operating mode signals (controls only multiplexers): (low voltage) (high voltage) strap flow-through while RSTIN# asserted latched deasserting edge RSTIN#. RSTIN# used make sure that card driving GPAR signal when latched.
GPAR
NOTE: straps, have internal pull-ups (HA7# pull-up) enabled during their sampling window. Therefore, strap that connected driven external logic will sampled high.
2.11.2
Strap Input Signals
Signal Name Type Description Core Frequency (FSBFREQ) Select Strap. This strap latched rising edge PWROK. These pins have default internal pull-up resistor Core frequency MHz, frequency Core frequency MHz, frequency Core frequency MHz, frequency
BSEL[1:0]
CMOS
Reserved
Intel® 82848P
Signal Description
2.11.3
Full Warm Reset States
Figure Full Warm Reset Waveforms
Intel® ICH5 Power
ICH5 PWROK ICH5 PCIRST# RSTIN# CPURST#
Write CF9h
Power
PWROK
Reset State
Unknown
Full Reset Warm Reset
Running
Warm Reset
Running
register bits assume their default values during full reset. PCIRST# resets internal flops state machines (except configuration register bits). full reset occurs when PCIRST# (MCH RSTIN#) asserted PWROK deasserted. warm reset occurs when PCIRST# (MCH RSTIN#) asserted PWROK also asserted. following table describes reset states.
Reset State RSTIN# PWROK
Full Reset Warm Reset Does Occur Normal Operation
Intel® 82848P
Signal Description
This page left intentionally blank
Intel® 82848P
Register Description
Register Description
contains sets software accessible registers, accessed host processor address space:
Control registers mapped into processor space that controls access
configuration space.
Internal configuration registers residing within partitioned into three logical
device register sets ("logical" since they reside within single physical device). first register dedicated host-hub interface functionality (controls i.e., DRAM configuration, other chipset operating parameters, optional features). second register dedicated host-AGP/PCI_B bridge functions (controls AGP/PCI_B interface configurations operating parameters). third register dedicated host-CSA control. This configuration scheme necessary accommodate existing future software configuration model supported Microsoft where host bridge functionality will supported controlled dedicated specific driver virtual PCI-to-PCI bridge functionality will supported standard enumeration configuration software. term "virtual" used designate that real physical embodiment PCI-to-PCI bridge functionality exists within MCH, that MCH's internal configuration register sets organized this particular manner create that impression standard configuration software. supports configuration space accesses using mechanism denoted Configuration Mechanism specification. internal registers (both Mapped configuration registers) accessible host processor. registers accessed Byte, Word (16-bit), DWord (32-bit) quantities, with exception CONFIG_ADDRESS which only accessed DWord. multi-byte numeric fields "little-endian" ordering (i.e., lower addresses contain least significant parts field).
Register Terminology
Term Description Read Only. register read only, writes this register have effect. Read/Write. register with this attribute read written. Read/Write/Lock. register with this attribute read, written, Locked. Read/Write Clear. register with this attribute read written. However, write clears (sets corresponding write effect. Read/Write Once. register with this attribute written only once after power After first write, becomes read only. Lock. register with this attribute becomes Read Only after lock set.
R/W/L R/WC R/WO
Reserved Bits
Some registers described this section contain reserved bits. These bits labeled "Reserved". Software must deal correctly with fields that reserved. reads, software must appropriate masks extract defined bits rely reserved bits being particular value. writes, software must ensure that values reserved positions preserved. That values reserved positions must first read, merged with values other positions then written back. Note that software does need perform read-merge-write operation Configuration Address (CONFIG_ADDRESS) register.
Intel® 82848P
Register Description
Term
Description
Reserved Registers
addition reserved bits within register, contains address locations configuration space Host-HI Bridge entity that marked either "Reserved" "Intel Reserved". responds accesses Reserved address locations completing host cycle. When Reserved register location read, zero value returned. (Reserved registers bits size). Writes Reserved registers have effect MCH. Caution: Registers that marked "Intel Reserved" must modified system software. Writes "Intel Reserved" registers cause system failure. Reads "Intel Reserved" registers return non-zero value. Upon reset, sets internal configuration registers predetermined default states. Some register values reset determined external strapping options. default state represents minimum functionality feature required successfully bring system. Hence, does represent optimal system configuration. responsibility system initialization software (usually BIOS) properly determine DRAM configurations, operating parameters optional system features that applicable, program registers accordingly.
Default Value upon Reset
Overview Platform Configuration Structure
some previous chipsets, "MCH" "I/O Controller (ICHx)" were physically connected From configuration standpoint, both components appeared which also system's primary expansion bus. contained devices while ICHx considered device with multiple functions. 848P chipset platform configuration structure significantly different. ICH5 physically connected interface, from configuration standpoint, interface logically result, devices internal ICHx appear system's primary expansion physically attached ICH5 and, from configuration perspective, appears hierarchical behind PCI-to-PCI bridge; therefore, programmable number. Note that primary referred PCI_A this document from configuration standpoint. appears system software real behind PCI-to-PCI bridges resident devices contains four devices within single physical component. configuration registers four devices mapped devices residing
Device Host-HI Bridge/DRAM Controller. Logically this appears device residing
Physically Device contains standard registers, DRAM registers, Graphics Aperture controller, configuration other specific registers.
Device Host-AGP Bridge. Logically this appears "virtual" PCI-to-PCI bridge residing
Physically Device contains standard PCI-to-PCI bridge registers standard AGP/PCI configuration registers (including memory address mapping).
Device Port. Appears virtual PCI-CSA (PCI-to-PCI) bridge device. Device Function Overflow Device. purpose this device provide additional
configuration register space Device
Intel® 82848P
Register Description
Table shows Device assignment various internal devices. Table Internal Device Assignment
Function Device
DRAM Controller/8-bit Controller Host-to-AGP Bridge (virtual PCI-to-PCI) Intergrated (CSA) Overflow
Device Device Device Device
Logically, ICH5 appears multiple devices within single physical component also residing ICH5 devices PCI-to-PCI bridge. Logically, primary side bridge resides while secondary side standard expansion bus. Note: physical does exist interface internal devices ICH5 logically constitute configuration software.
Figure Conceptual Intel® 848P Chipset Platform Configuration Diagram
Processor
Host-AGP Device Device
Configuration Window Space
DRAM Control/ Interface Device Interface
Interface
Intel® ICH5
Device
Interface Bridge PBus
Intel® 82848P
Register Description
Routing Configuration Accesses
supports interfaces: interface AGP/PCI. configuration cycles selectively routed these interfaces. responsible routing configuration cycles proper interface. configuration cycles ICH5 internal devices Primary (including downstream devices) routed ICH5 AGP/PCI_B configuration cycles routed AGP. AGP/PCI_B interface treated separate from configuration point view. Routing configuration AGP/PCI_B controlled standard PCI-to-PCI bridge mechanism using information contained within Primary Number, Secondary Number, Subordinate Number registers corresponding PCI-toPCI bridge device. detailed description mechanism translating processor cycles configuration cycles buses described below.
3.3.1
Standard Configuration Mechanism
defines slot based "configuration space" that allows each device contain eight functions with each function containing 256, 8-bit configuration registers. specification defines cycles access configuration space: Configuration Read Configuration Write. Memory spaces supported directly processor. Configuration space supported mapping mechanism implemented within MCH. specification defines configuration mechanism access configuration space. configuration access mechanism makes CONFIG_ADDRESS register address 0CF8h though 0CFBh) CONFIG_DATA register address 0CFCh though 0CFFh). reference configuration register DWord write cycle used place value into CONFIG_ADDRESS that specifies bus, device that bus, function within device, specific configuration register device function being accessed. CONFIG_ADDRESS[31] must enable configuration cycle. CONFIG_DATA then becomes window into four bytes configuration space specified contents CONFIG_ADDRESS. read write CONFIG_DATA will result translating CONFIG_ADDRESS into appropriate configuration cycle. responsible translating routing processor's accesses CONFIG_ADDRESS CONFIG_DATA registers internal configuration registers, AGP/PCI_B.
3.3.2
Configuration Mechanism
decodes Number (bits 23:16) Device Number fields CONFIG_ADDRESS register. Number field CONFIG_ADDRESS configuration cycle targeting device. Host-HI Bridge entity within hardwired Device Host-AGP/PCI_B Bridge entity within hardwired Device Device contains test configuration registers.
3.3.3
Primary Downstream Configuration Mechanism
Number CONFIG_ADDRESS non-zero, less than value HostAGP/PCI_B device's Secondary Number register greater than value Host-AGP/ PCI_B device's Subordinate Number register, will generate Type Configuration Cycle. A[1:0] request packet Type configuration cycle will
Intel® 82848P
Register Description
Bits 31:2 CONFIG_ADDRESS register will translated A[31:2] field request packet configuration cycle shown Figure This configuration cycle will sent over cycle forwarded ICH5 ICH5 compares non-zero Number with Secondary Number Subordinate Number registers PCI-to-PCI bridges determine configuration cycle meant Primary PCI, ICH5's HIs, downstream bus.
3.3.4
AGP/PCI_B Configuration Mechanism
From chipset configuration perspective, AGP/PCI_B seen interfaces residing Secondary side virtual PCI-to-PCI bridges referred Host-PCI_B/AGP bridge. primary side, virtual PCI-to-PCI bridge attached Therefore, Primary Number register hardwired virtual PCI-to-PCI bridge entity converts Type Configuration cycles into Type Type configuration cycles AGP/PCI_B interface. Type configuration cycles that have Number that matches Secondary Number MCH's "virtual" Host-to-PCI_B/AGP bridge will translated into Type configuration cycles PCI_B/AGP interface. will decode Device Number field [15:11] assert appropriate signal IDSEL accordance with PCI-to-PCI bridge Type configuration mechanism. remaining address bits will mapped described Figure
Figure Configuration Mechanism Type Configuration Address Address Mapping
CONFIG_ADDRESS
Reserved Number Register Number Device Number Function
IDSEL
Reserved
Register Number
Function
GAD[31:0] Address AGP/PCI1 Type Configuration Cycle
Table
Configuration Address Decoding
Config Address AD[15:11] GAD[31:16] IDSEL Config Address AD[15:11] GAD[31:16] IDSEL
00000 00001 00010 00011 00100 00101 00110 00111
0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000
01000 01001 01010 01011 01100 01101 01110 01111 1xxxx
0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000
Intel® 82848P
Register Description
Number non-zero, greater than value programmed into Secondary Number register, less than equal value programmed into Subordinate Number register, configuration cycle targeting downstream targeted interface. will generate Type configuration cycle PCI_B/AGP. address bits will mapped described Figure Figure Configuration Mechanism Type Configuration Address Address Mapping
CONFIG_ADDRESS Reserve Number Device Number
Function Number
Reg. Index
Address AD[31:0]
Number
Device Number
Function Number
Reg. Index
prepare mapping configuration cycles AGP/PCI_B, initialization software will through following sequence: Scan devices residing using Type configuration accesses. every device residing that implements PCI-PCI bridge functionality, will configure secondary bridge with appropriate number scan further down hierarchy. This process will include configuration virtual PCI-to-PCI bridges within used device's address spaces software specific manner. Note: Although initial platform implementations will support hierarchical buses residing below AGP, this specification still must define this capability support PCI-66 compatibility. Note also that future implementations devices support hierarchical AGP-like buses coming root device.
Mapped Registers
contains registers that reside processor address space: Configuration Address (CONFIG_ADDRESS) register Configuration Data (CONFIG_DATA) register. Configuration Address register enables/disables configuration space determines what portion configuration space visible through Configuration Data window.
Intel® 82848P
Register Description
3.4.1
CONFIG_ADDRESS-Configuration Address Register
Address: Default Value: Access: Size: 0CF8h Accessed DWord 00000000h bits
CONFIG_ADDRESS 32-bit register that accessed only DWord. Byte Word reference will "pass through" Configuration Address register onto PCI_A cycle. CONFIG_ADDRESS register contains Number, Device Number, Function Number, Register Number which subsequent configuration access intended.
Descriptions Configuration Enable (CFGE).
Enable Disable
30:24 23:16
Reserved.
Number. When Number programmed target configuration cycle agent (MCH, ICH5, etc.). configuration cycle forwarded Number programmed target (i.e., device number equal Number non-zero matches value programmed into Secondary Number register Device Type configuration cycle will generated AGP/PCI_B. Number non-zero, greater than value Secondary Number register Device less than equal value programmed into Subordinate Number register Device Type configuration cycle will generated AGP/PCI_B. Number non-zero, does fall within ranges enumerated Device Secondary Number Subordinate Number register, then Type configuration cycle generated. Device Number. This field selects agent selected Number. When Number field decodes Device Number field. always Device Number Host-HI bridge entity, Device Number Host-PCI_B/AGP entity. Therefore, when Number Device Number equals 0,1, internal devices selected. Number non-zero matches value programmed into Device1 Secondary Number register Type configuration cycle will generated AGP/PCI_B. Device Number field decoded asserts only GADxx signal IDSEL. GAD16 asserted access Device GAD17 Device forth Device which will assert AD31. device numbers higher than cause type configuration access with IDSEL asserted, which will result Master Abort reported MCH's virtual PCI-toPCI bridge registers. Numbers resulting configuration cycles, propagates Device Number field A[15:11]. Numbers resulting AGP/PCI_B Type configuration cycles, Device Number propagated GAD[15:11]. Function Number. This field mapped GAD[10:8] during AGP/PCI_B configuration cycles A[10:8] during configuration cycles. This allows configuration registers particular function multi-function device accessed. ignores configuration cycles internal devices function number equal Register Number. This field selects register within particular Bus, Device, Function specified other fields Configuration Address register. This field mapped GAD[7:2] during AGP/PCI_B configuration cycles A[7:2] during configuration cycles.
15:11
10:8
Reserved.
Intel® 82848P
Register Description
3.4.2
CONFIG_DATA-Configuration Data Register
Address: Default Value: Access: Size: 0CFCh 00000000h bits
CONFIG_DATA 32-bit window into configuration space. portion configuration space referenced CONFIG_DATA determined contents CONFIG_ADDRESS.
Descriptions Configuration Data Window (CDW). CONFIG_ADDRESS access that CONFIG_DATA register will mapped configuration space using contents CONFIG_ADDRESS.
31:0
Intel® 82848P
Register Description
DRAM Controller/Host-Hub Interface Device Registers (Device
DRAM Controller/Host-Hub Interface Device Register Address (Device (Sheet
Address Offset Register Symbol Register Name Default Value Access
Table
00-01h 02-03h 04-05h 06-07h 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 35-50h 54-5Fh 61-89h 98-9Ch
PCICMD PCISTS SUBC APBASE SVID CAPPTR AGPM CSABCONT FPLLCONT PAM0 PAM1 PAM2 PAM3 PAM4 PAM5 PAM6 FDHC
Vendor Identification Device Identification Command Status Revision Identification Intel Reserved Sub-Class Code Base Class Code Intel Reserved Master Latency Timer Header Type Intel Reserved Aperture Base Configuration Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved Miscellaneous Config Intel Reserved Basic Control Intel Reserved FPLL Clock Control Intel Reserved Programmable Attribute Programmable Attribute Programmable Attribute Programmable Attribute Programmable Attribute Programmable Attribute Programmable Attribute Fixed DRAM Hole Control Intel Reserved
8086h 2570h 0006h 0090h register description 00000008h 0000h 0000h
R/WC R/WO R/WO R/W,
Intel® 82848P
Register Description
Table
DRAM Controller/Host-Hub Interface Device Register Address (Device (Sheet
Address Offset Register Symbol Register Name Default Value Access
A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B5-B7h B8-BBh BE-C3h C4-C5h C6-C7h C8-C9h CA-CEh CF-DDh DE-DFh E0-E3h E4-E8h E9-FFh
SMRAM ESMRAMC ACAPID AGPSTAT AGPCMD AGPCTRL APSIZE ATTBASE AMTT LPTT TOUD MCHCFG ERRSTS ERRCMD SKPD CAPREG
System Management Control Extended System Management Control Intel Reserved Capability Identifier Status Command Intel Reserved Control Aperture Size Intel Reserved Aperture Translation Table Control Register Priority Transaction Timer Intel Reserved Used DRAM Configuration Error Status Register Error Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved
00300002h register description register description 0000 0000h 00000000h 0400h 0000h 0000h 0000h 0000h FF_F104_A009h
R/W, R/W, RWC, R/WO, R/WC
Intel® 82848P
Register Description
3.5.1
VID-Vendor Identification Register (Device
Address Offset: Default Value: Access: Size: 00-01h 8086h bits
register contains vendor identification number. This 16-bit register, combined with Device Identification register, uniquely identifies device.
Descriptions Vendor Identification (VID)-RO. This register field contains standard identification Intel, 8086h.
15:0
3.5.2
DID-Device Identification Register (Device
Address Offset: Default Value: Access: Size: 02-03h 2570h bits
This 16-bit register, combined with Vendor Identification register, uniquely identifies device.
Descriptions Device Identification Number (DID)-RO. This 16-bit value assigned Host-HI Bridge Function
15:0
Intel® 82848P
Register Description
3.5.3
PCICMD-PCI Command Register (Device
Address Offset: Default Value: Access: Size: 04-05h 0006h bits
Since Device does physically reside PCI_A, many bits implemented.
Descriptions
15:10
Reserved
Fast Back-to-Back Enable (FB2B)-RO. Hardwired This controls whether master fast back-to-back write. Since Device strictly target this implemented. SERR Enable (SERRE)-R/W. This global enable Device SERR messaging. does have SERR signal. communicates SERR condition sending SERR message over ICH5.
Disable. SERR message generated Device Note that this only controls SERR messaging Device Device SERRE bits control error reporting error conditions occurring their respective devices. control bits used logical manner enable SERR message mechanism. Enable. enabled generate SERR messages over specific Device error conditions that individually enabled ERRCMD register. error status reported ERRSTS PCISTS registers.
Address/Data Stepping Enable (ADSTEP)-RO. Hardwired Parity Error Enable (PERRE)-RO. Hardwired PERR# implemented MCH. Palette Snoop Enable (VGASNOOP)-RO. Hardwired Memory Write Invalidate Enable (MWIE)-RO. Hardwired will never issue memory write invalidate commands. Special Cycle Enable (SCE)-RO. Hardwired Master Enable (BME)-RO. Hardwired always enabled master Memory Access Enable (MAE)-RO. Hardwired always allows access main memory. Access Enable (IOAE)-RO. Hardwired
Intel® 82848P
Register Description
3.5.4
PCISTS-PCI Status Register (Device
Address Offset: Default Value: Access: Size: 06-07h 0090h R/WC bits
PCISTS 16-bit status register that reports occurrence error events Device interface. Since Device does physically reside PCI_A, many bits implemented.
Descriptions Detected Parity Error (DPE)-RO. Hardwired Signaled System Error (SSE)-R/WC. Software sets this writing Device generated SERR message over enabled Device error condition. Device error conditions enabled PCICMD ERRCMD registers. Device error flags read/reset from PCISTS ERRSTS registers. Received Master Abort Status (RMAS)-R/WC.
Software sets this writing this bit. generated request that receives Master Abort completion packet Master Abort Special Cycle.
Received Target Abort Status (RTAS)-R/WC. Software sets this writing this bit. generated request that receives Target Abort completion packet Target Abort Special Cycle. Signaled Target Abort Status (STAS)-RO. Hardwired will generate Target Abort completion packet Special Cycle. DEVSEL Timing (DEVT)-RO. Hardwired Device does physically connect PCI_A. These bits (fast decode) that optimum DEVSEL timing PCI_A limited MCH. Master Data Parity Error Detected (DPD)-RO. Hardwired PERR signaling messaging implemented MCH. Fast Back-to-Back (FB2B)-RO. Hardwired Device does physically connect PCI_A. This (indicating fast back-to-back capability) that optimum setting PCI_A limited MCH.
10:9
Reserved
Capability List (CLIST)-RO. Hardwired indicate configuration software that this device/function implements list capabilities. list capabilities accessed register CAPPTR configuration address offset 34h. Register CAPPTR contains offset pointing start address within configuration space this device where Capability standard register resides.
Reserved
Intel® 82848P
Register Description
3.5.5
RID-Revision Identification Register (Device
Address Offset: Default Value: Access: Size: following table bits
This register contains revision number Device
Descriptions Revision Identification Number (RID)-RO. This 8-bit value that indicates revision identification number Device Stepping
3.5.6
SUBC-Sub-Class Code Register (Device
Address Offset: Default Value: Access: Size: bits
This register contains Sub-Class Code Device
Descriptions Sub-Class Code (SUBC)-RO. This 8-bit value that indicates category bridge Device
Host Bridge.
3.5.7
BCC-Base Class Code Register (Device
Address Offset: Default Value: Access: Size: bits
This register contains Base Class Code Device
Descriptions Base Class Code (BASEC)-RO. This 8-bit value that indicates Base Class Code Device Bridge device.
Intel® 82848P
Register Description
3.5.8
MLT-Master Latency Timer Register (Device
Address Offset: Default Value: Access: Size: bits
Device master. Therefore, this register implemented.
Descriptions
Reserved
3.5.9
HDR-Header Type Register (Device
Address Offset: Default Value: Access: Size: bits
This register identifies header layout configuration space. physical register exists this location.
Descriptions Header (HDR)-RO. Hardwired indicating that single function device with standard header layout.
Intel® 82848P
Register Description
3.5.10
APBASE-Aperture Base Configuration Register (Device
Address Offset: Default Value: Access: Size: 10-13h 00000008h bits
APBASE standard Base Address register that used base graphics aperture. standard configuration mechanism defines base address configuration register such that only fixed amount space requested (dependent which bits hardwired behave hardwired allow flexibility aperture), additional register called APSIZE used "back-end" register control which bits APBASE will behave hardwired This register will programmed specific BIOS code that will before generic configuration software run. Note: AGPM register (offset used prevent accesses aperture range before this register initialized configuration software appropriate translation table structure been established system memory.
Descriptions Upper Programmable Base Address (UPBITS)-R/W. These bits part aperture base configuration software locate base address graphics aperture. They correspond bits [31:28] base address processor's address space that will cause graphics aperture translation inserted into path memory read write. Middle Hardwired/Programmable Base Address (MIDBITS)-R/W. These bits part aperture base configuration software locate base address graphics aperture. They correspond bits [27:4] base address processor's address space that will cause graphics aperture translation inserted into path memory read write. These bits behave though they were hardwired programmed APSIZE bits APSIZE register. This will cause configuration software understand that granularity graphics aperture base address either finer more coarse, depending upon bits MCH-specific configuration software APSIZE. Lower Bits (LOWBITS)-RO. Hardwired 0's. This forces minimum aperture size selectable this register without regard aperture size definition enforced APSIZE register. Prefetchable (PF)-RO. Hardwired identifying graphics aperture range prefetchable specification base address registers. This implies that there side effects reads, device returns bytes reads regardless byte enables, merge processor writes into this range without causing errors. Addressing Type (TYPE)-RO. Hardwired indicating that address range defined upper bits this register located anywhere 32-bit address space specification base address registers. Memory Space Indicator (MSPACE)-RO. Hardwired identifying aperture range memory range specification base address registers.
31:28
27:22
21:4
Intel® 82848P
Register Description
3.5.11
SVID-Subsystem Vendor Identification Register (Device
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h R/WO bits
This value used identify vendor subsystem.
Descriptions Subsystem Vendor (SUBVID)-R/WO. This field should programmed during boot-up indicate vendor system board. After been written once, becomes read only.
15:0
3.5.12
SID-Subsystem Identification Register (Device
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h R/WO bits
This value used identify particular subsystem.
Descriptions Subsystem (SUBID)-R/WO. This field should programmed during BIOS initialization. After been written once, becomes read only.
15:0
3.5.13
CAPPTR-Capabilities Pointer Register (Device
Address Offset: Default Value: Access: Size: bits
CAPPTR provides offset that pointer location first device capability capability list.
Descriptions Capabilities Pointer Address- This field contains pointer offset first capability register block. this case first capability Product-Specific Capability, which located offset E4h.
Intel® 82848P
Register Description
3.5.14
AGPM-AGP Miscellaneous Configuration Register (Device
Address Offset: Default Value: Access: Size:
bits
Descriptions
Reserved
Aperture Access Global Enable (APEN)-R/W. This used prevent access graphics aperture from port (processor, AGP/PCI_B) before aperture range established configuration software appropriate translation table system memory been initialized. Disable.The default value this field must after system fully configured enable aperture accesses. Enable.
Reserved
3.5.15
CSABCONT-CSA Basic Control Register (Device
Address Offset: Default: Access: Size:
R/W, bits
Description
Reserved
Device Present bit-R/W
Device Enabled Device Enabled
Intel® 82848P
Register Description
3.5.16
FPLLCONT-Front Side Clock Control Register (Device
Address Offset: Default Value: Access: Size: R/W, bits
These register bits used changing frequency initializing memory clocks' delays.
Descriptions
Reserved
Memory Memory Clock Gate (DLLCKGATE)-R/W.
Writing this register will cleanly re-enable memory memory clocks from outputs (Default) Writing this register will cleanly disable memory memory clocks chipset core interface from outputs
NOTE: This should always written before writing FPLLSYNC
Reserved
Intel® 82848P
Register Description
3.5.17
PAM[0:6]-Programmable Attribute Registers
Address Offset: Default Value: Attribute: Size: 90-96h (PAM0-PAM6) R/W, bits
allows programmable memory attributes legacy memory segments various sizes 640-KB 1-MB address range. Seven Programmable Attribute (PAM) registers used support these features. Cacheability these areas controlled MTRR registers processor. bits used specify memory attributes each memory segment. These bits apply host-initiator only access areas. will forward system memory AGP, PCI, initiated accesses areas. These attributes are: Read Enable. When host read accesses corresponding memory segment claimed directed main memory. Conversely, when host read accesses directed PCI_A. Write Enable. When host write accesses corresponding memory segment claimed directed main memory. Conversely, when host write accesses directed PCI_A.
attributes permit memory segment Read Only, Write Only, Read/Write, disabled. example, memory segment segment Read Only. Each register controls regions, typically size. Each these regions 4-bit field. four bits that control each region have same encoding defined following table.
Bits Reserved Bits Reserved Bits Bits Description
Disabled DRAM disabled accesses directed interface. does respond target read write access this area. Read Only. Reads forwarded DRAM writes forwarded interface termination. This write protects corresponding memory segment. will respond interface target read accesses write accesses. Write Only. Writes forwarded DRAM reads forwarded interface termination. will respond interface target write accesses read accesses. Read/Write. This normal operating mode main memory. Both read write cycles from host claimed forwarded DRAM. will respond interface target both read write accesses.
time that accesses region occur, targeted segment must programmed both readable writable. example, consider BIOS that implemented expansion bus. During initialization process, BIOS shadowed main memory increase system performance. When BIOS shadowed system memory, should copied same address location. shadow
Intel® 82848P
Register Description
BIOS, attributes that address range should write only. BIOS shadowed first doing read that address. This read forwarded expansion bus. host then does write same address, which directed system memory. After BIOS shadowed, attributes that memory area read only that writes forwarded expansion bus. Figure Table show registers associated attribute bits. Figure Register Attributes
Offset PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved
Table
Register Attributes
Attribute Bits Memory Segment Comments Offset
PAM0[3:0] PAM0[7:6] PAM0[5:4] PAM1[1:0] PAM1[7:4] PAM2[1:0] PAM2[7:4] PAM3[1:0] PAM3[7:4] PAM4[1:0] PAM4[7:4] PAM5[1:0] PAM5[7:4] PAM6[1:0] PAM6[7:4]
Reserved Reserved 0F0000h-0FFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh BIOS Area Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension
details overall system address mapping scheme, Chapter
Intel® 82848P
Register Description
Application Area (00000h-9FFFh) area size, further divided into parts. 512-KB area 7FFFFh always mapped system memory controlled MCH, while 128-KB address range from 080000 09FFFFh mapped PCI_A system memory. default this range mapped system memory declared system memory hole (accesses forwarded PCI_A) FDHC configuration register. Video Buffer Area (A0000h-BFFFFh) Attribute bits control this 128-KB area. host-initiated cycles this region always forwarded either PCI_A unless this range accessed mode. Routing accesses controlled Legacy control mechanism virtual PCI-to-PCI bridge device embedded within MCH. This area programmed area SMRAM register. When used space, this range cannot accessed from AGP. Expansion Area (C0000h-DFFFFh) This 128-KB area divided into eight, 16-KB segments, that assigned with different attributes control register defined Table Extended System BIOS Area (E0000h-EFFFFh) This 64-KB area divided into four, 16-KB segments, which assigned with different attributes control register defined Table System BIOS Area (F0000h-FFFFFh) This area single, 64-KB segment, which assigned with different attributes control register defined Table
3.5.18
FDHC-Fixed Memory (ISA) Hole Control Register (Device
Address Offset: Default Value: Access: Size: R/W, bits
This 8-bit register controls fixed DRAM hole from 15-16
Descriptions Hole Enable (HEN)-R/W. This field enables memory hole system memory space. DRAM that lies "behind" this space remapped.
memory hole. =Memory hole from Reserved
Intel® 82848P
Register Description
3.5.19
SMRAM-System Management Control Register (Device
Address Offset: Default Value: Access: Size: R/W, Lock bits
SMRAMC register controls accesses Compatible Extended SMRAM spaces treated. open, close, lock bits function only when G_SMRAME Also, open must reset before lock set.
Descriptions
Reserved
Space Open (D_OPEN)-R/W. When D_OPEN=1 D_LCK=0, space DRAM made visible even when decode active. This intended help BIOS initialize space. Software should ensure that D_OPEN=1 D_CLS=1 same time. Space Closed (D_CLS)-R/W. When D_CLS space DRAM accessible data references, even decode active. Code references still access space DRAM. This will allow software reference through space update display even when mapped over range. Software should ensure that D_OPEN=1 D_CLS=1 same time. Note that D_CLS only applies Compatible space. Space Locked (D_LCK)-R/W. When D_LCK D_OPEN reset D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ TSEG_EN become read only. D_LCK normal configuration space write only cleared Full Reset. combination D_LCK D_OPEN provide convenience with security. BIOS D_OPEN function initialize space then D_LCK "lock down" space future that application software BIOS itself) violate integrity space, even program knowledge D_OPEN function. Global SMRAM Enable (G_SMRARE)-R/W/L. Compatible SMRAM functions enabled, providing DRAM accessible A0000h address while (ADS# with decode). enable Extended SMRAM function this Refer section more details. Once D_LCK set, this becomes read only. Compatible Space Base Segment (C_BASE_SEG)-RO. This field indicates location space. DRAM remapped. simply made visible conditions right access space, otherwise access forwarded Since supports only space between A0000h BFFFFh, this field hardwired 010.
Intel® 82848P
Register Description
3.5.20
ESMRAMC-Extended System Management Control (Device
Address Offset: Default Value: Access: Size: R/W, R/WC, Lock bits
Extended SMRAM register controls configuration Extended SMRAM space. Extended SMRAM (E_SMRAM) memory provides write-back cacheable SMRAM memory space that above
Descriptions Enable High SMRAM (H_SMRAME)-R/W/L. This controls memory space location (i.e., above below MB). When G_SMRAME H_SMRAME (this bit) high SMRAM memory space enabled. SMRAM accesses within range 0FEDA0000h 0FEDBFFFFh remapped DRAM addresses within range 000A0000h 000BFFFFh. Once D_LCK been set, this becomes read only. Invalid SMRAM Access (E_SMERR)-R/WC. This when processor accessed defined memory ranges Extended SMRAM (High Memory T-segment) while space with D-OPEN software's responsibility clear this bit. NOTE: Software must write this clear
SMRAM Cacheable (SM_CACHE)-RO. Hardwired Cache Enable SMRAM (SM_L1)-RO. Hardwired Cache Enable SMRAM (SM_L2)-RO. Hardwired TSEG Size (TSEG_SZ)-R/W. This field selects size TSEG memory block enabled. Memory from used system memory space (TOUD) TOUD Tseg_size partitioned away that only accessed processor interface only then when request packet. Non-SMM accesses this memory region sent interface when TSEG memory block enabled. Reserved Reserved TOUD TOUD TSEG Enable (T_EN)-R/W/L. Enabling SMRAM memory Extended SMRAM space only. When G_SMRAME TSEG_EN TSEG enabled appear appropriate physical address space. Note that once D_LCK set, this becomes read only.
Intel® 82848P
Register Description
3.5.21
ACAPID-AGP Capability Identifier Register (Device
Address Offset: Default Value: Access: Size: A0h-A3h 00300002h bits
This register provides standard identifier capability.
Descriptions
31:24 23:20
Reserved
Major Revision Number (MAJREV)-RO. These bits provide major revision number specification which this version conforms. This field hardwired value 0011b (i.e., implying 3.x). Minor Revision Number (MINREV)-RO. These bits provide minor revision number specification which this version conforms. This number hardwired value 0000 which implies that revision x.0. Together with major revision number this field identifies compliant device. Next Capability Pointer (NCAPTR)-RO. capability first last capability described capability pointer mechanism therefore these bits hardwired indicate capability linked list. Capability (CAPID)-RO. This field identifies linked list item containing registers. This field value 0000_0010b assigned SIG.
19:16
15:8
3.5.22
AGPSTAT-AGP Status Register (Device
Address Offset: Default Value: Access: Size: A4-A7h 1F004217h 1F004A13h mode bits
This register reports device capability/status.
Descriptions Request Queue (RQ)-RO. Hardwired indicate maximum outstanding command requests handled MCH. This field contains maximum number command requests configured manage.
31:24 23:16
Reserved
ARQSZ-RO. LOG2 optimum asynchronous request size bytes minus used with target. MASTER should attempt issue group sequential back-to-back asynchronous requests that total this size which group naturally aligned.
15:13
Optimum_request_size (ARQSZ+4). Hardwired indicate 12:10
CAL_Cycle-RO. This field specifies required period MCH-initiated cycles calibrating buffers.
Hardwired indicate
SideBand Addressing Support (SBA)-RO. Hardwired indicating that supports sideband addressing.
Reserved
Intel® 82848P
Register Description
Descriptions Greater Than Four Gigabyte Support (GT4GIG)-RO. Hardwired indicating that does support addresses greater than Fast Write Support (FW)-RO. Hardwired indicating that supports fast writes from processor master. mode (AGP 30_MOD-RO. This hardware assertion PWROK based detection VREF comparator GVREF pin. mode, GVREF driven 0.75 while mode, GVREF driven 0.35 Note that output Vref comparator used "live" prior assertion PWROK used select appropriate pull-up, pull-down termination buffer depending mode selected.
(1.5 signaling) mode. signaling mode.
Data Rate Support (RATE)-RO. After reset, reports data transfer rate capability. Mode:
identifies device supports data transfer mode, identifies device supports data transfer mode, (unsupported) identifies device supports data transfer. Mode: identifies device supports data transfer mode, identifies device supports data transfer mode, reserved.
NOTES: mode (AGP_MODE=1) these bits indicating that both modes supported. mode these bits indicating that modes supported. supported)
Intel® 82848P
Register Description
3.5.23
AGPCMD-AGP Command Register (Device
Address Offset: Default Value: Access: Size: A8-ABh 00000000h mode 00000A00h mode bits
This register provides control operational parameters.
Descriptions
31:13
Reserved
PCAL_Cycle-R/W. This field programmed with period MCH-initiated cycles calibrating buffers both master target. This value updated with smaller value CAL_CYCLE from Master's Target's AGPSTAT.CAL_CYCLE. PCAL_CYCLE software only both Target Master have AGPSTAT.CAL_CYCLE 111. (default) 100-110 Reserved Calibration Cycle Needed Side Band AddressingEnable (SBAEN)-R/W. This ignored mode allow legacy software work. (When detected, sideband addressing mechanism automatically enabled hardware.)
12:10
Disable. Enable. Side band addressing mechanism enabled.
Enable (AGPEN)-R/W.
Disable. ignores operations, including sync cycle. operations received while this will serviced, even this reset this transitions from clock edge middle command being delivered mode, command will issued. Enable. responds operations delivered PIPE#, operations delivered Side Band Enable also Reserved
Greater Than Four Gigabyte Enable (GT4GIGE)-RO. Hardwired MCH, target, does support addressing greater than Fast Write Enable (FWEN)-R/W.
Disable. When this cleared, when data rate bits mode, memory write transactions from master standard protocol. Enable. When this set, will fast write protocol memory write transactions from master. Fast writes will occur data transfer rate selected data rate bits (2:0) this register. Reserved
Intel® 82848P
Register Description
Descriptions Data Rate Enable (DRATE)-R/W. setting these bits determines data transfer rate. (and only one) this field must indicate desired data transfer rate. same must both master target.
001= Transfer Mode (for signaling) 010= Transfer Mode (NOT SUPPORTED) 100= Transfer Mode (for signaling) 001= transfer mode (for signaling) 010= Transfer mode (for signaling) 100= reserved
3.5.24
AGPCTRL-AGP Control Register (Device
Address Offset: Default Value: Access: Size: B0-B3h 00000000h bits
This register provides additional control interface.
Descriptions
31:8
Reserved
GTLB Enable (GTLBEN)- R/W.
Disable (default). GTLB flushed clearing valid bits associated with each entry. this mode operation: accesses that require translation bypass GTLB requests that positively decoded graphics aperture force access translation table main memory before completing request Valid translation table entry fetches will cached GTLB Invalid translation table entry fetches will still cached GTLB (ejecting least recently used entry). Enable. Normal operations Graphics Translation Lookaside Buffer.
NOTE: This changed dynamically (i.e., while access GTLB occurs); however, completion configuration write that asserts deasserts this will delayed pending complete flush dirty entries from write buffer. This delay will incurred because this used mechanism signal chipset that graphics aperture translation table about modified completed modifications. first case, dirty entries need flushed before translation table changed. second case, dirty entries need flushed because them likely translation table entry which must made visible GTLB flushing memory.
Reserved
Override (OVER4X)-R/W. This back-door register allows BIOS force mode mode 3.0. Note that this must BIOS before configuration. override RATE[2:0] AGPSTS register will read 001.
Intel® 82848P
Register Description
3.5.25
APSIZE-Aperture Size Register (Device
Address Offset: Default Value: Access: Size: bits
This register determines effective size graphics aperture used particular configuration. This register updated MCH-specific BIOS configuration sequence before standard enumeration sequence takes place. register updated then default value will select aperture maximum size (i.e., MB). size table that will correspond 256-MB aperture practical most applications therefore these bits must programmed smaller practical value that will force adequate address range requested APBASE register from configuration software.
Descriptions
Reserved
Graphics Aperture Size (APSIZE)-R/W. Each APSIZE[5:0] operates similarly ordered bits APBASE[27:22] Aperture Base configuration register. When particular this field forces similarly ordered APBASE[27:22] behave hardwired When particular this field allows corresponding APBASE[27:22] read/ write accessible. Default default value (APSIZE[5:0]=000000b) forces default APBASE[27:22] read 000000b (i.e., bits respond hardwired This provides maximum aperture size another example, programming APSIZE[5:0] 111000b hardwires APBASE[24:22] 000b enables APBASE[27:25] read/write programmable.
000000 256-MB Aperture Size 100000 128-MB Aperture Size 110000 64-MB Aperture Size 111000 32-MB Aperture Size 111100 16-MB Aperture Size 111110 8-MB Aperture Size 111111 4-MB Aperture Size
Intel® 82848P
Register Description
3.5.26
ATTBASE-Aperture Translation Table Register (Device
Address Offset: Default Value: Access: Size: B8-BBh 00000000h bits
This register provides starting address Graphics Aperture Translation Table Base located main DRAM. This value used MCH's Graphics Aperture address translation logic (including GTLB logic) obtain appropriate address translation entry required during translation aperture address into corresponding physical DRAM address. ATTBASE register dynamically changed.
Descriptions Aperture Translation Table Base (TTABLE)-R/W. This field contains pointer base translation table used memory space addresses aperture range addresses main memory. Note that should modified only when GTLB been disabled.
31:12 11:0
Reserved
3.5.27
AMTT-AGP Control Register (Device
Address Offset: Default Value: Access: Size: bits
AMTT 8-bit register that controls amount time that MCH's arbiter allows AGP/PCI master perform multiple back-to-back transactions. MCH's AMTT mechanism used optimize performance master (using semantics) that performs multiple backto-back transactions fragmented memory ranges (and consequence long burst transfers). AMTT mechanism applies processor-AGP/PCI transactions well assures processor fair share AGP/PCI interface bandwidth. number clocks programmed AMTT represents guaranteed time slice (measured clocks) allotted current agent (either AGP/PCI master Host bridge) after which arbiter will grant another agent. default value AMTT disables this function. AMTT value programmed with 8-clock granularity. example, AMTT programmed 18h, then selected value corresponds time period MHz) clocks. BIOS.
Descriptions Multi-Transaction Timer Count Value (MTTC)-R/W. number programmed into these bits represents time slice (measured eight, clock granularity) allotted current agent (either AGP/PCI master Host bridge) after which arbiter will grant another agent.
Reserved
Intel® 82848P
Register Description
3.5.28
LPTT-AGP Priority Transaction Timer Register (Device
Address Offset: Default Value: Access: Size: bits
LPTT 8-bit register similar function AMTT. This register used control minimum tenure priority data transaction (both reads writes) issued using PIPE# mechanisms. number clocks programmed LPTT represents guaranteed time slice (measured clocks) allotted current priority transaction data transfer state. This does necessarily apply single transaction span over multiple low-priority transactions same type. After this time expires arbiter grant another agent there pending request. LPTT does apply case high-priority request where ownership transferred directly high-priority requesting queue. default value LPTT disables this function. LPTT value programmed with 8-clock granularity. example, LPTT programmed 10h, then selected value corresponds time period MHz) clocks.
Descriptions Priority Transaction Timer Count Value (LPTTC)-R/W. number clocks programmed these bits represents time slice (measured eight clock granularity) allotted current priority transaction data transfer state.
Reserved
3.5.29
TOUD-Top Used DRAM Register (Device
Address Offset: Default Value: Access: Size:
C4-C5h 0400h bits
Descriptions
15:3
Usable Dram (TOUD)-R/W. This register contains bits 31:19 maximum system memory address that usable operating system. Address bits 31:19 imply memory granularity Configuration software should this value either maximum amount usable memory (minus TSEG, graphics stolen memory stolen memory) system minimum address allocated memory graphics aperture, (minus TSEG, graphics stolen memory) whichever smaller. Address bits 18:0 assumed 0000h purposes address comparison. This register must least 0400h, minimum system memory. calculate value TOUD, configuration software should this value smaller following cases: maximum amount usable memory system minus optional TSEG. address allocated memory graphics aperture minus optional TSEG. NOTE: Even does need space, TOUD should never programmed above FEC0_0000h. TOUD programmed above this, address ranges that reserved will become accessible applications.
Reserved
Intel® 82848P
Register Description
3.5.30
MCHCFG-MCH Configuration Register (Device
Address Offset: Default Value: Access: Size:
C6-C7h 0000h R/W, bits
Descriptions
15:13
Number Stop Grant Cycles (NSG)-R/W. This field represents number Stop Grant transactions expected before Stop Grant Acknowledge packet sent ICH5. This field programmed BIOS after enumerated processors before enabled Stop Clock generation ICH5. Once this field been set, should modified. Note that each enabled thread within each processor will generate Stop Grant Acknowledge transactions.
Stop Grant sent after Stop Grant Stop Grant sent after Stop Grants 010-111= Reserved Reserved
System Memory Frequency Select (SMFREQ)-R/W. reset value these bits memory frequency determined following table, partly determined frequency. FSBFREQ[1:0] SMFREQ[11:10]=01 System Memory FSBFREQ[1:0] SMFREQ[11:10]=00 System Memory FSBFREQ[1:0] SMFREQ[11:10]=01 System Memory FSBFREQ[1:0] SMFREQ[11:10]=01 System Memory (320) FSBFREQ[1:0] SMFREQ[11:10]=10 System Memory others Intel Reserved Note that memory clock always runs frequency memory clock. NOTE: When writing value this register, software must perform clock synchronization sequence apply timings. value does applied until this completed.
11:10
Reserved
Present (MDAP)-R/W. This works with Enable bits BCTRL1 register Device control routing processor-initiated transactions targeting compatible memory address ranges. This should Device Enable set. Device enable set, then accesses address range x3BCh-x3BFh forwarded enable set, accesses address range x3BCh-x3BFh treated just like other accesses. That cycles forwarded address within corresponding IOBASE IOLIMIT enable set; otherwise, they forwarded resources defined following: Memory: 0B0000h-0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including address aliases, A[15:10] used decode) reference that includes locations listed above, their aliases, will forwarded interface, even reference includes locations listed above. following table shows behavior combinations VGA: Behavior References Illegal Combination USE). References Device MDA-only references (I/O address 3BFh aliases) will References AGP/PCI; References
Intel® 82848P
Register Description
Descriptions
Reserved
Mode (AGP)-RO. This reflects GPAR strap value. Note that strap value sampled assertion PWROK.
Reserved
Depth (IOQD)-RO. This reflects HA7# strap value. indicates depth IOQ. When strap sampled low, this will depth When strap sampled high, this will depth maximum bus, MCH). deep bus, Frequency Select (FSBFREQ)-RO. default value this strap assigned BSEL[1:0] pins latched rising edge PWROK. Core Frequency frequency Core Frequency frequency Core Frequency frequency Reserved
Intel® 82848P
Register Description
3.5.31
ERRSTS-Error Status Register (Device
Address Offset: Default Value: Access: Size: C8-C9h 0000h R/WC bits
This register used report various error conditions SERR messaging mechanism. SERR message generated 0-to-1 transition these flags enabled ERRCMD PCICMD registers). These bits regardless whether SERR enabled generated. Note: Software must write clear bits that set.
Descriptions
15:10
Reserved
Non-DRAM Lock Error (NDLOCK)-R/WC.
Lock operation detected. detected lock operation memory space that into DRAM.
Software Generated Flag-R/WC.
Source Device Software Trigger Source Device Software Trigger. Reserved
Detects Unimplemented Special Cycle (HIAUSC)-R/WC
unimplemented Special Cycle detected. detects Unimplemented Special Cycle
Access Outside Graphics Aperture Flag (OOGF)-R/WC
access address that outside graphics aperture range. access occurred address that outside graphics aperture range.
Invalid Access Flag (IAAF)-R/WC
invalid access. access attempted outside graphics aperture either range above memory.
Invalid Graphics Aperture Translation Table Entry (ITTEF)-R/WC
invalid graphics aperture translation table entry. Invalid translation table entry returned response access graphics aperture.
Detects Unsupported Command-R/WC. unsupported command detected. Bogus unsupported command received target MCH.
Reserved
Intel® 82848P
Register Description
3.5.32
ERRCMD-Error Command Register (Device
Address Offset: Default Value: Access: Size: CA-CBh 0000h bits
This register controls responses various system errors. Since does have SERR# signal, SERR messages passed from ICH5 over When this register set, SERR message will generated when corresponding flag ERRSTS register. actual generation SERR message globally enabled Device Command register.
Descriptions
15:10
Reserved
SERR Non-DRAM Lock (LCKERR)-R/W.
Disable Enable. generates SERR special cycle when processor lock cycle detected that does system memory. Reserved
SERR Target Abort Exception (TAHLA)-R/W.
Reporting this condition disabled. generates SERR special cycle over when originated cycle completed with Target Abort completion packet special cycle.
SERR Detecting Unimplemented Special Cycle (HIAUSCERR)-R/W.
does generate SERR message this event. SERR messaging Device globally enabled PCICMD register. generates SERR message over when Unimplemented Special Cycle received
SERR Access Outside Graphics Aperture (OOGF)-R/W.
Reporting this condition disabled. Enable. generates SERR special cycle over when access occurs address outside graphics aperture.
SERR Invalid Access (IAAF)-R/W.
Invalid Access condition reported. generates SERR special cycle over when access occurs address outside graphics aperture either range above memory.
SERR Invalid Translation Table Entry (ITTEF)-R/W.
Reporting this condition disabled. generates SERR special cycle over when invalid translation table entry returned response access graphics aperture.
SERR Detects Unsupported Command-R/W.
Detects Unsupported command will generate SERR. generates SERR when Unsupported command detected. Reserved
Intel® 82848P
R
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