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Intel® 865PE / 865P Chipset

Intel® 82865PE / 82865P Memory Controller Hub (MCH)

Intel® 865PE / 865P Chipset
Datasheet
Intel® 82865PE / 82865P Memory Controller Hub (MCH)
February 2004
Document Number: 252523-004
Intel® 82865PE / 82865P MCH Datasheet
Contents
1 Introduction ......................................................13
Signal Description ...............................................23
Register Description .............................................41
Intel® 82865PE / 82865P MCH Datasheet
System Address Map ........................................... 115
Functional Description .......................................... 123
Intel® 82865PE / 82865P MCH Datasheet
5.5.1 External Thermal Sensor Interface Overview .................137 5.5.2 External Thermal Sensor Usage Model .....................138 Clocking ....................................................139 Absolute Maximum Ratings .....................................141 Thermal Characteristics ........................................141 Power Characteristics .........................................142 Signal Groups ...............................................143 DC Parameters ..............................................145 MCH Ballout.................................................151 MCH Package Information......................................162 XOR Test Mode Initialization ....................................165 XOR Chain Definition..........................................167
Electrical Characteristics .......................................141
Ballout and Package Information ................................151
Testability.......................................................165
Intel® 82865PE / 82865P MCH Datasheet
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Intel® 865PE Chipset System Block Diagram........................ 17 Intel® 865P Chipset System Block Diagram ......................... 18 Intel® 82865PE / 82865P MCH Interface Block Diagram ................ 24 Intel® 865PE / 865P Chipset System Clock and Reset Requirements...... 38 Full and Warm Reset Waveforms ................................. 40 Conceptual Intel® 875PE / P Chipset Platform PCI Configuration Diagram .. 43 Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping ..................................................... 45 Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping ..................................................... 46 PAM Register Attributes ........................................ 60 Memory System Address Map................................... 116 Detailed Memory System Address Map ........................... 116 Single-Channel Mode Operation ................................. 125 Dual-Channel Mode Operation .................................. 125 Platform External Sensor....................................... 138 Intel® 865PE / 865PChipset System Clocking Block Diagram ........... 139 Intel® 82865PE / 82865P MCH Ballout Diagram (Top View-Left Side).... 152 Intel® 82865PE / 82865P MCH Ballout Diagram (Top View-Right Side) .. 153 Intel® 82865PE / 82865P MCH Package Dimensions (Top and Side Views)162 Intel® 82865PE / 82865P MCH Package Dimensions (Bottom View) ...... 163 XOR Toggling of HCLKP and HCLKN ............................. 165 XOR Testing Chains Tested Sequentially .......................... 166
Intel® 82865PE / 82865P MCH Datasheet
Tables
Intel® 82865PE / 82865P MCH Datasheet
Revision History
Revision -001 -002 -003 -004 · Initial Release · Corrected Default Value in A0-A3h, ACAPID Register in Section 3.5, Table 6 · Corrected bit A1 in Table 20, DRAM Address Translation, 512Mb, 64Mx8 from bit 15 to bit 16. · Revised for Intel® Pentium® 4 Processor on 90 nm Process Description Date May 2003 June 2003 June 2003 February 2004
Intel® 82865PE / 82865P MCH Datasheet
Intel® 82865PE / 82865P MCH Features
I Host Interface Support
I Communication Streaming Architecture (CSA) Interface Support
- Gigabit Ethernet (GbE) communication devices supported on the CSA interface (e.g., Intel® 82547EI GbE controller) - 8-bit Hub Interface 1.5 electrical / transfer protocol - 266 MB / s point-to-point connection - 1.5 V operation - Hub Interface 1.5 - 266 MB / s point-to-point connection to the ICH5 - 66 MHz base clock - 1.5 V operation - Single AGP device - AGP 3.0 with 4X / 8X AGP data transfers and 4X / 8X fast writes, respectively - 32-bit 4X / 8X data transfers and 4X / 8X fast writes - Peak BW of 2 GB / s. - 0.8 V and 1.5 V AGP signalling levels no 3.3 V support - AGP 2.0 1X / 4X AGP data transfers and 4X fast writes - 32-deep AGP request queue - 37.5 mm x 37.5 mm Flip Chip Ball Grid Array (FC-BGA) package - 932 solder balls
I Hub Interface (HI) Support
I AGP Interface Support
I System Memory Controller Support
I MCH Package
Intel® 82865PE / 82865P MCH Datasheet
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Intel® 82865PE / 82865P MCH Datasheet
Introduction
This Memory Controller Hub (MCH) datasheet is for the Intel® 82865PE MCH and Intel® 82865P MCH. The 82865PE MCH is part of the Intel® 865PE chipset and the 82865P MCH is part of the Intel® 865P chipset. Each chipset contains two main components: Memory Controller Hub (MCH) for the host bridge and I / O Controller Hub for the I / O subsystem. The MCH provides the processor interface, system memory interface, CSA interface, AGP interface, and hub interface in an 865PE / 865P chipset desktop platform. The 865PE chipset and 865P chipset use either the 82801EB ICH5 or 82801ER ICH5R for the I / O Controller Hub. The following are the key feature differences between the 82865PE MCH and 82865P MCH:
· Processor Front Side Bus (FSB) frequency
- 82865PE supports 800 MHz / 533 MHz / 400 MHz frequencies. - 82865P supports 533 MHz / 400 MHz frequencies.
· System Memory
- 82865PE supports DDR266, DDR333, and DDR400 - 82865P supports DDR266 and DDR333 The Intel® 865PE / 865P chipset platforms support the following processors:
· Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin
package.
· Intel® Pentium® 4 processor on 90 nm process.
Note: Unless otherwise specified, the information in this document applies to both the 82865PE MCH and the 82865P MCH. Also, unless otherwise specified, the term MCH applies to both the 82865PE MCH and the 82865P MCH. Unless otherwise specified, the term processor in this document refers to the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package and the Pentium 4 processor on 90 nm process. Unless otherwise specified, the term ICH5 refers to both the 82801EB ICH5 and 82801ER ICH5R.
Note:
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Table 1.
Terminology
This section provides the definitions of some of the terms used in this document. General Terminology (Sheet 1 of 2)
Channel Chipset Core Column Address Double-Sided DIMM DDR Full Reset GART MCH GTLB HI Host Intel® ICH5 Primary PCI FSB Row
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Table 1.
General Terminology (Sheet 2 of 2)
Terminology (Continued) Row Address Description The Row address is presented to the DRAMs during an Activate command and indicates which page to open within the specified bank (the bank number is also presented). Processor-to-MCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The Enhanced Mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting of source synchronous transfers for address and data, and FSB interrupt delivery. The Intel® Pentium® 4 processor implements a subset of the enhanced mode. Terminology often used to describe a DIMM that contains one DRAM row. Usually one row fits on a single side of the DIMM allowing the backside to be empty. Single Data Rate SDRAM. Synchronous Dynamic Random Access Memory. The physical PCI interface that is a subset of the AGP bus driven directly by the MCH. It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at 1.5 V (not 3.3 V or 5 V). Stub Series Terminated Logic for 2.6 Volts (DDR)
Related Documents
Intel® 865G / 865PE / 865P Chipset Platform Design Guide
Intel® 865G / 865PE / 865P Chipset Thermal Design Guide Intel® 82801EB I / O Controller Hub 5 (ICH5) and Intel® 82801ER I / O Controller Hub 5R (ICH5R) Datasheet Intel® Pentium® 4 Processors with 512-KB L2 Cache on 0.13 Micron Process Datasheet Intel® Pentium® 4 Processors on 90 nm Process Datasheet JEDEC Double Data Rate (DDR) SDRAM Specification Intel® PC SDRAM Specification Accelerated Graphics Port Interface Specification, Revision 2.0
NOTE: For additional related documents, refer to the Intel® 865G / 865PE / 865P Chipset Platform Design Guide.
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Intel® 865PE / 865P Chipset System Overview
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Figure 1. Intel® 865PE Chipset System Block Diagram
Processor 400 / 533 / 800 MHz FSB 2.1 GB / s System Memory Intel ® 865PE Chipset DDR AGP 8x / 4x Channel A 2.1 GB / s up to 3.2 GB / s Channel B 2.1 GB / s up to 3.2 GB / s DDR
CSA Interface Gigabit Ethernet
Intel® 82865PE MCH
DDR DDR
266 MB / s HI 1.5 USB 2.0 8 ports, 480 Mb / s
Power Management Clock Generation
2 Serial ATA Ports 150 MB / s
2 ATA 100 Ports
Flash BIOS
LPC Interface
Sys Blk 875P 1
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Figure 2. Intel® 865P Chipset System Block Diagram
Processor 400 / 533 MHz FSB 2.1 GB / s System Memory Intel ® 865P Chipset DDR AGP 8x / 4x Channel A 2.1 GB / s up to 2.7 GB / s Channel B 2.1 GB / s up to 2.7 GB / s DDR
CSA Interface Gigabit Ethernet
Intel ® 82865P MCH
DDR DDR
266 MB / s HI 1.5 USB 2.0 8 ports, 480 Mb / s
Power Management Clock Generation
2 Serial ATA Ports 150 MB / s
2 ATA 100 Ports
Flash BIOS
LPC Interface
Sys Blk 875P 1
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Intel® 82865PE / 82865P MCH Overview
Host Interface
System Memory Interface
· Supports one or two 64-bit wide DDR data channels · For the 82865PE MCH, the available bandwidth up to 3.2 GB / s (DDR400) for single-channel · · · · · · · · · ·
mode and 6.4 GB / s (DDR400) in dual-channel mode. For the 82865P MCH, the available bandwidth up to 2.7 GB / s (DDR333) for single-channel mode and 5.4 GB / s (DDR333) in dual-channel mode. Support for non ECC. Supports 128-Mb, 256-Mb, 512-Mb DDR technologies Supports only x8, x16, DDR devices with four banks Registered DIMMs not supported Supports opportunistic refresh Up to 16 simultaneously open pages (four per row, four rows maximum) SPD (Serial Presence Detect) scheme for DIMM detection support Suspend-to-RAM support using CKE Supports configurations defined in the JEDEC DDR1 DIMM specification only
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Single-Channel DDR Configuration
Up to 4.0 GB of DDR Supports up to four DDR DIMMs (2 DIMMs per channel), single-sided and / or double-sided 82865PE MCH supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs 82865P MCH supports DDR266 and DDR333 unregistered non-ECC DIMMs Supports up to 32 simultaneous open pages Does not support mixed-mode / uneven double-sided DDR DIMMs
Dual-Channel DDR Configuration - Lockstep
Up to 4.0 GB of DDR Supports up to four DDR DIMMs, single-sided and / or double-sided DIMMS must be populated in identical pairs for dual-channel operation Supports 16 simultaneous open pages (four per row) 82865PE MCH supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs 82865P MCH supports DDR266 and DDR333 unregistered non-ECC DIMMs
Hub Interface
Communications Streaming Architecture (CSA) Interface
The CSA interface connects the MCH with a Gigabit Ethernet (GbE) controller. The MCH supports only HI 1.5 over the interface that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The CSA interface runs at 266 MT / s (with 66 MHz base clock) and uses 1.5 V signaling.
AGP 8X Interface
Intel® 82865PE / 82865P MCH Datasheet
Introduction
Clock Ratios
Table 2 lists the supported system memory clock ratios. AGP, CSA, and HI run at 66 MHz common clock and asynchronous to the chipset core. There is no required skew or ratio between FSB / chipset core and 66 MHz system clocks.
Table 2.
System Memory Clock Ratios
Host Clock 100 MHz 133 MHz 200 MHz (82865PE MCH only) 133 MHz 200 MHz (82865PE MCH only) 200 MHz (82865PE MCH only) DRAM Clock 133 MHz 133 MHz 133 MHz 166 MHz 160 MHz 200 MHz Ratios 3 / 4 1 / 1 3 / 2 4 / 5 5 / 4 1 / 1 DRAM Data Rate 266 MT / s 266 MT / s 266 MT / s 333 MT / s 320 MT / s 400 MT / s DRAM Type DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM Peak Bandwidth 2.1 GB / s 2.1 GB / s 2.1 GB / s 2.7 GB / s 2.6 GB / s 3.2 GB / s
Intel® 82865PE / 82865P MCH Datasheet
Introduction
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Intel® 82865PE / 82865P MCH Datasheet
Signal Description
This section provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O I / O s / t / s Input pin Output pin Bi-directional Input / Output pin Sustained Tri-state. This pin is driven to its inactive state prior to tri-stating.
The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I / O Specification for complete details. The MCH integrates AGTL+ termination resistors, and supports VTT from1.15 V to 1.55 V (not including guard banding). AGP interface signals. These signals are compatible with AGP 2.0 1.5 V signaling and AGP 3.0 0.8 V swing signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. Hub Interface 1.5 compatible signals Low Voltage TTL 3.3 V compatible signals Stub Series Terminated Logic 2.6 V compatible signals.
2.6 VGPIO 2.6 V buffers used for misc GPIO signals 3.3 VGPIO 3.3 V buffers used for DAC / DCC signals CMOS CMOS buffers.
Host Interface signals that perform multiple transfers per clock cycle may be marked as either "4X" (for signals that are "quad-pumped") or 2X (for signals that are "double-pumped"). Note that the processor address and data bus signals are logically inverted signals. In other words, the actual values are inverted of what appears on the processor bus. This must be taken into account and the addresses and data bus signals must be inverted inside the MCH host bridge. All processor control signals follow normal convention. A 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix.
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Figure 3. Intel® 82865PE / 82865P MCH Interface Block Diagram
Processor System Bus Interface
AGP Interface
System Memory DDR Channel A Voltage Refernce, RCOMP, VSWING, and Power
System Memory DDR Channel B
Hub Interface Clocks, Reset, & Test
CSA Interface
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Host Interface Signals
BPRI#
BREQ0#
O AGTL+
CPURST#
O AGTL+
DBSY# DEFER#
I / O AGTL+ O AGTL+
NOTE: This signal is called DBI3:0 in the Intel processor specification. DRDY# I / O AGTL+ Data Ready: This signal is asserted for each cycle that data is transferred.
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Signal Name
Description Host Address Bus: HA31:3# connect to the processor address bus. During processor cycles the HA31:3# are inputs. The MCH drives HA31:3# during snoop cycles on behalf of HI and AGP / Secondary PCI initiators. HA31:3# are transferred at 2X rate. Note that the address is inverted on the processor bus. NOTE: The MCH drives the HA7# signal, which is then sampled by the processor and the MCH on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. Host Address Strobe: HADSTB1:0# are source synchronous strobes used to transfer HA31:3# and HREQ4:0# at the 2X transfer rate. Strobe HADSTB0# HADSTB1# Address Bits A16:3#, REQ4:0# A31:17#
HA31:3#
HADSTB1:0#
HD63:0#
Host Data: These signals are connected to the processor data bus. Data on HD63:0# is transferred at a 4X rate. Note that the data signals may be inverted on the processor bus, depending on the DINV3:0 signals. Differential Host Data Strobes: These signals are differential source synchronous strobes used to transfer HD63:0# and DINV3:0# at the 4X transfer rate.
HDSTBP3:0# HDSTBN3:0#
Strobe HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0#
Data Bits HD63:48#, DINV3# HD47:32#, DINV2# HD31:16#, DINV1# HD15:0#, DINV0#
I / O AGTL+ I / O AGTL+ I AGTL+
Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. HIT# is also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. HITM# is also driven in conjunction with HIT# to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic (i.e., no HI or AGP / PCI snoopable access to system memory are allowed when HLOCK# is asserted by the processor). Host Request Command: These signals define the attributes of the request. HREQ4:0# are transferred at 2X rate. They are asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the MCH Host Bridge are defined in the Chapter 5.
HITM#
HLOCK#
HREQ4:0#
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Signal Name HTRDY# PROCHOT#
Type O AGTL+ I / 0 AGTL+
RS2:0#
The following is the list of processor bus interface signals that are not supported by the MCH.
Signal Name Not Supported AP1:0# DP3:0# HA35:32 RSP# IERR# BINIT# MCERR# Function Not Supported Address bus parity Data parity Upper address bits Response (RS) parity Processor Internal Error Bus Initialization Signal Machine Check Error Thus, MCH Does Not Support Parity protection on address bus Data parity errors on host interface Only supports a 4-GB system address space Response parity errors on host interface Responding to processor internal error Reset of the Host Bus state machines. Signaling or recognition of Machine Check Error
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Memory Interface
DDR DRAM Interface A
The following DDR signals are for DDR channel A:
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
DDR DRAM Interface B
The following DDR signals are for DDR channel B:
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Hub Interface
Signal Name HI10:0 HISTRS HISTRF Type I / O sts HI15 I / O sts HI15 I / O sts HI15 Description Packet Data: HI10:0 are the data signals used for HI read and write operations. Packet Strobe: HISTRS is one of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: HISTRF is one of two differential strobe signals used to transmit or receive packet data over HI.
CSA Interface
Signal Name CI10:0 CISTRS CISTRF Type I / O sts HI15 I / O sts HI15 I / O sts HI15 Description Packet Data: CI10:0 are data signals used for CI read and write operations. Packet Strobe: CISTRS is one of two differential strobe signals used to transmit or receive packet data over CI. Packet Strobe Complement: CISTRF is one of two differential strobe signals used to transmit or receive packet data over CI.
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
AGP Interface Signals
AGP Addressing Signals
NOTES: 1. The previous table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When GPIPE# is used to queue addresses the master is not allowed to queue addresses using the SB bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset. 2. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 3. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
AGP Flow Control Signals
Signal Name Type Description Read Buffer Full: This signal indicates if the master is ready to accept previously requested low priority read data. When GRBF(#) is asserted, the MCH is not allowed to return low priority read data to the AGP master on the first block. GRBF(#) is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data, it is not required to implement this signal. Write Buffer Full: This signal indicates if the master is ready to accept fast write data from the MCH. When GWBF(#) is asserted, the MCH is not allowed to drive fast write data to the AGP master. GWBF(#) is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data, it is not required to implement this signal. NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
GRBF# (2.0) GRBF (3.0)
GWBF# (2.0) GWBF (3.0)
AGP Status Signals
Signal Name GST2:0 (2.0) GST2:0 (3.0) Type O AGP Description Status: These signals provide information from the arbiter to an AGP Master on what it may do. GST2:0 only have meaning to the master when its GGNT(#) is asserted. When GGNT(#) is deasserted, these signals have no meaning and must be ignored. GST2:0 are always an output from the MCH and an input to the master. Encoding 000 001 010 011 100 101 110 111 Meaning Previously requested low priority read data (Async read for AGP 3.0 signaling mode) is being returned to the master. Previously requested high priority read data is being returned to the master. Reserved in AGP 3.0 signaling mode. The master is to provide low priority write data (Async write for AGP 3.0 signaling mode) for a previously queued write command. The master is to provide high priority write data for a previously queued write command. Reserved in AGP 3.0 signaling mode. Reserved. Reserved. Reserved. The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting GPIPE# (4X signaling mode) or start a PCI transaction by asserting GFRAME(#).
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
AGP Strobes
GADSTB0 (2.0) GADSTBF0 (3.0)
GADSTB0# (2.0) GADSTBS0 (3.0)
GADSTB1 (2.0) GADSTBF1 (3.0)
GADSTB1# (2.0) GADSTBS1 (3.0)
GSBSTB (2.0) GSBSTBF (3.0)
NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
PCI Signals-AGP Semantics
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using PCI protocol, these signals completely preserve PCI 2.1 semantics. The exact roles of all PCI signals during AGP transactions are defined in the following table.
GIRDY# (2.0) GIRDY (3.0)
GTRDY# (2.0) GTRDY (3.0)
GSTOP# (2.0) GSTOP (3.0) GDEVSEL# (2.0) GDEVSEL (3.0) GREQ# (2.0) GREQ (3.0) GGNT# (2.0) GGNT (3.0)
GAD31:0
GC / BE3:0# (2.0) GC# / BE3:0 (3.0)
GPAR (2.0) GPAR (3.0)
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Signal Name
NOTES: 1. Note that PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic. 2. LOCK# signal is not supported on the AGP interface (even for PCI operations). 3. (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing) 4. (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing)
PCI Pins during PCI Transactions on AGP Interface
PCI signals described in a previous table behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP interface.
Test Signals
TESTP2
TESTP1
TESTP0
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Clocks, Reset, and Miscellaneous
Signal Name HCLKP HCLKN Type I CMOS I LVTTL (3.3 V) I LVTTL (3.3 V) I LVTTL (3.3 V) I EXTTS# LVTTL (3.3 V) Description Differential Host Clock In: These pins receive a low voltage differential host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the host clock domain 0.7 V. 66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP / PCI and HI clock domains. Note that this clock input is required to be 3.3 V tolerant. Reset In: When asserted, this signal will asynchronously reset the MCH logic. This signal is connected to the PCIRST# output of the ICH5. All AGP / PCI output and bi-directional signals will also tri-state compliant to PCI Revision 2.0 and 2.1 specifications. This input should have a Schmitt trigger to avoid spurious resets. Note that this input needs to be 3.3 V tolerant. Power OK: When asserted, PWROK is an indication to the MCH that the core power and GCLKIN have been stable for at least 10 µs. External Thermal Sensor Input: This is an open-drain signal indicating an OverTemp condition in the platform. This signal should remains asserted for as long as the Over-temp Condition exists. This input pin can be programmed to activate hardware management of memory reads and writes and / or trigger software interrupts.
GCLKIN
RSTIN#
PWROK
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
RCOMP, VREF, VSWING
NOTE: Refer to the Intel® 865G / 865PE / 865P Chipset Platform Design Guide for platform design information.
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Power and Ground Signals
MCH Sequencing Requirements
Power Plane and Sequencing Requirements:
· Clock Valid Timing. · GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK. · HCLKN / HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#.
Figure 4. Intel® 865PE / 865P Chipset System Clock and Reset Requirements
POWER ~100 ms
PWROK ~1 ms
RSTIN#
10 us min GCLKIN valid
10 us min HCLKN / HCLKP valid
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
The MCH uses the rising edge of PWROK to latch strap values. During S3, when power is not valid, the MCH requires that PWROK de-assert and then re-assert when power is valid so that it can properly re-latch the straps.
Signals Used As Straps
Functional straps
Strap Input Signals
Intel® 82865PE / 82865P MCH Datasheet
Signal Description
Full and Warm Reset States
Figure 5. Full and Warm Reset Waveforms
Intel® ICH5 Power
ICH5 PWROK In 1 ms min ICH5 PCIRST# Out MCH RSTIN# In 1 ms MCH CPURST# Out
Write to CF9h
MCH Power
MCH PWROK In
MCH Reset State
Unknown
Full Reset Warm Reset
Running
Warm Reset
Running
All register bits assume their default values during full reset. PCIRST# resets all internal flops and state machines (except for a few configuration register bits). A full reset occurs when PCIRST# (MCH RSTIN#) is asserted and PWROK is deasserted. A warm reset occurs when PCIRST# (MCH RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states.
Reset State Full Reset Warm Reset Does Not Occur Normal Operation RSTIN# L L H H PWROK L H L H
Intel® 82865PE / 82865P MCH Datasheet
Register Description
The MCH contains two sets of software accessible registers, accessed via the host processor I / O address space:
· Control registers I / O mapped into the processor I / O space that controls access to PCI and AGP
configuration space.
· Internal configuration registers residing within the MCH are partitioned into three logical
Register Terminology
Reserved Bits
Intel® 82865PE / 82865P MCH Datasheet
Register Description
Description In addition to reserved bits within a register, the MCH contains address locations in the configuration space of the Host-HI Bridge entity that are marked either "Reserved" or "Intel Reserved". The MCH responds to accesses to Reserved address locations by completing the host cycle. When a Reserved register location is read, a zero value is returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved registers have no effect on the MCH. Caution: Registers that are marked as "Intel Reserved" must not be modified by system software. Writes to "Intel Reserved" registers may cause system failure. Reads to "Intel Reserved" registers may return a non-zero value. Upon a reset, the MCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the MCH registers accordingly.
Reserved Registers
Default Value upon a Reset
Overview of the Platform Configuration Structure
· Device 0: Host-HI Bridge / DRAM Controller. Logically this appears as a PCI device residing
on PCI bus 0. Physically Device 0 contains the standard PCI registers, DRAM registers, the Graphics Aperture controller, configuration for HI, and other MCH specific registers.
· Device 1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing
on PCI bus 0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP / PCI configuration registers (including the AGP I / O and memory address mapping).
· Device 3: CSA Port. Appears as a virtual PCI-CSA (PCI-to-PCI) bridge device. · Device 6: Function 0: Overflow Device. The purpose of this device is to provide additional
configuration register space for Device 0.
Intel® 82865PE / 82865P MCH Datasheet
Register Description
Table 3 shows the Device # assignment for the various internal MCH devices. Table 3. Internal MCH Device Assignment
MCH Function DRAM Controller / 8-bit HI Controller Host-to-AGP Bridge (virtual PCI-to-PCI) Intergrated GBE (CSA) Overflow Bus 0, Device # Device 0 Device 1 Device 3 Device 6
Logically, the ICH5 appears as multiple PCI devices within a single physical component also residing on PCI bus 0. One of the ICH5 devices is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI 0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus 0 does not exist and the hub interface and the internal devices in the MCH and ICH5 logically constitute PCI Bus 0 to configuration software.
Figure 6. Conceptual Intel® 875PE / P Chipset Platform PCI Configuration Diagram
Processor
Host-AGP Bus 0 Device 1 CSA Bus 0 Device 3
PCI Configuration Window I / O Space
DRAM Control / Hub Interface Bus 0 Device 0, 6 Hub Interface Intel® ICH5
Hub Interface
LPC Bus 0 Device Fcn 0
Hub Interface - PCI Bridge PBus 0 Fcn 0
Intel® 82865PE / 82865P MCH Datasheet
Register Description
Routing Configuration Accesses
Standard PCI Bus Configuration Mechanism
PCI Bus 0 Configuration Mechanism
Primary PCI and Downstream Configuration Mechanism
Intel® 82865PE / 82865P MCH Datasheet
Register Description
Figure 7. Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping
31 1 Reserved 24 23 Bus Number 16 15 14 11 10 8 7 Register Number 2 1 x 0 x Device Number Function #
24 23 IDSEL
8 7 Register Number
Function #
AGP GAD31:0 Address AGP / PCI1 Type 0 Configuration Cycle
Table 4.
Configuration Address Decoding
Config Address AD15:11 00000 00001 00010 00011 00100 00101 00110 00111 AGP GAD31:16 IDSEL 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 Config Address AD15:11 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx AGP GAD31:16 IDSEL 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000
Intel® 82865PE / 82865P MCH Datasheet
Register Description
Function Number
Reg. Index
PCI Address AD31:0 31
Bus Number 16 15
Device Number
Function Number
Reg. Index 2 1
I / O Mapped Registers
I / O Address: Default Value: Access: Size: 0CF8h Accessed as a DWord 00000000h R / W 32 bits
Intel® 82865PE / 82865P MCH Datasheet
Register Description
I / O Address: Default Value: Access: Size: 0CFCh 00000000h R / W 32 bits