Analog 10-Channel, 12-bit, 1MSPS Fully differential single-ended modes

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Analog 10-Channel, 12-bit, 1MSPS Fully differential single-ended modes

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Precision Analog Microcontroller 12-bit Analog PWM, ARM7TDMI®
Analog 10-Channel, 12-bit, 1MSPS Fully differential single-ended modes VREF Analog Input Range Dual 12-bit Voltage Output DACs On-Chip 20ppm/°C Voltage Reference On-Chip Temperature Sensor (±3°C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download debug Clocking options: Trimmed On-Chip Oscillator External Watch crystal External clock source 45MHz with Programmable Divider Memory Bytes Flash/EE Memory, Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals UART, Serial 30-Pin GPIO Port
ADuC7024
General Purpose Timers Wake-up Watchdog Timers Power Supply Monitor Three-phase 16-bit generator Programmable Logic (Array) Power Specified operation Active Mode: (@1MHz) 300mW (@45MHz) Packages Temperature Range LFCSP 9x9mm body package LQFP 12x12mm body package Fully specified -40°C 85°C operation Tools Low-Cost QuickStart Development System Full Third-Party Support
APPLICATIONS
Industrial Control Automation Systems Smart Sensors, Precision Instrumentation Base Station Systems, Optical Networking (See general description page
FUNCTIONAL BLOCK DIAGRAM
ADuC7024
ADC0 ADC7 ADC8 ADC9 CMP0 CMP1 VREF XCLKI XCLKO
12-BIT 1MSPS 12-BIT TEMP SENSOR BANDGAP 12-BIT
DAC0 DAC1 PWM0H PWM0L
2kX32 SRAM 31kX16 FLASH/EEPROM SERIAL UART, SPI, 2xI2C GEN. PURPOSE TIMERS
Threephase
PWM1H PWM1L PWM2H PWM2L
ARM7TDMI-BASED WITH ADDITIONAL PERIPHERALS
GPIO
JTAG
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 2004 Analog Devices, Inc. rights reserved. Fax: 781.326.8703
ADuC7024
TABLE CONTENTS
ADuC7024-Specifications Terminology Absolute Maximum Ratings. Ordering Guide. function descriptions
General Description. Overview ARM7TDMI core. Memory organisation In-Circuit Serial Downloader. Outline Dimensions
Rev. Page
ADUC7024-SPECIFICATIONS
ADuC7024
Table (AVDD IOVDD 3.6V, VREF Internal Reference, fCORE 45MHz, specifications TMAX TMIN, unless otherwise noted.)
Parameter CHANNEL SPECIFICATIONS Accuracy Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Differential Nonlinearity Code Distribution CALIBRATED ENDPOINT ERRORS Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential mode Single-ended mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT9 Input Voltage Range Input Impedance CHANNEL SPECIFICATIONS ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ADuC7024 Unit Test Conditions/Comments fSAMPLE 1MSPS ±1.5 ±0.5 ±2.0 +1/-0.9 ±0.5 +1/-0.9 Bits 10kHz Sine Wave, fSAMPLE 1MSPS 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference input voltage
VCM8±VREF/2 VREF 0.625 AVDD
Volts Volts ppm/°C
During Acquisition 0.47µF from VREF (pin AGND Measured 25°C
100pF ±0.5 Bits
Guaranteed Monotonic output unbuffered output buffered fullscale DAC0
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ADuC7024
Parameter ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 Output Impedance CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis Response Time TEMPERATURE SENSOR Voltage Output 25°C Voltage Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Watchdog Timer (WDT)4 Timeout Period Flash/EE MEMORY Endurance10 Data Retention11 Digital Inputs Input Leakage Current Input Capacitance Logic Inputs4 VINL, Input Voltage VINH, Input High Voltage Logic Outputs VOH, Output High Voltage VOL, Output Voltage CLOCK RATE STARTUP TIME Power-On From Idle Mode From Power-Down Mode Programmable Logic Array (PLA) Propagation Delay ADuC7024 DACREF 2.5V DACVDD AVDD-1.2 -2.0 2.79 3.07 ±2.5 10,000 355.5 45.5 Unit
Test Conditions/Comments
DACREF range: DACGND DACVDD
nV-sec mV/°C Cycles Years Logic inputs including XTAL1 XTAL2 ISOURCE 20µA ISINK 1.6mA programmable core clock selections within this range Core Clock selectable Trip Points selected nominal Trip Point Voltage Output buffered Output unbuffered change major carry
Hysteresis turned CMPHYST CMPCON register Response time modified CMPRES bits CMPCON register
55°C digital inputs including XTAL1 XTAL2
From input output
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Parameter POWER REQUIREMENTS Power Supply Voltage Range AVDD AGND IOVDD IOGND ADuC7024 Unit Test Conditions/Comments
ADuC7024
External Crystal Internal External Crystal Internal 1MHz clock 1MHz clock 45MHz clock 45MHz clock
Power Supply Current Normal Mode
Power Supply Current Idle Mode Power Supply Current Power Down Mode
Temperature Range -40° +85°C Channel Specifications guaranteed during normal MicroConverter core operation. These specification apply input channels. These numbers production tested supported design and/or characterization data production release. Based external system components, user need execute system calibration remove external endpoint achieve these specifications. calculation includes distortion noise components. Channel-to-channel crosstalk measured adjacent channels. input signal centered common-mode voltage (VCM) long this value within voltage input range specified. When using external reference input pin, internal reference must disabled setting REFCON Memeory Mapped Register Endurance qualified 50,000 cycles JEDEC Std. method A117 measured -40°C, +25°C +85°C. Typical endurance 25°C 70,000 cycles. Retention lifetime equivalent junction temperature (Tj) 55°C JEDEC Std. method A117. Retention lifetime will derate with junction temperature. Power supply current consumption measured normal, idle power-down modes under following conditions: Normal Mode: Idle Mode: Power-Down: DVDD power supply current increases typically during Flash/EE memory program erase cycle.
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ADuC7024
TERMINOLOGY
Specifications
Integral Nonlinearity This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition full scale, point above last code transition. Differential Nonlinearity This difference between measured ideal change between adjacent codes ADC. Offset Error This deviation first code transition (0000 000) (0000 001) from ideal, i.e., +1/2 LSB. Gain Error This deviation last code transition from ideal voltage (Full Scale LSB) after offset error been adjusted out. Signal (Noise Distortion) Ratio This measured ratio signal (noise distortion) output ADC. signal amplitude
fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitisation process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02N 1.76) Thus 12-bit converter, this Total Harmonic Distortion Total Harmonic Distortion ratio harmonics fundamental.
SPECIFICATIONS
Relative Accuracy Relative accuracy endpoint linearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error. Voltage Output Settling Time This amount time takes output settle within level full-scale input change.
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ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings 25°C unless otherwise noted)
Parameter AVDD DVDD AGND DGND DVDD DGND, AVDD AGND Digital Input Voltage DGND Digital Output Voltage DGND VREF AGND Analog Inputs AGND Operating Temperature Range Industrial ADuC7024 Storage Temperature Range Junction Temperature Thermal Impedance (ADuC7024BCP) Lead Temperature, Soldering Vapor Phase sec) Infrared sec) Rating -40°C +85°C
ADuC7024
CONFIGURATION 64-Lead
IDENTIFIER
ADuC7024 VIEW (Not Scale)
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
64-Lead LQFP
IDENTIFIER
ADuC7024 64-LEAD LQFP
VIEW (Not Scale)
ORDERING GUIDE
Model ADuC7024BCP ADuC7024BST EVAL_ADuC7024QS Temperature Range -40°C 85°C -40°C 85°C Package Description 64-Lead Chip Scale Package Lead Plastic Quad Flatpack Development System Package Option CP-64 ST-64
Contact factory chip availability.
Caution
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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ADuC7024
FUNCTION DESCRIPTIONS
Table Function Descriptions
Pin# Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 P4.6/PLAO[14] P4.7/PLAO[15] Type* Function
BM/P0.0/CMPOUT/PLAI[7]
P0.6/T1/MRST/PLAO[3] IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADCBUSY P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13]
Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Ground voltage reference ADC. optimal performance analog power supply should separated from IOGND DGND Bias point Negative Analog Input pseudo differential mode. Must connected ground signal convert. This bias point must between DAC0 Voltage Output Single-ended differential Analog input DAC1 Voltage Output Single-ended differential Analog input JTAG Test Port Input Test Mode Select. Debug download access JTAG Test Port Input Test Data Debug download access General Purpose Input-Output Port 4.6/ Programmable Logic Array Output Element General Purpose Input-Output Port 4.7/ Programmable Logic Array Output Element Multifunction pin: Boot Mode. ADuC7024 will enter UART serial download mode reset will execute code pulled high reset through 1kOhm resistor/ General Purpose Input-Output Port Voltage Comparator Output/ Programmable Logic Array Input Element Multifunction pin: driven after reset General Purpose Output Port Timer Input Power reset output Programmable Logic Array Output Element JTAG Test Port Input Test Clock. Debug download access JTAG Test Port Output Test Data Out. Debug download access Ground GPIO. Typically connected DGND 3.3V Supply GPIO input on-chip voltage regulator. 2.5V. Output on-chip voltage regulator. Must connected 0.47µF capacitor DGND Ground core logic. General Purpose Input-Output Port 3.0/ phase high side output Programmable Logic Array Input Element General Purpose Input-Output Port 3.1/ phase side output Programmable Logic Array Input Element General Purpose Input-Output Port 3.2/ phase high side output Programmable Logic Array Input Element General Purpose Input-Output Port 3.3/ phase side output Programmable Logic Array Input Element General Purpose Input-Output Port JTAG Test Port Input Test Reset. Debug download access ADCBUSY signal output Reset Input. (active low) General Purpose Input-Output Port phase high side output Programmable Logic Array Input General Purpose Input-Output Port phase side output Programmable Logic Array Input Element
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Pin# Mnemonic Type* Function
ADuC7024
Multifunction pin: External Interrupt Request active high General Purpose Input-Output Port Start conversion input signal Programmable Logic Array Output Element Multifunction pin: External Interrupt Request active high General Purpose Input-Output Port ADCBUSY signal Programmable Logic Array Output Element Serial Port Multiplexed: General Purpose Input-Output Port safety UART Programmable Logic Array Output Element Start conversion input signal Serial Port Multiplexed: General Purpose Input-Output Port Output External Clock signal UART Programmable Logic Array Output Element Output crystal oscillator inverter Input crystal oscillator inverter input internal clock generator circuits General Purpose Input-Output Port 3.6/ safety Programmable Logic Array Input Element General Purpose Input-Output Port 3.7/ Output External Clock signal /Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port UART Programmable Logic Array Output Element Serial Port Multiplexed: General Purpose Input-Output Port UART Programmable Logic Array Input Element Ground GPIO. Typically connected DGND 3.3V Supply GPIO input on-chip voltage regulator. General Purpose Input-Output Port Programmable Logic Array Output Element General Purpose Input-Output Port Programmable Logic Array Output Element Serial Port Multiplexed: General Purpose Input-Output Port UART Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port UART Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port 1.3/ UART I2C1 /Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port UART I2C1 /Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port UART I2C0 Programmable Logic Array Input Element Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer Input UART I2C0 Programmable Logic Array Input Element General Purpose Input-Output Port Programmable Logic Array Output Element
IRQ0/P0.4/CONVSTART/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
P0.7/ECLK/SPM8/PLAO[4] XCLKO XCLKI P3.6/PWMTRIP/PLAI[14] P3.7/ECLK/PLAI[15] P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/PLAO[8] P4.1/PLAO[9] P1.5/SPM5/PLAI[5]
P1.4/SPM4/PLAI[4]
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0] P4.2/PLAO[10]
Rev. Page
ADuC7024
Pin#
Type* Function General Purpose Input-Output Port Programmable Logic Array Output Element General Purpose Input-Output Port Programmable Logic Array Output Element General Purpose Input-Output Port Programmable Logic Array Output Element 2.5V internal Voltage Reference. Must connected 0.47uF capacitor when using internal reference. External Voltage Reference DACs. Range: DACGND DACVDD Ground DAC. Typically connected AGND Analog Ground. Ground reference point analog circuitry 3.3V Analog Power 3.3V Power Supply DACs. Typically connected AVDD Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Comparator positive input Single-ended differential Analog input Comparator negative input
Mnemonic P4.3/PLAO[11] P4.4/PLAO[12] P4.5/PLAO[13] VREF DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Input, Output, Supply.
Rev. Page
GNDREF IOGND IOGND AGND IOVDD DGND IOVDD AVDD RESET LVDD
ADuC7024
ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADCNEG TEMP SENSOR Threephase
12-BIT 1MSPS
DACVDD
ADuC7024
12-BIT VOLTAGE OUTPUT 12-BIT VOLTAGE OUTPUT
DACGND DACREF DAC0/ADC12
CONTROL
CONTROL
DAC1/ADC13
P3.0/PWM0H/PLAI P3.1/PWM0L/PLAI P3.2/PWM1H/PLAI P3.3/PWM1H/PLAI P3.4/PWM2H/PLAI P3.5/PWM2H/PLAI 8192 BYTES USER bits) P3.6/PWMTRIP/PLAI KBYTES FLASH/EE (31k bits)
BM/P0.0/CMPOUT/PLAO VREF
CMPOUT/IRQ VREF DOWNLOADER BAND REFERENCE
ARM7TDMI CORE
WAKEUP/ TIMER POWER SUPPLY MONITOR
XCLKO XCLKI P3.7/ECLK/PLAI
PROG. CLOCK DIVIDER
JTAG EMULATOR
P4.6/PLAO P4.7/PLAO
PROG. LOGIC ARRAY
SPI/I2 SERIAL INTERFACE
UART SERIAL PORT
SERIAL PORT MULTIPLEXER
INTERRUPT CONTROLLER
IRQ0/P0.4/CONVSTART/PLAO IRQ1/P0.5/ADCBUSY/PLAO
TCK/XCLK
P0.7/ECLK/SPM8/PLAO
P0.3/TRST/ADCBUSY
P1.0/SPM0/PLAI
P4.0/PLAO
P4.1/PLAO
P4.3/PLAO
P4.4/PLAO
P4.5/PLAO
P4.2/PLAO
P1.6/SPM6/PLAI
P1.5/SPM5/PLAI
P1.1/SPM1/PLAI
P1.2/SPM2/PLAI
P1.3/SPM3/PLAI
P1.4/SPM4/PLAI
P1.7/SPM7/PLAI
Figure Detailed Block Diagram
Rev. Page
P0.6/MRST/PLAO
ADuC7024
GENERAL DESCRIPTION
ADuC7024 fully integrated, 1MSPS, 12-bit data acquisition system incorporating high performance multichannel ADC, 16/32-bit Flash/EE Memory single chip. consists single-ended inputs. additional inputs available multiplexed with output pins. operate single-ended differential input modes. input voltage VREF. drift bandgap reference, temperature sensor voltage comparator complete peripheral set. part also integrates buffered voltage output DACs onchip. output range programmable three voltage ranges. device operates from on-chip oscillator generating internal high-frequency clock MHz. This clock routed through programmable clock divider from which core clock operating frequency generated. microcontroller core ARM7TDMI, 16/32-bit RISC machine, offering MIPS peak performance. Bytes non-volatile Flash/EE provided on-chip well Bytes SRAM. Both Flash/EE SRAM memory arrays mapped into single linear array. On-chip factory firmware supports in-circuit serial download UART JTAG serial interface ports while nonintrusive emulation also supported JTAG interface. These features incorporated into low-cost QuickStart Development System supporting this MicroConverter family. parts operate from 2.7V 3.6V specified over industrial temperature range -40°C 85°C. When operating 45MHz power dissipation 300mW. ADuC7024 available 64-lead LFCSP package 64-lead LQFP.
compressed into 16-bits, Thumb instruction set. Faster execution from 16-bit memory greater code density usually achieved using Thumb instruction instead instruction set, which makes ARM7TDMI core particularly suitable embedded applications. However Thumb mode limitations: Thumb code usually uses more instructions same job, code usually best maximising performance time-critical code. Thumb instruction does include some instructions that needed exception handling, code needs used exception handling. ARM7TDMI User Guide details core architecture, programming model both Thumb instruction sets.
Long multiple
ARM7TDMI instruction includes four extra instructions which perform 32-bit 32-bit multiplication with 64-bit result 32-bit 32-bit multiplication-accumulation (MAC) with 64-bit result.
EmbeddedICE
EmbeddedICE provides integrated on-chip support core. EmbeddedICE module contains breakpoint watchpoint registers which allow code halted debugging purposes. These registers controlled through JTAG test port. When breakpoint watchpoint encountered, processor halts enters debug state. Once debug state, processor registers inspected well Flash/EE, SRAM Memory Mapped Registers.
OVERVIEW ARM7TDMI CORE
ARM7 core 32-bit Reduced Instruction Computer (RISC). uses single 32-bit instruction data. length data bits length instruction word bits. ARM7TDMI ARM7 core with additional features: support Thumb bit) instruction set. support debug support long multiplies include EmbeddedICE module support embedded system debugging.
Exceptions
supports five types exceptions, privileged processing mode each type. five type exceptions are: Normal interrupt IRQ. provided service generalpurpose interrupt handling internal external events Fast interrupt FIQ. provided service data transfer communication channel with latency. priority over Memory abort Attempted execution undefined instruction Software interrupt (SWI) instruction which used make call operating system. Typically programmer will define interrupts higher priority interrupt, i.e. faster response time, programmer define interrupt FIQ.
Thumb mode
instruction 32-bits long. ARM7TDMI processor supports second instruction that been
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Registers
ARM7TDMI total registers, which general purpose registers status registers. Each operating mode dedicated banked registers. When writing user-level programs, general purpose 32-bit registers r14), program counter (r15) current program status register (CPSR) usable. remaining registers used only system-level programming exception handling. When exception occurs, some standard register replaced with registers specific exception mode. exception modes have replacement banked registers stack pointer (r13) link register (r14) represented Figure fast interrupt mode more registers fast interrupt processing, that interrupt processing begin without need save restore these registers thus save critical time interrupt handling process.
(PC)
ADuC7024
maximum latency calculation similar, must allow fact that higher priority could delay entry into handling routine arbitrary length time. minimum latency interrupts four cycles total which consists shortest time request take through synchronizer plus time enter exception mode. Note that ARM7TDMI will always (32-bit) mode when privileged modes, i.e. when executing interrupt service routines.
MEMORY ORGANISATION
ADuC7024 incorporates separate blocks memory, 8kByte SRAM 64kByte On-Chip Flash/EE memory. 62kByte On-Chip Flash/EE memory available user, remaining 2kBytes reserved factory configured boot page. These blocks mapped shown Figure Note that default, after reset, Flash/EE memory mirrored address 0x00000000. possible remap SRAM address 0x00000000 clearing REMAP MMR. This remap function described more details Flash/EE memory chapter.
FFFFFFFFh FFFF0000h
usable user mode
system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq
MMRs Reserved
0008FFFFh
r13_und r13_irq r14_und r14_irq
Flash/EE
SPSR_irq SPSR_und
00080000h
CPSR user mode
SPSR_fiq
SPSR_svc
SPSR_abt
Reserved
00011FFFh
mode
mode
abord mode
undefined mode mode
00010000h 0000FFFFh
SRAM Re-mappable Memory Space (Flash/EE SRAM)
Figure register organisation
00000000h
Figure Physical memory
Interrupt latency
worst case latency FIQ, assuming that enabled, consists longest time request take pass through synchronizer, plus time longest instruction complete (the longest instruction LDM) which loads registers including plus time data abort entry, plus time entry. this time, ARM7TDMI will executing instruction 0x1C (FIQ interrupt vector address). maximum total time processor cycles, which just over nanoseconds system using continuous processor clock.
Memory Access
ARM7 core sees memory linear array byte location where different blocks memory mapped outlined Figure above. ADuC7024 memory organisation configured little endian format: least significant byte located lowest byte address most significant byte highest byte address.
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ADuC7024
bit31 Byte3 Byte2 Byte1 bits bit0 Byte0 0xFFFFFFFFh
0xFFFFFFFF 0xFFFFFC3C
0xFFFFFC00 0xFFFFF820 0xFFFFF800 0xFFFFF46C
0x00000004h 0x00000000h
Flash Control Interface
GPIO
0xFFFFF400 0xFFFF0B54
Figure little endian format
Flash/EE Memory
total 64kBytes Flash/EE organised bits. bits user space bits reserved boot loader. page size this Flash/EE memory 256Bytes. 62kBytes Flash/EE available user code nonvolatile data memory. There distinction between data program code shares same space. real width Flash/EE memory bits, which means that mode (32-bit instruction), accesses Flash/EE necessary each instruction fetch. therefore recommended Thumb mode when executing from Flash/EE memory optimum access speed. maximum access speed Flash/EE memory 45MHz Thumb mode 22.5MHz full mode. More details Flash/EE access time outlined later `Execution from SRAM Flash/EE' section this datasheet.
0xFFFF0B00 0xFFFF0A14
0xFFFF0A00 0xFFFF0948
I2C1
0xFFFF0900 0xFFFF0848
I2C0
0xFFFF0800 0xFFFF0730
UART
0xFFFF0700 0xFFFF0620
0xFFFF0600 0xFFFF0538
0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370
SRAM
8kBytes SRAM available user, organized bits, i.e. 2kWords. code directly from SRAM 45MHz given that SRAM array configured 32-bit wide memory array. More details SRAM access time outlined later `Execution from SRAM Flash/EE' section this datasheet.
Bandgap Reference Power Supply Monitor Oscillator Control Watchdog Timer Wake Timer General Purpose Timer
Memory Mapped Registers
Memory Mapped Register (MMR) space mapped into upper pages Flash/EE space accessed indirect addressing through ARM7 banked registers. space provides interface between on-chip peripherals. registers except core registers reside area. shaded locations shown Figure unoccupied reserved locations should accessed user software. Table shows full memory map. `Access' column corresponds access time reading writing MMR. Table shows full memory map.
0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0310
Timer
0xFFFF0300 0xFFFF0238 0xFFFF0220 0xFFFF0110 0xFFFF0000
Remap System Control Interrupt Controller
Figure Memory Mapped
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Table Complete MMRs list
Address Name Byte Access Type address base 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR Cycle 0x0414 0x0418 PLLCON PLLKY2 Page Address Name Byte Access Type
ADuC7024
Page Cycle
address base 0xFFFF0440 0x0440 0x0444 PSMCON CMPCON
Reference address base 0xFFFF0480 0x048C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0530 0x0534 0x0600 0x0604 0x0608 0x060C REFCON ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF DAC0CON DAC0DAT DAC1CON DAC1DAT address base 0xFFFF0500
System Control address base 0xFFFF0200 0x0220 0x0230 0x0234 REMAP RSTSTA RSTCLR
Timer address base 0xFFFF0300 0x0300 0x0304 0x0308 0x030C 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C T0LD T0VAL T0CON T0CLRI T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI
address base 0xFFFF0600
UART base address 0xFFFF0700 0x0700 COMTX COMRX COMDIV0 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C
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COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMSTA1 COMSCR COMIEN1 COMIID1 COMADR COMDIV2
base address 0xFFFF0400 0x0404 0x0408 0x040C 0x0410 POWKY1 POWCON POWKY2 PLLKY1
ADuC7024
Address Name Byte Access Type I2C0 base address 0xFFFF0800 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 0x0834 0x0838 0x083C 0x0840 0x0844 I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYTE I2C0ALT I2C0CFG I2C0DIVH I2C0DIVL I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 Cycle 0x0A08 0x0A0C 0x0A10 Page Address
Name SPITX SPIDIV SPICON Byte Access Type Cycle Page
base address 0xFFFF0B00 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 0xF400 0xF404 0xF408 0xF40C 0xF410 0xF420 0xF424 0xF428 0xF430 0xF434 0xF438 0xF440 0xF444
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PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLADOUT GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP1DAT GP1SET GP1CLR GP2DAT GP2SET
I2C1 base address 0xFFFF0900 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYTE I2C1ALT I2C1CFG I2C1DIVH I2C1DIVL I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3
GPIO base address 0xFFFFF400
base address 0xFFFF0A00 0x0A00 0x0A04 SPISTA SPIRX
Address 0xF448 0xF450 0xF454 0xF458 0xF460 0xF464 0xF468 0xF800 0xF804 0xF808 0xF80C 0xF810 0xF818 0xF81C Name GP2CLR GP3DAT GP3SET GP3CLR GP4DAT GP4SET GP4CLR FEESTA FEEMOD FEECON FEEDAT FEEADR FEESIGN FEEPRO Byte Access Type Cycle Page
ADuC7024
Development Tools
entry level, cost development system available ADuC702X family. This system consists following PCbased (Windows® compatible) hardware software development tools: Hardware: ADuC702X Evaluation board Serial Port programming cable JTAG emulator Software: Integrated Development Environment, incorporating assembler, compiler intrusive JTAG-based debugger Serial Downloader software Example Code Miscellaneous: CD-ROM Documentation
Flash/EE base address 0xFFFFF800
IN-CIRCUIT SERIAL DOWNLOADER
Serial Downloader Windows application that allows user serially download assembled program (Intel format file) on-chip program FLASH/EE memory serial port standard
base address= 0xFFFFFC00 0xFC00 0xFC04 0xFC08 0xFC0C 0xFC10 0xFC14 0xFC18 0xFC1C 0xFC20 0xFC24 PWMCON PWMSTA PWMDAT0 PWMDAT1 PWMCFG PWMCH0 PWMCH1 PWMCH2 PWMEN PWMDAT2
`Access' column corresponds access time reading writing MMR. depends AMBA (Advanced Microcontroller Architecture) used access peripheral. processor AMBA busses, (Advanced High-performance Bus) used system modules (Advanced Peripheral Bus) used lower performance peripheral.
Rev. Page
ADuC7024
OUTLINE DIMENSIONS
0.60
INDICATOR
VIEW
8.75
BOTTOM VIEW
7.80 7.65 7.50
0.45 0.40 0.35 0.80 0.65 0.05 0.02 0.50 SEATING PLANE
1.00 0.90 0.80 0.20
7.63
COMPLIANT JEDEC STANDARDS MO-220-VMMD
Figure 64-Lead Frame Chip Scale Package [LFCSP] (CP-64)-Dimensions shown millimetres
0.063 (1.60) 0.006(0.15) 0.002(0.05) 0.024 0.006 (0.60 0.15) SEATING PLANE
0.47(12.0) 0.39(10.0)
VIEW
3.5o 3.5o
0.02 (0.50)
0.0087 0.002 (0.22 0.05)
Figure 64-Lead Package [LQFP] (S-64)-Dimensions shown millimetres
Rev. Page
PR04773-0-3/04(PrC)
9.00
0.60
0.30 0.25 0.18
INDICATOR

Analog 10-Channel, 12-bit, 1MSPS Fully differential single-ended modes

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