BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS merged combination bipo

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BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS merged combination bipo

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5821 5822
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS
merged combination bipolar technology gives these devices interface flexibility beyond reach standard logic buffers power driver arrays. UCN5821A, UCN5821LW, UCN5822A, UCN5822LW each have eight-bit CMOS shift register CMOS control circuitry, eight CMOS data latches, eight bipolar current-sinking Darlington output drivers. UCN5821A/LW UCN5822A/LW identical except rated output voltage. BiMOS devices have much higher data-input rates than original BiMOS circuits. With logic supply, they will typically operate better than MHz. With supply, significantly higher speeds obtained. CMOS inputs compatible with standard CMOS NMOS logic levels. circuits require appropriate pull-up resistors. using serial data output, drivers cascaded interface applications requiring additional drive lines. UCN5821/22A furnished standard 16-pin plastic DIP; UCN5821/22LW 16-lead wide-body SOIC surface-mount applications. UCN5821A also available operation from -40°C +85°C. order, change prefix from `UCN' `UCQ'.
Data Sheet 26185.12F
CLOCK SERIAL DATA LOGIC GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE POWER GROUND
SHIFT REGISTER
LATCHES
Dwg. PP-026A
Note package SOIC package electrically identical share common terminal number assignments.
ABSOLUTE MAXIMUM RATINGS 25°C Free-Air Temperature
Output Voltage, VOUT UCN5821A UCN5821LW UCN5822A UCN5822LW Logic Supply Voltage, Input Voltage Range, -0.3 Continuous Output Current, IOUT Package Power Dissipation, Package Code Package Code `LW' Operating Temperature Range, -20°C +85°C Storage Temperature Range, -55°C +150°C
Caution: CMOS devices have input static protection susceptible damage when exposed extremely high static electrical charges.
FEATURES Data Input Rate CMOS, NMOS, Compatible Internal Pull-Down Resistors Low-Power CMOS Logic Latches High-Voltage Current-Sink Outputs Automotive Capable
Always order complete part number, e.g., UCN5821A
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5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
CLOCK SERIAL DATA LOGIC GROUND
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE (ACTIVE LOW)
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
STROBE OUTPUT ENABLE
BIPOLAR
POWER GROUND
Dwg. FP-013A
Dwg. EP-010-3
NOTE There indeterminate resistance between logic ground power ground. proper operation, these terminals must externally connected together.
CLOCK SERIAL DATA
Number Outputs (IOUT
UCN5821A Max. Allowable Duty Cycle Ambient Temperature 25°C 40°C 50°C 60°C 70°C 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
Number Outputs (IOUT
UCN5821LW Max. Allowable Duty Cycle Ambient Temperature 25°C 40°C 50°C 60°C 70°C 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
7.2K
Dwg. A-14,314
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 1985, 2004 Allegro MicroSystems, Inc.
5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS +25°C, (unless otherwise specified).
Limits Characteristic Output Leakage Current Symbol ICEX Test Conditions UCN5821A/LW, VOUT UCN5822A/LW, VOUT UCN5821A/LW, VOUT +70°C UCN5822A/LW, VOUT +70°C Collector-Emitter Saturation Voltage VCE(SAT) IOUT IOUT IOUT Input Voltage VIN(0) VIN(1) Input Resistance Supply Current IDD(ON) Driver Driver Driver IDD(OFF) Drivers OFF, Inputs Drivers OFF, Inputs Min. 10.5 Max. Units
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5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
Serial Data present input transferred shift register logic logic transition CLOCK input pulse. succeeding CLOCK pulses, registers shift data information towards SERIAL DATA OUTPUT. SERIAL DATA must appear input prior rising edge CLOCK input waveform.
CLOCK DATA STROBE
OUTPUT ENABLE
Dwg. A-12,627
(VDD +25°C, Logic Levels Ground)
Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) Minimum Data Active Time After Clock Pulse (Data Hold Time) Minimum Data Pulse Width Minimum Clock Pulse Width Minimum Time Between Clock Activation Strobe Minimum Strobe Pulse Width
TIMING CONDITIONS
Information present register transferred respective latch when STROBE high (serial-to-parallel conversion). latches will continue accept data long STROBE held high. Applications where latches bypassed (STROBE tied high) will require that ENABLE input high during serial data entry. When ENABLE input high, output buffers disabled (OFF) without affecting information stored latches shift register. With ENABLE input low, outputs controlled state latches.
Typical Time Between Strobe Activation Output Transition
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input Serial Data Strobe Output Input Logic Level High Logic Level Irrelevant Latch Contents Output Enable Output Contents
Present State
Previous State
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5821A UCN5822A
Dimensions Inches (controlling dimensions)
0.014 0.008
0.430 0.280 0.240
0.300
0.070 0.045
0.100 0.775 0.735
0.005
0.210
0.015
0.150 0.115 0.022 0.014
Dwg. MA-001-16A
Dimensions Millimeters (for reference only)
0.355 0.204
10.92 7.11 6.10
7.62
1.77 1.15
2.54 19.68 18.67
0.13
5.33
0.39
3.81 2.93 0.558 0.356
Dwg. MA-001-16A
NOTES: Lead thickness measured seating plane below. Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown.
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5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5821LW UCN5822LW
Dimensions Inches (for reference only)
0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013 0.4133 0.3977 0.050
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-16A
Dimensions Millimeters (controlling dimensions)
0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33 10.50 10.10 1.27
2.65 2.35 0.10 MIN.
Dwg. MA-008-16A
NOTES: Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5821 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS
products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro products authorized critical components life-support devices systems without express written approval. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use.
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BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS merged combination bipo

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