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DELIC-LC DELIC-PB Embedded Line Port Interface Controller
20570 Version 20571 Version
Wired Communications
Edition 2003-08-04 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 8/4/03.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
20571 Version
Wired Communications
20570 Version
DELIC-LC DELIC-PB Embedded Line Port Interface Controller
20570 Preliminary Revision History: Previous Version: Page
2003-08-04 2000-08-22
Subjects (major changes since last revision) Trademarks changed
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com Note: OCEM® OakDSPCore® (OAK®) registered trademarks ParthusCeva, Inc.
20570 20571
Table Contents 1.4.1 1.4.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.4 3.2.4.1 3.2.4.2 3.3.1 3.4.1 3.4.2 3.4.3 3.4.4 3.5.1 3.5.2 4.2.1 4.2.2
Data Sheet
Page
Introduction DELIC-LC Features DELIC-PB Features Logic Symbol Typical Applications Applications DELIC-LC Applications DELIC-PB Descriptions Diagram DELIC-LC Diagram DELIC-PB Definitions Functions DELIC-LC Definitions Functions DELIC-PB Strap Definitions Interface Description Overview Interfaces IOM-2000 Interface Overview IOM-2000 Frame Structure Data Interface Command Status Interface State Machine INFO Structure Interface Mode State Diagram State Machine LT-S Mode LT-T Mode IOM®-2 Interface Signals Channels Interface Intel/Infineon Motorola Mode De-multiplexed Multiplexed Mode Non-DMA Mode DELIC External Interrupts JTAG Test Interface Boundary Scan Test Controller Functional Description Functional Overview Block Diagram IOM-2000 Transceiver Unit TRANSIU Overview Features TRANSIU Initialization
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Table Contents 4.2.3 4.2.4 4.2.4.1 4.2.4.2 4.2.4.3 4.2.4.4 4.2.5 4.2.5.1 4.2.5.2 4.2.5.3 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.2.6.4 4.2.7 4.2.7.1 4.2.7.2 4.2.7.3 4.2.8 4.2.9 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.1.4 4.4.1.5 4.4.1.6 4.4.1.7 Page
Initialization Mode Control Framing Bits IOM-2000 Framing (F-Bit) Multiframing Bits Fa/N DC-Balancing (L-Bit) Mode Control Framing Bits IOM-2000 Framing (LF-Bit) Multiframing (M-Bit) DC-Balancing IOM-2000 Command Status Interface Initialization Mode Command Bits Operational Mode Command/Status Bits Command/Status Transmission Command Status format Data IOM-2000 Data Interface Mode Scrambler/Descrambler Mode DECT Synchronization Interface Test Loop IOM-2 Unit IOMU Overview Features IOMU Functional Operational Description Frame-Wise Buffer Swapping I-buffer Logical Structure Access D-Buffer IOM-2 Interface Data Rate Modes IOMU Serial Data Processing IOMU Parallel Data Processing IOM-2 Push-Pull Open-Drain Modes Support DRDY Signal from QUAT-S Unit PCMU Functional Operational Description Frame-Wise Buffer Swapping Inaccessible Buffer (I-buffer) Accessible Buffer (D-Buffer) PCMU Interface Data Rate Modes PCMU Serial Data Processing PCMU Parallel Data Processing PCMU Tri-state Control Logic A-law/µ-law Conversion Unit
Data Sheet
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Table Contents 4.6.1 4.6.2 4.6.3 4.6.4 4.6.4.1 4.6.4.2 4.6.4.3 4.6.4.4 4.6.4.5 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.5.1 4.7.5.2 4.7.6 4.7.7 4.7.8 4.7.9 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.9.1 4.9.2 4.9.3 4.10 4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 4.10.6 4.10.7 Page
HDLC Unit HDLC Overview Functionality HDLCU Unit Overview HDLCU Operation Initialization HDLCU Transmitting Message Ending Transmission Aborting Transmission Access HDLCU Buffers GHDLC Unit GHDLC Overview GHDLC Channel External Configurations GHDLC General Modes GHDLC Protocol Features External Configuration Handshaking Mode External Tri-State Point-to-Multi-Point Mode Arbitration GHDLCs Collision GHDLC Memory Allocation GHDLC Interrupts GHDLC Possible Data Rates DELIC-PB GHDLC Using external Controller Control Unit General Address Decoding Interrupt Handling Time Statistics Data Program Arbitration Boot Support Reset Execution Boot Strap Setting General Mailbox Overview Mailbox Mailbox Mailbox (DELIC-PB only). Handshake Intel Infineon mode Motorola mode Memory Memory Flyby modes Mode. Transmit Mailbox Receive Mailbox FIFOs access
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Data Sheet
20570 20571
Table Contents 4.11 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 4.11.7 4.11.8 5.1.1 5.1.2 5.1.3 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.1.6 6.2.1.7 6.2.1.8 6.2.1.9 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.4 6.2.2.5 6.2.3 6.2.3.1 6.2.3.2 6.2.3.3 6.2.3.4 6.2.4 6.2.4.1
Data Sheet
Page
Clock Generator Overview Clock Selection Master/Slave Mode Clocks Selection DELIC Clock System Synchronization IOM-2 Clock Selection IOM-2000 Clock Selection REFCLK Configuration GHDLC Clock Selection DELIC Memory Structure Address Space Register Address Space Program Address Space Data Address Space Address Space Register Description Register Detailed Register Description TRANSIU Register Description TRANSIU IOM-2000 Configuration Register TRANSIU Channel Configuration Registers Command Registers (VIPCMR0, VIPCMR1, VIPCMR2) Status Registers TRANSIU Initialization Channel Command Register TRANSIU Initialization Channel Status Register (TICSTR) Test Loop Register Scrambler Mode Register Scrambler Status Register IOMU Register Description IOMU Control Register IOMU Status Register IOMU Tri-State Control Register IOMU DRDY Register IOMU Data Prefix Register PCMU Register Description PCMU Command Register PCMU Status Register PCMU Tri-state Control Registers PCMU Data Prefix Register A-/µ-law Unit Register Description A/µ-law Unit Control Register
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Table Contents 6.2.4.2 6.2.4.3 6.2.5 6.2.5.1 6.2.5.2 6.2.5.3 6.2.5.4 6.2.6 6.2.6.1 6.2.6.2 6.2.6.3 6.2.6.4 6.2.6.5 6.2.6.6 6.2.6.7 6.2.6.8 6.2.6.9 6.2.6.10 6.2.6.11 6.2.6.12 6.2.6.13 6.2.6.14 6.2.6.15 6.2.7 6.2.7.1 6.2.7.2 6.2.7.3 6.2.7.4 6.2.8 6.2.8.1 6.2.8.2 6.2.8.3 6.2.9 6.2.9.1 6.2.9.2 6.2.9.3 6.2.9.4 6.2.9.5 6.2.9.6 6.2.9.7 6.2.9.8 6.2.10
Data Sheet
Page
A/µ-law Input Register A/µ-law Output Register HDLCU Registers Description HDLCU Control Register HDLCU Status Register Channel Command Vector Channel Status Vector GHDLC Register Description GHDLC Test/ Normal Mode Register GHDLC Channel Mode Register GHDLC Interrupt Register GHDLC Interrupt Control Register GHDLC Receive Channel Status Registers GHDLC Receive Data Status GHDLC Mode Registers GHDLC Channel Transmit Command Registers ASYNC Control Register LCLK0 Control Register LCLK1 Control Register LCLK2 Control Register LCLK3 Control Register Muxes Control Register GHDLCU Frame Frequency Register Description Interrupt Mask Register Status Event Register Statistics Counter Register Statistics Register Configuration Registers Interface Configuration Register Device Version Register Interrupt Vector Register Mailbox Registers Description Command Register Mailbox Busy Register Mailbox Generic Data Register Mailbox (General Mailbox) Data Registers Command Register Mailbox Busy Register Mailbox Generic Data Register Mailbox (General Mailbox) Data Registers Mailbox Registers Description
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Table Contents 6.2.10.1 6.2.10.2 6.2.10.3 6.2.11 6.2.11.1 6.2.11.2 6.2.11.3 6.2.11.4 6.2.11.5 6.2.11.6 6.2.11.7 6.2.11.8 6.2.11.9 6.2.11.10 6.2.11.11 6.2.11.12 8.6.1 8.6.1.1 8.6.1.2 8.6.2 8.6.2.1 8.6.2.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 Page
Mailbox Transmit Counter Register Mailbox Receive Counter Register Mailbox Interrupt Status Register Clock Generator Register Description Control Register Control Register CLKOUT Control Register DCXO Reference Clock Select Register REFCLK Control Register DCL_2000 Control Register Control Register Control Register L1_CLK Control Register Sync Register Real-time Counter Register Strap Status Register
Package Outlines Electrical Characteristics Timing Diagrams Absolute Maximum Ratings Operating Range Characteristics Capacitances Recommended 16.384 Crystal Parameters Characteristics Access Timing Access Timing Motorola Mode Access Timing Intel/Infineon Mode Access Timing Access Timing Motorola mode Access Timing Intel/Infineon Mode Interrupt Acknowledge Cycle Timing IOM-2 Interface Timing Interface Timing IOM-2000 Interface Timing LNC0.3 (Local Network Controller) Interface Timing JTAG Emulation Interface Timing
Data Sheet
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Table Contents Page
Application Hints DELIC Connection External Microprocessors DELIC Worksheets Output Driver Anomaly
Glossary
Data Sheet
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Data Sheet
Page
Block Diagram DELIC-LC Block Diagram DELIC-PB Logic Symbol DELIC-LC Line Cards Upn). DELIC-LC/PB Line Card Subscribers DELIC-PB Analog Line Card Subscribers DELIC-PB Small DELIC-PB Port SDSL Line Card Configuration DELIC-LC Configuration DELIC-PB Overview IOM-2000 Interface Structure (Example with VIP) IOM-2000 Data Sequence with Channels) IOM-2000 Data Order VIPs with Channels) IOM-2000 CMD/STAT Handling with Channels) IOM-2000 Command/Status Sequence VIPs with Channels) State Diagram State Diagram LT-S Mode LT-T Mode State Diagram (Conditional Unconditional States) IOM®-2 Interface Digital Line card Mode. DELIC Multiplexed De-multiplexed Mode Block Diagram Channel Assignment. IOMU Integration DELIC IOM-2 Interface Timing Single/Double Clock Mode IOM-2 Interface Open-Drain Mode IOM-2 Interface Push-Pull Mode DRDY Signal Behavior. DRDY Sampling Timing PCMU Integration DELIC IOM-2 Interface Timing Single/Double Clock Mode HDLC Data Flow Receive Direction HDLCU General Block Diagram Data Processing GHDLC GHDLC Interface Lines GHDLC Receive Transmit Buffer Structure Statistics Registers DMA-timing TX-direction Infineon/ Intel mode DMA-timing RX-direction Infineon/ Intel mode DELIC Clock Generator TRANSIU Buffer Addresses. write-transaction timing Motorola mode read-transaction timing Motorola mode.
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Page
write-transaction Timing Intel/Infineon Mode read-transaction Timing Intel/Infineon Mode Write Cycle Motorola Mode Read Cycle Motorola Mode Write Cycle Intel/Infineon Demultiplexed Mode Read Cycle Intel/Infineon Demultiplexed Mode Write Cycle Intel/Infineon Multiplexed Mode Read Cycle Intel/Infineon Multiplexed Mode Interrupt Acknowledge Cycle Timing Motorola mode. Interrupt Acknowledge Cycle Timing Intel/Infineon mode IREQ Deactivation Timing IOM-2 Interface Timing DRDY Timing Timing IOM-2 Timing IOM-2 Timing Slave Mode(Input clocks) Timing Master Mode Interface Timing Parameters Timing Input Mode IOM-2000 Interface Timing Timing IOM-2000 LNC0.3 (Local Network Controller) Interface Timing LCLK0.3 Timing Output mode. LCLK0.3 Timing Input mode Test-interface (Boundary scan) Timing Reset Indication Timing CLOCKOUT Timing L1_CLK Timing XCLK Timing REFCLK Timing DELIC Connection Intel 80386EX (Demuxed Configuration) DELIC Connection Infineon C165 (Demuxed Configuration). DELIC-LC unit mode ports with MBit/s) Command/ Indication handshake general mailbox Behavior Output Driver last Behavior Output Driver last
Data Sheet
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List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Data Sheet
Page
IOM®-2 Interface Pins (DELIC-LC) IOM-2000 Interface Port (DELIC-LC) Port (DELIC-LC) Microprocessor Interface Pins (DELIC-LC). Interface Ports Ports (DELIC-LC) Clock Generator Pins (DELIC-LC) (additionally IOM/PCM clocks) Power Supply Pins (DELIC-LC) JTAG Emulation Interface Pins (DELIC-LC) Test Interface Pins (DELIC-LC) IOM®-2 Interface Pins (DELIC-PB) IOM-2000 Interface Port (DELIC-PB) Port (DELIC-PB) Microprocessor Interface Pins (DELIC-PB) Interface Ports Ports (DELIC-PB) Clock Generator Pins (DELIC-PB) (additionally IOM/PCM clocks) Power Supply Pins (DELIC-PB) JTAG Emulation Interface Pins (DELIC-PB) Test Interface Pins (DELIC-PB) Strap Pins (Evaluated During Reset) Control Bits Mode Line Control Bits Mode Line INFO Structure Interface State Machine Codes LT-S State Machine Codes LT-T Mode State Machine Codes (Conditional States) Controller Instruction Codes Differences between DELIC-LC DELIC-PB Mode Multiframe Positions. I-Buffer Logical Memory Mapping D-Buffer Address Space Frequency Different IOM-2 Modes. I-Buffer Logical Memory Mapping Input Buffers. I-Buffer Logical Memory Mapping Output Buffers Access D-Buffer Input Blocks Access D-Buffer Output Blocks Mode MBit/s) Mode 4MBit/s) MBit/s) MBit/s) (1st Half) Mode MBit/s) (2nd Half) Mode GHDLCU Receive Buffer Configuration Interrupt
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List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Data Sheet
Page
Overview Clock Signals Registers Address Space Program address space Occupied Data Address space memory mapped registers address space Address Space Table TRANSIU Register Scrambler Register IOMU Register PCMU Register A-/µ-law Unit Register HDLCU Register GHDLC Register Register Configuration Register General Mailbox Register Mailbox Register Clock Generator Register Available ISDN Modes each Channel Tristate Control Assignment IOM-2 Time Slots. behavior during transactions Normal Fly-By mode. .232 Transaction timing Motorola Mode behavior during Transactions Normal Fly-By Modes .236 Transaction Timing Intel/Infineon Mode Timing Write Cycle Motorola Mode Timing Read Cycle Motorola Mode Timing Write Cycle Intel/Infineon Demultiplexed Mode Timing Read Cycle Intel/Infineon Demultiplexed Mode Timing Write Cycle Intel/Infineon Multiplexed Mode Timing Read Cycle Intel/Infineon Multiplexed Mode Interrupt Acknowledge Cycle Timing IOM-2 Interface Timing (IOM-2 Data Clock) Timing (IOM-2 IOM-2000 Frame-Sync) Timing Interface Timing (PCM Data Clock) timing Master mode (output mode) Timing Input mode IOM-2000 Interface Timing DCL_2000 (IOM-2000 Data Clock) Timing LNC0.3 Interface Timing
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List Tables Table Table Table Table Table Table Table Table Table Page
LCLK0.3 Timing Output mode. LCLK0.3 Timing Input mode CLK_DSP Input Clock Timing Test Interface Timing Reset RESIND (Reset Indication) timing CLOCKOUT Timing L1_CLK Timing XCLK Timing REFCLK Timing
Data Sheet
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Preliminary
Preface
This document provides reference information DELIC-PB version V2.3. Organization this Document This Data Sheet divided into chapters appendices. organized follows: Chapter Introduction Gives general description product family, lists features, presents some typical applications. Chapter Descriptions Lists locations with associated signals, categorizes signals according function, describes signals. Chapter Interface Description Describes DELIC external interfaces. Chapter Functional Description Describes features main functional blocks. Chapter DELIC Memory Structure Containes memory organisation OAK®. Chapter Register Description Containes detailed register description. Chapter Package Outlines Chapter Electrical Characteristics Timing Diagrams Containes specification. Contains specification. Chapter Application Hints Provides e.g. worksheet Chapter Glossary Chapter Index Your Comments welcome your comments this document continuously aiming improving documentation. Please send your remarks suggestions e-mail sc.docu_comments@infineon.com Please provide subject your e-mail: device name (DELIC-LC/ -PB), device number (PEB 20570/ 20571), device version (Version 2.3), body your e-mail: document type (Data Sheet), issue date (2003-08-04) document revision number 3.1).
Data Sheet
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Preliminary Introduction
Introduction
DELIC chipset realizes multiple ISDN interfaces together with controller functionality typically needed Central Office systems. This functionality comprises voice channel handling, signaling control, layer-1 control, even signal processing tasks. Moreover provides programmable master/slave clock generator with PLLs, universal interface interface. controller part, DELIC, available different versions: DELIC-LC (PEB 20570) line card controller providing voice channel switching, multiple HDLC layer-1 control three VIPs ISDN channels). Other transceiver analog digital channels) additionally connected IOM-2/GCI interface. DELIC-PB (PEB 20571) additionally provides programmable telecom including program data RAM. This used layer-1 control, protocol support signal processing. flexibility gained programmability allows Infineon offer different application specific solutions with same silicon just software configuration. configuration tool assists user finding valid system configuration. Even more customer specific DSP-routines integrated with assistance Infineon. transceiver part, VIP, available different versions: 20590 first channel) ISDN transceiver that implements multiple interfaces within device. user decide programming which mode desired channel shall work. total channels provided layer-1 subscriber trunk line characteristic. programmed DELIC IOM-2000 interface. VIP's eight channels programmable following maximum partitioning between channels: Max. number Channels
VIP-8 20591 Additionally features VIP, VIP-8 allows combination interface (i.e. each channels programmed mode)
Data Sheet
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Preliminary Block diagrams: Introduction
DELIC-LC
IOM-2 Interface
IOM-2
2000
IOM-2000 Interface
HDLC Controllers
Signaling Controller
Clocks
Mailbox
JTAG
Interface
DELIC-LC-PB1.vsd
Figure
Block Diagram DELIC-LC
DELIC-PB
IOM-2 Interface
IOM-2
Program
2000
Voice handling
Data
IOM-2000 Interface
HDLC Controllers
Async/Sync Controller
Clocks
Mailbox Mailbox
JTAG
Interface
Emulation Interface
Figure
Block Diagram DELIC-PB
Data Sheet
Serial Port/ I/O-ports
DELIC-LC-PB.vsd
Switch
Interface
Serial Port/ I/O-ports
Switch
Interface
2003-08-04
Preliminary
Embedded Line Port Interface Controller DELIC-LC DELIC-PB
20570 20571
Version
DELIC-LC Features
DELIC-LC optimized line card applications: IOM-2000 interface supporting three VIPs i.e. ISDN channels IOM-2 (GCI) ports (configurable ports) supporting ISDN channels analog subscribers Four ports with 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s Switching matrix (8-bit switching) HDLC controllers assignable B-channel kbit/s kbit/s) Serial communication controller: high-speed signaling channel 2.048 Mbit/s General purpose ports Standard multiplexed de-multiplexed interface: Infineon, Intel, Motorola Programmable based Master/Slave clock generator, providing system clocks from single 16.384 crystal source JTAG compliant test interface single power supply, tolerant inputs
DELIC-PB Features
Compared DELIC-LC, having fixed functionality, DELIC-PB provides high degree flexibility terms selected number ports channels). Additionally features computing power typical DSP-oriented tasks like conferencing, DTMF etc. Microsoft Windows based configuration tool, Configurator, enables generate application specific functionality. features mainly determined firmware integrated telecom DSP.
Type 20570
Data Sheet
Package P-TQFP-100-3
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20570 20571
Preliminary List maximum available features: IOM-2000 interface supporting three VIPs i.e. ISDN channels Support DASL mode IOM-2 (GCI) ports (also configurable ports) supporting ISDN channels analog subscribers four ports with 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s Switching matrix (switching 4-/8- time slots) HDLC controllers assignable B-channel kbit/s kbit/s) serial communication controllers: them with 8.192 Mbit/s data rate General purpose ports DECT synchronization support Standard multiplexed de-multiplexed interface: Infineon, Intel, Motorola Dedicated support mailbox DMA-channels Integrated core OAK+ MIPS layer control, signalling DSPalgorithms) kWord on-chip program memory kWord on-chip data memory kWord work load measurement run-time statistics, alive indication chip debugging unit Serial program debugging interface connected JTAG port A-/µ-law conversion unit Programmable based Master/Slave clock generator, providing system clocks from single 16.384 crystal source JTAG compliant test interface single power supply, compatible inputs Note: each feature consumes system resources (DSP-MIPS, memory, port pins), maximum available number supported interfaces HDLC channels limited totally available resources. System Configurator tool (see DELIC Software User's Manual) helps determine valid configuration. Introduction
Data Sheet
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Preliminary Introduction
Logic Symbol
P-TQFP-100-3
Power Supply
IOM-2 Interfaces
IOM-2000/ Interface
DELIC-LC PEB20570 DELIC-PB
20571
PCM/ Interfaces
Clock Signals
Signaling Interface
P-TQFP-100-3
Interface
JTAG Interface
Test Interface
DELIC-logic-DS.vsd
Figure
Logic Symbol
Data Sheet
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Preliminary Introduction
1.4.1
Typical Applications Applications DELIC-LC
following figures show example configurations DELIC-LC Line card applications different ISDN interface standards. Figure three transceiver connected DELIC-LC IOM2000 interface, whereas Figure IOM-2 (GCI) interface used.
20590
IOM-2000 DELIC-LC
20570 20590 Signaling 2.048 Mbit/s
20590 Infineon C166
Memory
Figure
DELIC-LC Line Cards Upn)
Data Sheet
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20570 20571
Preliminary Introduction
HYBRID HYBRID
AFE/
IOM-2
DELIC-LC/PB 20570 (PEB 20571)
HYBRID HYBRID
AFE/
HYBRID
AFE/
HYBRID
HYBRID
Signaling
AFE/
HYBRID
Memory
Infineon C166
Figure
DELIC-LC/PB Line Card Subscribers
Note: this application DELIC-PB also meaningful.
1.4.2
Applications DELIC-PB
HV-SLIC HV-SLIC
SLICOFI-2
IOM-2
SLICOFI-2 DELIC-PB
IOM-2
HV-SLIC HV-SLIC
HV-SLIC
20571
SLICOFI-2
HV-SLIC
HV-SLIC
SLICOFI-2
HV-SLIC
Signaling
Memory
Infineon C166
Figure
DELIC-PB Analog Line Card Subscribers
Data Sheet
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Preliminary Introduction
HV-SLIC HV-SLIC
SLICOFI-2
IOM-2
HV-SLIC HV-SLIC
SLICOFI-2 DELIC-PB 20571 20590
IOM-2000
Central Office
Mbit/s service
Power Supply
Memory
Infineon C166
Figure
DELIC-PB Small
MBit/s SOCRATES DELIC-PB 20571 8.192 Mbit/s IOM-2 4.096 Mbit/s
SOCRATES
ASIC
Voice
REFCLK 8.192 Mbit/s 8.192 Mbit/s Data
SOCRATES
SOCRATES
C165
Memory
Figure
DELIC-PB Port SDSL Line Card
Data Sheet
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Preliminary Descriptions
Descriptions
Diagram DELIC-LC
(top view) P-TQFP-100-3
DCL_2000/ LRTS1
LTSC0/ LRTS0
LCxD0/LCTS0
TRST
TDI/ SCANEN
STAT/ LCTS1
RxD2/ LCTS2
RxD3/ LCTS3
CMD/ LCLK1
RxD1/LRxD3
DSP_STOP
LTxD1
LRxD1
LCLK0
LRxD0
LTxD0
JTCK
RxD0/LRxD2 TSC0/ LRTS2 TXD0/LTxD2 TSC1/ LRTS3 TxD1/LTxD3 TSC2 TxD2/LCLK2 TSC3 TxD3/LCLK3 RESIND REFCLK VSSA CLK16-XI CLK16-XO VDDA VSSA VSSA VDDA VDDA
DELIC-LC 20570
1718 2122 2425
SCANMO L1_CLK DRDY RESET CLKOUT
CLK_DSP DSP_FRQ
DCXOPD
DREQT
MODE
DREQR
XCLK
IACK
IREQ
Figure
Data Sheet
Configuration DELIC-LC
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Preliminary Descriptions
Diagram DELIC-PB
(top view) P-TQFP-100-3
DCL_2000/ LTSC1/LRTS1 STAT/ LCxD1/LCTS1 RxD3/ LCxD3/LCTS3 RxD2/ LCxD2/LCTS2
LTSC0/ LRTS0
LCxD0/LCTS0
TRST
TDI/ SCANEN
CMD/ LCLK1
RxD1/LRxD3
DSP_STOP
LTxD1
LRxD1
LCLK0
LRxD0
LTxD0
JTCK
RxD0/LRxD2 TSC0/ LTSC2/LRTS2 TXD0/LTxD2 TSC1/ LTSC3/LRTS3 TxD1/LTxD3 TSC2 TxD2/LCLK2 TSC3 TxD3/LCLK3 RESIND REFCLK VSSA CLK16-XI CLK16-XO VDDA VSSA VSSA VDDA VDDA
DELIC-PB 20571
1718 2122 2425
SCANMO L1_CLK DRDY A4/DACK RESET CLKOUT
CLK_DSP DSP_FRQ
DCXOPD
DREQT
MODE
XCLK
IREQ
DREQR
IACK
Figure
Configuration DELIC-PB
Data Sheet
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Preliminary Descriptions
Definitions Functions DELIC-LC
Note: column "During Reset" refers time period that starts with activation RESET input ends with deactivation RESIND output. During this period, DELIC strap pins (refer Table driven external pulldown pull-up resistors define DELIC configuration. external pull-down pull-up resistors connected strap pins, value each strap during reset will determined internal pull-up pull-down resistor, according default strap value each pin. user must ensure that connected circuits influence sampling strap pins during reset. column "After Reset" describes behavior every pin, from deactivation RESIND output until DELIC registers programmed.
Data Sheet
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Preliminary Table IOM®-2 Interface Pins (DELIC-LC) During Out(O) Reset After Reset Function Frame Synchronization Clock kHz) Used both IOM-2 IOM2000 interface IOM-2 Data Clock 2.048 4.096 Descriptions
Symbol
TESTStrap (3), (pull-up), refer Table High High
DRDY
O(OD) O(OD)
High Data Downstream IOM-2 Interface Channel0 High Data Downstream IOM-2 Interface Channel1 Data Upstream IOM-2 Interface Channel Data Upstream IOM-2 Interface Channel Channel Ready Stop/Go information D-channel control interface LT-T. Affects only IOM-2 port DRDY means DRDY means STOP DRDY used, this connected 'High' level
Data Sheet
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Preliminary Table IOM-2000 Interface Port (DELIC-LC) During After Reset Reset Function IOM-2000 Data Clock 3.072, 6.144 12.288 'request-to-send' functionality (Async mode) High High Data Transmit Transmits IOM-2000 data Transmit Serial Data Port (Async mode). Data Receive Receives IOM-2000 data from Receive Serial Data Port (Async mode). High High IOM-2000 Command Transmits DELIC commands VIP. Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 IOM-2000 Status Receives status information from VIP. LNC1 Clear Send 'clear-to-send' functionality (Async mode) Descriptions
Symbol
DCL_2000
LRTS1
LTxD1
(OD)
LRxD1
LCLK1
STAT
LCTS1
Data Sheet
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Preliminary Table Port (DELIC-LC) After Reset Function Receive Serial Data Port (HDLC Async mode). Descriptions
Symbol During Reset LRxD0 LTxD0 (OD) High
High Transmit Serial Data Port (HDLC Async mode). LNC0 Tristate Control Request Send modes selectable: output valid (HDLC mode). Supplies control signal external driver. ('low' when corresponding TxD-output valid). 'request-to-send' functionality (Async mode) LNC0 Collision Data Clear Send modes selectable: Collision Data (HDLC Mode). 'clear-to-send' functionality (Async mode)
LTSC0 LRTS0
PLLH Bypass" strap. Pull-up refer Page
LCxD0 LCTS0
LCLK0
Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384
Data Sheet
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Preliminary Table Microprocessor Interface Pins (DELIC-LC) After Reset Function Data When operated address/data multiplex mode, this used multiplexed bus. Address pins externally connected bus. Descriptions
Symbol During Reset
direction these pins depends value following pins: RD/DS, MODE
Address (bits When operated address/data multiplex mode, this used multiplexed bus. Data pins externally connected bus.
DREQR
CLOCK MASTER Strap (pulldown), refer Table EMULL ATION BOOT Strap (pulldown), refer Table
Strap
DREQT
Strap
Chip Select "low" this line selects registers read/write operations. Write (Intel/Infineon Mode) Indicates write access. Read/Write (Motorola Mode) Indicates direction data transfer
Data Sheet
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Preliminary Table Descriptions Microprocessor Interface Pins (DELIC-LC) (cont'd) After Reset Function Read (Intel/Infineon Mode) Indicates read access. Data Strobe (Motorola Mode) During read cycle, indicates that DELIC should place valid data bus. During write access, indicates that valid data bus. Address Latch Enable Controls on-chip address latch multiplexed mode. While 'high', latch transparent. falling edge latches current address. also evaluated determine mode ('low'=multiplexed, 'high'=demultiplexed) Mode Selection Selects mode ('low'=Intel/Infineon, 'high'=Motorola)
Symbol During Reset
MODE
IREQ
(OD)
High (OD)
High Interrupt Request programmable (OD) push/pull (active high low) opendrain. This signal activated when DELIC requests interrupt. When operated open drain mode, multiple interrupt sources connected. Interrupt Acknowledge System Reset DELIC forced into reset state. Reset Indication Indicates that DELIC executing reset. DELIC remains reset state least after termination RESET pulse.
IACK RESET
RESIND
Data Sheet
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Preliminary Table Descriptions Interface Ports Ports (DELIC-LC) After Reset Function Frame Synchronization Clock. kHz/4 when input when output. Note: When configured input, configuration restricted 2.048 input. Data Clock (input output) 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 Receive Data Port Receive Serial Data Port (Async mode) High High Transmit Data Port Transmit Serial Data Port Async mode) Reset Counter Bypass" strap pull-up refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). LNC2 Request Send 'request-to-send' functionality (Async mode) RxD2 LCTS2 TxD2 LCLK2 weak weak Receive Data Port LNC2 'clear-to-send' functionality (Async mode) Transmit Data Port External Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384
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Symbol During Reset
RxD0 LRxD2
O(OD)
TxD0 LTxD2
TSC0
LRTS2
Data Sheet
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Preliminary Table Descriptions Interface Ports Ports (DELIC-LC) (cont'd) After Reset Function Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). Receive Data Port Receive Serial Data Port (Async mode) High High Transmit Data Port Transmit Serial Data Port (Async mode) PowerDown strap pull-up refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). LNC3 Request Send 'request-to-send' functionality (Async mode) Receive Data Port LNC3 'clear-to-send' functionality (Async mode) weak weak Transmit Data Port External Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 TEST(1) strap refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding output valid).
Symbol During Reset TSC2
TEST(1) strap refer Page
RxD1 LRxD3
O(OD)
TxD1 LTxD3
TSC1
LRTS3
RxD3 LCTS3
TxD3 LCLK3
TSC3
Data Sheet
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Preliminary Table Descriptions Clock Generator Pins (DELIC-LC) (additionally IOM/PCM clocks) During After Function Reset Reset 16.384 External Crystal Input 16.384 External Crystal Output DCXO Power Down Bypass Activating this input powers down on-chip DCXO PLL. input CLK16-XI used directly internal 16.384 clock, oscillator shaper bypassed. Required testing; during normal operation this input should permanently (`0'). External Clock Provides clock other than 61.44 from external oscillator. Operational Frequency Selection (e.g. test purpose) clocked internally 61.44 clock driven CLK_DSP input Layer-1 Clock 15.36 7.68 General Purpose Clock Output 2.048 MHz, 4.096 MHz, 8.192 MHz, 15.36 16.384 External Reference Clock Synchronization input from Layer-1 kHz, 1.536 MHz) This connected VIP's REFCLK output 1.536 MHz. Reference Clock Input: Synchronization DELIC clock system Output: Used drive fraction XCLK system clock master programmable)
Symbol CLK16-XI CLK16-XO DCXOPD
CLK_DSP
DSP_FRQ
L1_CLK CLKOUT
XCLK
REFCLK
Data Sheet
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Preliminary Table Power Supply Pins (DELIC-LC) Symbol During After Reset Reset Function Power Supply Used core logic interfaces pure environment Descriptions
Digital Ground
VDDA
Power Supply Analog Logic Used DCXO Analog Ground Used DCXO
VSSA
Data Sheet
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Preliminary Table Symbol JTCK JTAG Emulation Interface Pins (DELIC-LC) During After Reset Reset Function Descriptions
Used boundary scan according IEEE 1149.1 JTAG Test Clock Provides clock JTAG test logic. Used also serial emulation interface. Test Mode Select transition this required step through controller state machine. Test Data Input appropriate controller state test data instruction shifted this line. Used also serial emulation interface. This must driven board during reset operation ensure functioning DELIC SCAN Enable When both SCANMO SCANEN asserted, full-scan tests DELIC activated. used during normal operation. Test Data Output appropriate controller state test data instruction shifted this line. Used also serial emulation interface. Test Reset Provides asynchronous reset controller state machine. Stop Stops external logic during breakpoints. Activated when stop issued.
SCANEN
TRST
DSP_STOP
BOOT Strap (pulldown) refer Table
Data Sheet
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Preliminary Table Test Interface Pins (DELIC-LC) During Reset After Reset Function Scan Mode driven during device tests, input used enable full scan tests DELIC. SCANMO should tied during normal operation. Descriptions
Symbol SCANMO
Data Sheet
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Preliminary Descriptions
Definitions Functions DELIC-PB
Note: column "During Reset" refers time period that starts with activation RESET input ends with deactivation RESIND output. During this period, DELIC strap pins (refer Table driven external pulldown pull-up resistors define DELIC configuration. external pull-down pull-up resistors connected strap pins, value each strap during reset will determined internal pull-up pull-down resistor, according default strap value each pin. user must ensure that connected circuits influence sampling strap pins during reset. column "After Reset" describes behavior every pin, from deactivation RESIND output until DELIC registers programmed.
Data Sheet
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Preliminary Table IOM®-2 Interface Pins (DELIC-PB) During Out(O) Reset After Reset Function Frame Synchronization Clock kHz) Used both IOM-2 IOM2000 interface IOM-2 Data Clock 2.048 4.096 Descriptions
Symbol
TESTStrap (3), (pull-up), refer Table High High
DRDY
O(OD) O(OD)
High Data Downstream IOM-2 Interface Channel0 High Data Downstream IOM-2 Interface Channel1 Data Upstream IOM-2 Interface Channel Data Upstream IOM-2 Interface Channel Channel Ready Stop/Go information D-channel control interface LT-T. Affects only IOM-2 port DRDY means DRDY means STOP DRDY used, this connected 'High' level
Data Sheet
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Preliminary Table IOM-2000 Interface Port (DELIC-PB) During After Reset Reset Function IOM-2000 Data Clock 3.072, 6.144 12.288 LNC1 Tristate Control /Request Send modes selectable: output valid (HDLC mode). Supplies control signal external driver. ('low' when corresponding TxD-output valid). 'request-to-send' functionality (Async mode) High High Data Transmit Transmits IOM-2000 data Transmit Serial Data Port (HDLC Async mode). Data Receive Receives IOM-2000 data from Receive Serial Data Port (HDLC Async mode). High High IOM-2000 Command Transmits DELIC commands VIP. Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 IOM-2000 Status Receives status information from VIP. LNC1 Collision Data Clear Send Collision Data (HDLC Mode). 'clear-to-send' functionality (Async mode) Descriptions
Symbol
DCL_2000
LTSC1/ LRTS1
LTxD1
(OD)
LRxD1
LCLK1
STAT
LCxD1/ LCTS1
Data Sheet
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Preliminary Table Port (DELIC-PB) After Reset Function Receive Serial Data Port (HDLC Async mode). Descriptions
Symbol During Reset LRxD0 LTxD0 (OD) High
High Transmit Serial Data Port (HDLC Async mode). LNC0 Tristate Control Request Send modes selectable: output valid (HDLC mode). Supplies control signal external driver. ('low' when corresponding TxD-output valid). 'request-to-send' functionality (Async mode) LNC0 Collision Data Clear Send modes selectable: Collision Data (HDLC Mode). 'clear-to-send' functionality (Async mode)
LTSC0 LRTS0
PLLBypass" strap. pull-up refer Page
LCxD0 LCTS0
LCLK0
Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384
Data Sheet
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Preliminary Table Symbol DACK/ Microprocessor Interface Pins (DELIC-PB) During Reset After Reset Function Data When operated address/data multiplex mode, this used multiplexed bus. Address pins externally connected bus. Descriptions
direction these pins depends value following pins: RD/DS, MODE
Address (bits except When operated address/data multiplex mode, this used multiplexed bus. Data pins externally connected bus.
address bus/ Acknowledge non-DMA mode DACK/A4 input should connected address-bus. mode internally connected `0'. Request Receive Direction configured active high active (the default active high)
DREQR
CLOCK MASTER Strap (pulldown), refer Table EMULL ATION BOOT Strap (pulldown), refer Table
DREQT
Request Transmit Direction configured active high active (the default active high)
Data Sheet
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Preliminary Table Symbol Descriptions Microprocessor Interface Pins (DELIC-PB) (cont'd) During Reset After Reset Function Chip Select "low" this line selects registers read/write operations. Write (Intel/Infineon Mode) Indicates write access. Read/Write (Motorola Mode) Indicates direction data transfer Read (Intel/Infineon Mode) Indicates read access. Data Strobe (Motorola Mode) During read cycle, indicates that DELIC should place valid data bus. During write access, indicates that valid data bus. Address Latch Enable Controls on-chip address latch multiplexed mode. While 'high', latch transparent. falling edge latches current address. also evaluated determine mode ('low'=multiplexed, 'high'=demultiplexed) Mode Selection Selects mode ('low'=Intel/Infineon, 'high'=Motorola)
MODE
IREQ
(OD)
High (OD)
High Interrupt Request programmable (OD) push/pull (active high low) opendrain. This signal activated when DELIC requests interrupt. When operated open drain mode, multiple interrupt sources connected. Interrupt Acknowledge
IACK
Data Sheet
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Preliminary Table Symbol RESET Descriptions Microprocessor Interface Pins (DELIC-PB) (cont'd) During Reset After Reset Function System Reset DELIC forced into reset state. Reset Indication Indicates that DELIC executing reset. DELIC remains reset state least after termination RESET pulse.
RESIND
Data Sheet
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Preliminary Table Descriptions Interface Ports Ports (DELIC-PB) After Reset Function Frame Synchronization Clock. kHz/4 when input when output. Note: When configured input, configuration restricted 2.048 input. Data Clock (input output) 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 Receive Data Port Receive Serial Data Port (HDLC Async mode) High High Transmit Data Port Transmit Serial Data Port (HDLC Async mode) Reset Counter Bypass" strap pull-up refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). LNC2 Tristate Control Request Send modes selectable: output valid (HDLC mode). Supplies control signal external driver. ('low' when corresponding TxDoutput valid). 'request-to-send' functionality (Async mode)
Symbol During Reset
RxD0 LRxD2
O(OD)
TxD0 LTxD2
TSC0
LTSC2/ LRTS2
Data Sheet
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Preliminary Table Descriptions Interface Ports Ports (DELIC-PB) (cont'd) After Reset Function Receive Data Port LNC2 Collision Data modes selectable: Collision Data HDLC Mode). 'clear-to-send' functionality (Async mode) weak weak Transmit Data Port External Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 TEST(1) strap refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). Receive Data Port Receive Serial Data Port (HDLC Async mode) High High Transmit Data Port Transmit Serial Data Port (HDLC Async mode)
Symbol During Reset RxD2 LCxD2/ LCTS2
TxD2 LCLK2
TSC2
RxD1 LRxD3
O(OD)
TxD1 LTxD3
Data Sheet
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Preliminary Table Descriptions Interface Ports Ports (DELIC-PB) (cont'd) After Reset Function Tristate Control Port Supplies control signal external driver ('low' when corresponding TxDoutput valid). LNC3 Tristate Control Request Send modes selectable: output valid (HDLC mode). Supplies control signal external driver. ('low' when corresponding TxDoutput valid). 'request-to-send' functionality (Async mode) Receive Data Port LNC3 Collision Data modes selectable: Collision Data (HDLC Mode). 'clear-to-send' functionality (Async mode) weak weak Transmit Data Port External Clock Port When configured output driven following frequencies: 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 TEST(1) strap refer Page Tristate Control Port Supplies control signal external driver ('low' when corresponding output valid).
Symbol During Reset TSC1
LTSC3/ LRTS3
PowerDown strap pull-up refer Page
RxD3 LCxD3/ LCTS3
TxD3 LCLK3
TSC3
Data Sheet
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Preliminary Table Descriptions Clock Generator Pins (DELIC-PB) (additionally IOM/PCM clocks) During After Function Reset Reset 16.384 External Crystal Input 16.384 External Crystal Output DCXO Power Down Bypass Activating this input powers down on-chip DCXO PLL. input CLK16-XI used directly internal 16.384 clock, oscillator shaper bypassed. Required testing; during normal operation this input should permanently (`0'). External Clock Provides clock other than 61.44 from external oscillator. Operational Frequency Selection (e.g. test purpose) clocked internally 61.44 clock driven CLK_DSP input Layer-1 Clock 15.36 7.68 General Purpose Clock Output 2.048 MHz, 4.096 MHz, 8.192 MHz, 15.36 16.384 External Reference Clock Synchronization input from Layer-1 kHz, 1.536 MHz) This connected VIP's REFCLK output 1.536 MHz. Reference Clock Input: Synchronization DELIC clock system Output: Used drive fraction XCLK system clock master programmable)
Symbol CLK16-XI CLK16-XO DCXOPD
CLK_DSP
DSP_FRQ
L1_CLK CLKOUT
XCLK
REFCLK
Data Sheet
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Preliminary Table Power Supply Pins (DELIC-PB) During After Reset Reset Function Power Supply Used core logic interfaces pure environment Descriptions
Symbol
Digital Ground
VDDA
Power Supply Analog Logic Used DCXO Analog Ground Used DCXO
VSSA
Data Sheet
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Preliminary Table Symbol JTCK JTAG Emulation Interface Pins (DELIC-PB) During After Reset Reset Function Descriptions
Used boundary scan according IEEE 1149.1 JTAG Test Clock Provides clock JTAG test logic. Used also serial emulation interface. Test Mode Select transition this required step through controller state machine. Test Data Input appropriate controller state test data instruction shifted this line. Used also serial emulation interface. This must driven board should connected pullup during reset operation ensure functioning DELIC SCAN Enable When both SCANMO SCANEN asserted, full-scan tests DELIC activated. used during normal operation. Test Data Output appropriate controller state test data instruction shifted this line. Used also serial emulation interface. Test Reset Provides asynchronous reset controller state machine. Stop Stops external logic during breakpoints. Activated when stop issued.
SCANEN
TRST
DSP_STO
BOOT Strap (pulldown) refer Table
Data Sheet
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Preliminary Table Test Interface Pins (DELIC-PB) During Reset After Reset Function Scan Mode driven during device tests, input used enable full scan tests DELIC. SCANMO should tied during normal operation. Descriptions
Symbol SCANMO
Data Sheet
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Preliminary Descriptions
Table DREQR (11)
Strap Definitions
Strap Pins (Evaluated During Reset) Strap Name Strap Function CLOCK MASTER (default) Clock Slave used inputs. 2.048 Clock Master used outputs. 2.048
DSP_STOP BOOT (63)
(default) starts running from address FFFEH, executes boot routine. starts running directly from address 0000H. boot routine executed. Regular Work Mode
(40): TSC3 (83): TSC2 (81)
TEST(2) TEST(1) TEST(0)
111: (default)
Test mode Test mode Test mode Test mode Test mode undefined
DREQT (10)
EMULATION (default) After reset boot-routine loads program BOOT µP-interface (via general mail-box). After reset boot-routine loads program mail-box (via JTAG interface).
Data Sheet
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Preliminary Table LTSC (60) Strap Pins (Evaluated During Reset) (cont'd) BYPASS DSP_CLK input (the fall-back clock) used source clock division chain. (Only testing). Descriptions
(default) output used source clock division chain. TSC1 (79) TSC0 (77) POWER DOWN 1:(default) RESET COUNTER BYPASS powered-down. (for IDDQ tests) reset-counter bypassed, thus internal reset filtered reset. internal reset lasts cycles after deactivation RESET.
(default) internal reset lasts cycles after deactivation RESET Note: When strap pins driven externally during reset, they driven internal pull-ups/pull-downs. reduce power consumption, internal pull-up/ pull-down resistors connected only during activated RESET input. ensure default value straps, pins must driven during reset. case fixed external pull-up/pull-down, pull-up/pull-down resistance +/-10% recommended. Note: Because internal pull-ups weak recommended connect used strap during reset, external pull-up/ pull-down resistor, even it's supposed driven it's default strap-value.
Data Sheet
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Preliminary Interface Description
Interface Description
Overview Interfaces
DELIC provides following system interfaces: IOM-2000 Interface serial layer interface driving three VIP/ VIP8 (Versatile ISDN Port, 20590/ 20591). Each provides eight 2B+D ISDN channels, which programmed IOM-2000 mode mode. IOM-2 (GCI) Interface standard IOM-2 (GCI) ports with eight 2B+D ISDN channels each, data rate 2.048 Mbit/s. They combined 4.096 Mbit/s highway. Interface Four standard Master/Slave interfaces with time slots each, data rate 2.048 Mbit/s. They combined 4.096 Mbit/s highways 8.192 Mbit/s highway. Additionally, time slots time slots frame transmitted rate 16.384 Mbit/s. Serial Communication Interface (GHDLC) asynchronous serial port supporting HDLC formatted data frames data rate 8.192 Mbit/s. Microprocessor Interface standard 8-bit multiplexed/de-multiplexed interface, compatible Intel/Infineon (e.g. 80386EX, C166) Motorola (e.g. 68340, 801) systems. includes separate mailboxes, normal data transfer, fast transfers. JTAG Boundary Scan Test Interface DELIC provides standard test interface according IEEE 1149.1. 4-bit controller reset input. JTAG pins TDI, JTCK also used interface emulation.
Data Sheet
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Preliminary Interface Description
3.2.1
IOM-2000 Interface Overview
IOM-2000 interface represents concept connecting ISDN layer-1 devices DELIC. transceiver unit (TRANSIU) perform layer-1 protocol, which enables flexible efficient operation transceiver (VIP/ VIP8). VIP/ VIP8 supports types ISDN interfaces: 2-wire (ping-pong) interfaces 4-wire interfaces. detailed description please refer VIP/ VIP8 Data Sheet. IOM-2000 interface consists following signals: Frame Synchronization: IOM-2000 uses same IOM-2 ports. Data Interface: Data transmitted line from DELIC with DCL_2000 rising edge. Data received line from DELIC, sampled with DCL_2000 falling edge. Command/Status Interface: Configuration control information VIP's layer-1 transceivers exchanged STAT lines. Data/Command Clock: Data commands transmitted 3.072 MHz. When DELIC drives VIPs, transmission rate increased. Reference Clock: LT-T mode, provides reference clock synchronized exchange. LT-S mode, DELIC always clock master VIP. data ctrl data Data Transmit Receive mode f=3.072 kbit/s) Data Transmit Receive mode f=3.072 kbit/s) Channel_0 DCL_2000 STAT DELIC
20570 (PEB 20571)
S/T: UPN:
Channel_7
20590 (PEB 20591)
Figure
Data Sheet
Overview IOM-2000 Interface Structure (Example with VIP)
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Preliminary Interface Description
3.2.2 3.2.2.1
IOM-2000 Frame Structure Data Interface
ISDN line side VIP, data ternary coded. Since contains logic detect level signal, only data value transferred IOM-2000 DELIC. Mode mode, only data sent IOM-2000 data interface. Mode mode, data control information sent IOM-2000 data interface. Every data control associated with Thus, each line signal, bits transferred Bit0 assigned user data, bit1 carries control information. Table Control Bits Mode Line Logical received line interface Logical received line interface Received E-bit inverted transmitted D-bit (E=D) (LT-T only) F-bit (Framing) received; indicates start frame
ctrl (bit1) data (bit0) Function
Table
Control Bits Mode Line Logical transmitted line interface Logical transmitted line interface used F-bit (Framing) transmitted; indicates start frame
ctrl (bit1) data (bit0) Function
Note: 'data' always transmitted prior 'ctrl' DX/DR lines (refer Figure 12).
Data Sheet
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Preliminary Interface Description
F-bit
3.072
data ctrl bit0 bit0 (data) bit0 DX/DR bit0 (data) bit1 bit0 (ctrl) bit1 bit0 (ctrl) bit2 bit1 (data) bit2 bit1 (data) LT-S mode: mode: data
Ch1,3,5,7 mode (LT-S) Ch0,2,4,6 mode
last frame last LT-S frame
bit37 (ctrl)
Figure
IOM-2000 Data Sequence with Channels)
Note: Data transfer IOM-2000 interface always starts with (related channels), whereas STAT bits transfer always starts with (bit register registers follow Intel structure (LSB=20, MSB=231) Unused bits don't care ('x') order reception transmission each channel always channel channel freely programmable channel assignment multiple VIPs IOM-2000 (e.g., VIP_0, VIP_0, VIP_1, VIP_0,.) possible.
Data Sheet
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Preliminary Interface Description
F-bit bit0 Ch23 bit0 Ch24 bit0 DX/DR
12.288
used (don't care) Ch31 bit0 bit1 Ch23 bit1 Ch24 bit1 used (don't care) Ch31 bit1
bit37 (example channels mode) Ch23 bit37 Ch24 bit37 Ch31 bit37
used
Figure
IOM-2000 Data Order VIPs with Channels)
Receive Data Channel Shift receive direction (DR), data IOM-2000 channels (ch0.7 used, ch23 three VIPs used) shifted channels with respect transmitted data channels (DX), assuming start transmission bit0 with signal. DELIC transmitting ch0, while receiving same time, etc.
Data Sheet
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Preliminary Interface Description
3.2.2.2
Command Status Interface
STAT lines configuration control interface between DELIC VIP. streams partitioned into 32-bit words carrying information dedicated VIPs (CMD_0 STAT_0) followed information dedicated individual channels same (CMD_0_0 CMD_2_7 STAT_0_0 STAT_2_7). Note: opposed data, command status bits sent channel-wise, starting with channel_0. transmission clock same DR/DX data clock.
3.072 3x32-bit empty C_0C0 C_0C1 C_0C2 C_0C3 C_0C4 C_0C5 C_0C6 C_0C7
Command bits VIP_0
Commands bits VIP_0 channel_7 3x32-bit empty S_0C0 S_0C1 S_0C2 S_0C3 S_0C4 S_0C5 S_0C6 S_0C7
STAT
Status bits VIP_0
Status bits VIP_0 channel_7 Note: refers CMD_0, STAT_0 C_0C0 refers CMD_0_0, S_0C0 STAT_0_0
Figure
IOM-2000 CMD/STAT Handling with Channels)
Note: position each within IOM-2000 frame programmable pins (VIP_ADR0, VIP_ADR1) IOM-2000 channels 0.7, 8.15 16.23.
empty 32-bit words VIP_0 VIP_1 empty 32-bit words VIP_2 empty 32-bit words VIP_0 VIP_0 VIP_1 VIP_2 reserved
STAT
Figure
Data Sheet
IOM-2000 Command/Status Sequence VIPs with Channels)
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Preliminary Commands VIP_n (CMD_n, Initialization control information each sent DELIC following sequence every IOM-2000 line CMD_n bits VIP_n): Note: bits programmed Command register (VIPCMR0.2). CMD_n DELCH(2:0) EXREF REFSEL(2:0) RD_n PLLPPS SH_FSC DELRE WR_n Interface Description
Commands VIP_n, Channel_m (CMD_n_m, Initialization control information each channel sent DELIC following sequence every IOM-2000 line CMD_n_m bits VIP_n Channel_m): Note: bits except WR_ST, SMINI(2:0) MSYNC programmed TRANSIU Initialization Channel Command register (TICCR); bits WR_ST, SMINI(2:0) MSYNC reside TRANSIU data RAM. CMD_n_m AAC(1:0) MODE(2:0)
Data Sheet
SMINI(2:0) MSYNC EXLP PLLS DHEN PDOWN LOOP TX_EN PLLINT BBC(1:0) OWIN(2:0) MF_EN MOSEL(1:0)
WR_ST
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Preliminary Status from VIP_n Status information sent each following sequence STAT line STAT_n bits VIP_n): STAT_n DELAY(7:0) Note: Bits DELAY read from Status register (VIPSTR) TRANSIU. unused Status from VIP_n, Channel_m Status information sent each channel following sequence STAT line STAT_n_m bits VIP_n Channel_m): STAT_n_m MSYNC* FCV* FSYNC* SLIP FECV RxSTA(1:0) Interface Description
Note: Marked bits evaluated DELIC, only testing. Bits SLIP, FECV directly accessible TRANSIU receive data RAM. unused
Data Sheet 2000-08-22
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Preliminary Interface Description
3.2.3 3.2.3.1
State Machine
INFO Structure Interface
Signals controlling indicating internal state transceiver state machines called INFOs. Four different INFOs (INFO sent over interface, depending actual state (Synchronized, Activated, Pending Activation,.). When line deactivated, INFO (=no signal line) exchanged transceivers either line. When line activated, INFO upstream direction) INFO downstream direction) continuously sent. INFO contain transmitted data (B1, INFO used activation synchronization. Table Name INFO INFO INFO Structure Interface Direction Description Upstream signal line Downstream Upstream Asynchronous Wake Signal burst rate Code violation framing burst rate Code violation framing
INFO
Upstream
INFO
Downstream burst rate Code violation frame Upstream burst rate code violation framing User data channels channels scrambled, bit2) optional
INFO
INFO
Downstream burst rate code violation framing User data channels channels scrambled, bit2) optional
Data Sheet
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Preliminary Note: 1)The channel superframe contains: code violation kbit/s (once every fourth frame)] bits transparent[1 kbit/s channel] bits transparent[2 kbit/s channel] 2)DC balancing bit; Framing Interface Description
Data Sheet
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Preliminary Interface Description
3.2.3.2
Mode State Diagram
RESET
Test
ctiva
Note: Send Continuous Pulses Send Single Pulses test signal invoked test signal invoked Uncond. Transitions RES, TM1, TM2,
ARx,
interface
Ind.
Cmd.
ARx, interface
DELPHI SM.vsd
ctiva
Figure
Data Sheet
State Diagram
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Preliminary Interface Description
state machine unconditional conditional states (refer Figure 16): Unconditional States Reset This state entered unconditionally after appears RESET after receipt command (software reset). analog transceiver part disabled (transmission INFO interface awake detector inactive. Hence, activation from terminal (TE) possible. Test Mode test signal (iti) sent interface this state dependant command which originally invoked state. causes single alternating pulses transmitted (it1); causes continuous alternating pulses transmitted (it2). burst mode technique normally employed interface suspended this state test signals transmitted continuously. Pending Deactivation access conditional states from above unconditional states, pending deactivation state must entered. This occurs after receipt command. this state awake detector activated state left only when line settled (i.e., INFO been detected command Note: Although shown normal command, seen unconditional command. matter which state reception command will always result pending deactivation state being entered. Conditional States Wait This state entered from pending deactivation state once INFO been identified. From here line either activated, deactivated test loop entered. Deactivated This power down state physical protocol. awake detection active device will respond INFO (wake signal) initiating activation.
Data Sheet
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Preliminary Pending Activation This state results from request activation line, either from terminal (INFO from layer-2 device (AR, AR2). INFO then transmitted waits responding INFO from remote device. Synchronized This state reached after synchronization upon receipt INFO i.e. after maximum this state, INFO supplied remote terminal synchronization. Activated Info code violation framing (F-bit), whereas INFO none. Upon reception frames without code violation bit, activated state entered INFO transmitted. line activated; INFO sent remote INFO received from remote. synchronization recognition INFO fails, receiver will attempt resynchronize. Upon entering this state, INFO transmitted. This similar original synchronization procedure pending activation state (the indication given layer different). However, before, recognition INFO leads synchronized state. Table Command Deactivate request Reset Test mode Test mode Activate request State Machine Codes Abbr. Code 0000 0001 0010 0011 1000 1010 Remark Initiates complete deactivation from exchange side transmitting INFO Transmission pseudo-ternary pulses frequency Transmission pseudo-ternary pulses frequency Used start exchange initiated activation Transmission INFO switching loop TE), Interface Description
Activate request test loop
Data Sheet
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Preliminary Table Command State Machine Codes (cont'd) Abbr. Code 1100 1111 Remark Transmission INFO zero Deactivation acknowledgement, quiescent state Interface Description
Activate indication "blocked" Deactivate confirmation
unconditional commands Note: state machine does support loops neither commands (ARL) Indications provided mailbox protocol. loop programmed setting bits TICCMR:LOOP TICCMR:EXLP defining internally externally loop. Indication Timing Resynchronizing Activate request only activation indication Activate indication Abbr. Code 0000 0100 1000 0111 1100 1111 Remark Deactivate state, activation from line possible Receiver synchronous INFO received INFO received, synchronous receiver Receiver synchronous, i.e., activation completed INFO received after deactivation request
Deactivate indication
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Preliminary Interface Description
3.2.4
State Machine
finite state machine DELIC controls line activation/deactivation procedures transmission special pulse patterns. Such actions initiated primitives (INFOs) interface codes sent mailbox. Depending application mode transfer direction, state machines support different codes conditional unconditional states: LT-S mode Codes: States: data downstream Commands: reset, test mode, activate req,. data upstream Indications: sync, code violation, timer out,. deactivated, activated, pending, lost framing, test mode
state diagram shown Figure LT-T mode Codes data upstream Commands: reset, test, activate request,. data downstream Indications: command acknowledged,. Conditional states: power pending deactivation, synchronized, slip detected,. state diagram shown Figure Unconditional states entered from conditional state should left with command TIM: test mode, reset state,. layer-1 activation deactivation procedures implemented DELIC similar ones implemented 2084, QUAT-S.
Data Sheet
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Preliminary Interface Description
3.2.4.1
Table Command
LT-S Mode
LT-S State Machine Codes Abbr. Code 0000 0001 0010 0011 1000 1111 Remark Initiates complete deactivation from exchange side transmitting INFO Transmission pseudo-ternary pulses frequency Transmission pseudo-ternary pulses frequency Used start exchange initiated activation Deactivation acknowledgement, quiescent state
Deactivate request Reset Test mode Test mode Activate request Deactivate confirmation
unconditional commands Note: LT-S state machine does support loops. neither commands Indications provided mailbox protocol. loop programmed setting bits TICCMR:LOOP TICCMR:EXLP respective channel. Indication Timing Resynchronizing Activate request Code violation received Abbr. Code 0000 0100 1000 1011 Receiver synchronous INFO received After each multi-frame reception least illegal code violation indicated four times Receiver synchronous, i.e., activation completed Timer expired INFO received after deactivation request Remark
Activate indication Deactivate indication
1100 1111
Data Sheet
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Preliminary Interface Description
RESET
ARD1)
State
State
32ms
ARD1)
activated
ARD1)
Note: Send Continuous Pulses Send Single Pulses test signal invoked test signal invoked
ctiva
interface
Ind.
Cmd.
Lost
DELPHI LT-S SM.vsd
tate
interface
Figure
Data Sheet
State Diagram LT-S Mode
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Preliminary LT-S Mode States deactivated line interface transmitting. There signal detected interface, activation command received. pending activation result INFO detected line command, line interface begins transmitting INFO waits reception INFO timer supervise reception INFO implemented software. case command, loop closed. activated Normal state where INFO transmitted interface. line interface remains this state long neither deactivation test mode requested, receiver does loose synchronism. When receiver synchronism lost, INFO sent automatically. After reception INFO transmitter continues sending INFO lost framing This state reached when line interface lost synchronism state activated. pending deactivation This state triggered deactivation request unstable state: status (state wait DR") issued DELIC when either INFO received, internal timer expires. wait Final state after deactivation request. line interface remains this state until response other words issued. Test mode Single alternating pulses sent interface repetition rate). Test mode Continuous alternating pulses sent interface kHz). Interface Description
Data Sheet
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Preliminary Interface Description
3.2.4.2
Table Command
LT-T Mode
LT-T Mode State Machine Codes (Conditional States) Abbr. Code 0000 0001 0010 Remark Requests line interface change into power-up state Reset state machine. Transmission Info reaction incoming infos Transmission single pulses S/Tinterface. pulses transmitted with alternating polarity frequency kHz. Transmission continuous pulses S/T-interface. pulses sent with alternating polarity rate kHz. unconditional command (x). Activation Request with priority Dchannel transmission. This command used start LT-T initiated activation. Dchannel priority highest priority. should used request signaling information transfer. Activation request with priority Dchannel transmission. This command used start LT-T initiated activation. Dchannel priority lower priority. should used request packet data transfer. Activation loop This command forces line interface into power down" mode.
Timing Request Reset Test mode
Test mode
0011
Activate request, priority
1000
Activate request, priority
AR10
1001
Activate request loop Deactivate indication
1010 1111
unconditional commands
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Preliminary Indication Deactivate request Reset Test mode Test mode Slip detected Abbr. Code SLIP 0000 0001 0010 0011 0011 0100 0111 1000 1010 1011 Remark Deactivation request left from F7/F8 Reset acknowledge acknowledge acknowledge Frame wander larger than Signal received, receiver synchronous Line interface powered INFO received Loop closed After each multiframe reception least illegal code violation indicated four times. Loop activated INFO received, D-channel priority INFO received, D-channel priority Line interface powered down Interface Description
Re-synchronization during level detect Power Activate request Activate request loop Code violation received
Activate indication loop Activate indication with priority class Activate indication with priority class Deactivate confirmation
AI10
1110 1100 1101 1111
Data Sheet
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Preliminary Interface Description
AR2)
TMI4) TMI4) it5)
synch nize
TMI4) State
AI3) AR2) ctiva
RESET
i0*TO1
DELPHI RESET
(from DR1)
i0*TO1
(from
transition from stands AR10 stands AI10 stands test signal invoked test signal invoked
TO1:
Figure
Data Sheet
LT-T Mode State Diagram (Conditional Unconditional States)
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Preliminary LT-T Mode (Conditional States) power down This deactivated state physical protocol. receive line awake unit active. power This state similar power down". state invoked Command "0000" static low). pending deactivation line interface reaches this state after receiving INFO (from states F8). From this state activation only possible from line (transition pending deactivation" unsynchronized"). power down state reached only after receiving pending activation Activation been requested from terminal; INFO transmitted; INFO still received; "Power transmitted channel. This state stable: timer (ITU I.430) implemented software. F5/8 unsynchronized reception signal ceases transmit INFO adapts receiver circuit, awaits identification INFO INFO This state also reached after line interface lost synchronism states respectively. synchronized When receives activation signal (INFO responds with INFO waits normal frames (INFO activated This normal active state with layer protocol activated both directions. From state synchronized", state reached almost after reception INFO slip detected When slip detected between interface clocking system IOM-2 interface clocks (phase wander more than data disturbed) line interface enters this state, synchronizing again internal buffer. After this state relinguished. Interface Description
Data Sheet
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Preliminary LT-T Mode (Unconditional States) unconditional states should left with command TIM. Test mode Single alternating pulses sent interface repetition rate). Test mode Continuous alternating pulses sent interface (120 kHz). Reset state hardware software reset (RES) forces line interface idle state where analog components disabled (transmission INFO line awake detector inactive. Restriction LT-T Mode first TRANSIU Channels (i.e. Channel_0 channel_1 IOM2000 frame, referring VIP_0, ch_0 ch_1) work LT-T mode. order have optimized usage LT-channels recommended proceed follows: only used, channels applied LT-T mode using DCL_2000 clock 6.144 mapping channel 8.15. VIPs used, channels applied LT-T mode using DCL_2000 12.288 mapping VIPs channel 8.23. VIPs used channels (channel 2.23) applied LT-T mode using DCL_2000 12.288 MHz. Interface Description
Data Sheet
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Preliminary Interface Description
IOM®-2 Interface
IOM-2 standardized interface interchip communication ISDN line cards digital exchange systems developed ALCATEL, Siemens, Plessey ITALTEL. IOM-2 interface four-wire interface with clock, frame clock data line direction. flexible data clock. This way, data transmission requirements optimized different applications.
Figure
IOM®-2 Interface Digital Line card Mode
Note: Laundered mode, identical IOM-2 subchannels provided. analog Line cards, 6-bit Channel available signaling information. digital Line cards, dedicated 2-bit D-channel carries signaling information.
3.3.1
MONITOR
Signals Channels
Frame Synchronization Clock, Data Clock, 4.096 Data Downstream, 4.096 Mbit/s Data Upstream, 4.096 Mbit/s User data channels, kbit/s each Monitor Channel Signaling Channel, kbit/s Command/Indication Channel Monitor Receive handshake signal Monitor Transmit handshake signal
detailed clock data rates, refer IOMU feature description Chapter 4.3.2
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Preliminary Interface Description
Interface
interface operated different modes. This chapter describes configure DELIC each mode.
3.4.1
Intel/Infineon Motorola Mode
processor mode selected MODE input DELIC. "Low" level selects Infineon/ INTEL mode, "HIGH" level selects Motorola mode.
3.4.2
De-multiplexed Multiplexed Mode
both modes, A-bus D-bus used parallel. A-bus should connected LSBs AD-bus, coming from also multiplexed mode. mode determined according input pin. When permanently driven `1', DELIC works de-multiplexed mode. Otherwise DELIC works multiplexed mode. next figure describes connection DELIC address data buses different modes. Note: Motorola mode used only with de-multiplexed bus. Intel/Infineon mode used with both, multiplexed de-multiplexed bus.
Data Sheet
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Preliminary Interface Description
Multiplexed Mode
DELIC
LATCH
De-multiplexed Mode
DELIC
LATCH
Figure
DELIC Multiplexed De-multiplexed Mode
Note: both modes only LSBs A-bus AD/bus connected Address inputs DELIC. mode DACK/A4 input used DACK, internally driven `0'. this case A/AD-bus also connected DELIC.
Data Sheet
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Preliminary Interface Description
3.4.3
Non-DMA Mode
internal interface between on-chip established Mailboxes: 'general' Mailbox dedicated Mailbox. non-DMA mode provides option combine them together building double-sized 'general' Mailbox. DELIC configured non-DMA mode dedicated interface configuration register (MCFG:DMA). Mode Mailbox accessed only controller. DACK input (together with signals) used access Mailbox. Only general Mailbox accessed directly mode, DACK/A4 used DACK, A-bus AD-bus coming from must used address line DELIC. this case driven internally `0'. Note: de-multiplexed mode should connected DELIC's D4input pin. Non-DMA mode This default mode (after reset).The general Mailbox Mailbox data registers concatenated into double-sized general Mailbox, accessible This broad Mailbox consists dedicated Mailbox Mailbox. Each them contains data bytes command byte. non-DMA mode, DACK/A4 used order include Mailbox data registers interface address space.
3.4.4
DELIC External Interrupts
DELIC contains only source external interrupt general Mailbox. This interrupt source OCMD register Mailbox. Releasing interrupt done resetting OBUSY:BUSY. Masking done resetting MASK interface Configuration Register (MCFG:IMASK). interrupt vector issued contents Mailbox command register MCMD. Motorola mode, interrupt vector issued upon first IACK pulse, while Infineon/Intel mode issued upon second IACK pulse. latter case, interrupt vector first IACK pulse needed), should issued external interrupt controller.
Data Sheet
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Preliminary Interface Description
JTAG Test Interface
DELIC provides fully IEEE Standard 1149.1 compatible boundary scan support allow cost effective board testing. consists Complete boundary scan test Test access port controller (TAP) Five dedicated pins: JTCK, TMS, TDI, (according JTAG) additional TRST enable asynchronous resets controller 32-bit IDCODE register
3.5.1
Boundary Scan Test
Depending functionality boundary scan cells provided. Type Input Output Number Boundary Scan Cells Usage Input Output, enable
When controller appropriate mode data shifted into/out boundary scan pins TDI/TDO using clock 6.25 JTCK. sequence DELIC pins taken from BSDL files.
3.5.2
Controller
Test Access Port (TAP) controller implements state machine defined JTAG standard IEEE 1149.1. Transitions cause controller perform state change. controller supports standard instructions: Table Code 0000 0001 0010 0011 1111 Controller Instruction Codes Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE BYPASS Function External testing Internal testing Snap-shot testing Reading code register Bypass operation
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Preliminary EXTEST used verify board interconnections. When controller state "update DR", output pins updated with falling edge JTCK. When entered state "capture levels input pins latched with rising edge JTCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When controller state "update DR", inputs updated internally with falling edge JTCK. When entered state "capture levels outputs latched with rising edge JTCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. Note: 0011 (IDCODE) default value instruction register. SAMPLE/PRELOAD provides snap-shot level during normal operation used either preload (TDI) shift (TDO) boundary scan test vector. Both activities transparent system functionality. IDCODE 32-bit identification register serially read TDO. contains version number bits), device code bits) manufacturer code bits). fixed '1'. code DELIC version '0010'. Version 0010 Device Code 0000 0000 0101 0111 Manufacturer Code 0000 1000 Output Interface Description
Note: state "test logic reset" code "0011" loaded into instruction code register. BYPASS, entering shifted after JTCK clock cycle, e.g. skip testing selected printed circuit board.
Data Sheet
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Functional Description
functionality DELIC-PB comprises functionality DELIC-LC, following chapter describes functionality DELIC-PB. differences between chip versions (considering also firmware) seen below: Table Differences between DELIC-LC DELIC-PB DELIC-LC Cha. MBit/s Cha. 0.23 available available; used increment general mailbox without threshold DELIC-PB Cha. MBit/s Cha. 0.31 available used operation general mailbox variable, limited DSP-RAM with threshold
Functionality GHDLC channels (maximum configuration) GHDLC maximum data rate HDLC channels (maximum configuration) interface DMA- mailbox
Number switching connections Multi-bit switching (1-bit, 2-bit, 3-bit.8-bit) DECT-synchronization delay measurement support 'Firmware Alive Indication' function DSP- time statistic counter DSP-PBX-library conferencing, tone generation/ detection, DTMF receiver/ generator music hold Free programmability DSP-system
Data Sheet
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Figure
Data Sheet
/GCI
Preliminary
Different Lines
Unit Unit
PCM/ LNC2.3
2.048 Mbit/s 4.096 Mbit/s
Layer-1
Block Diagram
HDLC Unit GHDLC Unit
Subscribers
LNC0
UPN/
IOM-2000/ LNC16 TRANSIU
OAK+ Memory
Different Lines:
Functional Overview Block Diagram
REFCLK
Clocks 16.384
Mail Mail
Interrupt Controller JTAG
61.44
VIP/ VIP-8
Interface
TEST
DELIC
Siemens C166
DMAC
MEMORY
Functional Description
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4.2.1
IOM-2000 Transceiver Unit TRANSIU Overview Features
TRANSIU controls layer-1 channels three VIP/ VIP8 connected IOM-2000 interface IOM-2000 interface: channels programmed TRANSIU interface interface LT-S (subscriber master) LT-T (trunk slave) mode Note: number interfaces 20590 limited Therefore required program TRANSIU correctly required mode (refer TRANSIU register description) Data rates: 3.072 Mbit/s VIP), 6.144 Mbit/s VIPs) 9.216 Mbit/s VIPs) Data maintenance handling interface, including multiframe control D-channel collision control.
4.2.2
TRANSIU Initialization
Reset Status IOM-2000 channels configured interface, LT-S mode data rate TRANSIU 3.072 Mbit/s buffers related IOM-2000 undefined Command Status buffers have value
Channel Programming Every IOM-2000 channel configured TRANSIU mode channel LT-S mode channel LT-T mode Data Rate Programming TRANSIU supports three configurations regarding number VIPs connected IOM-2000: connected data rate 3.072 Mbit/s: IOM-2000 channels clock rate 3.072 VIPs connected data rate 6.144 Mbit/s: IOM-2000 channels clock rate 6.144 Three VIPs connected data rate 9.216 Mbit/s: IOM-2000 channels clock rate 12.288 MHz. (Note difference between clock rate actual data rate)
Data Sheet
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4.2.3
Initialization
During startup requires frames with right DCL_2000 synchronize DELIC. During this time able detect commands data from DELIC.
4.2.4 4.2.4.1
Mode Control Framing Bits IOM-2000 Framing (F-Bit)
framing recognized IOM-2000 interface, when both data control bits equal `1'. transmit direction data control bits inserted TRANSIU beginning every transmitted frame; receive direction framing used frame start recognition.
4.2.4.2
Multiframing Bits
interface, multiframe includes frames. start multiframe indicated Fa-bits (the M-bit every 20-th frame, Fa-bit every 5-th frame). channel provides additional capability data exchange between LT-S between Central Office (CO) LT-T multiframe level. LT-Sto-TE direction S-channel (S-bit frame) used. opposite direction LT-S) data transferred Q-channel. Q-bits defined bits position every 5-th frame. Q-bit position identified LT-S direction. multiframe provided structuring Q-bits groups four (Q1-Q4). S-channel coding with respect frame number shown Table LT-S LT-T Figure Channel Assignment
IOM-2000 DELIC
Data Sheet
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Preliminary Table Mode Multiframe Positions LT-S LT-S LT-T, LT-T, position M-bit LT-S LT-T, S-bit LT-S LT-T position Functional Description
Frame number
Note: 1.Only frame positions (within 20-frame multiframe) that carry Q-channel information shown here 2.The S-bits, which used, `1'. IOM-2000 interface, multiframe information included DX/DR data stream (transparently VIP). values multiframe controlled software DELIC. When multiframe synchronization achieved lost, mirrors received bits. Once multiframe synchronization established, sends multiframe synchronization command (MSYNC bit). Upon reception MSYNC, stops mirroring -bit.
4.2.4.3
Fa/N
transmit direction Fa/N pair coded such that binary opposite equal binary `0', except every 5-th frame when `1', which indicates Q-bit position receive direction, positions represent Q-channel.
Data Sheet
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Preliminary Functional Description
4.2.4.4
DC-Balancing (L-Bit)
transmit (downstream) direction L-bit generated compliance with ITU-T I.430: balance number following previous balance odd. balance number following previous balance even. inserted according Balancing Control (BBC) sent DELIC line. receive (upstream) direction, balancing received line, evaluated.
4.2.5 4.2.5.1
Mode Control Framing Bits IOM-2000 Framing (LF-Bit)
interface framing (LF) always logical `1'. transmit direction LF-bit inserted TRANSIU beginning every transmitted frame. assumes start frame when detecting first (LF-bit) data stream IOM-2000 line together with IOM-2000 pulse. This required clock rate signal comparison frame length interface. code violation position generated when INFO1 transmitted, according command bits SMINI(2:0). receive direction first recognized line after signal", which represented logic `0', treated LF-bit. code violation LF-bit position recognized when INFO received. This information forwarded DELIC part receiver status bits RxSTA(1:0).
4.2.5.2
Multiframing (M-Bit)
interface, multiframes composed four frames. multiframe included M-bit position. Every fourth M-bit, code violation indicates start multiframe. transmit direction, extracts multiframe bits IOM-2000 data coming from DELIC inserts them frame line side. receive direction, extracts multiframe bits data coming from line inserts them IOM-2000 frame DELIC. multiframe counter guarantees timing multiframe. synchronized (reset) every 20th frame (=every 40th IOM-2000 frame) command 'SH_FSC' issued DELIC. Note: SH_FSC performs functionality short pulse OCTAT-P QUAT-S.
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Preliminary T-bit T-bit received line inserted IOM-2000 data receive (DR) line multiframe (M-bit) position every frame; i.e. only usual T-bit position every third frame, also S-bit position code violation (CV) position. DELIC software evaluate received T-bit provide user with additional data channel (under consideration). Note that this additional feature OCTAT-P. transmit direction, T-bit value sent data stream from DELIC VIP, passed transparently terminal. T-bit value programmed DELIC's data RAM. required e.g. DECT synchronization. S-bit S-bit received line interface extracted data stream, logical with detected far-end code violation. result sent DELIC status 'FECV'. transmit direction, S-bit value sent data stream from DELIC VIP, passed transparently terminal. S-bit value programmed DELIC's data RAM. required e.g. switching digital loop terminal. CV-bit code violation received line transmitted DELIC. Functional Description
4.2.5.3
DC-Balancing
DC-balancing inserted according Balancing Control (BBC) transmitted command line. receive direction, balancing received, evaluated.
4.2.6
IOM-2000 Command Status Interface
Command/Status bits used channel programming divided into group used only during initialization, group used during normal operation.
4.2.6.1
Initialization Mode Command Bits
bits this group used initialization operation modes where immediate reaction required. initialization group includes command bits channel address, stored register TICCMR. Note that usage this group bits limited that only channel accessed each frame.
Data Sheet
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Preliminary Functional Description
test mode, command word VIP_n (CMD_n) Channel_m VIP_n (CMD_n_m) read DELIC next frame after issuing bits 'RD_n' 'RD'. mirrors command word exactly received, despite bits 'WR', 'WR_ST', 'RD'. status saved TRANSIU initialization status (TICSTR) register, which includes status bits channel address. Note: commands must read during normal operation, since this case reporting status DELIC would possible.
4.2.6.2
Operational Mode Command/Status Bits
bits this group used during normal operation, hence they evaluated every frame. They include receiver status bits some command bits. operational mode command/status bits buffered Data RAM. receiver status bits reflect status change, status itself, i.e. current value line interface INFOs, until values change. FECV only reported DELIC upon changes.
4.2.6.3
Command/Status Transmission
command/status bits transmitted/received TRANSIU same rate data transmission rate, starting with FSC. Transmit Direction command information prepared VIPCMR0-2 registers command bits from initialization command group prepared TICCMR register channels TRANSIU operation mode command format Data Receive Direction received status stored VIPSTR0-2 registers "read_status" command transmitted previous frame channels, received status from this channel saved TICSTR register together with 5-bit channel address TRANSIU operation mode status format Data
Data Sheet
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Preliminary Functional Description
4.2.6.4
Command Status format Data
operational mode command status bits usually served completely firmware. there need this bits user. Operational Mode Command bits data RAM: Address:see memory data byte data byte data byte SMINI(2:0) MSYNC WR_ST
WR_ST
Write Command TST1 Bits (S/T, UPN) Data sent these bits invalid SMINI(2:0) MSYNC contain valid data Multiframe Synchronization (LT-T) mirrors FA-bit stops FA-bit mirroring (for multiframe synchronization) State Machine Initialization (S/T, UPN) Command from DELIC layer-1 state machine. Depending state, transmit data interface. responds sending receiver status bits STAT_n_m.RxSTA(1:0) DELIC. INFO INFO INFO LT-T, INFO LT-S INFO LT-T, INFO LT-S Test mode 'Send Continuous Pulses SCP': '1s' transmitted (UPN) S/T) Test mode 'Send Single Pulses SSP' burst rate) other states reserved
MSYNC
SMINI(2:0)
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Preliminary Operational Mode Status bits data RAM: Address:see memory data byte data byte data byte MSYNC FSYNC SLIP FECV RxSTA(1:0) Functional Description
RxSTA(1:0)
Receiver Status Change (S/T, UPN) Receiver synchronized line; signal line (INFO Level detected line (any signal) (INF LT-S mode) Receiver synchronized line, activated (INFO LT-T mode) Receiver synchronized activated (INFO LT-T mode INFO LT-S UPN) Far-end Code Violation (S/T, UPN) Normal operation Illegal code: FECV according ANSI T1.605 detected (S/T) Frame Slip Detected (LT-T) frame slip detected frame slip more than detected LT-T channel F-Bit Synchronous (S/T test mode only!) Code Violation F-Bit detected (UPN test mode only!) Multiframe Synchronous (UPN), Level Detected (S/T), test mode!
FECV
SLIP
FSYNC MSYNC
Note: with marked bits evaluated DELIC, only testing. Bits SLIP, FECV directly available software TRANSIU receive data RAM.
4.2.7
IOM-2000 Data Interface
Data processing frame handling TRANSIU fully controlled. Serial data received transmitted IOM-2000 Interface arranged Shift Receive Shift Transmit RAM. processed bytes stored TRANSIU Current Buffer. Every frame TRANSIU Current Buffers switched.
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4.2.7.1
Mode
data received transmitted nominal rate kbit/s. first half frame data transmitted `zeros' received, second half frame `zeros' transmitted data received. Scrambling de-scrambling B-channel data done automatically. received transmitted data stored Data following format: Mode Receive Transmit Data Format
B1-channel data B2-channel data D-channel M-bit Operation Mode Command/Status bits transmit direction, depending multiframe position, M-bit contains either T-bit S-bit with following functionality: T-bit: D-channel available info terminal DECT synchronization signal S-bit: switches remote loop terminal device
4.2.7.2
Scrambler/Descrambler
B-channel data channels IOM-2000 interface scrambled give flat continuous power density spectrum line. Scrambling done according ITU-T V.27 with generator polynomial Initialization History (HRAM) scrambler activated/deactivated each channel separately write history address. During initialization writes value with (other bits importance) every History address associated channel that scrambled, value with every channel that must scrambled. same values must written descrambler history RAM. HRAM addresses are: 0x9000 0x9017 (scrambler channel 0.23) 0x9020 0x9037 (descrambler channel 0.23)
Data Sheet
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Preliminary Functional Description
example, order activate scrambling descrambling channel number must execute write operations follows: Write "xxxxxxxxxxxxxxx1" address 0x9002 Write "xxxxxxxxxxxxxxx1" address 0x9022 These writes executed only when scrambler idle mode, i.e. value 0x0003 written address 0xD010.
4.2.7.3
Mode
Data received/transmitted nominal rate kbit/s. Each data translated into bits IOM_2000: data (bit0) control (bit1). LT-S Mode Transmit Data Format
B1-channel data B2-channel data D-channel Operation Mode Command/Status bits LT-S Mode Receive Data Format
channel data channel data D-channel Operation Mode Command/Status bits LT-T Mode Receive Data Format
B1-channel data B2-channel data D-channel Operation Mode Command/Status bits
Data Sheet
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Preliminary Functional Description
Collision Detection Number Collision detected first D-bit S-frame half (corresponds second echo-bit frame half) Collision detected second D-bit S-frame half (corresponds first echo-bit frame half) Collision Detection Indication collision D-channel Collision D-channel detected
LT-T Mode Transmit Data Format
B1-channel data B2-channel data D-channel Operation Mode Command/Status bits
4.2.8
DECT Synchronization Interface
DECT systems DELIC supports synchronization different radio base stations (RBS). Synchronization controlled T-bit Up-frame. detailed description procedure found DELIC-PB Software User's Manual.
4.2.9
Test Loop
DELIC/VIP allows internal well remote loops testing programming registers TICCMR TUTRL.
Data Sheet
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Preliminary Functional Description
4.3.1
IOM-2 Unit IOMU Overview Features
IOMU provides access incoming time slots from IOM-2 interface. switch timeslots other DELIC system interfaces. Features access switching data PCMU TRANSIU (providing constant switching delay frames) access extracting D-channel information access control IOM-2 Command/Indication (C/I) Monitor channel information Interface Configuration IOM-2 ports providing IOM-2 channels ISDN analog subscribers) Available data rate modes: port kbit/s each time slots frame) port kbit/s each time slots frame) ports 2.048 Mbit/s each time slots frame) port 4.096 Mbit/s time slots frame) Single double data rate clock selectable data rates data rates MBit/ Programmable tri-state control each port channel time slots) Push-pull open-drain configuration DRDY signal D-channel control when connected QUAT-S 2084
Data Sheet
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Preliminary Functional Description
4.3.2
IOMU Functional Operational Description
DELIC CLOCKS
Interface
IOM-2 Interface
PCMU
SWITCHING
D,C/I D.C/I
D,C/I D.C/I
IOMU
SWITCHING
DRDY
HDLCU
IOM-2000 Interface
TRANSIU
Figure
IOMU Integration DELIC
4.3.2.1
Frame-Wise Buffer Swapping
main task IOMU serial-to-parallel conversion incoming IOM-2 data parallel data format which directly read DSP. This access required perform switching B-channels, extraction D-channels, layer-1 control IOM-2 Monitor channels. data conversion IOMU done frame-wise swapping based circular buffer structure. During each frame, buffer assigned IOMU (I-buffer), other (D-buffer). every frame, buffers swapped.
4.3.2.2
I-buffer Logical Structure
logical partitioning each frame buffer into input output blocks determined according requested data rate shown table below. address each data byte I-buffer output blocks must selected according port time slot index, which should transmitted.
Data Sheet
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20570 20571
Preliminary Table Data Rate 2.048 Mbit/s kbit/s kbit/s 4.096 Mbit/s I-Buffer Logical Memory Mapping Input Blocks -Output Blocks out0 out1 -Functional Description
4.3.2.3
Access D-Buffer
D-buffer mapped fixed address space. Every access D-buffer space directed automatically appropriate sub-buffer.
Table Data-Rate Mode
D-Buffer Address Space D-Buffer 8000H 801FH 8000H 8005H 8000H 800BH 8000H 803FH 8020H 803FH out0 8040H 805FH 8040H 8045H 8040H 804BH 8040H 807FH out1 8060H 807FH
time slots/frame time slots/frame time slots/frame time slots/frame
4.3.2.4
IOM-2 Interface Data Rate Modes
IOMU support different serial data rates IOM-2 interface: kbit/s time slots frame) kbit/s time slots frame) 2.048 Mbit/s time slots frame IOM-2 channels frame) 4.096 Mbit/s time slots frame IOM-2 channels frame)
IOMU circular buffer handle time slots frame. Thus, when 4.096 Mbit/s mode, only IOM-2 port used. this case IOM-2 port remains IDLE mode, i.e. output tri-stated.
Data Sheet
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20570 20571
Preliminary Table Frequency Different IOM-2 Modes IOM-2 Mode 1x384 kbit/s 1x768 kbit/s 1536 2x2.048 Mbit/s 1x4.096 Mbit/s 2.048 4.096 4.096 Functional Description
Single/Double Rate Mode Single Double
IOMU meets IOM-2 interface timing specifications described below. Single Data Rate Mode Serial transmission DD0/DD1 with every rising edge Sampling incoming serial data (DU0/DU1) with every falling edge Sampling with every falling edge. Sampling after sampling considered start frame. Double Data Rate Mode cycles (the bits aligned frame start) Serial transmission DU0/1 with every second rising edge. Sampling incoming serial data (DD0/1) with second falling edge each bit. Sampling every falling edge. Sampling after sampling considered start frame.
Figure shows IOM-2 interface timing with single double rate DCL. more details refer general IOM-2 interface description.
Data Sheet
2000-08-22
20570 20571
Preliminary Functional Description Single Data Rate
Frame Start
DD0/1 DU0/1
TS31 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 TS31 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
Double Data Rate
Frame Start
DD0/1 DU0/1
TS31 bit0 bit7 bit6 bit5 bit4
TS31 bit0
bit7 Upstream Sampling
bit6
bit5 Sampling
bit4
Figure
IOM-2 Interface Timing Single/Double Clock Mode
4.3.2.5
IOMU Serial Data Processing
IOMU serial data processing according IOM-2 specifications. Incoming serial data converted into parallel bytes, stored I-buffer input blocks. sequence every time slot received from (bit (bit Transmission performed opposite direction, from (bit (bit
4.3.2.6
IOMU Parallel Data Processing
data read from IOMU frame buffers always reside byte 16-bit word. high byte read word driven 8-bit IOMU Data Prefix Register (IDPR). data prefix used accelerate A-/µ-law linear conversions (refer Chapter 4.5). Note: octet written location IOMU frame buffers should reside byte LSB). high byte written word "don't care".
Data Sheet
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Preliminary Functional Description
4.3.2.7
IOM-2 Push-Pull Open-Drain Modes
IOM-2 ports configured Push-Pull Open-Drain modes dedicated IOMU Control Register. When programmed Open-Drain, DD0/DD1 tristated when supposed transmitted, during time slot quadruplet with associated Tri-State Register set. both cases external pull-up resistor, which used when working open-drain mode, will "pull" value `1'. Note: When IOMU programmed time slots frame mode, tristated, independently IOM-2 interface push-pull open-drain mode. DELIC
IOMU
ITSR
downstream0 data
downstream1 data
Figure
IOM-2 Interface Open-Drain Mode DELIC
downstream0 data
IOMU
ITSR
downstream1 data
Figure
Data Sheet
IOM-2 Interface Push-Pull Mode
2000-08-22
20570 20571
Preliminary Functional Description
4.3.2.8
Support DRDY Signal from QUAT-S
DRDY input used when connecting Infineon QUAT-S transceiver DELIC IOM-2 interface. driven QUAT-S inform DELIC when Dchannel occupied another S-interface device. IOMU supports synchronous DRDY mode, i.e. QUAT-S operated LT-T mode. this mode, DRDY signal valid only during D-channels. DRDY means STOP (ABORT HDLC message), DRDY means
IOM-2 IOM-2
IOM-2
IOM-2
IOM-2
DRDY
valid
stop
stop
stop
Figure
DRDY Signal Behavior
IOMU DRDY support features: Sampling DRDY only once every D-channel, first bit. Sampling with first falling edge single data-rate mode), with second falling edge double data-rate mode), refer Figure DRDY support IOM-2 port only (with constant delay frame) status DRDY line read from register IDRDYR
First D-channel second D-channel
DRDY
valid
Sample point DRDY single data-rate mode Single Data-Rate Sample point DRDY double data-rate mode Double Data-Rate
Figure
DRDY Sampling Timing
Note: DRDY used, DRDY 'high'.
Data Sheet 2000-08-22
20570 20571
Preliminary Functional Description
Unit
Interface Features PCMU enables control ports. accesses incoming time slots, prepares outgoing time slots. general, PCMU enables switch time slots from ports. basic structure programming model PCMU similar IOMU. Note that PCMU provides double capacity IOMU. Thus handle ports overall time slots frame receive direction time slots frame transmit direction. following PCMU data rate modes available: Four streams 2.048 Mbit/s each (single double clock) streams 4.096 Mbit/s each (single double clock) stream 8.192 Mbit/s (single double clock) stream 16.384 Mbit/s (single clock). programmable, whether first second time slots frame handled PCMU.
Tristate control performed pins TSCn, programmable time slot port.
Data Sheet
2000-08-22
20570 20571
Preliminary Functional Description
4.4.1
PCMU Functional Operational Description
interface
PDC, TSC2 TSC3
Unit Unit
RXD0, TXD0, TSC0 RXD1, TXD1, TSC1 RXD2, TXD2 RXD3, TXD3
HDLC Unit
GHDLC Unit
OAK+
TRANSIU
Memory
Figure
PCMU Integration DELIC
PCM-unit signals share port pins with GHDLC-unit. multiplexer controlled register MUXCTRL allows define required functionality.
4.4.1.1
Frame-Wise Buffer Swapping
main task PCMU serial-to-parallel conversion incoming data parallel data format (and vice versa) which directly read DSP. This access required perform switching B-channels. data conversion PCMU done frame-wise swapping based circular buffer structure. During each frame, buffer assigned PCMU (I-buffer), other (D-buffer). every frame, buffers swapped.
4.4.1.2
Inaccessible Buffer (I-buffer)
logical partitioning each frame buffer into input output blocks determined according requested data rate shown table below. address each data byte I-buffer output blocks must selected according port time slot index, which should transmitted.
Data Sheet 2000-08-22
20570 20571
Preliminary Table Data Rate related port 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 16.384 Mbit/s RXD0 Functional Description I-Buffer Logical Memory Mapping Input Buffers Input Blocks RXD1 RXD2 RXD3
Table Data Rate
I-Buffer Logical Memory Mapping Output Buffers Output Buffer Blocks out0 out1 TXD1 out2 TXD2 out3 TXD3 TXD0 -FFH
related port 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 16.384 Mbit/s
Note: 16.384 Mbit/s only first half frame saved buffer
4.4.1.3
Accessible Buffer (D-Buffer)
D-buffer mapped fixed address space. Every access D-buffer space directed automatically appropriate sub-buffer. Table Data Rate related port 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s RXD0 A000H A03FH A000H A07FH Access D-Buffer Input Blocks Input Buffer Blocks RXD1 RXD2 A040H A07FH RXD3
A000H A01FH A020H A03FH A040H A05FH A060H A07FH
16.384 Mbit/s A000H A07FH
Data Sheet
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Preliminary Table Data Rate out0 related port 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s TXD0 A080H A09FH A080H A0BFH A080H A0FFH Access D-Buffer Output Blocks Output Buffer Blocks out1 TXD1 A0A0H A0BFH out2 TXD2 A0C0H A0DFH A0C0H A0FFH out3 TXD3 A0E0H A0FFH Functional Description
16.384 Mbit/s A080H A0FFH Note: 16.384 Mbit/s only first half frame saved buffer
4.4.1.4
PCMU Interface Data Rate Modes
PCMU support different serial data rates: ports with 2048 Mbit/s time slots frame) ports with 4.096 Mbit/s time slots frame) port with 8.196 Mbit/s (128 time slots frame) port with 16.384 Mbit/s (only time slots frame supported)
PCMU circular buffer handle time slots frame. Thus, when e.g. configured 4.096 Mbit/s mode, only port used. this case port remain IDLE mode, i.e. TXD1, TXD3 output pins tri-stated. data rate modes 8.192 MBit/s, single rate Data Clock (PDC) double rate Data Clock selected. 16.384 mode only single clock supported. Single Data Rate Mode Serial transmission TXDn with every rising edge Sampling incoming serial data (RXDn) with every falling edge Sampling with every falling edge. Sampling after sampling considered start frame. Double Data Rate Mode cycles (the bits aligned frame start) Serial transmission TXDn with every second rising edge. Sampling incoming serial data (RXDn) with second falling edge each bit. Sampling every falling edge. Sampling after sampling considered start frame.
2000-08-22
Data Sheet
20570 20571
Preliminary Functional Description
Figure shows interface timing with single double rate PDC. Single Data Rate
Frame Start
TS31 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 TS31 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
Double Data Rate
Frame Start
TS31 bit0 bit7 bit6 bit5 bit4
TS31 bit0
bit7 data Sampling
bit6
bit5 Sampling
bit4
Figure
IOM-2 Interface Timing Single/Double Clock Mode
4.4.1.5
PCMU Serial Data Processing
incoming serial data converted into parallel bytes, stored I-buffer input blocks. sequence every time slot received from (bit (bit Transmission performed from (bit (bit
4.4.1.6
PCMU Parallel Data Processing
data read from PCMU frame buffers always reside byte 16-bit word. high byte read word driven 8-bit PCMU Data Prefix Register (PDPR). data prefix used accelerate A-/µ-law linear conversions (refer Chapter 4.5). octet written location PCMU frame buffers should reside byte LSB). high byte written word "don't care".
Data Sheet
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Preliminary Functional Description
4.4.1.7
PCMU Tri-state Control Logic
There eight 16-bit tri-state control registers PCMU. Each determines whether associated time slot valid invalid. controlled time slot invalid controlled time slot valid tri-state bits control data transmit pins TXD0 TXD3. special set/reset write method used updating tri-state control registers. Every tri-state control register mapped addresses: first used operation, second reset operation. Both addresses used read operation. operation: This operation executed during write access address registers. bits register according bits written word. other bits maintain their value. Reset operation: This operation executed during write access reset address registers. bits register reset according bits written word. other bits maintain their value. Tristate Control Registers (PTS0-7) accessed DSP. Every them controls signal ports, time slot. time slot port controlled every depend data rate mode. 1x256 TS/frame, depends also selected half frame. Each signals controls directly respective port, also driven outward corresponding TSCn output pin. time slot frame mode, next table depicts which port controlled each register, during which time slot. each register controls first time slot listed time slot range, controls second etc. Table Time Slots 0.15 16.31 Mode MBit/s) TSC0 PTSC0 PTSC1 TSC1 PTSC2 PTSC3 TSC2 PTSC4 PTSC5 TSC3 PTSC6 PTSC7
time slot frame mode, only ports used. TSC1 TSC3 permanently (all time slots invalid). Table Time Slots 0.15 16.31 32.47 48.63
Data Sheet
Mode 4MBit/s) TSC0 PTSC0 PTSC1 PTSC2 PTSC3 TSC1 inactive inactive inactive inactive
TSC2 PTSC4 PTSC5 PTSC6 PTSC7
TSC3 inactive inactive inactive inactive
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20570 20571
Preliminary Functional Description
time slot frame mode, only port used. TSC1, TSC2 TSC3 permanently (all time slots invalid). time slot frame mode, only half frame used. pins permanently during other half frame. Table Time Slots 0.15 16.31 32.47 48.63 64.79 80.95 96.111 112.127 MBit/s) MBit/s) (1st Half) Mode TSC0 PTSC0 PTSC1 PTSC2 PTSC3 PTSC4 PTSC5 PTSC6 PTSC7 TSC1 inactive inactive inactive inactive inactive inactive inactive inactive TSC2 inactive inactive inactive inactive inactive inactive inactive inactive TSC3 inactive inactive inactive inactive inactive inactive inactive inactive
Note: same structure applies frame (first frame half) mode, except that time slots (0.127) transmitted first half frame. Table Time Slots 0.127 128.143 144.159 160.175 176.191 192.207 208.223 224.239 240.255 MBit/s) (2nd Half) Mode TSC0 inactive PTSC0 PTSC1 PTSC2 PTSC3 PTSC4 PTSC5 PTSC6 PTSC7 TSC1 inactive inactive inactive inactive inactive inactive inactive inactive inactive TSC2 inactive inactive inactive inactive inactive inactive inactive inactive inactive TSC3 inactive inactive inactive inactive inactive inactive inactive inactive inactive
Note: Concerning behavior output driver also "PCM Output Driver Anomaly" Page
Data Sheet
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20570 20571
Preliminary Functional Description
A-law/µ-law Conversion Unit
A-/µ-law Unit performs bi-directional conversion between linear representation voice data companded representation (according A-law µ-law). conversion possible B-channels transceived IOM-2, IOM-2000 PCM. A-/µ-law Linear Conversion conversion done table. bytes translate A-law value into linear, while high words translate µ-law linear. issues read cycle, which MSBs 16-bit address represent table address, LSBs actual value which converted. converted linear value contents read from ROM. Note that wait states required this direction conversion. A-law values stored MSBs. LSBs always '0'. µlaw values stored MSBs. LSBs always '0'. Linear A-/µ-law Conversion conversion done dedicated hardware. programs control register perform either A-law µ-law conv
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