Bidirectional Controlled Synthesiser DS3900 March 1995 SP552

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Bidirectional Controlled Synthesiser DS3900 March 1995 SP552

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SP5524
Bidirectional Controlled Synthesiser
DS3900 March 1995
SP5524 single-chip frequency synthesiser designed tuning systems. Control data entered standard format. device controllable open-collector output ports (P0-P3, P7), each capable sinking 10mA. addition, 3-bit 5-level input. information these ports read BUS. device fixed address three programmable addresses, allowing more synthesisers used system.
CHARGE PUMP CRYSTAL CRYSTAL
DRIVE OUTPUT INPUT INPUT OUTPUT PORT OUTPUT PORT/ADD SELECT PORT
SP5524S
PORT
PORT
PORT
FEATURES Complete Single Chip System
MP16
Fig. connections view
Programmable Power Consumption (215mW Typ.) Radiation Phase Lock Detector Varactor Drive Disable Controllable Outputs, Bi-directional 5-Level Variable Address Picture Picture Protection
APPLICATIONS Satellite when Combined with SP4902 Prescaler
Cable Tuning Systems VCRs
ORDERING INFORMATION
SP5524S MPAS (Tubes) SP5524S MPAD (Tape Reel)
Normal handling precautions should observed.
SP5524
ELECTRICAL CHARACTERISTICS
TAMB -10°C +80°C, These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Output voltage Charge pump current Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P0-P3, sink current (see note P0-P3, leakage current (see note Input Ports input current high input current input voltage input voltage high input current high input current Min. 13,14 13,14 Typ. ±170 6400 6-11 6-11 6,8,9 6,8,9 Parallel resonant crystal (note VOUT note VOUT Max. mVrms 100MHz 1GHz mVrms 50MHz Fig. Units Conditions
Input voltage Input voltage When Sink current Byte Byte Byte
Table levels
NOTES Source impedance between output ports ground approximately This should taken into account when calculating output port saturation voltages. recommended crystal series resistance quoted refers conditions including start-up.
SP5524
ABSOLUTE MAXIMUM RATINGS
voltages referred Parameter Supply voltage input voltage Port voltage Total port output current input offset Charge pump offset Drive output offset Crystal oscillator offset SDA, input voltage Min. 13,14 6-11 6-11 6-11 13-14 Value Max. +150 +150 °C/W °C/W With applied applied Port state Port state Units Conditions
Storage temperature Junction temperature MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption
PRESCALER
LOCK DETECTOR
PROGRAMMABLE DIVIDER
FDIV
PHASE COMP
FCOMP
DIVIDER 4512
4MHz
CRYSTAL
POWER DETECTOR
CHARGE PUMP
TRANSCEIVER
DIVIDER RATIO LATCH
CHARGE PUMP
DRIVE OUTPUT
6-BIT LATCH PORT INFORMATION
ADDRESS SELECT
3-BIT
CONTROL DATA LATCH
LOGIC
LEVEL COMP
Fig. Block diagram
SP5524
SP5524 programmed from BUS. Data Clock lines respectively defined format. synthesiser either accept data (write mode) send data (read mode). Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage address byte (R/W) sets device into read mode high write mode low. When SP5524 receives correct address byte pulls line during acknowledge period during following acknowledge periods after further data bytes programmed. When SP5524 programmed into read mode controlling device accepting data must pull down line during following acknowledge period read another status byte.
FUNCTIONAL DESCRIPTION
WRITE MODE (FREQUENCY SYNTHESIS)
When device write mode Bytes select synthesised frequency while Bytes select output port states charge pump information. Once correct address received acknowledged, first next byte determines whether that byte interpreted Byte logic frequency information logic charge pump output port information. Additional data bytes entered without need readdress device until stop condition recognised. This allows smooth frequency sweep fine tuning purposes. transmission data stopped mid-byte (e.g., another device bus) then previously programmed byte maintained. Frequency data from Bytes stored 15-bit shift register used control division ratio 15-bit programmable divider which preceded divide-by-8 prescaler amplifier give excellent sensitivity local oscillator input; input impedance shown Fig. programmed frequency calculated multiplying programmed division ratio times comparison frequency FCOMP. When frequency data entered, phase comparator, charge pump varactor drive amplifier, adjusts
local oscillator control voltage until output programmable divider frequency phase locked comparison frequency. reference frequency generated external source capacitively coupled into provided onchip 4MHz crystal controlled oscillator. Note that comparison frequency when 4MHz reference used. Byte programming data (CP) controls current charge pump circuit, logic ±170µA logic ±50µA, allowing compensation variable tuning slope tuner also enable fast channel changes over full band. Byte (T0) disables charge pump logic Byte (OS) switches charge pump drive amplifier's output when logic Byte (T1) selects test mode where phase comparator inputs available logic connects COMP FDIV Byte programs output ports P0-P3, logic high impedance output, logic impedance (on).
READ MODE
When device read mode status data read from device line takes form shown Table (POR) power reset indicator logic power supply device dropped below nominal programmed information lost (e.g., when device initially turned on). when read sequence terminated stop command. outputs high impedance when device initially powered (FL) indicates whether device phase locked, logic present device locked logic device unlocked. Bits (I2, show status Ports respectively. logic indicates level logic high level. ports used inputs they should programmed high impedance state (logic1). These inputs will then respond data complying with standard voltage levels. Bits (A2,A1,A0) combine give output 5-level ADC. 5-level used feed information microprocessor from section television, illustrated Fig.
SP5524
Address Programmable divider Programmable divider Charge pump test bits port control bits
Byte Byte Byte Byte Byte
Table Write data format (MSB transmitted first)
Address Status byte
Byte Byte
Table Read data format
Voltage input Voltage input Always valid
Table levels
MA1,
Table Address selection
Acknowledge Variable address bits (see Table Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power Reset indicator Phase lock detect flag Digital information from ports respectively 5-level data from (see Table Don't care
Fig. Data formats
SP5524
APPLICATION
typical application shown Fig. input/output interface circuits shown Fig.
130V 112V 180n 2N3904 VARACTOR DRIVE
4MHz
OSCILLATOR OUTPUT
CONTROL MICRO
SP5524S TUNER
112V
2N3906 2N3906 2N3906
BAND INPUTS
SECTION
SIGNAL
Fig. Typical application
INTO
OPERATING WINDOW
1000 FREQUENCY (MHz)
1300
1500
Fig. Typical input sensitivity
SP5524
VREF
INPUTS
CHARGE PUMP
DRIVE OUTPUT
input
Loop amplifier
PORT SCL/SDA
ONLY
Ports inputs
CRYSTAL
CRYSTAL
Reference oscillator
Fig. Input/output interface circuits
SP5524
S11:ZO NORMALISED
FREQUENCY MARKER STEP 250MHz
Fig. Typical input impedance
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Bidirectional Controlled Synthesiser DS3900 March 1995 SP552

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