Integrated 10-channel V-driver Register compatible with AD9991 AD9995
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Signal Processor with Vertical Driver Precision Timing Generator AD9925
Integrated 10-channel V-driver Register compatible with AD9991 AD9995 3-field (6-phase) vertical clock support additional vertical outputs advanced CCDs Complete on-chip timing generator Precision Timing core with <600 resolution Correlated double sampler (CDS) 10-bit variable gain amplifier (VGA) 12-bit Black level clamp with variable level control On-chip horizontal drivers 2-phase 4-phase H-clock modes Electronic mechanical shutter support On-chip driver external crystal On-chip sync generator with external sync input CSPBGA package with 0.65 pitch
AD9925 complete front solution digital still camera other imaging applications. Based AD9995 product, AD9925 includes analog front fully programmable timing generator, combined with 10-channel vertical driver (V-driver). Precision Timing core allows adjustment high speed clocks with approximately resolution operation. on-chip V-driver supports channels with 3-field (6-phase) CCDs. additional vertical outputs used with certain CCDs containing advanced video mode readout. Voltage levels supported. analog front includes black level clamping, CDS, VGA, 12-bit ADC. timing generator V-driver provide necessary clocks: H-clocks, Vertical clocks, sensor gate pulses, substrate clock, substrate bias control. internal registers programmed using 3-wire serial interface. Packaged CSPBGA, AD9925 specified over operating temperature range -25°C +85°C.
APPLICATION
Digital still cameras Digital video camcorders camera modules
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9925
0dB, -2dB, -4dB CCDIN 42dB VREF 12-BIT CLAMP INTERNAL CLOCKS HORIZONTAL DRIVERS DCLK DOUT
PRECISION TIMING GENERATOR
MSHUT STROBE
V3A, V5A, SUBCK
V-DRIVER XSG1 XSG6 VERTICAL TIMING CONTROL INTERNAL REGISTERS SYNC GENERATOR
SUBCK
RSTB
04637-0-001
VSUB
SYNC
Figure Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. rights reserved.
AD9925 TABLE CONTENTS
Specifications. Digital Specifications. Vertical Driver Specifications Analog Specifications. Timing Specifications. Absolute Maximum Ratings. Package Thermal Characteristics Caution. Configuration Function Descriptions. Terminology Equivalent Circuits Typical Performance Characteristics System Overview Precision Timing High Speed Timing Generation. Horizontal Clamping Blanking. Horizontal Timing Sequence Example. Vertical Timing Generation. Vertical Timing Example. Shutter Timing Control Example Exposure Readout Interlaced Frame FG_TRIG Operation. Analog Front-End Description Operation. Vertical Driver Signal Configuration Power-Up Synchronization Standby Mode Operation Circuit Layout Information. Serial Interface Timing Complete Listing Register Bank Complete Listing Register Bank Complete Listing Register Bank Outline Dimensions Ordering Guide
REVISION HISTORY
4/04-Revision Initial Version
Rev. Page
AD9925 SPECIFICATIONS
Table
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGES AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD Driver) HVDD Drivers) DRVDD (Data Output Drivers) DVDD (Digital) VERTICAL DRIVER SUPPLY VOLTAGES VDVDD (Vertical Driver Input Logic Supply) VH1, (Vertical Driver High Supply 3-Level Outputs) VM1, (Vertical Driver Supply 3-Level 2-Level Outputs) VL1, (Vertical Driver Supply 3-Level 2-Level Outputs) POWER DISSIPATION-AFETG Section Only (see Figure Power Curves) MHz, Supply, Load Each Output, Load Standby Mode Standby Mode Standby Mode Power from HVDD Only1 Power from RGVDD Only Power from AVDD Only Power from TCVDD Only Power from DVDD Only Power from DRVDD Only POWER DISSIPATION-Vertical Driver Section Only (VDVDD, Normal Operation 15.0 -7.5 Standby Mode2 Standby Mode2 Standby Mode2 MAXIMUM CLOCK RATE (CLI) 11.5 -1.0 -9.0 15.0 -7.5 +150 16.0 +1.0 -5.0 Unit
total power dissipated HVDD supply approximated using equation Total HVDD Power [CLOAD HVDD Pixel Frequency] HVDD Reducing H-loading and/or using lower HVDD supply will reduce power dissipation. CLOAD total capacitance seen H-outputs. power dissipated vertical driver circuitry depends logic states inputs well actual operation; default values used each measurement, each mode operation. Load conditions described Vertical Driver Specifications section.
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AD9925 DIGITAL SPECIFICATIONS
RGVDD HVDD DVDD DRVDD TMIN TMAX, unless otherwise noted. Table
Parameter LOGIC INPUTS High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance LOGIC OUTPUTS (Powered DVDD, DRVDD) High Level Output Voltage Level Output Voltage H-DRIVER OUTPUTS (Powered HVDD, RGVDD) High Level Output Voltage Maximum Current Level Output Voltage Maximum Current Maximum Output Current (Programmable) Maximum Load Capacitance (for Each Output) Symbol Unit
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AD9925 VERTICAL DRIVER SPECIFICATIONS
VDVDD -7.5 shown load model, 25°C. Table
Parameter 3-LEVEL OUTPUTS (V1, V3A, V3B, V5A, V5B) (Simplified Load Conditions, 6000 Ground) Delay Time, Delay Time, Rise Time, Fall Time, Output Currents -7.25 -0.25 +0.25 +14.75 2-LEVEL OUTPUTS (V4, (Simplified Load Conditions, 6000 Ground) Delay Time, Delay Time, Rise Time, Fall Time, Output Currents -7.25 -0.25 SUBCK OUTPUT (Simplified Load Conditions, 1000 Ground) Delay Time, Delay Time, Rise Time, Fall Time, Output Currents -7.25 +14.75 SERIAL VERTICAL CLOCK RESISTANCE VERTICAL CLOCK RESISTANCE Symbol Unit
tPLM, tPMH tPML, tPHM tRLM, tRMH tFML, tFHM 10.0 -5.0 -7.2
tPLM tPML tRLM tFML 10.0 -5.0
tPLH tPLH tRLH tFHL -4.0
V-DRIVER INPUT
tRLM, tRMH, tRLH
V-DRIVER OUTPUT
tPML, tPHM, tPHL tFML, tFHM, tFHL
04637-0-079
tPLM, tPMH, tPLH
Figure Definition V-Driver Timing Specifications
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AD9925 ANALOG SPECIFICATIONS
AVDD1 fCLI MHz, typical timing specifications, TMIN TMAX, unless otherwise noted. Table
Parameter Allowable Reset Transient Maximum Input Range before Saturation Gain (Default Setting) Gain Gain Maximum Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (Code Maximum Clamp Level (Code 255) ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Differential Nonlinearity (DNL) Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Gain (VGA Code Maximum Gain (VGA Code 1023) Peak Nonlinearity, Input Signal Total Output Noise Power Supply Rejection (PSR) 1.25 +200/-100 1024 Guaranteed -1.0 Unit Steps Notes Note Input Characteristics Definition1
Note Positive Offset Definition1
Steps Measured Output Bits Includes Entire Signal Chain
±0.5 Guaranteed
+1.0
40.5
41.5
42.5
Gain (0.0351 Code) Gain Applied Grounded Input, Gain Applied Measured with Step Change Supply
Input signal characteristics defined
INPUT SIGNAL RANGE GAIN)
04637-0-002
500mV RESET TRANSIENT +200mV OPTICAL BLACK PIXEL
Rev. Page
AD9925 TIMING SPECIFICATIONS
AVDD DVDD DRVDD fCLI MHz, unless otherwise noted. Table
Parameter MASTER CLOCK, (Figure Clock Period High/Low Pulse Width Delay from Rising Edge Internal Pixel Position CLPOB Pulse Width1, (Figure Figure SAMPLE LOCATION1 (Figure Sample Edge Sample Edge DATA OUTPUTS (Figure Figure Output Delay from DCLK Rising Edge1 Pipeline Delay from SHP/SHD Sampling DOUT SERIAL INTERFACE (Figure Figure Maximum Frequency Setup Time Hold Time SDATA Valid Rising Edge Setup Falling Edge SDATA Valid Hold Falling Edge SDATA Valid Read Symbol tCONV tCLIDLY 12.5 27.8 11.2 Unit Pixels Cycles
13.9 13.9
16.6
fSCLK
Parameter programmable. Minimum CLPOB pulse width functional operation only. Wider typical pulses recommended achieve good clamp performance.
Rev. Page
AD9925 ABSOLUTE MAXIMUM RATINGS
Table
Parameter VDVDD VH1, VM1, AVDD TCVDD HVDD RGVDD DVDD DRVDD Output Output Digital Outputs Digital Inputs SCK, SDATA REFT/REFB, CCDIN Junction Temperature Lead Temperature, With Respect VDVSS VDVSS VDVSS VDVSS AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS HVSS DVSS DVSS DVSS AVSS VDVSS VDVSS -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VDVSS VDVSS +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVDD HVDD DVDD DVDD DVDD AVDD Unit
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance CSPBGA Package: 40.3°C/W
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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AD9925 CONFIGURATION FUNCTION DESCRIPTIONS
CORNER INDEX AREA
AD9925
TOPVIEW (Not Scale)
Figure 96-Lead CSPBGA Package Configuration
Rev. Page
04637-0-003
AD9925
Table Function Descriptions
Mnemonic HVSS HVSS HVDD HVDD RGVSS RGVDD TCVDD SYNC TCVSS AVSS CCDIN AVDD REFT REFB MSHUT SUBCK RSTB STROBE Type1 Description2 Driver Ground Driver Ground Horizontal Clock Horizontal Clock Driver Supply Driver Supply Horizontal Clock Horizontal Clock Driver Ground Reset Gate Clock Driver Supply Analog Supply Timing Core Clock Output Crystal External System Sync Input Analog Ground Timing Core Reference Clock Input Analog Ground Signal Input Analog Supply Voltage Reference Bypass Voltage Reference Bottom Bypass Mechanical Shutter Pulse Substrate Clock Shutter) Vertical Driver Supply Vertical Driver High Supply Reset Bar; Active Pulse 3-Wire Serial Load Pulse 3-Wire Serial Clock 3-Wire Serial Data Input Vertical Transfer Clock Vertical Transfer Clock Strobe Pulse Vertical Driver Supply Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Vertical Sync Pulse (Input Slave Mode, Output Master Mode) Horizontal Sync Pulse (Input Slave Mode, Output Master Mode) Digital Ground Digital Logic Power Supply D10, L11, Mnemonic DCLK DRVDD DRVSS VSUB VDVDD VDVSS Type1 Description2 Vertical Transfer Clock Vertical Transfer Clock Data Clock Output Data Output (LSB) Data Output Data Output Data Output Data Output Data Output Data Output Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Data Output Data Output Data Output Data Output Data Output (MSB) Vertical Driver Supply Vertical Driver High Supply Vertical Driver Supply Data Output Driver Supply Data Output Driver Ground Substrate Bias V-Driver Logic Supply V-Driver Logic Ground Internally Connected Internally Connected Internally Connected Internally Connected Internally Connected Internally Connected Internally Connected
Analog Input, Analog Output, Digital Input, Digital Output, Digital Input/Output, Power, Vertical Driver Output 2-Level, Vertical Driver Output 3-Level. Figure circuit configuration.
DVSS DVDD
Rev. Page
AD9925 TERMINOLOGY
Differential Nonlinearity (DNL) ideal exhibits code transitions that exactly apart. deviation from this ideal value. Thus, every code must have finite width. missing codes guaranteed 12-bit resolution indicates that 4096 codes, respectively, must present over operating conditions. Peak Nonlinearity Peak nonlinearity, full signal chain specification, refers peak deviation output AD9925 from true straight line. point used zero scale occurs before first code transition. Positive full scale defined Level beyond last code transition. deviation measured from middle each particular output code true straight line. error then expressed percentage full-scale signal. input signal always appropriately gained fill ADC's full-scale range. Total Output Noise output noise measured using histogram techniques. standard deviation output codes calculated represents noise level total signal chain specified gain setting. output noise converted equivalent voltage, using relationship (ADC Full Scale/2n codes) when resolution ADC. AD9925, 0.488 Power Supply Rejection (PSR) measured with step change applied supply pins. specification calculated from change data outputs given step change supply voltage.
Rev. Page
AD9925 EQUIVALENT CIRCUITS
AVDD
DVDD
04637-0-004
100k
AVSS
AVSS
DVSS
Figure RSTB Inputs
DVDD DRVDD
HVDD RGVDD
DATA
THREESTATE
DOUT
04637-0-075
Figure CCDIN
THREE-STATE
OUTPUT
04637-0-005
DVSS
DRVSS
HVSS RGVSS
Figure Digital Data Outputs Figure Drivers
DVDD
DVSS
Figure Digital Inputs
04637-0-006
Rev. Page
04637-0-007
AD9925 TYPICAL PERFORMANCE CHARACTERISTICS
3.3V
POWER DISSIPATION (mW)
3.0V 2.7V
GAIN (dB)
04637-0-084
SAMPLE RATE (MHz)
GAIN CODE (Decimal)
1000
Figure Power Sample Rate
Figure Total Output Noise Gain
-0.2 -0.4 -0.6 -0.8
04637-0-080
-1.0
1000
1500 2000 2500 3000 OUTPUT CODE
3500
4000
1000
1500 2000 2500 3000 OUTPUT CODE
3500
4000
Figure Typical Performance
Figure 13.Typical Performance
GAIN (dB)
04637-0-081
GAIN CODE (Decimal)
1000
Figure Typical Gain Curve
Rev. Page
04637-0-082
04637-0-083
AD9925
SYSTEM OVERVIEW
Figure shows typical system block diagram AD9925 used master mode. output processed AD9925's circuitry, which consists CDS, VGA, black level clamp, ADC. digitized pixel information sent digital image processor chip, which performs post-processing compression. operate CCD, timing parameters programmed into AD9925 from system microprocessor through 3-wire serial interface. From system master clock, CLI, provided image processor external crystal, AD9925 generates CCD's horizontal vertical clocks internal clocks. External synchronization provided SYNC pulse from microprocessor, which will reset internal counters re-sync outputs. AD9925 also contains optional reset pin, RSTB, which used perform asynchronous hardware reset function. Alternatively, AD9925 operated slave mode, which provided externally from image processor. this mode, AD9925 timing will synchronized with H-drivers included AD9925, allowing these clocks directly connected CCD. H-drive voltage supported. high voltage V-driver also included vertical clocks, allowing direct connection CCD. SUBCK VSUB signals require external transistors, depending used. AD9925 also includes programmable MSHUT STROBE outputs, which used trigger mechanical shutter strobe (flash) circuitry. Figure Figure show maximum horizontal vertical counter dimensions AD9925. internal horizontal vertical clocking controlled these counters, specify line pixel locations. Maximum length 8192 pixels line, maximum length 4096 lines field.
MAXIMUM COUNTER DIMENSIONS
DOUT CCDIN
V1A, V3A, V3B, V5A, V5B, SUBCK, VSUB
AD9925
AFETG V-DRIVER
DCLK
MSHUT STROBE
DIGITAL IMAGE PROCESSING ASIC
13-BIT HORIZONTAL 8192 PIXELS
SERIAL INTERFACE SYNC RSTB
04637-0-008
12-BIT VERTICAL 4096 LINES
04637-0-009
Figure Vertical Horizontal Counters Figure Typical System Block Diagram, Master Mode
LENGTH 4096 LINES
LENGTH 8192 PIXELS
Figure Maximum VD/HD Dimensions
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04637-0-010
AD9925
PRECISION TIMING HIGH SPEED TIMING GENERATION
AD9925 generates high speed timing signals using flexible Precision Timing core. This core foundation that generates timing used both AFE: reset gate (RG), horizontal drivers SHP/SHD sample clocks. unique architecture makes routine system designer optimize image quality providing precise control over horizontal readout correlated double sampling. high speed timing AD9925 operates same either master slave mode configuration. more information synchronization pipeline delays, Power-Up Synchronization section. AD9925 also includes master clock output, CLO, which inverse CLI. This output used crystal driver. crystal placed between pins generate master clock AD9925. more information using crystal, Figure
High Speed Clock Programmability
Figure shows high speed clocks SHP, generated. pulse programmable rising falling edges inverted using polarity control. horizontal clocks, have programmable rising falling edges polarity control. clocks always inverses respectively. Table summarizes high speed timing registers their parameters. Figure shows typical 2-phase H-clock arrangement which programmed same edge location edge location registers bits wide, there only valid edge locations available. Therefore, register values mapped into four quadrants, with each quadrant containing edge locations. Table shows correct register values corresponding edge locations.
Timing Resolution
Precision Timing core uses master clock input (CLI) reference. This clock should same pixel clock frequency. Figure illustrates internal timing core divides master clock period into steps edge positions. Using frequency, edge resolution Precision Timing core system clock available, also possible reference clock programming CLIDIVIDE register (Addr x30). AD9925 will then internally divide frequency two.
POSITION
P[0]
P[12]
P[24]
P[36]
P[48] P[0]
tCLIDLY
PIXEL PERIOD
Figure High Speed Clock Resolution from Master Clock Input
Rev. Page
04637-0-011
NOTES PIXEL CLOCK PERIOD DIVIDED INTO POSITIONS, PROVIDING FINE EDGE RESOLUTION HIGH SPEED CLOCKS. THERE FIXED DELAY FROM INPUT INTERNAL PIXEL PERIOD POSITION (tCLIDLY TYP)
AD9925
SIGNAL
PROGRAMMABLE CLOCK POSITIONS: RISING EDGE FALLING EDGE SAMPLE LOCATION SAMPLE LOCATION RISING EDGE POSITION FALLING EDGE POSITION INVERSE RISING EDGE POSITION FALLING EDGE POSITION INVERSE
Figure High Speed Clock Programmable Locations
Figure shows default timing locations high speed clock signals.
Digital Data Outputs
AD9925 data output DCLK phase programmable using DOUTPHASE register (Addr x37, Bits [5:0]). edge from programmed, shown Figure Normally, DOUT DCLK signals will track phase, based DOUTPHASE register contents. DCLK output phase also held fixed with respect data outputs changing DCLKMODE register high (Addr x37, [6]). this mode, DCLK output will remain fixed phase equal (the inverse CLI) while data output phase still programmable. There fixed output delay from DCLK rising edge DOUT transition, called tOD. This delay programmed four values between using DOUTDELAY register (Addr x37, Bits [8:7]). default value pipeline delay through AD9925 shown Figure After input sampled SHD, there cycle delay until data available.
H-Driver Outputs
addition programmable timing positions, AD9925 features on-chip output drivers outputs. These drivers powerful enough directly drive inputs. H-driver current adjusted optimum rise/fall time into particular load using DRVCONTROL register (Addr x35). 3-bit drive setting each output adjustable increments, with minimum setting equal three-state maximum setting equal 30.1 shown Figure Figure Figure outputs inverses respectively. H1/H2 crossover voltage approximately output swing. crossover voltage programmable.
Table Timing Core Register Parameters SHP/SHD
Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength Length Range High/Low Edge Location Edge Location Edge Location Current Steps Description Polarity Control Inversion, Inversion) Positive Edge Location Negative Edge Location Sampling Location Internal Signals Drive Current Outputs (4.1 Step)
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04637-0-012
AD9925
SIGNAL
H1/H3
H2/H4
04637-0-013
NOTE USING SAME TOGGLE POSITIONS GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 2-Phase H-Clock Operation
Table Precision Timing Edge Locations
Quadrant Edge Location (Dec) Register Value (Dec) Register Value (Bin) 000000 001011 010000 011011 100000 101011 110000 111011
POSITION
P[0]
P[12]
P[24]
P[36]
P[48] P[0]
PIXEL PERIOD RGr[0] RGf[12]
Hr[0] H1/H3
Hf[24]
H2/H4
SHP[24] SIGNAL
SHD[48]
NOTES SIGNAL EDGES FULLY PROGRAMMABLE POSITIONS WITHIN PIXEL PERIOD. DEFAULT POSITIONS EACH SIGNAL SHOWN.
Figure High Speed Timing Default Locations
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04637-0-014
AD9925
P[0] PIXEL PERIOD P[12] P[24] P[36] P[48] P[0]
DCLK
DOUT
NOTES DATA OUTPUT (DOUT) DCLK PHASE ADJUSTABLE WITH RESPECT PIXEL PERIOD. WITHIN CLOCK PERIOD, DATA TRANSITION PROGRAMMED DIFFERENT LOCATIONS. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE DOUT RISING EDGE PROGRAMMABLE.
Figure Digital Output Phase Adjustment
tCLIDLY
CCDIN SAMPLE PIXEL (INTERNAL) N+10 N+11 N+12 N+13
DCLK PIPELINE LATENCY CYCLES DOUT N-13 N-12 N-11 N-10
04637-0-016
NOTES DEFAULT TIMING VALUES SHOWN: SHDLOC DOUT PHASE DCLKMODE HIGHER VALUES AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION RIGHT, WITH RESPECT LOCATION
Figure Digital Data Output Pipeline Delay
HORIZONTAL CLAMPING BLANKING
AD9925's horizontal clamping blanking pulses fully programmable suit variety applications. Individual control provided CLPOB, PBLK, HBLK during different regions each field. This allows dark pixel clamping blanking patterns changed each stage readout, which accommodates different image transfer timing high speed line shifts. divide readout field into different regions. different vertical sequence assigned each region, allowing CLPOB PBLK signals changed accordingly with each change vertical timing.
CLPOB Masking Area
Additionally, AD9925 allows CLPOB signal disabled during certain lines field, without changing existing CLPOB pattern settings. There ways CLPOB masking. First, CLPOBMASK registers used specify individual lines within field. These lines will contain active CLPOB pulse. CLPMASKTYPE this mode operation. Second, CLPMASK registers used specify blocks adjacent lines. CLPMASK start line values programmed specify starting ending lines field where CLPOB patterns will ignore. There three sets start values, allowing three CLPOB masking areas created. CLPMASKTYPE high this mode operation.
Individual CLPOB PBLK Patterns
horizontal timing consists CLPOB PBLK, shown Figure These signals independently programmed using registers Table SPOL start polarity signal, TOG1 TOG2 first second toggle positions pulse. Both signals active should programmed accordingly. separate pattern CLPOB PBLK programmed each vertical sequences. described Vertical Timing Generation section, separate vertical sequences created, each containing unique pulse pattern CLPOB PBLK. Figure shows sequence change positions
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04637-0-015
AD9925
CLPOB masking registers specific certain vertical-sequence; they always active existing field timing. disable CLPOB masking feature, these registers should maximum value 0xFFF (default value). larity horizontal clock signals during blanking period. Setting HBLKMASK high will High during blanking, shown Figure with CLPOB PBLK signals, HBLK registers available each vertical sequence, which allows different blanking signals used with different vertical timing sequences. additional feature ability enable H3/H4 signals remain active during HBLK. this, register Addr 0xE7 equal This feature useful output used drive (last horizontal gate) input CCD.
Individual HBLK Patterns
HBLK programmable timing shown Figure similar CLPOB PBLK. However, there start polarity control. Only toggle positions used designate start stop positions blanking period. Additionally, there polarity control HBLKMASK that designates poTable CLPOB PBLK Pattern Registers
Register SPOL TOG1 TOG2 CLPOBMASK Length Range High/Low 4095 Pixel Location 4095 Pixel Location 4095 Line Location
CLPMASKTYPE
High/Low
Description Starting Polarity CLPOB/PBLK Vertical Sequence First Toggle Position within Line Vertical Sequence Second Toggle Position within Line Vertical Sequence CLPOBMASK0 through CLPOBMASK5 specify individual lines field CLPOB pulse temporarily disabled. These registers also used specify three ranges adjacent lines, rather than individual lines. When (default), CLPOBMASK registers select individual lines field disable CLPOB pulse. When high, range masking enable, allowing three blocks adjacent lines have CLPOB signal masked. CLPOBMASK0 CLPOBMASK1 start/end first block lines, CLPOBMASK2 CLPOBMASK3 start/end second block, CLPOBMASK4 CLPOBMASK5 start/end third block.
CLPOB PBLK ACTIVE
ACTIVE
NOTES PROGRAMMABLE SETTINGS: START POLARITY (CLAMP BLANK REGION ACTIVE LOW) FIRST TOGGLE POSITION SECOND TOGGLE POSITION
Figure Clamp Preblank Pulse Placement
Table HBLK Pattern Registers
Register HBLKMASK H3HBLKOFF HBLKALT Length Range High/Low High/Low Alternation Mode Description Masking Polarity H1/H3 H1/H3 Low, H1/H3 High). Addr 0xE7, [6]. Set=1 keep H3/H4 active during HBLK pulse. Normal Enables Odd/Even Alternation HBLK Toggle Positions Disable Alternation. TOG1 TOG2 ,TOG3 TOG6 Even. TOG1to TOG2 Even, TOG3 TOG6 Odd. First Toggle Position within Line Each Vertical Sequence Second Toggle Position within Line Each Vertical Sequence Third Toggle Position within Line Each Vertical Sequence Fourth Toggle Position within Line Each Vertical Sequence Fifth Toggle Position within Line Each Vertical Sequence Sixth Toggle Position within Line Each Vertical Sequence
HBLKTOG1 HBLKTOG2 HBLKTOG3 HBLKTOG4 HBLKTOG5 HBLKTOG6
4095 Pixel Location 4095 Pixel Location 4095 Pixel Location 4095 Pixel Location 4095 Pixel Location 4095 Pixel Location
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04637-0-017
AD9925
Generating Special HBLK Patterns
There toggle positions available HBLK. Normally, only toggle positions used generate standard HBLK interval. However, additional toggle positions used generate special HBLK patterns, shown Figure pattern this example uses toggle positions generate extra groups pulses during HBLK interval. changing toggle positions, different patterns created.
Generating HBLK Line Alternation
further feature AD9925 ability alternate different HBLK toggle positions even lines. This used conjunction with vertical pattern odd/even alternation own. When written HBLKALT register, TOG1 TOG2 only used lines, while TOG3 TOG6 only used even lines. Writing HBLKALT register gives opposite result: TOG1 TOG2 used even lines while TOG3 TOG6 used lines. Vertical Timing Generation section more information.
HBLK BLANK
BLANK
04637-0-018
PROGRAMMABLE SETTINGS: FIRST TOGGLE POSITION START BLANKING SECOND TOGGLE POSITION BLANKING
Figure Horizontal Blanking (HBLK) Pulse Placement
HBLK
H1/H3
H1/H3
H2/H4
04637-0-019
NOTE POLARITY DURING BLANKING PROGRAMMABLE OPPOSITE POLARITY
Figure HBLK Masking Control
TOG1 TOG2 TOG3 TOG4 TOG5 TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
Figure Generating Special HBLK Patterns
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04637-0-020
AD9925
Increasing H-Clock Width during HBLK
AD9925 will also allow pulse width increased during HBLK interval. H-clock pulse width increase reducing H-clock frequency (see Figure 27). HBLKWIDTH register, Bank Address 0x38, 3-bit register, allowing H-clock frequency reduced 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14. reduced frequency will only occur pulses that located within HBLK area. Table HBLK Width Register
Register HBLKWIDTH Length Range 1/14 Description Controls width during HBLK fraction pixel rate same frequency pixel rate pixel frequency, i.e., doubles pulse width pixel frequency pixel frequency pixel frequency 1/10 pixel frequency 1/12 pixel frequency 1/14 pixel frequency
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure shows example layout. horizontal register contains dummy pixels, which will occur each line clocked from CCD. vertical direction, there optical black (OB) lines front readout back readout. horizontal direction pixels front back. Figure shows basic sequence layout used during effective pixel readout. pixels each line used CLPOB signals. PBLK optional often used blank digital outputs during noneffective pixels. HBLK used during vertical shift interval. HBLK, CLPOB, PBLK parameters programmed vertical sequence registers. More elaborate clamping schemes used, such adding separate sequence clamp during entire shield lines. This requires configuring separate vertical sequence reading lines.
HBLK
H1/H3 1/FPIX (1/FPIX)
H2/H4
04637-0-070
H-CLOCK FREQUENCY REDUCED DURING HBLK SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, 1/14 USING HBLKWIDTH REGISTER
Figure Generating Wide H-Clock Pulses during HBLK Interval
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AD9925
VERTICAL LINES EFFECTIVE IMAGE AREA VERTICAL LINES
PIXELS HORIZONTAL REGISTER
04637-0-021
PIXELS
DUMMY PIXELS
Figure Example Configuration
OPTICAL BLACK
CCDIN
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT SHIFT
H1/H3 H2/H4
HBLK PBLK CLPOB
05637-0-022
Figure Horizontal Sequence Example
VERTICAL TIMING GENERATION
AD9925 provides very flexible solution generating vertical timing support multiple CCDs different system architectures. vertical transfer clocks used shift each line pixels into horizontal output register CCD. AD9925 allows these outputs individually programmed into various readout configurations, using 4-step process. Figure shows overview vertical timing generated four steps. First, individual pulse patterns created using vertical pattern group registers. Second, vertical pattern groups used build sequences, where additional information added. Third, readout entire field constructed dividing field into different regions then assigning sequence each region. Each field contain seven different regions accommodate different steps readout, such high speed line shifts unique vertical line transfers. different fields created. Finally, mode register allows different fields combined into order various readout configurations.
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AD9925
CREATE VERTICAL PATTERN GROUPS (MAXIMUM GROUPS). VPAT VERTICAL SEQUENCE (VPAT0, REP)
BUILD VERTICAL SEQUENCES ADDING LINE START POSITION, REPEATS, HBLK/CLPOB PULSES (MAXIMUM VERTICAL SEQUENCES).
VPAT VERTICAL SEQUENCE (VPAT9, REP)
VERTICAL SEQUENCE (VPAT9, REP)
MODE REGISTER CONTROL WHICH FIELDS USED, WHAT ORDER (MAXIMUM FIELDS COMBINED ORDER)
BUILD EACH FIELD DIVIDING INTO DIFFERENT REGIONS ASSIGNING DIFFERENT VERTICAL SEQUENCE EACH (MAXIMUM REGIONS EACH FIELD) (MAXIMUM FIELDS) FIELD
FIELD
FIELD
FIELD REGION VERTICAL SEQUENCE REGION V-SEQUENCE REGION VERTICAL SEQUENCE REGION V-SEQUENCE REGION 2:REGION V-SEQUENCE VERTICAL SEQUENCE REGION V-SEQUENCE
FIELD
FIELD
REGION VERTICAL SEQUENCE REGION V-SEQUENCE FIELD FIELD FIELD FIELD REGION V-SEQUENCE REGION VERTICAL SEQUENCE FIELD FIELD
04637-0-023
Figure Summary Vertical Timing Generation
Rev. Page
AD9925
Vertical Pattern Groups (VPAT)
vertical pattern groups define individual pulse patterns each output signal. Table summarizes registers available generating each vertical pattern groups. start polarity (VPOL) determines starting polarity vertical sequence programmed high each output. first, second, third toggle position (XVTOG1, XVTOG2, XVTOG3) pixel locations within line where pulse transitions. fourth toggle position (XVTOG4) also available vertical pattern groups toggle positions 12-bit values, allowing their placement anywhere horizontal line. separate register, VPATSTART, specifies start position Table Vertical Pattern Group Registers
Register XVPOL XVTOG1 XVTOG2 XVTOG3 XVTOG4 VPATLEN FREEZE1 RESUME1 FREEZE2 RESUME2 Length Range High/Low 4096 Pixel Location 4096 Pixel Location 4096 Pixel Location 4096 Pixel Location 4096 Pixels 4096 Pixel Location 4096 Pixel Location 4096 Pixel Location 4096 Pixel Location Description Starting Polarity Each Output First Toggle Position within Line Each Output Second Toggle Position within Line Each Output Third Toggle Position within Line Each Output Fourth Toggle Position, Only Available Vertical Pattern Groups also Vertical Pattern Groups Total Length Each Vertical Pattern Group Holds Outputs Their Current Levels (Static Resumes Operation Outputs Finish Their Pattern Holds Outputs Their Current Levels (Static Resumes Operation Outputs Finish Their Pattern
vertical pattern groups within line (see Vertical Sequences (VSEQ) section). VPATLEN register designates total length vertical pattern group, which will determine number pixels between each pattern repetitions, when repetitions used (see Vertical Sequences (VSEQ) section). Additional VPAT groups provided Register Bank outputs. This allows AD9925 remain backward compatible with AD9995 register settings while still providing additional flexibility with CCDs.
START POSITION VERTICAL PATTERN GROUP PROGRAMMABLE VERTICAL SEQUENCE REGISTERS
PROGRAMMABLE SETTINGS EACH VERTICAL PATTERN: START POLARITY FIRST TOGGLE POSITION SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE, FOURTH TOGGLE POSITION AVAILABLE VERTICAL PATTERN GROUPS TOTAL PATTERN LENGTH OUTPUTS
Figure Vertical Pattern Group Programmability
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AD9925
Masking Using Freeze/Resume Registers
shown Figure FREEZE/RESUME registers used temporarily mask outputs. pixel locations begin masking (FREEZE) masking (RESUME) create area which vertical toggle positions ignored. pixel location specified FREEZE register, outputs will held static their current state, high low. outputs held until pixel location specified RESUME register, which point signals will continue with remaining toggle positions, exist. sets FREEZE/RESUME registers provided, allowing vertical outputs interrupted twice same line. FREEZE RESUME positions programmed vertical pattern group registers separately enabled using VMASK registers. VMASK registers described Vertical Sequences (VSEQ) section.
MASKING AREA
Figure Vertical Masking
FREEZE
MASKING AREA
RESUME
NOTES TOGGLE POSITIONS WITHIN FREEZE-RESUME MASKING AREA IGNORED. H-COUNTER CONTINUES COUNT DURING MASKING. 2.TWO SEPARATE MASKING AREAS AVAILABLE EACH VPAT GROUP, USING FREEZE1/RESUME1 FREEZE2/RESUME2 REGISTERS.
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Figure Vertical Masking Using FREEZE/RESUME Registers
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AD9925
Hold Area Using Freeze/Resume Registers
FREEZE/RESUME registers also used create hold area, which outputs temporarily held then later continued starting point where they were held. shown Figure Figure this different than VMASK, because outputs continue from where they stopped rather than continuing from where they would have been. hold area temporarily stops pixel counter outputs while v-masking allows counter continue during masking area. either hold area hold area, shown Figure Figure hold operation controlled Bank vertical sequence registers, described Vertical Sequences (VSEQ) section.
FREEZE
HOLD AREA XV1-XV6
RESUME
HOLD AREA XV7-XV8
04637-0-072 04637-0-028
NOTES WHEN HOLD V-SEQUENCE, FREEZE RESUME REGISTERS USED SPECIFY HOLD AREA BOUNDRIES. WHEN XV78HOLDEN HOLD AREA, ONLY XV1-XV6. H-COUNTER XV1-XV6 WILL STOP DURING HOLD AREA.
Figure Vertical Hold Area Using FREEZE/RESUME Registers
HOLD AREA FREEZE RESUME
NOTES WHEN HOLD VERTICAL SEQUENCE, FREEZE RESUME REGISTERS USED SPECIFY HOLD AREA BOUNDRIES. WHEN XV78HOLDEN ALSO HOLD AREA. H-COUNTER WILL STOP DURING HOLD AREA.
Figure Apply Hold Area
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AD9925
Vertical Sequences (VSEQ)
vertical sequences created selecting vertical pattern groups adding repeats, start position, horizontal clamping blanking information. vertical sequences programmed, each using registers shown Table Figure shows different registers used generate each vertical sequence. VPATSEL register selects which vertical pattern group will used given vertical sequence. basic vertical pattern group have repetitions added high speed line shifts line binning using VPATREPO VPATREPE registers. Generally, same number repetitions programmed into both registers, different number repetitions required even lines, separate values used each register (see Generating Line Alternation Vertical Sequence HBLK section). VPATSTART register specifies where line vertical pattern group will start. VMASK register used conjunction with FREEZE/RESUME registers enable optional masking vertical outputs. Either both FREEZE1/RESUME1 FREEZE2/RESUME2 registers enabled using VMASK register. line length pixels) programmable using HDLEN registers. Each vertical sequence have different line length accommodate various image readout techniques. maximum number pixels line 8192. Note that 13th (MSB) line length located separate register. Also note that last line field separately programmable using HDLAST register, located field register section. Additional vertical sequences provided Register Bank outputs. This allows AD9925 remain backward compatible with AD9995 register settings while still providing additional flexibility with CCDs. described Hold Area Using Freeze/Resume Registers section, hold registers Bank used specify hold area instead vertical masking. FREEZE/RESUME registers used define hold area. XV78HOLDEN registers used specify whether will hold area not.
Table Vertical Sequence Registers (see Table Table HBLK, CLPOB, PBLK Registers)
Register VPATSEL VMASK Length Range Vertical Pattern Group Mask Mode Description Selected Vertical Pattern Group Each Vertical Sequence. Enables Masking Outputs Locations Specified FREEZE/RESUME Registers. Mask. Enable Freeze1/Resume1. Enable Freeze2/Resume2. Enable Both Number Repetitions Vertical Pattern Group Lines. odd/even alternation required, equal VPATREPE. Number Repetitions Vertical Pattern Group Even Lines. odd/even alternation required, equal VPATREPO. Start Position Selected Vertical Pattern Group. Line Length Lines Each Vertical Sequence. Note that 13th (MSB) line length located separate register, maintain compatibility with AD9995. Enable Hold Area Instead Vertical Masking, Using FREEZE/RESUME Registers. Enable Hold Area. Disable. Enable.
VPATREPO VPATREPE VPATSTART HDLEN HOLD1 XV78HOLDEN1
4095 Repeats 4095 Repeats 4095 Pixel Location 8191 Pixels High/Low High/Low
Located Bank vertical sequence registers XV8.
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AD9925
VERTICAL PATTERN GROUP CLPOB PBLK PROGRAMMABLE SETTINGS EACH VERTICAL SEQUENCE: START POSITION LINE SELECTED VERTICAL PATTERN GROUP LINE LENGTH VERTICAL PATTERN SELECT (VPATSEL) SELECT VERTICAL PATTERN GROUP NUMBER REPETITIONS VERTICAL PATTERN GROUP NEEDED) START POLARITY TOGGLE POSITIONS CLPOB PBLK SIGNALS MASKING POLARITY TOGGLE POSITIONS HBLK SIGNAL VPAT VPAT
HBLK
Figure Vertical Sequence Programmability
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AD9925
Complete Field: Combining Vertical Sequences
After vertical sequences have been created, they combined create different readout fields. field consists seven different regions, within each region, different vertical sequence selected. Figure shows sequence change positions (SCP) designate line boundary each region, then VSEQSEL registers select which vertical sequence used during each region. Registers control outputs also included field registers. Table summarizes registers used create different fields. different fields preprogrammed using field registers. VEQSEL registers, each region, select which vertical sequences will active during each region. SWEEP registers used enable SWEEP mode during region. MULTI registers used enable multiplier mode during region. registers create line Table Field Registers
Register VSEQSEL SWEEP MULTI VDLEN HDLAST VPATSECOND SGMASK SGPATSEL SGLINE1 SGLINE2 Length Range Sequence High/Low High/Low 4095 Line 4095 Lines 8191 Pixels Vertical Pattern Group High/Low, Each Pattern No., Each 4095 Line 4095 Line Description Selected Vertical Sequence Each Region Field. Enables Sweep Mode Each Region, When High. Enables Multiplier Mode Each Region, When High. Sequence Change Position Each Region. Total Number Lines Each Field. Length Pixels Last Line Each Field. 13th (MSB) located separate register maintain compatibility with AD9995. Selected Vertical Pattern Group Second Pattern Applied During Line. High Mask Each Individual Output. XSG1 [0], XSG2 [1], XSG3 [2], XSG4 [3], XSG5 [4], XSG6 [5]. Selects Pattern Number Each Output. XSG1 [1:0], XSG2 [3:2], XSG3 [5:4], XSG4 [7:6], XSG5 [9:8], XSG6 [11:10]. Selects Line Field Where Signals Active. Selects Second Line Field Repeat Signals.
boundaries each region. VDLEN register specifies total number lines field. total number pixels line (HDLEN) specified vertical sequence registers, HDLAST register specifies number pixels last line field. Note that 13th (MSB) last line length located separate register. During sensor gate (SG) line, VPATSECOND register used second vertical pattern group outputs. SGMASK register used enable disable each individual output. There single each output, setting high will mask output setting will enable output. SGPAT register assigns four different patterns each output. individual patterns created separately using pattern registers. SGLINE1 register specifies which line field will contain outputs. optional SGLINE2 register allows same pulses repeated different line.
REGION REGION REGION REGION REGION REGION REGION
VSEQSEL0
VSEQSEL1 SGLINE
VSEQSEL2
VSEQSEL3
VSEQSEL4
VSEQSEL5
VSEQSEL6
FIELD SETTINGS: SEQUENCE CHANGE POSITIONS (SCP1 SCP6) DEFINE EACH SEVEN REGIONS FIELD VSEQSEL0 VSEQSEL6 SELECTS DESIRED VERTICAL SEQUENCE (0-9) EACH REGION SGLINE1 REGISTER SELECTS WHICH LINE FIELD WILL CONTAIN SENSOR GATE PULSE(S)
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Figure Complete Field Divided into Regions
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AD9925
Generating Line Alternation Vertical Sequence HBLK
During resolution readout, some CCDs require different number vertical clocks alternate lines. AD9925 support this using VPATREPO VPATREPE registers. This allows different number VPAT repetitions programmed even lines. Note that only number repeats different even lines, VPAT group remains same. Additionally, HBLK signal also alternated even lines. When HBLKALT register high, HBLK TOG1 HBLK TOG2 positions will used lines, while HBLK TOG3 HBLK TOG6 positions will used even lines. This allows HBLK interval adjusted even lines needed. Figure shows example VPAT repetition alternation HBLK alternation used together. also possible VPAT HBLK alternation separately.
Second Vertical Pattern Group during Active Line
Most CCDs require additional vertical timing during sensor gate (SG) line. AD9925 supports option output second vertical pattern group during line when sensor gates XSG1 XSG6 active. Figure shows typical line that includes separate sets vertical pattern group XV6. vertical pattern group start line selected same manner other regions, using appropriate VSEQSEL register. second vertical pattern group, unique line, selected using VPATSECOND register, located with field registers. start position second VPAT group uses VPATLEN register from selected VPAT registers. Because VPATLEN register used start position VPAT length, possible program multiple repetitions second VPAT group.
VPATREPO VPATREPE VPATREPO
TOG1 HBLK
TOG2
TOG3
TOG4
TOG1
TOG2
NOTES NUMBER REPEATS VERTICAL PATTERN GROUP ALTERNATED EVEN LINES HBLK TOGGLE POSITIONS ALTERNATED BETWEEN EVEN LINES, ORDER GENERATE DIFFERENT HBLK PATTERNS ODD/EVEN LINES
Figure Odd/Even Line Alteration VPAT Repetitions HBLK Toggle Positions
START POSITION SECOND VPAT GROUP USES VPATLEN REGISTER
SECOND VPAT GROUP
Figure Example Second VPAT Group during Sensor Gate Line
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AD9925
Sweep Mode Operation
AD9925 contains additional mode vertical timing operation called sweep mode. This mode used generate large number repetitive pulses that span across multiple lines. example where this mode needed start readout operation. image exposure, before image transferred sensor gate pulses, vertical interline registers should free charge. This accomplished quickly shifting charge using long series pulses from outputs. Depending vertical resolution CCD, three thousand clock cycles will needed shift charge each vertical line. This operation will span across multiple line lengths. Normally, AD9925 vertical timing must contained within line length, when sweep mode enabled, boundaries will ignored until region finished. enable sweep mode within region, program appropriate SWEEP register high. Figure shows example sweep mode operation. number vertical pulses needed will depend vertical resolution CCD. output signals generated using vertical pattern registers (shown Table 15). single pulse created using polarity toggle position registers. number repetitions then programmed match number vertical shifts required CCD. Repetitions programmed vertical sequence registers using VPATREP registers. This produces pulse train appropriate length. Normally, pulse train would truncated line length, with sweep mode enabled this region, boundaries will ignored. Figure sweep region occupies lines. After sweep mode region completed next region, normal sequence operation will resume. When using sweep mode sure region boundaries (using Sequence Change Positions) appropriate lines, prevent sweep operation from overlapping next vertical sequence.
Multiplier Mode
generate very wide vertical timing pulses, vertical region configured into multiplier region. This mode uses vertical pattern registers slightly different manner. Multiplier mode used support unusual timing requirements, such vertical pulses that wider than single line length. start polarity toggle positions still used same manner standard VPAT group programming, VPATLEN used differently. Instead using pixel counter counter) specify toggle position locations (VTOG1, VPAT group, VPATLEN multiplied with VTOG position allow very long pulses generated. calculate exact toggle position, counted pixels after start position, following equation.
Multiplier Mode Toggle Position VTOG VPATLEN
Because VTOG register multiplied VPATLEN, resolution toggle position placement reduced. VPATLEN then toggle position accuracy reduced 4-pixel steps, instead single pixel steps. Table summarizes VPAT group registers used multiplier mode operation. multiplier mode, VPATREPO VPATREPE registers should always programmed same value highest toggle position. example shown Figure illustrates this operation. first toggle position two, second toggle position nine. nonmultiplier mode, this would cause vertical sequence toggle pixel then pixel within single line. However, toggle positions multiplied VTPLEN first toggle occurs pixel count second toggle occurs pixel count Sweep mode also been enabled allow toggle positions cross line boundaries.
Table Multiplier Mode Register Parameters
Register MULTI XVPOL XVTOG1 XVTOG2 XVTOG3 VPATLEN VPATREP Length Range High/Low High/Low 4095 Pixel Location 4095 Pixel Location 4095 Pixel Location 1023 Pixels 4096 Description High Enables Multiplier Mode Starting Polarity Signal Each VPAT Group First Toggle Position Signal Each VPAT Group Second Toggle Position Signal Each VPAT Group Third Toggle Position Signal Each VPAT Group Used Multiplier Factor Toggle Position Counter VPATREPE/VPATREPO Should Same Value TOG2 TOG3
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AD9925
LINE
LINE
LINE
LINE
LINE
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REGION
REGION SWEEP REGION
REGION
Figure Example Sweep Region High Speed Vertical Shift
START POSITION VPAT GROUP STILL PROGRAMMED VERTICAL SEQUENCE REGISTERS
VPATLEN
PIXEL NUMBER
MULTIPLIER MODE VERTICAL PATTERN GROUP PROPERTIES: START POLARITY (ABOVE: STARTPOL FIRST, SECOND, THIRD TOGGLE POSITIONS (ABOVE: VTOG1 VTOG2 LENGTH VPAT COUNTER (ABOVE: VPATLEN THIS MINIMUM RESOLUTION TOGGLE POSITION CHANGES TOGGLE POSITIONS OCCUR LOCATION EQUAL (VTOG VPATLEN) SWEEP REGION ENABLED, VERTICAL PULSES ALSO CROSS BOUNDRIES, SHOWN ABOVE
Figure Example Multiplier Region Wide Vertical Pulse Timing
Vertical Sensor Gate (Shift Gate) Patterns
interline CCD, sensor gates (SG) used transfer pixel charges from light-sensitive image area into light-shielded vertical registers. From light-shield vertical registers, image then read line-by-line using vertical transfer pulses conjunction with high speed horizontal clocks. Table contains summary pattern registers. AD9925 outputs, XSG1 XSG6. Each outputs assigned four programmed patterns, using SGPATSEL registers. Each pattern generated similar manner vertical pattern groups, with programmable start polarity (SGPOL), first toggle position (SGTOG1), second toggle position (SGTOG2). active line where pulses occur programmable using SGLINE1 SGLINE2 registers. Additionally, XSG1 XSG6 outputs individually disabled using SGMASK register. individual masking allows patterns preprogrammed, appropriate pulses different fields separately enabled. maximum flexibility, SGPATSEL, SGMASK, SGLINE registers separately programmable each field. Complete Field: Combining Vertical Sequences more details. Additionally, there register Bank (Addr 0x55) that overrides masking field registers (Bank SGMASK_OVR register allows sensor gate masking changed without modifying field register values. Setting SGMASKOVR_EN high enables SGMASK override function. SGMASK_OVR register updated, masking values will update immediately.
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AD9925
Table Pattern Registers (Also Field Registers Table
Register SGPOL SGTOG1 SGTOG2 SGMASK_OVR SGMASKOVR_EN
Length
Range High/Low 4095 Pixel Location 4095 Pixel Location Individual Bits Disable/Enable
Description Sensor Gate Starting Polarity Pattern First Toggle Position Pattern Second Toggle Position Pattern Masking, Overrides Values Field Registers Enables SGMASK Fast Update
PATTERNS
Figure Vertical Sensor Gate Pulse Placement
MODE Register
MODE register single register that selects field timing AD9925. Typically, field, vertical sequence, vertical pattern group information programmed into AD9925 start-up. During operation, MODE register allows user select combination field timing meet current requirements system. advantage using MODE register conjunction with preprogrammed timing that greatly reduces system programming requirements during camera operation. Only register writes required when camera operating mode changed rather than having write vertical timing information with each camera mode change. basic still camera application might require five different fields vertical timing: draft mode operation, auto-focusing, three still image readout. register timing information five fields would loaded start-up. Then, during camera operation, MODE register Table MODE Register Data Breakdown (D23 MSB)
Total Number Fields First Field Only Fields Invalid Seventh Field Field Field Invalid Sixth Field Field Field Invalid Fifth Field Field Field Invalid
would select which field timing would active depending camera being used. Table shows MODE register bits used. three MSBs, D21, used specify many total fields will used. value from selected using these three bits. remaining register bits divided into 3-bit sections, select which fields used which order. seven fields used single MODE write. AD9925 will start with field timing specified first field bits, next will switch timing specified second field bits, After completing total number fields specified Bits D21, AD9925 will repeat starting first field again. This will continue until write MODE register occurs. Figure shows examples MODE register settings different field configurations.
D11.D10.D9 Fourth Field Field Field Invalid
D8.D7.D6 Third Field Field Field Invalid
D5.D4.D3 Second Field Field Field Invalid
D2.D1.D0 First Field Field Field Invalid
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PROGRAMMABLE SETTINGS EACH PATTERN: START POLARITY PULSE FIRST TOGGLE POSITION SECOND TOGGLE POSITION ACTIVE LINE PULSES WITHIN FIELD (PROGRAMMABLE FIELD REGISTER, EACH PATTERN)
AD9925
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD SECOND FIELD FIELD THIRD FIELD FIELD MODE REGISTER CONTENTS 0x600088 FIELD FIELD FIELD
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD SECOND FIELD FIELD MODE REGISTER CONTENTS 0x400023 FIELD FIELD
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD SECOND FIELD FIELD THIRD FIELD FIELD FOURTH FIELD FIELD MODE REGISTER CONTENTS 0x80050D FIELD FIELD FIELD FIELD
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Figure Using MODE Register Select Field Timing
VERTICAL TIMING EXAMPLE
better understand AD9925 vertical timing generation used, consider example timing chart Figure This particular example illustrates using general 3-field readout technique. described previous field section, each readout field should divided into separate regions perform each step readout. sequence change positions (SCP) determine line boundaries each region, then VSEQSEL registers will assign particular vertical sequence each region. vertical sequences will contain specific timing information required each region: pulses (using VPAT groups), HBLK/CLPOB timing, patterns active lines. This particular timing example requires four regions each three fields, labeled Region Region Region Region Because AD9925 allows individual fields programmed, Field Field Field registers used meet requirements this timing example. four regions each field very similar this example, individual registers each field allow flexibility accommodate other timing charts. Region high speed vertical shift region. Sweep mode used generate this timing operation, with desired number high speed vertical pulses needed clear charge from CCD's vertical registers. Region consists only lines uses standard single line vertical shift timing. timing this region area will same timing Region Region sensor gate line, where pulses transfer image into vertical registers. This region require second vertical pattern group active line. Region also uses standard single line vertical shift timing, same timing Region summary, four regions required each three fields. timing Region Region essentially same, reducing complexity register programming. Other registers will need used during actual readout operation, such MODE register, shutter control registers (TRIGGER, SUBCK, VSUB, MSHUT, STROBE), gain register. These registers will explained other examples.
Important Note about Signal Polarities
When programming AD9925 generate XV8, XSG1 XSG6, SUBCK signals, important note that vertical driver circuit will invert these signals. Carefully check required timing signals needed output vertical driver circuit adjust polarities signals accordingly.
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EXPOSURE (tEXP) THIRD FIELD READOUT
FIRST FIELD READOUT
SECOND FIELD READOUT
Figure Timing Example-Dividing Each Field into Regions
REGION REGION FIELD REGION
REGION
REGION REGION
REGION REGION FIELD
REGION REGION
REGION REGION FIELD
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SUBCK
MSHUT OPEN
OPEN
CLOSED
VSUB
AD9925
AD9925
SHUTTER TIMING CONTROL
image exposure time controlled substrate clock signal (SUBCK), which pulses substrate clear accumulated charge. AD9925 supports three types electronic shuttering: normal, high precision, speed shutter. Along with SUBCK pulse placement, AD9925 accommodate different readout configurations, further suppress SUBCK pulses during multiple field readouts. AD9925 also provides programmable outputs control external mechanical shutter (MSHUT), strobe/flash (STROBE), bias select signal (VSUB).
High Precision Shutter Operation
High precision shuttering used same manner normal shuttering, uses additional register control very last SUBCK pulse. this mode, SUBCK still pulses once line, last SUBCK field will have additional SUBCK pulse, whose location determined SUBCK2TOG register, shown Figure Finer resolution exposure time possible using this mode. Leaving SUBCK2TOG register maximum value will disable last SUBCK pulse (default setting).
Speed Shutter Operation
Normal high precision shutter operations used when exposure time less than field long. long exposure times greater than field interval, speed shutter operation used. AD9925 uses separate exposure counter achieve long exposure times. number fields speed shutter operation specified EXPOSURE register (Addr 0x62). shown Figure this shutter mode will suppress SUBCK outputs 4095 fields periods). outputs suppressed during exposure period programming VDHDOFF register generate speed shutter operation, necessary trigger start long exposure writing TRIGGER Register When this high, next edge, AD9925 will begin exposure operation. value greater than specified EXPOSURE register, AD9925 will suppress SUBCK output subsequent fields. exposure generated using TRIGGER register, EXPOSURE register then behavior SUBCK will different than normal shutter high precision shutter operations, which TRIGGER register used.
Normal Shutter Operation
default, AD9925 always operating normal shutter configuration, which SUBCK signal pulsing every field (see Figure 45). SUBCK pulse occurs once line, total number repetitions within field will determine length exposure time. SUBCK pulse polarity toggle positions within line programmable using SUBCKPOL SUBCK1TOG registers (see Table 19). number SUBCK pulses field programmed SUBCKNUM register (Addr 0x63). shown Figure SUBCK pulses will always begin line following active line, which specified SGACTLINE registers each field. SUBCKPOL, SUBCK1TOG, SUBCK2TOG, SUBCKNUM, SUBCKSUPPRESS registers updated start line after sensor gate line, described Updating Register Values section.
tEXP
SUBCK
tEXP
SUBCK PROGRAMMABLE SETTINGS: PULSE POLARITY USING SUBCKPOL REGISTER NUMBER PULSES WITHIN FIELD USING SUBCKNUM REGISTER (SUBNUM=3 ABOVE EXAMPLE) PIXEL LOCATION PULSE WITHIN LINE PULSE WIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER
Figure Normal Shutter Mode
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AD9925
tEXP
SUBCK NOTES SUBCK PULSE ADDED LAST SUBCK LINE. LOCATION PULSE FULLY PROGRAMMABLE USING SUBCK2 TOGGLE POSITION REGISTER.
tEXP
Figure High Precision Shutter Mode
TRIGGER EXPOSURE
tEXP
SUBCK NOTES SUBCK SUPPRESSED MULTIPLE FIELDS PROGRAMMING EXPOSURE REGISTER GREATER THAN ZERO. ABOVE EXAMPLE USES EXPOSURE TRIGGER REGISTER MUST ALSO USED START SPEED EXPOSURE. VD/HD OUTPUTS ALSO SUPPRESSED USING VDHDOFF REGISTER
Figure Speed Shutter Mode Using EXPOSURE Register
Table Shutter Mode Register Parameters
Register TRIGGER READOUT EXPOSURE VDHDOFF SUBCKPOL1 SUBCK1TOG1 SUBCK2TOG1 SUBCKNUM1 SUBCKSUPPRESS1 Length Range On/Off Five Signals Fields 4095 Fields On/Off High/Low 4095 Pixel Locations 4095 Pixel Locations 4095 Pulses 4095 Pulses Description Trigger VSUB[0], MSHUT[1], STROBE[2], Exposure[3], Readout Start Number Fields Suppress SUBCK after Exposure Number Fields Suppress SUBCK during Exposure Time (Low Speed Shutter) Disable VD/HD Output during Exposure Off) SUBCK Start Polarity SUBCK1 SUBCK2 Toggle Positions First SUBCK Pulse (Normal Shutter) Toggle Positions Second SUBCK Pulse Last Line (High Precision) Total Number SUBCKs Field, Pulse Line Number Lines Further Suppress SUBCK after Line
Register updated updated start line after sensor gate line.
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AD9925
SUBCK Suppression
Normally, SUBCKs will begin pulse line following sensor gate line (VSG). With some CCDs, SUBCK pulse needs suppressed more lines following line. SUBCKSUPPRESS register allows suppression SUBCK pulses additional lines following line. possible independently trigger readout operation without triggering exposure operation. This will cause readout occur next SUBCK output will suppressed according value READOUT register. TRIGGER register also used control STROBE, MSHUT, VSUB signal transitions. Each these signals individually controlled, although they will dependent triggering exposure readout operation. Figure complete example triggering exposure readout operations.
Readout after Exposure
After exposure, readout data occurs, beginning with sensor gate (VSG) operation. default, AD9925 generating pulses every field. case where only single exposure single readout frame needed, such CCD's preview mode, SUBCK pulses operate every field. However, many cases, during readout SUBCK output needs further suppressed until readout completed. READOUT register specifies number additional fields after exposure continue suppression SUBCK. READOUT programmed additional fields should preprogrammed start-up, same time exposure write. typical interlaced frame readout mode will generally require additional fields SUBCK suppression (READOUT 3-field, 6-phase will require three additional fields SUBCK suppression after readout begins (READOUT SUBCK output required start back during last field readout, simply program READOUT register less than total number readout fields. Like exposure operation, readout operation must triggered using TRIGGER register.
VSUB Control
readout bias (VSUB) programmed accommodate different CCDs. Figure shows different modes that available. Mode VSUB goes active during field last SUBCK when exposure begins. position (rising edge Figure programmable line within field. VSUB will remain active until image readout. Mode VSUB activated until start readout. additional function called VSUB keep-on also available. When this high, VSUB output will remain (active) even after readout finished. disable VSUB later time, this back low.
MSHUT STROBE Control
MSHUT STROBE operation shown Figure Figure Figure Table shows registers parameters controlling MSHUT STROBE outputs. MSHUT output switched with MSHUTON registers, will remain until location specified MSHUTOFF registers. location MSHUTOFF fully programmable anywhere within exposure period, using (field), (line), (pixel) registers. STROBE pulse defined positions. STROBON_FD field which STROBE turned measured from field containing last SUBCK before exposure begins. STROBON_ register gives line pixel positions with respect STROBON_FD. STROBE position programmable field, line, pixel location with respect field last SUBCK.
Using TRIGGER Register
described above, default, AD9925 will output SUBCK signals every field. This works well continuous single field exposure readout operations, such CCD's live preview mode. However, requires longer exposure time, multiple readout fields needed, TRIGGER register needed initiate specific exposure readout sequences. Typically, exposure readout bits TRIGGER register used together. This will initiate complete exposure-plus readout operation. Once exposure been completed, readout will automatically occur. values EXPOSURE READOUT registers will determine length each operation.
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AD9925
TRIGGER VSUB
tEXP
SUBCK VSUB MODE MODE
READOUT
VSUB OPERATION: ACTIVE POLARITY POLARITY (ABOVE EXAMPLE VSUB ACTIVE HIGH) ON-POSITION PROGRAMMABLE, MODE TURNS START EXPOSURE, MODE TURNS START READOUT OFF-POSITION OCCURS READOUT OPTIONAL VSUB KEEP-ON MODE WILL LEAVE VSUB ACTIVE READOUT
Figure VSUB Programmability
TRIGGER EXPOSURE MSHUT
tEXP
SUBCK
MSHUT
MSHUT PROGRAMMABLE SETTINGS: ACTIVE POLARITY ON-POSITION UPDATED SWITCHED TIME OFF-POSITION PROGRAMMED ANYWHERE FROM FIELD LAST SUBCK UNTIL FIELD BEFORE READOUT
Figure MSHUT Output Programmability
TRIGGER Register Limitations
While TRIGGER register used perform complete exposure readout operation, there limitations use. Once exposure-plus readout operation been triggered, another exposure/readout operation cannot triggered right away. There must least idle field intervals) before next exposure/readout triggered again. same limitation applies triggering MSHUT signal. There must least idle field after completion MSHUT operation before another MSHUT operation programmed.
VSUB trigger requires idle fields between exposure/readout operations order ensure proper VSUB on/off triggering. VSUB signal required turned between each successive exposure/readout operation, then this limitation ignored. Using VSUB keep-on mode useful when successive exposure/readout operations required.
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AD9925
TRIGGER EXPOSURE STROBE
tEXP
SUBCK
STROBE STROBE PROGRAMMABLE SETTINGS: ACTIVE POLARITY ON-POSITION PROGRAMMABLE FIELD DURING EXPOSURE TIME (WITH RESPECT FIELD CONTAINING LAST SUBCK) OFF-POSITION PROGRAMMABLE FIELD DURING EXPOSURE TIME
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Figure STROBE Output Programmability
Table VSUB, MSHUT, STROBE Register Parameters
Register VSUBMODE[0] VSUBMODE[1] VSUBON[11:0] VSUBON[12] MSHUTPOL[0] MSHUTPOL[1] MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX Length Range High/Low High/Low 4095 Line Location High/Low High/Low On/Off 4095 Line/Pix Location 4095 Field Location 4095 Line/Pix Location High/Low 4095 Field Location 4095 Line/Pix Location 4095 Field Location 4095 Line/Pix Location Description VSUB Mode Mode Mode (See Figure 44). VSUB Keep-On Mode. VSUB Will Stay Active after Readout When High. VSUB Position. Active Starting Line Field. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable Active Open). MSHUT Position Line [11:0] Pixel [23:12] Location. Field Location Switch MSHUT. (Inactive Closed). Line/Pixel Position Switch MSHUT. (Inactive Closed). STROBE Active Polarity. STROBE Field Location, with Respect Last SUBCK Field. STROBE Line/Pixel Position. STROBE Field Location, with Respect Last SUBCK Field. STROBE Line/Pixel Position.
Rev. Page
SERIAL WRITES
STILL IMAGE READOUT
SUBCK
tEXP
STROBE
EXAMPLE EXPOSURE READOUT INTERLACED FRAME
Figure Example Exposure Still Image Readout Using Shutter Signals Mode Register
Rev. Page
OPEN CLOSED MODE MODE STILL IMAGE FIRST FIELD DRAFT IMAGE
MSHUT
MECHANICAL SHUTTER
OPEN
VSUB
STILL IMAGE SECOND FIELD STILL IMAGE THIRD FIELD DRAFT IMAGE
DRAFT IMAGE
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AD9925
AD9925
Write READOUT register (Addr x61) specify number fields further suppress SUBCK while data readout. this example, READOUT Write EXPOSURE register (Addr x62) specify number fields suppress SUBCK outputs during exposure. this example, EXPOSURE Write TRIGGER register (Addr x60) enable STROBE, MSHUT, VSUB signals start exposure/readout operation. trigger these events Figure register TRIGGER Readout will automatically occur after exposure period finished. Write MODE register (x1B) configure next five fields. first fields during exposure same current draft mode fields, following three fields still frame readout fields. registers draft mode field three readout fields have already been programmed. VD/HD falling edge will update serial writes from VSUB mode (Addr x67), VSUB output turns line specified VSUBON register (Addr x68). STROBE output turns location specified STROBEON STROBEOFF registers (Addr x71). MSHUT output turns location specified MSHUTOFF registers (Addr x6C). next falling edge will automatically start first readout field. next falling edge will automatically start second readout field. next falling edge will automatically start third readout field. Write MODE register reconfigure single draft mode field timing. Write MSHUTON register (Addr x6A) open mechanical shutter.
VD/HD falling edge will update serial writes from outputs return draft mode timing. SUBCK output resumes operation. MSHUT output returns position (active open). VSUB output returns position (inactive).
Rev. Page
AD9925
FG_TRIG OPERATION
AD9925 contains additional signal that used conjunction with shutter operation general system operation. FG_TRIG signal internally generated pulse that output VSUB SYNC pins system combined with VSUB registers create four-toggle VSUB signal. FG_TRIG signal generated using start polarity first second toggle position registers, programmable with line pixel resolution. field placement FG_TRIG pulse matched field count specified MODE register operation. FG_TRIGEN register contains 3-bit value specify which field count will contain FG_TRIG pulse. Figure shows FG_TRIG pulse generated using these registers. After FG_TRIG signal specified, enable using FG_TRIGEN register. default, FG_TRIG will mapped SYNC output, long SYNC configured output (SYNCENABLE Alternatively, FG_TRIG pulse mapped VSUB output writing SHUT_EXTRA Register Table FG_TRIG Operation Registers
Register SYNCENABLE VSUBON SHUT_EXTRA Address 0x12 0x68 0xE7 Width [12:0] [8:0] Description Configures SYNC Output. default, FG_TRIG signal outputs SYNC pin. Controls VSUB Position Polarity. When SHUT_Extra FG_TRIG toggles combined with VSUB signal. Selects Whether FG_TRIG Signal Used with VSUB. [2:0] send FG_TRIG signal VSUB pin. [7:4] combine FG_TRIG VSUB signals. FG_TRIG Enable. [2:0] Selects field count pulse (based mode field counter). enable FG_TRIG signal output. FG_TRIG Start Polarity. FG_TRIG First Toggle Position, Line Location. FG_TRIG First Toggle Position, Pixel Location. FG_TRIG Second Toggle Position, Line Location. FG_TRIG Second Toggle Position, Pixel Location.
final application FG_TRIG signal combine with existing VSUB signal, generate additional toggle positions. setting SHUT_EXTRA VSUB toggles FG_TRIG toggles XOR'd together sent VSUB output. Figure Figure show this application more detail.
FG_TRIG INTERNAL VSUB INTERNAL SHUT_EXTRA[3] SHUT_EXTRA[8]
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VSUB OUTPUT
Figure Combining Internal FG_TRIG Internal VSUB Signals
FG_TRIGEN
0xEB
[3:0]
FG_TRIGPOL FG_TRIGLINE1 FG_TRIGPIX1 FG_TRIGLINE2 FG_TRIGPIX2
0xF2 0xF3 0xF4 0xF5 0xF6
[11:0] [12:0] [11:0] [12:0]
MODE REGISTER FIELD COUNT
FIELD
FIELD
FIELD
FIELD
FIELD
FG_TRIG
FG_TRIG PROGRAMMABLE SETTINGS: ACTIVE POLARITY FIRST TOGGLE POSITION, LINE PIXEL LOCATION SECOND TOGGLE POSITION, LINE PIXEL LOCATION FIELD PLACEMENT BASED MODE REGISTER FIELD COUNT
Figure Generating FG_TRIG Signal
Rev. Page
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AD9925
VSUB INTERNAL FG_TRIG INTERNAL VSUB SHUT_XTRA[8]=0 VSUB SHUT_XTRA[8]=1
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Figure Combining FG_TRIG VSUB Create Four Toggle Positions VSUB Output
Rev. Page
AD9925
1.0µF 1.0µF REFB REFT RESTORE 1.5V 1.0V 2.0V
AD9925
INTERNAL VREF DOUT PHASE 42dB FULL SCALE OUTPUT DATA LATCH DOUT
0.1µF
CCDIN
12-BIT
GAIN REGISTER
OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER
DOUT PHASE
CLPOB
PBLK
CLAMP LEVEL REGISTER
Figure Analog Front-End Functional Block Diagram
ANALOG FRONT-END DESCRIPTION OPERATION
AD9925 signal processing chain shown Figure Each processing step essential achieving high quality image from pixel data. gain curve follows linear-in-dB characteristic. exact gain calculated gain register value using equation
Restore
reduce large offset output signal, restore circuit used with external series coupling capacitor. This restores level signal approximately compatible with supply voltage AD9925.
Gain (dB) (0.0351 Code)
where Code range 1023.
Correlated Double Sampler
circuit samples each pixel twice extract video information reject frequency noise. timing shown Figure illustrates internally generated clocks, SHD, used sample reference level level signal, respectively. placement sampling edges determined setting SAMPCONTROL register located Addr 0x63. Placement these clock signals critical achieving best performance from CCD.
GAIN (dB)
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PRECISION TIMING GENERATION
TIMING GENERATION
GAIN REGISTER CODE 1023
Variable Gain Amplifier
stage provides gain range programmable with 10-bit resolution through serial digital interface. minimum gain needed match input signal with full-scale range When compared full-scale systems, equivalent gain range
Rev. Page
Figure Gain Curve
04637-0-046
AD9925
AD9925 uses high performance architecture, optimized high speed power. Differential nonlinearity (DNL) performance typically better than LSB. uses input range. Figure Figure typical linearity noise performance plots AD9925. CLPOB pulse should placed during CCD's optical black pixels. recommended that CLPOB pulse duration least pixels wide. Shorter pulse widths used, ability track frequency variations black level will reduced. Horizontal Clamping Blanking section timing examples.
Optical Black Clamp
optical black clamp loop used remove residual offsets signal chain track frequency variations CCD's black level. During optical black (shielded) pixel interval each line, output compared with fixed black level reference, selected user clamp level register. value programmed between steps. resulting error signal filtered reduce noise, correction value applied input through DAC. Normally, optical black clamp loop turned once horizontal line, this loop updated more slowly suit particular application. external digital clamping used during post-processing, AD9925 optical black clamping disabled using OPRMODE register. When loop disabled, clamp level register still used provide programmable offset adjustment.
Digital Data Outputs
AD9925digital output data latched using DOUT PHASE register value, shown Figure Output data timing shown Figure Figure also possible leave output latches transparent, that data outputs valid immediately from ADC. Programming CONTROL Register will output latches transparent. data outputs also disabled (three-stated) setting CONTROL Register data output coding normally straight binary, coding changed gray coding setting CONTROL Register
Rev. Page
AD9925
VERTICAL DRIVER SIGNAL CONFIGURATION
shown Figure XV8, XSG1 XSG6, XSUBCK outputs from internal AD9925 timing generator, SUBCK resulting outputs from AD9925 vertical driver. vertical driver performs mixing pulses amplifies them high voltages required driving CCD. Additionally, vertical driver outputs inverted from internal XSG, SUBCK polarities configured AD9925 registers. Table Table describe output polarities these signal versus their input levels. These tables must referred when determining register settings desired output levels. Figure Figure show graphically relationship between polarities signals inverted vertical driver output signals. Table Output Polarity
Vertical Driver Input XSG1 Output
Table Output Polarity
Vertical Driver Input XSG6 Output
Table Output Polarity
Vertical Driver Input XSG2 Output
AD9925
VERTICAL DRIVER XSG1 XSG6 XSG2 XSG3 INTERNAL TIMING GENERATOR XSG4 XSG5 2-LEVEL OUTPUTS 3-LEVEL OUTPUTS +15V, -7.5V
XSUBCK
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SUBCK
Figure AD9925 Internal Vertical Driver Input Signals
Rev. Page
AD9925
Table Output Polarity
Vertical Driver Input XSG3 Output
Table Output Polarity
Vertical Driver Input Output
Table Output Polarity Table Output Polarity
Vertical Driver Input Output Vertical Driver Input Output
Table Output Polarity Table Output Polarity
Vertical Driver Input XSG4 Output Vertical Driver Input Output
Table SUBCK Output Polarity
Vertical Driver Input XSUBCK SUBCK Output
Table Output Polarity
Vertical Driver Input XSG5 Output
Rev. Page
AD9925
XSG1
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Figure XV1, XSG1, Output Polarities
XSG6
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Figure XV2, XSG6, Output Polarities
XSG2
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Figure XV3, XSG2, Output Polarities
XSG3
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Figure XV3, XSG3, Output Polarities
Rev. Page
AD9925
XSG4
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Figure XV5, XSG4, Output Polarities
XSG5
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Figure XV5, XSG5, Output Polarities
XV4, XV6, XV7,
Figure XV4, XV6, XV7, Output Polarities
Rev. Page
04637-0-054
AD9925
POWER-UP SYNCHRONIZATION
Vertical Driver Power Supply Sequencing
recommended Power_Up Power_Down sequences shown Figure Figure respectively. shown, voltage level should never exceed voltage level during power-up power-down. Excessive current will result this requirement meet junction diode turning between VM1/VM2 supply pins.
12.0V 15.0V
VDVDD DVDD DRVDD HVDD RGVDD TCVDD AVDD 3.0V
-1.0V -0.5V
SAME TIME LATER EARLIER BEFORE REACHES 3.0V.
Figure AD9925 Power-Up Sequence
VDVDD DVDD DRVDD HVDD RGVDD TCVDD AVDD
04637-0-056
SAME TIME EARLIER, AFTER VDD.
Figure AD9925 Power-Down Sequence
Rev. Page
04637-0-055
-7.5V
AD9925
15.0V VDVDD DVDD DRVDD HVDD RGVDD TCVDD AVDD POWER SUPPLIES -7.5V (INPUT) SERIAL WRITES SYNC (INPUT)
tSYNC
FIELD
(OUTPUT)
(OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, DCLK CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER UPDATED VD/HD EDGE
04637-0-069
Figure Recommended Power-Up Sequence Synchronization, Master Mode
Recommended Power-Up Sequence Master Mode
When AD9925 powered following sequence recommended (refer Figure each step). Note that SYNC signal required master mode operation. external SYNC pulse available, also possible generate internal SYNC pulse writing SYNCPOL register, described next section. Turn power supplies AD9925 apply master clock CLI. Reset internal AD9925 registers writing SW_RESET register (Addr 0x10 Bank Write standby mode polarity registers 0x0A 0x0D proper polarities V-driver inputs, order avoid damage CCD. Table settings. V-driver supplies powered anytime after completing Step proper polarities. default, AD9925 STANDBY3 mode. place part into normal power operation, write 0x004 OPRMODE register (Addr 0x00 Bank Write BANKSELECT register (Addr This will select Register Bank Load Bank registers with required VPAT group, vertical sequence, field timing information. Write BANKSELECT register select Bank default, internal timing core held reset state with TGCORE_RSTB register Write TGCORE_RSTB register (Addr 0x15 Bank start internal timing core operation. Note: clock used input, CLIDIVIDE register (Addr 0x30) should before resetting timing core. Load required registers configure high speed timing, horizontal timing, shutter timing information.
Configure AD9925 master mode timing writing MASTER register (Addr 0x20 Bank Write OUT_CONTROL register (Addr 0x11 Bank 1).This will allow outputs become active after next SYNC rising edge. Generate SYNC event: SYNC high power-up, then bring SYNC input minimum Then bring SYNC back high. This will cause internal counters reset will start VD/HD operation. first VD/HD edge allows most Bank register updates occur, including OUT_CONTROL enable outputs.
Rev. Page
AD9925
Table Power-Up Register Write Sequence
Address 0x10 0x0A 0x0D 0x00 0x7F 0x00 0xFF 0x7F 0x15 0x31 0x71 0x20 0x11 0x13 Data 0x01 0x04 0x01 0x00 0x01 0x01 0x01 0x01 Description Reset Registers Default Values Standby V-Driver Input Signal Polarities Power-Up Oscillator Select Register Bank VPAT, Vertical Sequence, Field Timing Select Register Bank Reset Internal Timing Core Horizontal Shutter Timing Configure Master Mode Enable Outputs after SYNC SYNCPOL (for Software SYNC Only)
Power-Up Synchronization Slave Mode
power-up procedure SLAVE mode operation same procedure described MASTER mode operation, with exceptions: Eliminate Step write part into Master mode. SYNC pulse required SLAVE mode. Substitute Step with starting external signals. This will synchronize part, allow Bank register updates, start timing operation.
When AD9925 used SLAVE mode, inputs used synchronize internal counters. Following falling edge there will latency master clock edges (CLI) after falling edge until internal H-Counter will reset. reset operation shown Figure
Generating Software SYNC Without External SYNC Signal
external SYNC pulse available, possible generate internal SYNC AD9925 writing SYNCPOL register (Addr 0x13). software SYNC option used, SYNC input (Pin should tied ground (VSS). After power-up, follow same procedure before, Steps through Then, Step instead using external SYNC pulse, write SYNCPOL register. This will generate SYNC internally, timing operation will begin.
Vertical Toggle Position Placement Near Counter Reset
additional consideration during reset internal counters vertical toggle position placement. Prior internal counters being reset, there region pixels during which toggle positions should programmed. master mode, last pixels before falling edge should used toggle position placement XSG, SUBCK, HBLK, PBLK, CLPOB pulses (see Figure 70). Figure shows same example slave mode. same restriction applies, last pixels before counters reset cannot used. However, slave mode, counter reset delayed with respect VD/HD placement; therefore, inhibited area different than master mode.
SYNC During Master Mode Operation
SYNC input used time during operation resync AD9925 counters with external timing, shown Figure operation digital outputs suspended during SYNC operation setting SYNCSUSPEND register (Addr 0x14)
Additional Considerations Toggle Positions
addition avoiding toggle position placement near counter reset location, there couple other recommendations. Pixel location should used toggle positions SUBCK pulses. Also, propagation delay V-driver circuit should considered when programming toggle positions XSG, SUBCK pulses. delay V-driver circuit specified Table maximum
Rev. Page
AD9925
SYNC
SUSPEND
H124, VSG, SUBCK NOTES SYNC RISING EDGE RESETS VD/HD COUNTERS ZERO. SYNC POLARITY PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). DURING SYNC LOW, INTERNAL COUNTERS RESET VD/HD SUSPENDED USING SYNCSUSPEND REGISTER (ADDR 0x14). SYNCSUSPEND VERTICAL CLOCKS, HELD THEIR DEFAULT POLARITIES. SYNCSUSPEND CLOCK OUTPUTS CONTINUE OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure SYNC Timing Synchronize AD9925 with External Timing
H-COUNTER RESET
H-COUNTER (PIXEL COUNTER)
04637-0-076
NOTE INTERNAL H-COUNTER RESET CLOCK EDGES AFTER FALLING EDGE.
Figure External VD/HD Internal H-Counter Synchronization, Slave Mode
H-COUNTER RESET TOGGLE POSITIONS ALLOWED THIS AREA H-COUNTER (PIXEL COUNTER)
N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10
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NOTE TOGGLE POSITIONS CANNOT PROGRAMMED WITHIN PIXELS PIXEL LOCATION
Figure Toggle Position Inhibit Area, Master Mode
H-COUNTER RESET TOGGLE POSITIONS ALLOWED THIS AREA
H-COUNTER (PIXEL COUNTER)
N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10
04637-0-078
NOTE TOGGLE POSITIONS CANNOT PROGRAMMED WITHIN PIXELS PIXEL LOCATION
Figure Toggle Position Inhibit Area, Slave Mode
Rev. Page
04637-0-058
AD9925
STANDBY MODE OPERATION
AD9925 contains three different standby modes optimize overall power dissipation particular application. Bits [1:0] OPRMODE register control power-down state device: OPRMODE[1:0] Normal Operation (Full Power) OPRMODE[1:0] STANDBY1 Mode OPRMODE[1:0] STANDBY2 Mode OPRMODE[1:0] STANDBY3 Mode (Lowest Overall Power) Table Table summarize operation each powerdown mode. Note that OUT_CONTROL register takes priority over STANDBY1 STANDBY2 modes determining digital output states, STANDBY3 mode takes Table Standby Mode Operation
Block Timing Core Oscillator DCLK DOUT STANDBY3 (Default)1, High Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z OUT_CONT= LO2, Change Change Change Running High High VDHDPOL Value VDHDPOL Value STANDBY23, Running (4.3 High (4.3 (4.3 High (4.3 (4.3 VDHDPOL Value VDHDPOL Value STANDBY13, Only REFT, REFB Running (4.3 High (4.3 (4.3 High (4.3 (4.3 Running Running Running
priority over OUT_CONTROL. STANDBY3 lowest power consumption even shuts down crystal oscillator circuit between CLO. Thus, being used with crystal generate master clock, this circuit will powered down there will clock signal. When returning from STANDBY3 mode normal operation, timing core must reset least after OPRMODE register written This will allow sufficient time crystal circuit settle. shutter outputs also programmed hold specific value during Standby modes, detailed Table
exit STANDBY3, first write OPRMODE[1:0], then reset timing core after ~500 guarantee proper settling oscillator. STANDBY3 mode takes priority over OUT_CONTROL determining output polarities. These polarities assume OUT_CONT High., because OUT_CONTROL takes priority over STANDBY1 STANDBY2. STANDBY1 STANDBY2 will drive strength minimum value (4.3 mA).
Rev. Page
AD9925
Table Standby Mode Operation-Vertical Shutter Outputs (Programmable Polarities Available)
Block XSG6 XSG5 XSG4 XSG3 XSG1 XSG2 SUBCK VSUB MSHUT STROBE STANDBY3 (Default)1, OUT_CONT Low2, High High High High High High High High High High High STANDBY23 High High High High High High High High High High High STANDBY13 High High High High High High High High High High High
Polarities vertical shutter outputs programmable each standby mode, using STBYPOL registers. Default register values are: STBY3POL 00000000000000000 0x00 OCONTPOL STBY2POL STBY1POL 000011111111111000 0x3FF8 assignments programming polarity registers: (MSB) XV1, XV8, XV3, XV7, XV6, XSG6, XV5, XV4, XSG5, XSG4, XV2, XSG3, XSG1, XSG2, SUBCK, VSUB, MSHUT, STROBE (LSB).
Rev. Page
AD9925
CIRCUIT LAYOUT INFORMATION
AD9925 typical circuit connections shown Figure layout critical achieving good image quality from AD9925. supply pins, particularly AVDD1, TCVDD, RGVDD, HVDD supplies, must decoupled ground with good quality high frequency chip capacitors. decoupling capacitors should located close possible supply pins should have very impedance path continuous ground plane. There should also larger value bypass capacitor near each main supply-AVDD, HVDD, DRVDD, although this necessary each individual pin. most applications, easier share supply RGVDD HVDD, which done long individual supply pins separately bypassed. separate supply also used DRVDD, this supply should still decoupled same ground plane rest chip. separate ground DRVSS recommended. analog bypass pins (REFT REFB) should also carefully decoupled ground close possible their respective pins. analog input (CCDIN) capacitor should also located close pin.
20pF
traces should designed have inductance avoid excessive distortion signals. Heavier traces recommended, because large transient current demand CCD. possible, physically locating AD9925 closer will reduce inductance these lines. always, routing path should direct possible from AD9925 CCD. AD9925 also contains on-chip oscillator driving external crystal. Figure shows example application using typical crystal. exact values external resistors capacitors, best consult with crystal manufacturer's data sheet.
AD9925
20pF
04637-0-060
24MHz XTAL
Figure Crystal Driver Application
Rev. Page
AD9925
HORIZONTAL SYNC TO/FROM ASIC/DSP ANALOG SUPPLY 0.1µF -7.5V SUPPLY +15V SUPPLY 0.1µF 0.1µF
STROBE
VERTICAL SYNC TO/FROM ASIC/DSP VERTICAL CLOCK OUTPUTS CCD) STROBE CIRCUIT SERIAL INTERFACE (FROM ASIC/DSP)
DVDD
DVSS
DCLK ASIC/DSP
DCLK (LSB)
RSTB SUBCK MSHUT REFB REFT AVDD CCDIN AVSS AVSS TCVSS TCVSS SYNC TCVDD TCVDD RGVDD RGVSS RGVSS 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
EXTERNAL RESET INPUT (NORMALLY HIGH, PULSE RESET) +15V SUPPLY -7.5V SUPPLY
SUBCK OUTPUT SHUTTER CIRCUIT ANALOG SUPPLY 4.7µF ANALOG OUTPUT FROM
AD9925
DRAWN SCALE
DATA OUTPUTS DRIVER
(MSB) DRVDD DRVSS VSUB 0.1µF 0.1µF VDVDD VDVSS
4.7µF
MASTER CLOCK INPUT EXTERNAL SYNC INPUT ANALOG SUPPLY SUPPLY 0.1µF
VSUB
HVSS HVSS
HVSS
HVSS
HVSS
HVDD HVDD
HVDD
HVDD
HVDD
OUTPUTS CCD)
04637-0-061
0.1µF
SUPPLY 4.7µF
Figure AD9925 Typical Circuit Configuration
Rev. Page
AD9925
SERIAL INTERFACE TIMING
internal registers AD9925 accessed through 3-wire serial interface. Each register consists 8-bit address 24-bit data-word. Both 8-bit address 24-bit data-word written starting with LSB. write each register, 32-bit operation required, shown Figure Although many registers fewer than bits wide, bits must written each register. example, register only bits wide, then upper bits Don't Cares filled with during serial write operation. fewer than bits written, register will updated with data. Figure shows more efficient write registers, using AD9925's address auto-increment capability. Using this method, lowest desired address written first, followed multiple 24-bit data-words. Each 24-bit data-word will automatically written next highest register address. eliminating need write each 8-bit address, faster register loading achieved. Continuous write operations used starting with register location used write registers many entire register space.
8-BIT ADDRESS SDATA
24-BIT DATA
NOTES SDATA BITS LATCHED RISING EDGES. IDLE HIGH BETWEEN WRITE OPERATIONS. BITS MUST WRITTEN: BITS ADDRESS BITS DATA. REGISTER LENGTH BITS, THEN DON'T CARE BITS MUST USED COMPLETE 24-BIT DATA LENGTH. DATA VALUES UPDATED SPECIFIED REGISTER LOCATION DIFFERENT TIMES, DEPENDING PARTICULAR REGISTER WRITTEN REGISTER UPDATES SECTION MORE INFORMATION.
Figure Serial Write Operation
DATA STARTING REGISTER ADDRESS SDATA
DATA NEXT REGISTER ADDRESS
NOTES MULTIPLE SEQUENTIAL REGISTERS LOADED CONTINUOUSLY. FIRST (LOWEST ADDRESS) REGISTER ADDRESS WRITTEN, FOLLOWED MULTIPLE 24-BIT DATA-WORDS. ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL BITS MUST WRITTEN). HELD UNTIL LAST DESIRED REGISTER BEEN LOADED.
04637-0-062
Figure Continuous Serial Write Operation
Rev. Page
04637-0-063
AD9925
Register Address BANK BANK BANK
AD9925 address space divided into three different register banks, referred Register Bank Register Bank Register Bank Figure illustrates three banks divided. Register Bank Bank backward compatible with AD9995 registers. Register Bank contains registers AFE, miscellaneous functions, VD/HD parameters, timing core, CLPOB masking, patterns, shutter functions. Register Bank contains information vertical pattern groups, vertical sequences, field information. Register Bank contains registers accessing functionality. These additional outputs allow AD9925 used with newer CCDs requiring 8-phases vertical clocking. When writing AD9925, Addr 0x7F used specify which address bank being written write Bank data value written. write Bank data value written Addr 0x7F. write Bank data value written. Note that Register Bank contains many unused addresses. undefined addresses between Addr 0x00 Addr 0x7F considered Don't Cares, acceptable these addresses filled with during continuous register write operation. However, undefined addresses above 0x7F must written AD9925 operate properly. exception FG_TRIG registers 0xE7, 0xEB, 0xF2 through 0xF6, which written specified Page Default values Register Bank Bank undefined after power-up. Appropriate values should written into these register banks ensure proper operation.
REGISTER BANK ADDR 0x00 REGISTERS ADDR 0x10 MISCELLANEOUS REGISTERS ADDR 0x20 ADDR 0x30 ADDR 0x40 ADDR 0x50 PATTERN REGISTERS ADDR 0x60 SHUTTER REGISTERS ADDR 0x7F ADDR 0x8F INVALID ACCESS ADDR 0xFF ADDR 0xFF SWITCH REGISTER BANK BANK3 ADDR 0xCF ADDR 0xD0 VD/HD REGISTERS TIMING CORE REGISTERS CLPOB MASK REGISTERS ADDR 0x7E ADDR 0x7F ADDR 0x80 ADDR 0x00
REGISTER BANK ADDR 0x00
REGISTER BANK VPAT0 VPAT9 REGISTERS XV7, SIGNALS ADDR 0x4F ADDR 0x50 ADDR 0x77 VSEQ0 VSEQ9 REGISTERS XV7, SIGNALS SWITCH REGISTER BANK BANK
VPAT0 VPAT9 REGISTERS SIGNALS
SWITCH REGISTER BANK BANK VSEQ0 VSEQ9 REGISTERS SIGNALS
ADDR 0x7F
INVALID ACCESS
FIELD FIELD REGISTERS ADDR 0xFF
WRITE ADDRESS 0x7F SWITCH REGISTER BANKS
Figure Layout Internal Register Bank Bank Bank
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04637-0-064
AD9925
Updating Register Values
AD9925's internal registers updated different times, depending particular register. Table summarizes four different types register updates: Updated: Some registers Bank updated immediately, soon 24th data (D23) written. These registers used functions that require gating with next boundary, such power-up reset functions. These registers shaded gray Bank register list. bank select register (Addr 0x7F Bank Bank also updated. Updated: Most registers Bank well field registers Bank updated next falling edge. updating these values next edge, current field will corrupted, register values will applied next field. Bank register updates further delayed past falling edge, using UPDATE register (Addr 0x19). This will delay updated register updates line field. Note that Bank field registers affected UPDATE register. Line Updated: registers Bank updated active line, falling edge. These registers control SUBCK signal, that SUBCK output will updated until after line been completed. These registers crosshatched Bank register list. Updated: Bank Bank vertical pattern group vertical sequence registers (Addr 0x00 through Addr 0xCF, excluding Addr updated next where they will used. example, Figure this field selected Region Vertical Sequence vertical outputs. This means that write Vertical Sequence registers, vertical pattern group registers which referenced Vertical Sequence will updated SCP1. multiple writes done same register, last done before SCP1 will that updated. Likewise, register writes Vertical Sequence registers will updated SCP2, register writes Vertical Sequence registers will updated SCP3.
Table Register Update Locations
Update Type Updated Updated Line Updated Updated Register Bank Bank Only Bank Bank Bank Only Bank Bank Description Register immediately updated when 24th data (D23) clocked Register updated falling edge. updated registers Bank delayed further using UPDATE register Addr 0x19 Bank Bank updates will affected UPDATE register. Register updated falling edge active line. Register updated next when register will used.
UPDATED SERIAL WRITE UPDATED UPDATED UPDATED
SGLINE
REGION
REGION
REGION
REGION
Figure Register Update Locations (See Table Definitions)
Rev. Page
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VSEQ2
VSEQ3
VSEQ5
VSEQ8
AD9925 COMPLETE LISTING REGISTER BANK
registers updated, except where noted. Light gray cells updated dark gray cells line updated. Table Register
Address Data Content [11:0] [9:0] [7:0] [11:0] Default Value Register Name OPRMODE VGAGAIN CLAMPLEVEL CTLMODE Register Description Operation Modes (See Table detail) Gain Optical Black Clamp Level Control Modes (See Table detail)
Table Miscellaneous Register
Address Data Content [17:0] [17:0] [17:0] [17:0] [11:0] [23:0] Default Value 3FF8 3FF8 3FF8 Register Name STBY1POL STBY2POL STBY3POL OCONTPOL SW_RST OUTCONTROL SYNCENABLE SYNCPOL SYNCSUSPEND TGCORE_RSTB OSC_PWRDOWN UNUSED TEST UPDATE PREVENTUPDATE MODE UNUSED OUTPUTPBLK DVCMODE Register Description Polarities Output Signals during STANDBY1 Mode. Polarities Output Signals during STANDBY2 Mode. Polarities Output Signals during STANDBY3 Mode. Polarities Output Signals when OUTCONTROL Software Reset. Reset registers default, then self clear back Output Control. Make outputs inactive. Configures SYNC Input CLPOB/PBLK Output SYNC Active Polarity Active Low). Suspend Clocks during SYNC Active Suspend). Timing Core Reset Bar. Reset Core, Resume Operation. Oscillator Power-Down Oscillator Powered Down). Internal Only. Must Serial Update. Line (HD) field update updated registers. Prevents update updated registers. Prevent Update. Mode Register. Assigns Output when Configured Output. CLPOB, PBLK. Enable Mode. counter will reset every fields instead every field. VDLEN register should programmed total number lines contained fields, i.e., VDLEN lines will results 262.5 lines each field. Invert DCLK Output. Selects FG_TRIG Signal VSUB (see Page 43). H3HBLKOFF, Enable H3/H4 Outputs during HBLK (Page 19). Combines FG_TRIG VSUB signals (see Page 43). FG_TRIG Signal Enable (see Page 43). FG_TRIG Start Polarity. FG_TRIG First Toggle Position, Line Location. FG_TRIG First Toggle Position, Pixel Location. FG_TRIG Second Toggle Position, Line Location. FG_TRIG Second Toggle Position, Pixel Location.
[2:0] [5:4] [3:0] [11:0] [12:0] [11:0] [12:0]
INVERT_DCLK SHUT_EXTRA
FG_TRIGEN FG_TRIGPOL FG_TRIGLIN1 FG_TRIGPIX1 FG_TRIGLIN2 FG_TRIGPIX2
Rev. Page
AD9925
Table VD/HD Register
Address Data Content [11:0] [17:12] [11:0] Default Value Register Name MASTER VDHDPOL HDRISE VDRISE SCP0 Register Description VD/HD Master Slave Timing Slave Mode). VD/HD Active Polarity. High. Rising Edge Location Rising Edge Location SCP0. Used Fields.
Table Timing Core Register
Address Data Content [6:1] [12:7] [6:1] [12:7] [6:1] [12:7] [2:0] Default Value Register Name CLIDIVIDE H1POL H1POSLOC H1NEGLOC H3POL H3POSLOC H3NEGLOC RGPOL RGPOSLOC RGNEGLOC H1RETIME H3RETIME H1DRV Register Description Divide Input Clock Divide Polarity. Inversion, Inversion. Positive Edge Location. Negative Edge Location. Polarity. Inversion, Inversion. Positive Edge Location. Negative Edge Location. Polarity. Inversion, Inversion. Positive Edge Location. Negative Edge Location. Retime HBLK Internal Clock. Retime HBLK Internal Clock. Drive Strength Control Off. 12.9 17.2 21.5 25.8 30.1 Drive Strength Control (Same Values H1DRV). Drive Strength Control (Same Values H1DRV). Drive Strength Control (Same Values H1DRV). Drive Strength Control (Same Values H1DRV). Sampling Location. Sampling Location. DOUT Phase Control. DCLK Tracks DOUTPHASE. DCLK Does Track DOUTPHASE, Remains Fixed with Regards Data Output Delay (tOD) with Respect DCLK. Delay, Controls HBLK Width Fraction Frequency. same, 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14.
[5:3] [8:6] [11:9] [14:12] [5:0] [11:6] [5:0] [8:7]
H2DRV H3DRV H4DRV RGDRV SHPLOC SHDLOC DOUTPHASE DCLKMODE DOUTDLY HBLKWIDTH
[2:0]
Table CLPOB Masking Register
Address Data Content [11:0] [23:12] [11:0] [23:12] [11:0] [11:0] [12] Default Value Register Name CLPMASK0 CLPMASK1 CLPMASK2 CLPMASK3 CLPMASK4 CLPMASK5 CLPMASKTYPE Register Description CLPOB Line Masking Line Mask0 Range Start Line CLPOB Line Masking Line Mask0 Range Line CLPOB Line Masking Line Mask1 Range Start Line CLPOB Line Masking Line Mask1 Range Line CLPOB Line Masking Line Mask2 Range Start Line CLPOB Line Masking Line Mask2 Range Line CLPOB Line Masking, Enable CLPOB Range Masking
Rev. Page
AD9925
Table Pattern Register
Address Data Content [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [5:0] Default Value Register Name SGPOL_0 SGPOL_1 SGPOL_2 SGPOL_3 SGTOG1_0 SGTOG2_0 SGTOG1_1 SGTOG2_1 SGTOG1_2 SGTOG2_2 SGTOG1_3 SGTOG2_3 SGMASK_OVR SGMASKOVR_EN Register Description Start Polarity Pattern Start Polarity Pattern Start Polarity Pattern Start Polarity Pattern Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position Pattern Toggle Position SGMASK Override. These values will immediately override masking values located field registers. Masking Field Registers, Enable SGMASK Override.
Table Shutter Control Register
Address Data Content [4:0] Default Value Register Name TRIGGER Register Description Trigger VSUB [0], MSHUT [1], STROBE [2], Exposure [3], Readout [4]. Note that trigger readout automatically occur after exposure period, both exposure readout should triggered together. Number Fields Suppress SUBCK Pulses after Line. Number Fields Suppress SUBCK Pulses. disable VD/HD outputs during exposure (when field). Number SUBCK Pulses Suppress after Line. Number SUBCK Pulses Field. SUBCK Pulse Start Polarity. First SUBCK Pulse. Toggle Position First SUBCK Pulse. Toggle Position Second SUBCK Pulse. Toggle Position Second SUBCK Pulse. Toggle Position VSUB Readout Mode. Mode Mode Turn VSUB after Readout, Keep VSUB after Readout. VSUB Online Position. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable (Opens Shutter Next Edge). MSHUT Position-Line. MSHUT Position-Pixel. MSHUT Position-Field. MSHUT Position-Line. MSHUT Position-Pixel. STROBE Active Polarity. STROBE Position-Field. STROBE Position-Line. STROBE Position-Pixel. STROBE Position-Field. STROBE Position-Line. STROBE Position-Pixel. 13th SUBCK Toggle Position Placement.
[2:0] [11:0] [12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [12] [11:0] [23:12] [11:0] [11:0] [23:12] [11:0] [11:0] [23:12] [11:0] [11:0] [23:12] [3:0]
READOUT EXPOSURE VDHDOFF SUBCKSUPPRESS SUBCKNUM SUBCKPOL SUBCK1TOG1 SUBCK1TOG2 SUBCK2TOG1 SUBCK2TOG2 VSUBMODE VSUBKEEPON VSUBON VSUBPOL MSHUTPOL MSHUTON MSHUTON_LN MSHUTON_PX MSHUTOFF_FD MSHUTOFF_LN MSHUTOFF_PX STROBPOL STROBON_FD STROBON_LN STROBON_PX STROBOFF_FD STROBOFF_LN STROBOFF_PX SUBCKTOG13
Rev. Page
AD9925
Table Register Selection
Address Data Content [1:0] Default Value Register Name BANKSELECT Register Description Register Bank Access Bank Bank Bank Bank Bank Bank Bank
Table Operation Register Detail
Address Data Content [1:0] [7:6] [11:10] Default Value Name PWRDOWN CLPENABLE CLPSPEED FASTUPDATE PBLK_LVL TEST DCBYP TEST CDSGAIN Description Normal Operation, Standby1, Standby2, Standby3. Disable Clamp, Enable Clamp. Select Normal Clamp Settling, Select Fast Clamp Settling. Select Temporary Fast Clamping When Gain Updated. DOUT Value during PBLK: Blank Blank Clamp Level. Test Operation Only. Enable Restore Circuit, Bypass Restore Circuit during PBLK. Test Only.
Table Control Register Detail
Address Data Content [1:0] Default Value Name TEST TEST DOUTDISABLE DOUTLATCH GRAYENCODE Description Test Only. Test Only. Data Outputs Driven, Data Outputs Three-Stated. Latch Data Outputs with DOUT Phase, Output Latch Transparent. Binary Encode Data Outputs, Gray Encode Data Outputs.
Rev. Page
AD9925 COMPLETE LISTING REGISTER BANK
vertical pattern group vertical sequence registers updated, field registers updated. Table Vertical Pattern Group (VPAT0) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_0 UNUSED VPATLEN_0 XV1TOG1_0 XV1TOG2_0 XV1TOG3_0 XV2TOG1_0 XV2TOG2_0 XV2TOG3_0 XV3TOG1_0 XV3TOG2_0 XV3TOG3_0 XV4TOG1_0 XV4TOG2_0 XV4TOG3_0 XV5TOG1_0 XV5TOG2_0 XV5TOG3_0 XV6TOG1_0 XV6TOG2_0 XV6TOG3_0 FREEZE1_0 RESUME1_0 FREEZE2_0 RESUME2_0 Register Description VPAT0 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length VPAT0. Note: using VPAT0 second vertical sequence active line, this value start position second vertical sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Freeze Position Resume Position Freeze Position Resume Position
Rev. Page
AD9925
Table Vertical Pattern Group (VPAT1) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_1 UNUSED VPATLEN_1 XV1TOG1_1 XV1TOG2_1 XV1TOG3_1 XV2TOG1_1 XV2TOG2_1 XV2TOG3_1 XV3TOG1_1 XV3TOG2_1 XV3TOG3_1 XV4TOG1_1 XV4TOG2_1 XV4TOG3_1 XV5TOG1_1 XV5TOG2_1 XV5TOG3_1 XV6TOG1_1 XV6TOG2_1 XV6TOG3_1 FREEZE1_1 RESUME1_1 FREEZE2_1 RESUME2_1 Register Description VPAT1 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4]. XV6[5]. Unused. Total Length VPAT1. Note: using VPAT1 second vertical sequence active line, this value start position second vertical sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Freeze Position Resume Position Freeze Position Resume Position
Rev. Page
AD9925
Table Vertical Pattern Group (VPAT2) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_2 UNUSED VPATLEN_2 XV1TOG1_2 XV1TOG2_2 XV1TOG3_2 XV2TOG1_2 XV2TOG2_2 XV2TOG3_2 XV3TOG1_2 XV3TOG2_2 XV3TOG3_2 XV4TOG1_2 XV4TOG2_2 XV4TOG3_2 XV5TOG1_2 XV5TOG2_2 XV5TOG3_2 XV6TOG1_2 XV6TOG2_2 XV6TOG3_2 FREEZE1_2 RESUME1_2 FREEZE2_2 RESUME2_2 Register Description VPAT2 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length VPAT2. Note: using VPAT2 second vertical sequence active line, this value start position second vertical sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Freeze Position Resume Position Freeze Position Resume Position
Rev. Page
AD9925
Table Vertical Pattern Group (VPAT3) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_3 UNUSED VPATLEN_3 XV1TOG1_3 XV1TOG2_3 XV1TOG3_3 XV2TOG1_3 XV2TOG2_3 XV2TOG3_3 XV3TOG1_3 XV3TOG2_3 XV3TOG3_3 XV4TOG1_3 XV4TOG2_3 XV4TOG3_3 XV5TOG1_3 XV5TOG2_3 XV5TOG3_3 XV6TOG1_3 XV6TOG2_3 XV6TOG3_3 FREEZE1_3 RESUME1_3 FREEZE2_3 RESUME2_3 Register Description VPAT3 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused. Total Length VPAT3. Note: using VPAT3 second vertical sequence active line, this value start position second vertical sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Freeze Position Resume Position Freeze Position Resume Position
Rev. Page
AD9925
Table Vertical Pattern Group (VPAT4) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_4 UNUSED VPATLEN_4 XV1TOG1_4 XV1TOG2_4 XV1TOG3_4 XV2TOG1_4 XV2TOG2_4 XV2TOG3_4 XV3TOG1_4 XV3TOG2_4 XV3TOG3_4 XV4TOG1_4 XV4TOG2_4 XV4TOG3_4 XV5TOG1_4 XV5TOG2_4 XV5TOG3_4 XV6TOG1_4 XV6TOG2_4 XV6TOG3_4 FREEZE1_4 RESUME1_4 FREEZE2_4 RESUME2_4 Register Description VPAT4 Start Polarity. XV1[0], XV2[1], XV3[2], XV4[3], XV5[4], XV6[5]. Unused Total Length VPAT4. Note: using VPAT4 second vertical sequence active line, this value start position second vertical sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Freeze Position Resume Position Freeze Position Resume Position
Rev. Page
AD9925
Table Vertical Pattern Group (VPAT5) Register
Address Data Content [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] Default Value Register Name VPOL_5 UNUSED VPATLEN_5 XV1TOG1_5 XV1TOG2_5 XV1TOG3_5 XV2TOG1_5 XV2TOG2_5 XV2TOG3_5 XV3TOG1_5 XV3TOG2_5 XV3TOG3_5 XV4TOG1_5 XV4TOG2_5 XV4TOG3_5 XV5TOG1_5 XV5TOG2_5 XV5TOG3_5 XV6TOG1_5 XV6T
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