Endpoint Control Control Control Soft Core (RTL Interfa

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Endpoint Control Control Control Soft Core (RTL Interfa

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InventraMUSBLSFC Low-Speed Function Controller
Endpoint Control
Control Control
Soft Core (RTL
Interface
Interrupt Control Reg. Decoder Common Regs
Major Product Features:
Interrupts
Combine Endpoints
Complies with standard
Low-speed (1.5 Mbps) functions
DPLL
Controller
Address Generator
Cycle Control
Configurable
NRZI Stuff
Packet Enc/Dec Shift Register
FIFO Decoder
endpoints endpoints addition Endpoint
8-byte FIFOs each endpoint High-level 8-bit synchronous
Cycle Control
PVCI *-compatible interface
Synchronous interface
FIFOs MUSBLSFC Block Diagram
Suspend Resume signaling
supported
Fully synthesizable
Overview
MUSBLSFC core provides function controller that complies with specifications Low-speed (1.5 Mbps) functions. core user-configurable endpoints and/or endpoints addition Endpoint These additional endpoints used either Bulk Interrupt transfers. Both Endpoint each these additional endpoints associated with separate 8-byte FIFO. Alternatively single 8-byte FIFO shared between endpoint endpoint with same Endpoint number. MUSBLSFC interface connecting single block synchronous single-port which used endpoint FIFOs (added user). Access FIFOs internal control/status registers 8-bit synchronous interface which conforms Peripheral Virtual Component Interface (PVCI) defined VSIA. MUSBLSFC provides packet encoding, decoding checking interrupting only when endpoint data been successfully transferred. graphical user interface script provided configuring core user's requirements. (Note: Configuration developed tested using Tcl/Tk 8.3. with earlier version Tcl/Tk give unpredictable results.)
Scan test ready Graphical User Interface provided
core configuration
Deliverables:
Verilog/VHDL source code Synthesis script Design Compiler Verilog/VHDL testbench Sample firmware Product Specification; User Guide;
Programmer's Guide
Related Products
MUSBFSFC Full-Speed
Function Controller
MUSBHSFC High/Full-
Speed Function Controller
Peripheral Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraMUSBLSFC USB1.1 Low-Speed Function Controller
Structure MUSBLSFC function controller consists Serial Interface Engine (SIE), Controller, Interface, control block each endpoint. Serial Interface Engine handles NRZI encoding/decoding, stuffing/unstuffing, generation/checking. generates clock from input clock core, synchronizes this clock incoming data stream when receiving data from USB. generates headers packets transmitted decodes headers received packets. Controller Controller provides interface single block synchronous single-port that used buffer packets between USB. takes FIFO pointers from endpoint controllers, converts them address pointers within block generates access control signals. Interface Interface provides 8-bit synchronous VCI-compliant interface allow access control/status registers FIFOs each endpoint. generates interrupt when packet been successfully transmitted received, when core enters resumes from Suspend mode. Endpoint Controllers controller state machines used. control transfers over Endpoint bulk/interrupt transactions over Endpoints Reference Technology Gate Count: 5000 Configurable Options MUSBLSFC user-configurable for: number endpoints and/or endpoints that required addition Endpoint Whether these endpoints have separate FIFOs share FIFO between endpoint corresponding endpoint. Note: endpoints configured work with 8-byte FIFOs.
RAM_DATAI[7:0] RAM_DATAO[7:0] RAM_NWR Input Output Output RAM_NCE RAM_ADDR[n:0] FCLK CLKOUT NRST USB_NRSTO USB_SUSPEND
Signal Description MUSBLSFC maximum external signals, inputs outputs.
SIGNAL
DIDIF NDOE
TYPE DESCRIPTION INTERFACE SIGNALS
Input Input Input Output Output Output single-ended input. single-ended input. Differential input. output. output. Output enable DOP, DOM. Active low.
INTERFACE SIGNALS
MC_ADDR[3:0] MC_DI[7:0] MC_DO[7:0] MC_NOE MC_VAL MC_RNW MC_ACK MC_NINT Input Input Output Output Input Input Output Output Address bus. Data input. Data output. Data output enable. Active low. access validate Read write. access acknowledge. interrupt. Active low.
SYSTEM SIGNALS
Input Output Input Input Output Output Input clock. This clock should MHz. System clock output (1.5 Buffered version CLKOUT. Power-up reset. Active low. function reset output. Active low. This signal goes high when function Suspend mode.
INTERFACE SIGNALS
Output Output Enable. Active low. address bus. width dependent number type endpoints configured. Data input from RAM. Data output RAM. write enable. Active low.
2000-2001 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
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PD-40103.002-FO

Endpoint Control Control Control Soft Core (RTL Interfa

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