Soft Core (RTL High/Full-Speed Function Controller Endpoint

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Soft Core (RTL High/Full-Speed Function Controller Endpoint

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InventraMUSBHSFC
Soft Core (RTL
High/Full-Speed Function Controller
Endpoint Control
Control Control Combine Endpoints
Requests Interface
Interrupt Control Reg. Decoder Common Regs
Major Product Features:
Complies with standard
High/Full-speed (480/12 Mbps) functions
USynchronization
Sync
Packet Encode/Decode
Packet Encode Packet Decode Gen/Check
Controller
Buff Buff
Cycle Control
Configurable additional
endpoints
Configurable FIFO sizes from
TxRx Macrocell
Sync Detect Timers
FIFO Decoder Buff Buff
8192 bytes, with option dynamic FIFO sizing
Standard Device Requests handled
Cycle Control
efficiently software flexibility
UTMI Transceiver Macrocell
Interface
MUSBHSFC Block Diagram
Built-in 16/32-bit synchronous
BVCI *-compatible interface, optional AMBA bridge
Overview
MUSBHSFC core provides function controller that conforms specification High/Full-speed (480/12 Mbps) functions. core user-configurable endpoints endpoints addition Endpoint These additional endpoints individually programmed Bulk/Interrupt Isochronous transfers. Each endpoint requires FIFO associated with MUSBHSFC interface connecting single block synchronous single-port (added user.) FIFO Endpoint fixed bytes. other endpoint FIFOs from 8192 bytes size buffer either packets. Separate FIFOs associated with each endpoint: alternatively endpoint with same Endpoint number configured same FIFO, example reduce size block needed. MUSBHSFC provides Transceiver Macrocell Interface connect 8/16-bit High/Full-speed transceiver. Access FIFOs internal control/status registers 16/32-bit BVCI*-compatible synchronous interface optional 32-bit MUSBHSFC AMBA bridge. MUSBHSFC interface connecting single block synchronous that used endpoint FIFOs. device also offers support access endpoint FIFOs. (The optional MUSBHSFC bridge includes built-in controller.) MUSBHSFC provides packet encoding, decoding checking interrupting only when endpoint data been successfully transferred. graphical user interface script provided configuring core user's requirements. (Note: Configuration developed tested using Tcl/Tk 8.3. with earlier version Tcl/Tk give unpredictable results.)
Support access FIFOs Synchronous interface FIFOs Supports Suspend Resume
signaling
Soft connect/disconnect option Fully synthesizable Scan test ready Graphical User Interface provided
core configuration
Deliverables:
Verilog source code Synthesis script Design Compiler Verilog testbench Sample firmware Product Specification; User Guide;
Programmer's Guide
Related Products
MUSBFSFC Full-Speed
Function Controller
MUSBFDRC On-The-Go
Full-Speed Dual Role Controller
Basic Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraMUSBHSFC High-Speed Function Controller
Structure MUSBHSFC function controller consists Ure-synchronizing block, Packet Encoder/Decoder plus Generator/Checker block, Controller, Interface, plus control block each endpoint. function controller interfaces UTMI specification v1.05 transceiver macrocell. USync Block role this block resynchronize between transceiver macrocell 30/60 clock domain function controller's user-supplied clock (>30 MHz). This allows rest MUSBHSFC from clock without requiring further synchronization. 8-bit transceiver interface configured, this block will convert data 16-bit that user clock down used. block also performs high-speed detection handshaking. Interface core interfaced range different standards. interface provided MUSBHSFC itself 16/32-bit synchronous interface that compatible with VSIA standard `BVCI' Basic Virtual Component Interface. Connection other standard buses provided through addition optional bridges such MUSBHSFC bridge which provided with core. Packet Encoder/Decoder Packet Encoder/Decoder block generates headers packets transmitted decodes headers received packets. also performs generation checking. Endpoint Controllers controller state machines used. control transfers over Endpoint bulk/interrupt/ isochronous transactions over Endpoints Controller Controller provides interface single block synchronous RAM, which used buffer packets between USB. takes FIFO pointers from endpoint controllers, converts them address pointers within block generates access control signals.
2000-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
Signal Description Maximum external signals; inputs outputs.
UINTERFACE SIGNALS SIGNAL XCLK XCVRSEL TERMSEL SUSPENDM LINESTATE[1:0] OPMODE[1:0] XDATAOUT[tw:0] TXVALID TXVALIDH TXREADY XDATAIN[tw:0] RXVALID RXVALIDH RXACTIVE RXERROR MC_ADDR[aw:0] MC_DI[dw:0] MC_DO[dw:0] MC_NOE MC_CMDVAL MC_CMDACK MC_BE[bew:0] MC_CMD[1:0] MC_RSPVAL MC_RSPACK MC_FBV[fbw:0] MC_NINT DMA_REQ[n:0] RAM_ADDR[rw:0] RAM_DATAI[31:0] RAM_DATAO[31:0] RAM_NCE RAM_NWR NRST USB_NRSTO SOF_PULSE TYPE Input Output Output Output Input Output Output Output Output Input Input Input Input Input Input Input Input Output Output Input Output Input Input Output Input Output Output Output Output Input Output Output Output Input Input Output Output DESCRIPTION Transceiver macrocell clock. 60MHz/30MHz Transceiver select High-speed/Full-speed. Termination select High-speed/Full-speed. Suspend mode indicator. Show current state Operating mode selector Data transmitted. width bits bits. Transmit data valid. High byte XDATAOUT valid (16-bit only). Transmit data ready. Received data. width bits bits. Receive data valid. High byte XDATAIN valid (16-bit only). Valid Receive packet indicator. Receive error indicator. Address bus. 7-bit depending data width. Data input. Either 16-bit 32-bit. Data output. Either 16-bit 32-bit. Data output enable. Active low. command valid. command acknowledge. Byte enables. 4-bit depending data width. command: read, write. response valid. response acknowledge. FIFO Read Byte Valid indicators. interrupt. Active low. endpoint requests, each user endpoint. address bus. width dependent number type endpoints configured. data input bus. data output bus. select. Active low. write enable. Active low. SYSTEM SIGNALS System clock. Must greater than 30MHz. Power-up reset. Active low. function reset output. Active low. Frame Sync Pulse.
INTERFACE SIGNALS
INTERFACE SIGNALS
Configurable Options MUSBHSFC user-configurable for: number endpoints that support transfers. number endpoints that support transfers. FIFO sizes: bytes; 8192 bytes. Whether FIFOs shared between endpoint corresponding endpoint. widths transceiver interfaces. Reference Technology Gate Count: 11000 1700/1800 each additional endpoint 2700/2800 endpoint dynamic FIFO sizing required); 2200 High-Bandwidth support; 2400 2000/DMA channel AMBA bridge (Est. Gate Count displayed Configuration Screen)
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PD-40113.004-FO

Soft Core (RTL High/Full-Speed Function Controller Endpoint

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