Endpoint Control Control Control Soft Core (RTL Request

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Endpoint Control Control Control Soft Core (RTL Request

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InventraMUSBFSFC Full-Speed Function Controller
Endpoint Control
Control Control
Soft Core (RTL
Requests Interface
Interrupt Control Reg. Decoder Common Regs
Major Product Features:
Complies with standard
Interrupts
Combine Endpoints
Full-speed Mbps) functions
DPLL
Controller
Address Generator
Cycle Control
Configurable additional
endpoints
Configurable endpoint direction Configurable FIFOs each
NRZI Stuff
Packet Enc/Dec Shift Register
FIFO Decoder
Cycle Control
endpoint
Built-in 8-bit synchronous
PVCI *-compatible interface, optional AMBA bridge
Support access FIFOs Synchronous interface
MUSBFSFC Block Diagram
Overview
MUSBFSFC core provides function controller that complies with specifications Full-speed Mbps) functions. core user-configurable endpoints endpoints addition Endpoint These additional endpoints individually programmed Bulk/Interrupt Isochronous transfers. Each endpoint requires FIFO associated with MUSBFSFC interface connecting single block synchronous single-port which used endpoint FIFOs (added user). MUSBFSFC's interface configurable Endpoint FIFO that bytes deep. Other endpoint FIFOs from 2048 bytes deep buffer either packets. Separate FIFOs associated with each endpoint: alternatively endpoint endpoint with same Endpoint number configured same FIFO, example reduce size block needed. Access FIFOs internal control/status registers 8-bit PVCI*-compatible synchronous interface optional 32-bit MUSBFSFC AMBA bridge. There also support access Endpoint FIFOs. (The optional MUSBFSFC bridge includes built-in controller.) MUSBFSFC provides packet encoding, decoding checking interrupting only when endpoint data been successfully transferred. graphical user interface provided configuring core user's requirements. (Note: Configuration developed tested using Tcl/Tk 8.3. with earlier version Tcl/Tk give unpredictable results.)
FIFOs
Supports Suspend Resume
signaling
Fully synthesizable Scan test ready Graphical User Interface provided
core configuration
Deliverables:
Verilog/VHDL source code Synthesis script Design Compiler Verilog/VHDL testbench Sample firmware Product Specification; User Guide;
Programmer's Guide
Related Products
MUSBLSFC Low-Speed
Function Controller
MUSBHSFC High/Full-
Speed Function Controller
Peripheral Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraMUSBFSFC USB1.1 Full-Speed Function Controller
Structure MUSBFSFC function controller consists Serial Interface Engine (SIE), Controller, Interface, control block each endpoint. Serial Interface Engine handles NRZI encoding/decoding, stuffing/ unstuffing, generation/checking. generates clock from input clock core, synchronizes this clock incoming data stream when receiving data from USB. generates headers packets transmitted decodes headers received packets. Controller Controller provides interface block synchronous single-port used buffer packets between USB. takes FIFO pointers from endpoint controllers, converts them address pointers within block generates access control signals. Interface core interfaced range different standards. interface provided MUSBFSFC itself 8-bit synchronous interface that compatible with VSIA standard `PVCI' Peripheral Virtual Component Interface. Connection other standard buses provided through addition optional bridges such MUSBFSFC bridge which provided with core. Endpoint Controllers controller state machines used. control transfers over Endpoint bulk/interrupt/ isochronous transactions over Endpoints Configurable Options MUSBFSFC configured for: number endpoints that support transfers. number endpoints that support transfers. size FIFO associated with each endpoint: bytes 2048 bytes Whether FIFOs shared between endpoint corresponding endpoint.
2000-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
Signal Description MUSBFSFC maximum external signals, inputs outputs.
SIGNAL TYPE DESCRIPTION
INTERFACE SIGNALS
DIDIF NDOE Input Input Input Output Output Output single-ended input. single-ended input. Differential input. output. output. Output enable DOP, DOM. Active low.
INTERFACE SIGNALS
MC_ADDR[5:0] MC_DI[7:0] MC_DO[7:0] MC_NOE MC_VAL MC_RNW MC_ACK MC_NINT DMA_REQ[m:0] DMA_NACK Input Input Output Output Input Input Output Output Output Input Address bus. Data input. Data output. Data output enable. Active low. access validate. Read write. access acknowledge. interrupt. Active low. endpoint requests, each additional endpoint. Acknowledge. Active low.
SYSTEM SIGNALS
FCLK CLKOUT NRST USB_NRSTO SOF_PULSE USB_SUSPEND Input Output Input Input Output Output Output Input clock. This clock should 48MHz. System clock output derived from FCLK (12MHz). System clock input (buffered version CLKOUT). Power-up reset. Active low. function reset output. Active low. Frame Sync Pulse. High when function Suspend mode.
INTERFACE SIGNALS
RAM_NCE RAM_ADDR[n:0] RAM_DATAI[7:0] RAM_DATAO[7:0] RAM_NWR Output Output Input Output Output Enable. Active low. address bus. width dependent number type endpoints configured. Data input from RAM. Data output RAM. write enable. Active low.
Reference Technology Gate Count: 7500 1200-1300 each additional endpoint (AHB Bridge: 1900 (950 +1300/channel) with DMA) (Gate Count estimate selected configuration displayed Configuration Screen)
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PD-40104.003a-FO

Endpoint Control Control Control Soft Core (RTL Request

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