Endpoint Control Control Host Control Function Transmit Receive H

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Endpoint Control Control Host Control Function Transmit Receive H

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InventraMUSBFDRC Full-Speed Dual-Role Controller
Endpoint Control
Control Host Control Function Transmit Receive Host Transaction Scheduler Control
Soft Core (RTL
Requests Interface
Interrupt Control Reg. Decoder Common Regs
Major Product Features:
Operates either function
Interrupts
Combine Endpoints
DPLL
Controller
Address Generator
Cycle Control
optional bridge
controller peripheral host/peripheral point-to-point communications with another function
Complies with standard
NRZI Stuff
Packet Enc/Dec Shift Register
FIFO Decoder
Cycle Control
full-speed Mbps) functions with On-The-Go supplement specification
Supports point-to-point communi-
cations with full-speed low-speed device
Supports both Session Request
MUSBFDRC Block Diagram
Protocol (SRP) Host Negotiation Protocol (HNP)
Standard Device Requests handled
Overview
Inventra MUSBFDRC primarily provides `Dual-role' controller either host peripheral point-to-point communications with another function (which either full-speed low-speed). Alternatively used function controller full-speed peripheral. complies with both standard full-speed functions On-TheGo supplement specification. On-The-Go specification been introduced provide low-cost connectivity solution consumer portable devices such mobile phones, PDAs, digital still cameras players. Devices that solely peripherals initiate transfers through Session Request Protocol (SRP) while Dual-role devices support both Host Negotiation Protocol (HNP). MUSBFDRC user-configurable `Transmit' endpoints and/or `Receive' endpoints addition Endpoint individually programmable Bulk/Interrupt Isochronous transfers. Access FIFOs associated with these endpoints internal control/status registers either 8-bit PVCI-compatible synchronous interface optional 32-bit MUSBFDRC AMBA bridge. There also support access Endpoint FIFOs, including controller built into AMBA-AHB bridge. MUSBFDRC doesn't itself include these FIFOs this needs added user. interface offered core configurable endpoint FIFO sizes from bytes 2048 bytes (except Endpoint FIFO which fixed bytes.) graphical user interface provided configuring core user's requirements. estimate gate count selected configuration displayed configuration screen.
efficiently software flexibility
Supports Suspend Resume
signaling
Configurable additional
Transmit endpoints additional Receive endpoints
Configurable FIFOs, with option
dynamic FIFO sizing
Synchronous interface FIFOs Support access FIFOs Built-in PVCI*-compatible I/F,
optional AMBA bridge
Performs transaction scheduling
hardware
Graphical User Interface provided
core configuration
Deliverables:
Verilog VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
Peripheral Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraMUSBFDRC Full-Speed Dual-Role Controller
Modes Operation MUSBFDRC main modes operation Peripheral mode Host mode. When acting peripheral, MUSBFDRC provides encoding, decoding checking needed sending receiving packets interrupting only when endpoint data been successfully transferred. When acting host, MUSBFDRC additionally maintains frame counter automatically schedules SOF, Isochronous, Interrupt Bulk transfers. also includes support Session Request Host Negotiation Protocols required point-to-point communications, details which given On-The-Go supplement specification. Whether MUSBFDRC initially operates Host mode Peripheral mode depends whether being used device device. When MUSBFDRC operating device, initially configured operate Host mode. When operating device, MUSBFDRC initially configured operate Peripheral mode. MUSBFDRC determines whether device monitoring input, which should connected mini-AB receptacle. Session Request (SRP) session defined period when VBus VBus always supplied device bus. Sessions started associated with either device device setting Session DevCtl register. Where device wishes start session, will first pulsing data line, then pulsing VBus wake device. Sessions ended clearing Session bit. Host Negotiation (HNP) When MUSBFDRC device, automatically enters Host mode when session starts. When MUSBFDRC device, automatically enters Peripheral mode when session starts. however request that MUSBFDRC becomes Host setting Host DevCtl register. Host Negotiation then conducted using defined protocol when MUSBFDRC next enters Suspend mode. Reference Technology Gate Count: 6200 1500/1600 each additional Tx/Rx endpoint 2500/2600 endpoint dynamic FIFO sizing required)
2001-2003 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
Signal Description MUSBFDRC maximum external signals: inputs outputs.
INTERFACE SIGNALS SIGNAL DIDIF NDOE SPEED PUCON PDCON VBUSEN VBUSCHG VBUSVAL VBUSSES VBUSLO IDEN TYPE Input Input Input Output Output Output Output Output Output Output Output Input Input Input Input Output DESCRIPTION single-ended input. single-ended input. Differential input. output. output. Output enable DOP, DOM. Active low. Transceiver operating speed: Full-/Low-speed. Connect pull-up resistor Connect pull-down resistor VBus power enable (for operation device). Charge VBus (used when operating device). VBus compared selected VBus Valid threshold. VBus compared Session Valid threshold. VBus compared Session threshold. MUSBFDRC Connector 1=B-type, 0=A-type. Enable sampling line (allows power saving).
INTERFACE SIGNALS MC_ADDR[5:0] MC_DI[7:0] MC_DO[7:0] MC_NOE MC_VAL MC_RNW MC_ACK MC_NINT DMA_REQ[m:0] DMA_NACK Input Input Output Output Input Input Output Output Output Input Address bus. Data input. Data output. Data output enable. Active low. access validate. Read write. access acknowledge. interrupt. Active low. endpoint requests, each endpoint. Acknowledge. Active low.
INTERFACE SIGNALS RAM_NCE RAM_ADDR[n:0] RAM_DATAI[7:0] RAM_DATAO[7:0] RAM_NWR Output Output Input Output Output Enable. Active low. address bus. width dependent number type endpoints configured. data input bus. data output bus. write enable. Active low. SYSTEM SIGNALS FCLK CLKOUT NRST USB_NRSTO SOF_PULSE USB_SUSPEND Input Output Input Input Output Output Output Input clock. This clock should MHz. System clock output MHz). Buffered version CLKOUT clock. Power-up reset. Active low. function reset output. Frame Sync Pulse. High when MUSBFDRC Suspend mode.
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03/03
PD-40134.005-FO

Endpoint Control Control Host Control Function Transmit Receive H

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