Address Bits Read Write Strobes Soft Core (RTL Major Product

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Address Bits Read Write Strobes Soft Core (RTL Major Product

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InventraMPCMCIA1 PCMCIA Card Interface
Address Bits Read Write Strobes
Soft Core (RTL
Major Product Features:
Conforms PCMCIA Card
MPCMCIA1
Attribute Memory Enable Common Memory Enables PCMCIA PCMCIA Configuration Registers Peripheral Enables Address Data Memory Read Strobe Memory Write Strobe Control Status
Standard
bytes (Card Information
Structure) memory, loadable from ROM, Flash Memory EEPROM
Extended Attribute Memory Interface
bit) allow additional configuration registers memory implemented
Common Memory Interface
Serial Memory Flash
Serial Control Serial Data
allowing access Mbytes
Interface User Configurable Base Address
Flash Control Flash Data
Window Size
MPCMCIA1 Block Diagram
Fully synthesizable Scan test ready
Overview
MPCMCIA1 general purpose 16-bit Card Interface block PCMCIA card ASICs. provides 16-bit PCMCIA card, memory interfaces with user configurable address decoding, level edge triggered interrupts powerdown control. design also supports bytes memory, which Non-volatile e.g. ROM, SRAM automatically uploaded hardware reset from serial EEPROM, SRAM automatically uploaded hardware reset from Flash Memory This data area used define nature card possible configuration defined PCMCIA Card Standard. Having this area SRAM allows host computer interrogate card automatically configure itself drive card giving "Plug Play" facility. MPCMCIA1 supports accesses attribute memory, common memory I/O. accesses, however, supported.
Deliverables:
Verilog source code VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
www.mentor.com/inventra
InventraMPCMCIA1 PCMCIA Card Interface Soft Core
Memory Card Information Structure (CIS) memory data area used define nature card possible configuration. area allows host computer interrogate card automatically configure itself drive card, giving "Plug Play" facility. first bytes memory, implemented SRAM, automatically uploaded from external Flash device. device which access time less than clock cycles suitable (250 clock). This memory also automatically uploaded from external serial EEPROM serial port pins. serial memory that contains least bits, uses Microwirebus compatible with Thomson ST93CS56 suitable. Alternatively, serial port connected other intelligent devices card capable emulating serial EEPROM function. Configuration Registers line with PCMCIA Card Interface Standard, MPCMCIA1 implements following configuration registers: Configuration Option Register (COR) Configuration Status Register (CSR) Replacement Register (PRR) Socket Copy Register (SCR) Base Registers (IOBR0 Limit Register (IOLR) Operation power MPCMCIA1 memory mode configured PCMCIA memory interface. Writing value greater than zero Function Configuration Index places device mode configures PCMCIA interface. Setting Function Configuration Index zero places device memory mode. ference Technol Gate 2500
1997-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
Signal Description MPCMCIA1 external signals; inputs outputs.
SIGNAL RSET A[15:0] DI[15:0] DO[15:0] NDOEN1,2 NCE1, NOE, NREG NWAIT NIORD, NIOWR NINPACK NIREQ NIOIS16 NSPKR NSTSCHG NRESET POWDWN CLKO PDI[15:0] PDO[15:0] NPDOEN1,2 NCMCS1,2 NAMCS1 NIOCS1,2 NPOE, NPWE NPRI NPIREQ PAUD PBVD1,2 PREADY NPWAIT FCI4,5 SERCS SERCLK SERDO SERDI FA[7:0] FDI[7:0] NFCS NFRD RA[7:0] RDO[7:0] RDI[7:0] NRREB, NRWEB CISMEM0,1 MSPD0,1 TESTMODE TYPE Input Input Input Output Output Input Input Input Output Input Output Output Output Output Output Output Output Output Output Input Output Output Output Output Output Output Input Input Input Input Input Input Input Input Output Output Output Output Input Output Input Output Output Output Output Input Output Input Input Input Input DESCRIPTION Hardware reset Address Data inputs Data outputs Output enables data low/high byte byte, High byte transfer enable Memory read/write strobe Attribute memory selection Extends memory cycles mode read/write strobe mode Valid read cycle progress Mode Interrupt request Mode accesses possible Mode Binary audio Mode Status change Peripheral reset Power down mode selection Clock output (stops power down mode) Peripheral address Data input Data output Output enables peripheral data low/high byte Common memory peripheral low/high byte select Extended attribute memory byte select peripheral byte, high byte select Peripheral memory read/write strobe Peripheral ring indicate Peripheral interrupt Peripheral organization Peripheral binary audio input Peripheral battery voltage status detect Peripheral ready status Peripheral write protect status Peripheral extend cycle input function configuration index bits Serial chip select Serial clock Serial data Serial data input Flash address Data input from flash Flash chip select Flash read strobe address Data output memory Data input from memory read/write strobe Clock MHz) memory configuration bits 8-bit memory access speed configuration bits Scan test mode select
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PD-40073.004-FO

Address Bits Read Write Strobes Soft Core (RTL Major Product

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