32bit 33/66MHz Core w/Cardbus support Cardbus Soft Core (RTL

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32bit 33/66MHz Core w/Cardbus support Cardbus Soft Core (RTL

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InventraMPCI32
32bit 33/66MHz Core w/Cardbus support
Cardbus
Soft Core (RTL
Major Product Features:
Fully compliant with v2.2
Core Peripheral Apps.
Interface Target Register Interface Target FIFO Interface Master Interface Cardbus CSTSCHG Registers Power Management Interface EEPROM Interface Configuration Registers
specification
EEPROM
32bit data address buses 33/66MHz options Backend user clock
Target FIFOs
Controller (optional)
Master FIFOs
speed
Optional Power Management Interface
User Target Registers
Customer Backend Logic
User Config. Registers
v1.1) CLKRUN# protocol support v1.1)
Optional BIOS interface
Block Diagram
BAR, configurable address range
Cardbus CSTSCHG, Audio
interrupt support
Overview
InventraMPCI32 Peripheral Soft Core implements Master/Target function 32bit peripherals connecting 32bit Bus. core factory-configurable Target channels many other features including power management BIOS support. also implemented Target-only device required. target channels have either simple register file interface they interface dual FIFOs. FIFO option offers both increased performance support delayed reads posted writes. There also option dual FIFOs interfacing master channel. Versions available running either 33MHz 66MHz. design fully compliant with v2.2 local standard. also fully supports CLKRUN# power management protocol Cardbus specification, including CSTSCHG Status Changed Notification Wakeup protocol. will ideal peripheral cards, embedded drivers host bridge applications. order form available specifying configuration require. testbench provided with your core will tailored your chosen core configuration will contain full suite compliance tests. will also contain behavioral functional models that could re-used system-level testbench.
Target channels, with
Register file FIFO interface (configurable size)
Optional Master channel
with/without function
Separate FIFOs Support Interrupt Requests Configuration registers optionally
loadable from external EEPROM read/written backend
User registers patched into
configuration space
Vital Product Data Interface
supported
VHDL Verilog source Scan test ready
Potential Applications:
peripheral cards Embedded drivers host bridge applications
www.mentor.com/inventra
InventraMPCI32 32bit 33/66MHz Soft Core w/Cardbus support
Interface Interface offered InventraPCI Peripheral core complies fully with V2.2 Specification. signals synchronous with core system clock. Target Interface Target Interface provides necessary data command interface signals application interface. InventraPCI Peripheral core offers choice Register file FIFO interface target channels. Register file interface, which written/read either interface backend, defined bits wide, depth configurable. FIFO interface bits wide features separate FIFOs, also configurable depth. FIFO interface offers increased performance support posted writes delayed reads. Master Interface Master Interface provides necessary interface signals initiating burst transfers bus. backend supplies start address commands: further protocol handled master state machine. Again design features separate FIFOs configurable depth. optional controller used chain together transactions where data block size larger than FIFO. Configuration Registers registers configuration space available on-the-fly programming. Configuration registers optionally loadable external EEPROM Interface and/or backend interface. This used override default values Device Class Code, Subsystem etc. optional additional interface allows user custom registers into configuration address space. Reference Technology Gate Count: 10,000 30,000 (actual count depends options selected FIFO sizes used)
2000-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
BIOS Interface BIOS interface contains control circuitry needed support external BIOS ROM. core offers interface industry-standard EEPROM. core automatically assembles bytes from into words. Vital Product Data defined v2.2) also supported. Cardbus CSTSCHG Support CSTSCHG optional Cardbus signal that used card notify host changes such things card's Write Protect, Ready/Busy Battery Voltage status. also used `wake card slot that been powered down. MPCI provides standard registers controlling these functions controlling card-generated audio signals interrupts. Configuration Options core been designed offer range configuration options through mixture modular design parameterized code. Configurable features include speed, whether design offers both master target channels just target only, whether master channel includes interface, number target channels type target channel interface. sample version provided Inventra Soft Cores configured 66MHz master with targets, EEPROM interface, power management module, separate module. Other versions available request. Specifications
Core Specifics
(frontend) Width bits Peripheral Interface (backend) Width bits System Clock (fmax) 33/66MHz (depending specific core design implementation) Documentation Product Specification; User Guide Design File Formats Verilog VHDL Source Synthesis Scripts Scripts Timing Constraint Files with Synopsys Design Compiler Comprehensive Test Suite Tailored core configuration
Provided with Core
Knowledge Specification expected. user also expected familiar with design methodology.
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PD-40100.003-FO

32bit 33/66MHz Core w/Cardbus support Cardbus Soft Core (RTL

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