HSEN Soft Core (RTL Optional Clock Divider FSEN Clock E

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HSEN Soft Core (RTL Optional Clock Divider FSEN Clock E

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InventraMI2Cv2 Interface
HSEN
Soft Core (RTL
Optional Clock Divider FSEN
Clock Enable Filter
Major Product Features:
ISCL ISDA IFSDA
Conforms V2.1
specification
Supports High speed (3400kbits/s),
ADDRESS[2:0] WDATA[7:0]
Fast Standard transfer rates
Data Register
Supports isolation Master slave operation Multi-master systems supported
OSCL OSDA
Interface
RDATA[7:0] INTR
Supports both 7-bit 10-bit
addressing
Performs arbitration clock
Clock Data Controller
CKISO DAISO DAGND ENDRV
synchronization
address General Call
address detection
Interrupt address detection Allows operation from wide range
CLOCK
MI2Cv2 Block Diagram
input clock frequencies
8-bit PVCI -compatible
synchronous interface
Overview
MI2Cv2 provides interface between microprocessor that conforms V2.1 specification. programmed operate either master slave device performs arbitration master mode allow operate multi-master systems. slave mode, interrupt processor when recognizes 7-bit 10-bit address general call address. design supports both High speed (Hs) Fast Standard speed (F/S) transfer rates. user define transfer rate using either clock enable signals pair clock control registers similar that offered InventraMI2C MI2CV designs. Access core's internal control status regis ters provided synchronous PVCI*-compatible interface (with default acknowledge). This interface allows core readily interfaced range popular on-chip buses such AMBA buses associated with CoreConnectarchitecture. MI2Cv2 used application that uses devices. These primarily consumer telecommunications market segments. also used board-level communications protocol.
Fully synthesizable
Deliverables:
Verilog source code VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
Related Products:
MI2C Interface MI2CV Interface with
PVCI-compatible Interface
Peripheral Virtual Component Interface, defined VSIA (OCB v2.0)
www.mentor.com/inventra
InventraMI2Cv2 Interface Soft Core
Operating Modes MI2Cv2 operate four modes: Master Transmit; Master Receive; Slave Transmit; Slave Receive. MI2Cv2 will automatically enter Slave Transmit mode receives Slave Address Read bit. will similarly enter Slave Receive mode receives either Slave Address Write bit, General Call Address. Status Information state interface time indicated status code MI2Cv2's STAT register. There status codes corresponding different possible states MI2Cv2, plus further code that indicates when relevant status information available. states reported cover conditions from successful transmission errors loss arbitration. microprocessor should respond different conditions detailed MI2Cv2 Product Specification. Signal Description MI2Cv2 external signals; inputs outputs.
SIGNAL CLOCK HSEN FSEN ADDRESS[2:0] WDATA[7:0] ISCL ISDA IFSDA RESETN RDATA[7:0] CKISO DAISO DAGND INTR ENDRV OSCL OSDA TYPE Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output DESCRIPTION Master Clock Input Clock Enable, High speed (Hs) mode Clock Enable, Fast/Standard speed (F/S) mode Processor address lines Processor input data Access Validate Read/Write Indicator input clock line input data line input data line Master Reset, active Processor output data Isolate Isolate Drive ground Processor interrupt line Enables active pull-up during data transfer output clock line output data line
CKISO DAISO DAGND IFSDA
Clock Speed rate which data transmitted sampled from defined clock enables, Fast/Standard mode (FSEN) High speed mode (HSEN). defined clock speeds kbits/s `Standard mode', kbits/s `Fast mode' 3400 kbits/s `High speed mode' sampling rate must least10x maximum data rate used specified mode. This defines frequencies clock enables must have. required FSEN HSEN signals either generated externally clock divider that optionally included MI2Cv2 design. High Speed Mode Master arbitrate select high speed operation transmitting reserved 7-bit addresses form 00001xxxb. first five bits this address significant: remaining three bits used identify different High speed mode masters same bus. detecting code this form, MI2Cv2 enters High speed mode. will revert Fast/Standard speed mode detection STOP condition bus. Isolation devices that only operate Fast/Standard (F/S) speed confused High speed (Hs) data. prevent this, MI2Cv2 additional control logic which isolates portion from high speed section during high speed data transfers separate data input line IFSDA.The diagram below shows signals involved CKISO, DAISO DAGND IFSDA data input line might connected.
VDD1
VDD2
Reference Technology Gate Count: 1800 (NAND equivalents)
2000-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
MI2Cv2 with
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ISCL OSCL ISDA OSDA
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03/02
PD-40115.003-FO

HSEN Soft Core (RTL Optional Clock Divider FSEN Clock E

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