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CLOCK CLOCK DIVIDER CONTROLLER OSCL Major Product


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Soft Core (RTL InventraMI2CV Interface with PVCI-compatible
CLOCK
CLOCK DIVIDER
CONTROLLER
OSCL
Major Product Features:
Master slave operation Multi-master systems supported
ADDRESS[2:0] WDATA[7:0]
Allows 10-bit addressing with
SHIFT REGISTER INTERFACOSDA
Performs arbitration clock
synchronization
address General Call
ACTIVITY DETECTOR
ISCL
RDATA[7:0] INTR
FILTER
address detection
Interrupt address detection Supports speeds 400Kbits/s
ISDA
(`fast mode') MI2CV Block Diagram
Allows operation from wide range
input clock frequencies
Overview
MI2CV provides interface between microprocessor that conforms Philips Protocol (April 1995 Update). operate either master slave mode. performs arbitration master mode allow operate multi-master systems. slave mode, interrupt processor when recognises 7-bit 10-bit address general call address. Access core's internal control status registers provided synchronous PVCI-compatible interface (with default acknowledge). This interface allows core readily interfaced range popular on-chip buses such AMBA buses associated with CoreConnectarchitecture. MI2CV used applications which devices. These primarily consumer telecoms market segments. also used board level communications protocol.
8-bit PVCI -compatible
synchronous interface
Fully synthesizable
Deliverables:
Verilog source code VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
Related Product:
MI2Cv2 Interface
Peripheral Virtual Component Interface, defined VSIA (OCB v2.0)
www.mentor.com/inventra
InventraMI2CV Interface Soft Core
Operating Modes MI2CV operate four modes: Master Transmit; Master Receive; Slave Transmit; Slave Receive. MI2CV will automatically enter Slave Transmit mode receives Slave Address Read bit. will similarly enter Slave Receive mode receives either Slave Address Write bit, General Call Address. Status Information state interface time indicated status code recorded MI2CV's STAT register. There status codes corresponding different possible states MI2CV, plus further code that indicates when relevant status information available. states reported cover conditions from successful transmission errors loss arbitration. appropriate microprocessor responses reported interface condition MI2CV actions these invoke detailed MI2CV Product Specification.
MASTER
Signal Description MI2CV external signals; inputs outputs.
SIGNAL CLOCK RESETN ADDRESS[2:0] WDATA[7:0] RDATA[7:0] INTR ISDA ISCL OSDA OSCL TYPE Input Input Input Input Input Input Output Output Output Input Input Output Output DESCRIPTION Master clock input Reset, active Processor address lines Processor read/write indicator access validate Processor data input Processor data output Processor data output enable, active Processor interrupt line input data line input clock line output data line output clock line
Reference Technology Gate Count: 2500
SLAVE
IDLSTA
IDLSTART RECEIVED
SEND START
ADDR
ADDR CALL ADDR RECEIVED
SEND ADDR
LOST, ADDR RECEIVED LOST
FROM MASTER
SEND
EX.ADDR RESTART RECEIVED
SLAVE
LOST, ADDR RECEIVED
EX.ADDR (Restart)
LOST
SEND DATA DATA
AAK=1 AAK=0
SEND ACK/NACK
SEND NACK
DATA
SEND DATA
ACK, AAK=1
ACK/NACK
ACK, AAK=0 NACK STOP
SEND ACK/NACK
ACK/NACK
SEND DATA
ACK/NACK,
NACK,STP ACK/NACK,STP NACK,STA
ACK/NACK
ACK/NACK
SEND STOP
ACK/NACK
1997-2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
Corporate Headquarters Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, 97070 Phone: 503-685-7000 North American Support Center Phone: 800-547-4303 Fax: 800-684-1795
Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive Jose, California 95131 Phone: 408-436-1500 Fax: 408-436-1501
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Pacific Headquarters Mentor Graphics (Taiwan) Room 1603, 16F, International Trade Building No.333, Section Keelung Road Taipei, Taiwan, Phone: 886-2-27576020 Fax: 886-2-2756027
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04/02
PD-40135.001-FO

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