Transmit Buffer WDATA[7:0] Soft Core (RTL Major Product

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Transmit Buffer WDATA[7:0] Soft Core (RTL Major Product

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InventraMCAN2 Network Controller
Transmit Buffer
WDATA[7:0]
Soft Core (RTL
Major Product Features:
Supports full both 2.0A
RDATA[7:0]
(equivalent 1.2) 2.0B
Interface byte Receive FIFO
Supports 11-bit 29-bit identifiers Supports rates from less than
ADDRESS[7:0]
125KBaud more than 1MBaud
Acceptance Filter
64-byte Receive FIFO Synchronous PVCI -compatible
interface easy connection range microprocessors
Acceptance filtering
XTAL1
Timing Logic
Transmit Machine
Software-driven bit-rate detection
allowing plug-in support
Listen-Only Self-Reception modes
PROCESSOR
Self Test option Interrupt generated each error
Clock Divider
Receive Machine
Arbitration lost interrupt with
record position
Read/write error counters Programmable error limit warning
MCAN2 Block Diagram
Broadly compatible with Philips
SJA1000 PeliCAN mode
Fully synthesizable
Overview
InventraMCAN2 stand-alone controller Controller Area Network. provides interface between microprocessor which carries actions data encoding/decoding, message management, timing resynchronization involved transmitting receiving data over network. MCAN2 implements BOSCH Message Transfer Protocols 2.0A 2.0B. Specification 2.0A equivalent covers standard message formats (11-bit identifiers); specification 2.0B covers both standard extended message formats (both 11-bit 29-bit identifiers). MCAN2 broadly compatible with Philips SJA1000 working PeliCAN mode. interface compatible with Peripheral Virtual Component Interface (defined VSIA) ease connection range microprocessor buses.
Verified against Bosch CAN2.0
test suite
Deliverables:
Verilog VHDL source code Synthesis script Design Compiler Verilog VHDL testbench Reference technology netlist Product Specification, User Guide
Programmer's Guide
Peripheral Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraMCAN2 Network Controller Soft Core
Functional Description accesses MCAN2 controller through separate address, input data output data buses. Messages transmission placed Transmit Buffer from where they transmitted Transmit Engine within Processor. Messages received first filtered Acceptance Filter, then placed Receive FIFO. accesses Receive FIFO through 13-byte window referred Receive Buffer. Receive Buffer conjunction with Receive FIFO allows process message while other messages being received. Receive FIFO bytes length used circular fashion, giving capacity accommodate five Extended Frame Format messages time. interface provided TX0, signals. normally inverse programmed output Transmit clock required. Intended MCAN2 designed between Host microprocessor standard transceiver. transceiver responsible putting logical levels from MCAN2 onto bus. itself usually twisted pair which into differential inputs transceiver. figure below shows usual arrangement which drives transceiver. However, output (described above) gives system designer option creating their interface instead using standard transceiver.
MICROPROCESSOR
Signal Description MCAN2 external signals; inputs outputs.
SYMBOL WDATA[7:0] ADDRESS[7:0] XTAL1 NRST NINT_IN TEST RDATA[7:0] CLKOUT NINT NINT_EN TX0_EN TX1_EN XTAL1_IN NXTAL1_ENABLE TYPE Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Input Output DESCRIPTION Data input. Address bus. System clock. input (from transceiver). Reset, active low. Access Validate. Read signal. Input from NINT bi-direct buffer. Used wake device from Sleep Mode. Test allow better fault coverage). Data output. Clock output signal derived from divided input clock. Interrupt output. Used interrupt host microcontroller. Enable Interrupt signal, which opendrain. Serial output output driver Serial output output driver Enable signal TX0. Enable signal TX1. Gated system clock. Enable XTAL1_IN, active low. Used disable XTAL1_IN while Sleep Mode.
RDATA[7:0]
ADDRESS[7:0]
WDATA[7:0]
MCAN2
CANL
TRANSCEIVER (82C250)
CANH
Acceptance Filtering MCAN2 allows pre-filtering received messages applying Acceptance Filter received data. Only messages with identifier bits that match filter passed Receive FIFO. filtering carried using four 8-bit Acceptance Code Registers (which record patterns match), together with four 8-bit Acceptance Mask Registers which mark particular bits Acceptance Code patterns `don't care'. Both sets registers applied either single 32-bit filter first bytes each received message, separate 16-bit filters first bytes message. Acceptance Mask Registers allow groups messages with similar identifiers accepted. Reference Technology Gate Count: 22000
2000-2001 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
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PD-40107.001-FO

Transmit Buffer WDATA[7:0] Soft Core (RTL Major Product

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