Soft Core (RTL Major Product Features: Registers interface
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InventraM82801IDE ATA-5 UDMA/66 Controller Core
Soft Core (RTL
Major Product Features:
Registers interface
Configuration
compatible with Controller Intel 82801A Controller
Independent primary secondary
PVCI Interface Initiator
(Bus Master mode) Primary
channels
Primary Timing Data Buffering
Initiator Wrapper
Support devices
channel
Programmable control base
Target Wrapper
Target
(Bus Slave mode)
Secondary Timing
Secondary
address
Independently programmable timing
each device
M82801IDE Block Diagram
Programmable posted writes
read-prefetch each channel
Supports Modes 0,2,3,4
Overview
Inventra M82801IDE (Integrated Drive Electronics) controller, providing interface between data transmitted received from more devices. designed meet ATA-5 standard, interface register designed compatible with controller element Intel 82801A Controller. M82801IDE supports both primary secondary channels, with devices channel. timing each device individually configurable. Interface M82801IDE 32-bit synchronous interface that follows specification VSIA Peripheral Virtual Component (PVCI) Interface. This readily interfaced common types such AMBA AHB. interface intended MHz, allowing particularly easy interfacing 66MHz bus. However, also includes additional clock enable that makes equally easy with 33MHz bus. interface supports DMA, UDMA/33 UDMA/66 data transfer well (Modes also additional control signals allowing insertion external bi-directional data buffers required.
Supports Programmable Supports Ultra (33),
(66)
32-bit PVCI*-compatible synchronous
interface; optional PVCI bridge
Support plug play
interfaced
Support external bi-directional
buffers required
Fully synthesizable
Deliverables:
Verilog source code VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
Peripheral Virtual Component Interface, defined VSIA (OCB v2.0)
www.inventra.com
InventraM82801IDE ATA-5 UDMA/66 Controller Core
Clock (CLOCK)
M82801IDE designed 66MHz (period 15ns). timings PIO, UDMA given Product Specification have been calculated assuming that 66MHz clock used. deviation from recommended 66MHz, 15ns clock will reduce transfer bandwidth proportionally.
Signal Description
M82801IDE external signals: inputs outputs.
PVCI TARGET (BUS SLAVE) SIGNALS SIGNAL CLOCK CLOCK2 RESETN WDATA[31:0] RDATA[31:0] BE[3:0] ADDRESS[31:0] PBIRQ SBIRQ CFSEL RERROR[2:0] TYPE Input Input Input Input Output Input Input Input Input Output Output Output Input Output DESCRIPTION timing reference (66MHz) Clock modifier slowing down 33MHz Reset (Active low) 32-bit Target write data 32-bit Target read data Transfer byte enables (Free-BE mode supported) 32-bit address Target Read Write Target Data Valid indicator Target Acknowledge Primary interrupt request Secondary interrupt request Configuration register access, Data access Target Response Error
PVCI-compatible Interface
interface designed conform VSIA Peripheral Virtual Component Interface (PVCI) specification. generic format this interface allows bridges made from common standards M82801IDE without redesign M82801IDE core logic. PVCI Target Initiator interfaces both clocksynchronous: outputs registered inputs sampled rising edge CLOCK. signals uni-directional external logic would required form bi-directional multiplexed address/data buses. fastest transfers completed rising edge CLOCK after address, byte enables (BE[3:0]), Read /Write signal (RD) Data Valid signal (VAL) become valid. interface nominally runs 66MHz (the frequency CLOCK input). However, integration with slower buses such 33MHz bus, core includes CLOCK2 input which connected 33MHz timing reference tied 66MHz operation).
PVCI INITIATOR (BUS MASTER) SIGNALS NMRQ Output Master request (low true) NMGT Input Master request granted (low true) Output Initiator Read Write MVAL Output Initiator Data Valid indicator MACK Input Initiator Acknowledge MADDRESS[31:0] Output Initiator read write address MWDATA[31:0] Output 32-bit Initiator write data MRDATA[31:0] Input 32-bit Initiator read data MBE[3:0] Output Initiator byte enables MEOP Output Initiator Packet (inverted burst) MABORT Input Initiator Transfer abort MTABORT Input Target Transfer abort PIDEO[15:0] PIDEI[15:0] NPIDEEN PADD[2:0] NPIOR NPIOW PIORDY NPCS0 NPCS1 PDREQ NPDACK PIRQ NPDIR SIDEO[15:0] SIDEI[15:0] NSIDEEN SADD[2:0] NSIOR NSIOW SIORDY NSCS0 NSCS1 SDREQ NSDACK SIRQ NSDIR PRIMARY INTERFACE Output data Input data Output bi-direct control signal (low true) Output Address Output Read strobe (low true) Output Write strobe (low true) Input Allows device extend cycle Output select data/command (low true) Output select status/control (low true) Input transfer request Output transfer acknowledge (low true) Input interrupt Output External buffer control Write IDE, Read IDE) SECONDARY INTERFACE Output data Input data Output bi-direct control signal (low true) Output Address Output Read strobe (low true) Output Write strobe (low true) Input Allows device extend cycle Output select data/command (low true) Output select status/control (low true) Input transfer request Output transfer acknowledge (Low true) Input interrupt Output External buffer control Write IDE, Read IDE)
Data Port Transfers
Transfers to/from Data Port bits wide, with multiple byte writes PVCI interface being split into consecutive 16-bit transfers Data Port. These transfers take form prefetched reads posted writes. Post-write read-prefetch allow buffering sixteen double words 32-bit). Posted writes have priority over reads. posted writes must have finished before read take place posted writes prefetched reads share same buffers.
Interrupt Control
There provision within M82801IDE interrupt steering. M82801IDE controller simply synchronizes interrupt clock before passing synchronized interrupt bus. M82801IDE does however include some circuitry generation status information upon either interrupts becoming active.
Reference Technology Gate Count: 25000
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PD-40111.002-FO
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