RCLK RCLK_BAUD BRGE Soft Core (RTL BAUD RATE GENERATOR

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

RCLK RCLK_BAUD BRGE Soft Core (RTL BAUD RATE GENERATOR

Datasheet Thumbnail

Top Searches for this datasheet

InventraM16550S Enhanced UART with FIFOs Synchronous
RCLK RCLK_BAUD BRGE
Soft Core (RTL
BAUD RATE GENERATOR
BAUD
Major Product Features:
Software compatible with
16550AF device
ADDRESS[2:0] WDATA[7:0] RDATA[7:0] NDVL
Programmable word length, stop bits
FIFO
TRANSMIT MACHINE
parity
SOUT
Programmable baud rate generator PVCI -compatible interface Interrupt generator
FIFO
RXRDY,TXRDY
RECEIVE MACHINE
Diagnostic loop-back mode Scratch register 16-byte FIFOs
Modem Outputs RESETN CLOCK
MODEM CONTROL
Fully synthesizable
Modem Inputs
Scan test ready
M16550S Block Diagram
Deliverables:
Verilog source code
Overview
InventraM16550S core provides fully programmable UART that functionally compatible with 16550AF device with established InventraM16550A core. Like 16550AF M16550A, M16550S supports transmission word lengths from five eight bits, together with optional parity stop bits. also includes 16-byte FIFOs transmit receive, 16-bit programmable baud rate generator, 8-bit scratch register handshake lines, which configured either support singlebyte transfers (DMA Mode multiple-byte transfers (DMA Mode Unlike 16550AF M16550A, M16550S offers synchronous interface. This interface compatible with Peripheral Virtual Component Interface (PVCI) defined VSIA allows core readily interfaced range popular on-chip buses such AMBA buses associated with CoreConnectarchitecture. M16550S also includes eight modem control lines diagnostic loopback mode. Interrupts generated range Buffer/FIFO, Buffer/FIFO, Modem Status Line Status conditions.
VHDL source code Synthesis script Design Compiler Verilog VHDL testbenches Reference technology netlist Product Specification User Guide
Peripheral Virtual Component Interface, defined VSIA (OCB v1.0)
www.mentor.com/inventra
InventraM16550S Enhanced UART with Synchronous
Transmit Operation Transmission initiated writing data sent Holding Register FIFO enabled). data then transferred Shift Register. bits transmitted then shifted Shift Register using output from Baud Rate Generator clock. With FIFO enabled, core store bytes transmission time. Receive Operation Data sampled into Shift Register using either output from Baud Rate Generator RCLK input Receive clock (used divided 16). filter used remove spurious inputs that last less than periods Receive clock. When complete word been clocked into receiver, data bits transferred Buffer Register FIFO enabled) read CPU. With FIFO enabled, core store bytes received data time. Read/Write timing
READ
CLOCK
Signal Description M16550S external signals; inputs outputs.
INTERFACE SIGNALS SIGNAL CLOCK RESETN ADDRESS[2:0] WDATA[7:0] RDATA[7:0] NDVL TYPE Input Input Input Input Input Master Clock Input. Master Reset, active low. De-asserts ACK. Address lines. Read/Write indicator. High Read; Write. register read/written selected ADDRESS[2:0] DLAB (LCR[7]). Access Validate. DESCRIPTION
Output Access Acknowledge. Input Data Input. Must valid during write cycles.
Output Data Output. Register returned depends state ADDRESS[2:0] DLAB (LCR[7]). Output Output Valid, Bi-directional Buffer Control. Goes when both high indicate that output data valid. Output Interrupt Request. High whenever enabled interrupts valid. Output Handshake. Goes when FIFO contains data. Output Handshake. Goes when FIFO requires data. SERIAL INTERFACE SIGNALS
RXRDY TXRDY
WRITE
SIGNAL BAUD
TYPE Output Input Input
DESCRIPTION Receive/Transmit Clock, derived from divided value divisor latch DLM. Baud Rate Generator Enable. When low, Baud Rate Generator stopped. connected pre-scaler. Receive Clock. When RCLK_BAUD high, this input ignored. When RCLK_BAUD low, this input used generate receiver clock. RCLK Select. When tied high, Receive clock taken from Baud Rate Generator. When tied low, Receive clock taken from RCLK. Serial Input. Data clocked using RCLK/16. Serial Output. Data clocked using output from Baud Rate Generator, divided by16. Data Carrier Detect, MSR[7] status bit. Active low. Ring Indicator, MSR[6] status bit. Active low. Data Ready, MSR[5] status bit. Active low. Clear Send, MSR[4] status bit. Active low. General Control, MCR[3] control bit. Active low. General Control, MCR[2] control bit. Active low. Request Send, MCR[1] control bit. Active low. Data Terminal Ready, MCR[0] control bit. Active low.
BRGE
RCLK
ADDRESS[2:0]
ADDRESS VALID
ADDRESS VALID
RCLK _BAUD
Input
RDATA[7:0]
DATA VALID
WDATA[7:0]
DATA VALID
Input Output Input Input Input Input Output Output Output Output
SOUT NDCD
NDVL
Transmission Baud Rate principal method selecting transmission baud rate Divisor Latch, which allows incoming clock divided values between 65535. facilitate standard UART drivers, design also includes BRGE input which used conjunction with external logic) scale input frequency Baud Rate Generator frequency expected UART driver.
2000-2001 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
NDSR NCTS NOUT2 NOUT1 NRTS NDTR
Reference Technology Gate Count: 6800
Corporate Headquarters Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, 97070 Phone: 503-685-7000 North American Support Center Phone: 800-547-4303 Fax: 800-684-1795
Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive Jose, California 95131 Phone: 408-486-1500 Fax: 408-436-1501
European Headquarters Mentor Graphics Corporation Immeuble Pasteur 13/15, Jeanne Braconnier 92360 Meudon Foret France Phone: 33-1-40-94-74-74 Fax: 33-1-46-01-91-73
Pacific Headquarters Mentor Graphics (Taiwan) Room 1603, 16F, International Trade Building No.333, Section Keelung Road Taipei, Taiwan, Phone: 886-2-27576020 Fax: 886-2-2756027
Japan Headquarters Mentor Graphics Japan Co., Ltd. Gotenyama Hills 7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo Japan Phone: 81-3-5488-3030 Fax: 81-3-5488-3031 06/01
PD-40125.002-FO

RCLK RCLK_BAUD BRGE Soft Core (RTL BAUD RATE GENERATOR

Top Searches for this datasheet

Other recent searches