AMCXTFIF_SYS InventraSoft Core (RTL Major Product Features:

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AMCXTFIF_SYS InventraSoft Core (RTL Major Product Features:

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A-MCXFIFFIFO Memory Interface PE-MCXMACPEMXCMAC Core
AMCXTFIF_SYS
InventraSoft Core (RTL
Major Product Features:
GMII
A-MXCFIF Core
Fabric
AMCXTFIF_FAB
Operates 1000 Mbps Provides data queuing increased
Fabric Module
Generic Synchronous port SRAM Model
System Module
system level throughput
User definable storage sizes
AMCXRFIF_FAB
Fabric Module
Generic Synchronous port SRAM Model
AMCXRFIF_SYS
System Module
frequency independent ports Single multiple word data transfers Programmable storage
AMCXFIF_HST
Host Register Module
AMCXFIF_CLKRST
AMCXTFIF_W
Clock Reset Module
Watermark Module
level indicators, plus storage under-run indication
frame insertion inspection Automatic pause frame handshaking Programmable pause frame
HOST
handshaking reassertion interval
Graceful memory full frame drop
A-MCXFIF Application
Graceful enable disable Programmable frame word cut-
through threshold
Overview
A-MCXFIFfrom Alcatel flexible FIFO module, transmit receive buffering which significantly improve performance embedded 10/100/1000 Mbps Ethernet systems. integrates with PE-MCXMAC10/100/1000 Mbps Ethernet module (also available from Mentor Graphics Inventra Soft Core Library) functions PE-MCXMAC's modes. A-MCXFIF gate count, easily synthesizable FIFO module that offers increased system level throughput through allowing data queuing. Automatic pause frame handshaking transmit frame configuration data both supported. Other features this logic module clock-frequency-independent ports, single multiple word data transfers, full memory utilization with graceful memory full frame drop. A-MCXFIF module also provides programmable high receive storage level indicators pause frame handshaking re-assertion intervals, high transmit storage level indication, frame insertion inspection capabilities. A-MCXFIF module provided Verilog source code, with full test suite module level documentation. design synthesized .5µm CMOS better). A-MCXFIF ideal with synchronous dual-port memories.
storage frame rewind capabilities Full memory utilization Optional transmit frame
configuration data supported
gate count Fully synthesizable Scan insertion-friendly design Ideal with synchronous
dual-port memories
Deliverables:
Verilog source code Functional testbench Synopsys constraint files Module-level documentation
Mentor Graphics leading supplier broad range soft cores targeting standard-based communications applications. These highly re-usable cores help systems chip designers market faster.
www.mentor.com/inventra
A-MCXFIF FIFO Memory Interface Soft Core PE-MCXMAC
Structure A-MCXFIF consists following seven major logic sub-modules: AMCXTFIF_FAB FIFO Fabric Transmit Interface Module AMCXTFIF_SYS FIFO System Transmit Interface Module AMCXRFIF_FAB FIFO Fabric Receive Interface Module AMCXRFIF_SYS FIFO System Receive Interface Module AMCXTFIF_WFIFO System Watermark module AMCXFIF_HST FIFO Host Interface Module AMCXFIF_CLKRST FIFO Clock Reset Module Implementation A-MCXFIF module PE_MCXMAC core have been optimized multiple-MAC applications. These include switches, multi-port-port interface cards, NICs routers. exact nature common sections system data transport, address recognition statistics will application dependent, PE-MCXMAC A-MCXFIF cores have enough built-in flexibility cover almost system concept. Host Interface Options A-MCXFIF module PE_MCXMAC core connect host system. host system different types. switch system, host will generally embedded back plane switching fabric. Testbenches A-MCXFIF supplied with testbenches, which verifies A-MCXFIF when integrated with PE-MCXMAC, which verifies their operation together. Each testbench described separate Verification document. Signal Description
Clock Reset Signals External hard reset; Reset bypass AMCXMAC transmit clock (post tree) A-MCXFIF Fabric clock (post tree) A-MCXFIF receive clock (post tree) A-MCXFIF Fabric clock (post tree) Host Signals Host reset Host clock Host chip select Host read write Host address Host input data Host output data Host output data enable System Transmit Signals AMCXMAC transmit clock enable Transmit packet start frame Transmit packet data Transmit packet frame Transmit packet under Transmit packet control frame Transmit packet override Transmit packet mode; mode Transmit packet need data Pause request Pause value Pause acknowledge Transmit packet retransmit Transmit packet abort System Receive Signals AMCXMAC receive Clock enable Receive packet start frame System Receive data Receive packet data valid Receive packet frame Receive packet drop frame Receive statistics vector pulse Receive unicast address match Fabric Transmit Signals Fabric transmit ready Fabric transmit accept Fabric transmit start frame; frame Fabric transmit frame data Fabric transmit data valid Fabric transmit packet enable Fabric transmit packet generate Fabric transmit packet mode Fabric transmit control frame Fabric transmit high watermark Fabric Receive Signals Fabric receive accept Fabric receive start frame; frame Fabric receive frame data Fabric receive data valid Input Input Input Input Output Input Input Input Input Input Input Input Output Input Output Output Output Output Output Output Output Input Output Output Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Input Input Input Input Output Output Output
2002 Mentor Graphics Corporation, Rights Reserved. Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
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PD-59060.001-FO

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