STS-192 SONET/SDH/FEC/GbE 16-bit Transceiver with Compensation sp

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

STS-192 SONET/SDH/FEC/GbE 16-bit Transceiver with Compensation sp

Datasheet Thumbnail

Top Searches for this datasheet

S19237
STS-192 SONET/SDH/FEC/GbE 16-bit Transceiver with Compensation
speed phase detector, clock dividers, clock distribution. device utilizes on-chip clock synthesis components that allow slower external clock reference, 155.52 622.08 equivalent FEC/10GbE rate), support existing system clocking schemes. low-jitter, 16-bit, Voltage Differential Signaling (LVDS) interfaces guarantee compliance with bit-error rate requirements Telecordia ITU-T (GR-253 ILR) standards. device also compliant standard Transponders, SFI4 Phase Parallel Electrical Interface standard, IEEE Draft P802.3ae, standard.
AMCC Suggested Interface Devices
VERRAZANO (S2509) Quad STS-48 SONET/SDH/ Digital Wrapper Backplane SERDES STS-192 POS/ASONET/ Mapper STS-192 POS/ASONET/ Mapper Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, Device STS-192 Pointer Processor
Product Brief
PB1304_v2.03_10/03/03
Glance
Features
Operational from 9.953 Gbps 10.709 Gbps Power (1.0 Typical) CMOS 0.13 Micron Technology 1.8/2.5/3.3 Power Supply Built-In Self Test (BIST) feature with Error Counter On-chip High-Frequency PLLs Clock Recovery Clock Generation 16-bit LVDS Parallel Data Path Lock Detect Indicators Serial Reference Loop Timing Modes Line Diagnostic Loopback Mode Faulty Mode Identification SONET Jitter Transfer Compliance with External XVCO -40°C 85°C Industrial Temperature Range Supports High Speed Management Data Control (MDIO) Complies with SFI-4 Phase Telecordia/ITU-T GR-253-ILR, 300pin MSA, IEEE Draft P802.3ae Standards Rating Pins heatsink airflow required power sequencing required PBGA Package, options pitch pitch
Description
S19237 SONET/SDH/FEC Gigabit Ethernet (GbE) transceiver latest additions AMCC's SuperPHYproduct family. S19237 device provides fully integrated serialization/de-serialization capabilities power intermediate long reach OC-192 applications. device performs necessary parallel-to-serial serial-to-parallel functions conformance with SONET/SDH transmission standards. standard operating range from 9.953 Gbps 10.709 Gbps. Figure shows typical network application. Other application block diagrams shown Figure Figure Figure
GANGES (S19202) GANGES (S19202) HUDSON (S19203)
Overview
S19237 used implement front SONET/SDH/FEC/ 10GbE equipment which consists primarily serial transmit interface serial receive interface. system timing circuitry consists high-
MEKONG (S19204) KHATANGA (S19205)
STS-192c SONET/SDH Framer/Mapper with Integrated Gbps
S3390
AMCC
GANGES HUDSON MEKONG KHATANGA
AMCC S19237
AMCC S19237
AMCC
GANGES HUDSON MEKONG KHATANGA
Figure System Block Diagram
Empowering Intelligent Optical Networks
S19237
STS-192 SONET/SDH/FEC/GbE 16-bit Transceiver with Compensation
sequence operations follows: Transmitter Operations 16-bit parallel input Parallel-to-serial conversion Serial data output Receiver Operations Serial input limiting post-amp compensation
Enable Negative Feedback Offset Adjust Compensates FR-4
Product Brief
PB1304_v2.03_10/03/03
Variable gain limiting amplifier Threshold phase adjustment improved Clock data recovery Serial-to-parallel conversion 16-bit parallel data clock output Internal clocking control functions transparent user.
Transmitter Features Reference Frequency 155.52 622.08 equivalent FEC/ 10GbE rate) 155.52 622.08 equivalent FEC/10GbE rate) Clock Outputs Internal, Self-Initializing FIFO Decouple Transmit Clocks Programmable Output Differential Swing Receiver Features Clock Recovery from 9.953 10.709 Gbps compensation. Tolerates additional ps/nm with OSNR penalty Tolerates Standard FR-4 Material 10GbE Jitter Tolerance Compliance Adaptive Post-Amplifier Offset Adjust minimize offset high OSNR conditions Phase Adjust -0.11 +0.085 Reference Frequency 155.52 equivalent FEC/ 10GbE rate) Capability Interface with SingleEnded Differential TIAs (Center Option) Input Sensitivity (single-ended measurement) 10-12
MDIO ASIC
AMCC S19237
MDIO AMCC S19237
ASIC
Adjust Mitigation Equalization Adjust
Figure Mid-Plane Application Block Diagram
Enable Negative Feedback Offset Adjust Adjust Mitigation Equalization Adjust
MDIO ASIC FRAMER AMCC S19237 MODULE
Compensates FR-4 (Improves Performance extends reach standard Module)
Figure Application Block Diagram
ASIC FRAMER
MODULE
Laser
AMCC S19237
Laser Driver
Applications
SONET/SDH 10GbE-Based Transmission Systems SONET/SDH Modules Section Repeaters Drop Multiplexers (ADM) Broad-Band Cross-Connects Fiber Optic Terminators Test Equipment
AMCC reserves right make changes products, discontinue product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied upon current. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2003 Applied Micro Circuits Corporation. Rights Reserved.
Post Amplifier Required
Figure Application Block Diagram
Prefix Integrated Circuit Device 19237 Package PB12 (255 PBGA, pitch) (255 PBGA, pitch)
Prefix
XXXXX
Device
Package
Figure S19237 Ordering Information
Distribute only need-to-know basis, subject applicable NDA. disclosed used other person without prior authorization.
Confidential Proprietary
6290 Sequence Drive Diego, 92121 Tel: 450-9333 Fax: 450-9885 http://www.amcc.com
Empowering Intelligent Optical Networks

STS-192 SONET/SDH/FEC/GbE 16-bit Transceiver with Compensation sp

Top Searches for this datasheet

Other recent searches