Features AS-i Complete Specification V2.11 compliant Integrated E

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Features AS-i Complete Specification V2.11 compliant Integrated E

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Advanced AS-Interface
Features
AS-i Complete Specification V2.11 compliant Integrated EEPROM Additional addressing channel using opto-electronic interface Extended address mode operation programmable option slaves) High impedance AS-i line input, additional pins further impedance optimizations voltage output, approximately volts, stabilized volt voltage output, stabilized, CMOS logic supplied directly (e.g. status indicator output (compliant with standard indication recommendation) Integrated watchdog
Description
monolithic CMOS integrated circuit certified AS-i (Actuator Sensor-interface) networks. AS-i networks intended industrial automation. main advantage AS-i solutions that actuators sensors connected using two-wire unshielded cable that easy install. This cable transports both power information/data. AS-i network communication based master-slave principle. network extended cable lengths greater than 100m) using repeater mode configuration. AS-i standard automation industry based 62026-2 50295. device available 28-pin SSOP package.
Block Diagram
U5RD OSC1/2
RCAP CCAP
A2SI
POWERFAIL DETECTION
ELECTRONIC INDUCTOR
POWER SUPPLY
OSCILLATOR
RECEIVE TRANSMIT
ASI+
ASIP
DIGITAL LOGIC
ASI-
ASIN
THERMAL PROTECTION
GND2
Figure Block Diagram
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
Description
Name ASIP ASIN OSC2 OSC1 U5RD UOUT Type INOUT INOUT SUPPLY INOUT SUPPLY SUPPLY IN/OUT SUPPLY Description connected AS-i-line ASI+ reverse polarity protection diode connected AS-i-line ASICommon ports except ASIP/ASIN connected ASI- line) Addressing channel input Input peripheral fault indication Crystal oscillator x-tal) Crystal oscillator external clock input Output data Output data Output data Output data Digital ground, must connected Input/output parameter Input/output parameter receive strobe "Master Mode" Input/output parameter power fail "Master Mode" Input/output parameter data clock "Master Mode" Input data Input data Input data Input data Parameter strobe output Data strobe output/reset input Digital supply input, should connected Output "AS-i-Diagnosis" addressing channel output connection external components Internal supply that might used supply external circuits well Supply external circuitry (e.g. sensor, actuator, etc.), approx. VUIN minus volt Input power supply block (usually connected AS-i-line ASI+ reverse polarity protection diode)
Table Description
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
Configuration
ASIP ASIN OSC2 OSC1 U5RD PFigure Configuration, 28-Pin SSOP
A2SI
Functional Block Description
Power Supply
on-chip electronic inductor provides de-coupled voltage UOUT power supply regulates internal operating voltage. de-coupling circuit (electronic coil) connected between UOUT pins guarantees high impedance seen UIN. external capacitor resistor required allow lowpass filter with very high time constant. This high time-constant value necessary maximize input impedance. de-coupling circuit limits current that drawn from UOUT. power supply will shut down de-coupling circuit case overload condition prevent total malfunction complete AS-i line. regulated volt supply voltage connected U5R. external capacitors necessary cope with fast internal external load changes (spikes). Current drawn from subtracted from total load current. power supply circuit dissipates major amount power. total power dissipation shall exceed specified values Figure ground reference voltage both UOUT defined pin. This must connected ASI- (ref. Figure
Receiver
receiver detects signals AS-i line delivers appropriate pulses digital logic. value input signal removed signal band-pass filtered. digital output signals extracted from -shaped input pulses comparators. maximum voltage first negative pulse determines threshold level following pulses. maximum value digitally filtered guarantee stable conditions (burst spikes have effect). This approach combines fast adaptation changing signal amplitudes with high detection safety. receiver delivers positive (P-PULSE) negative (N-PULSE) pulses IC's logic. logic resets comparators after receiving REC-RESET signal. When receiver turned transmitter turned reduce power consumption.
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
Transmitter
transmitter draws modulated current between ASIP ASIN pins generate communication signals. shape current corresponds integral sin2-function. transmitter uses current high current driver. order activate high current drive capability, small current will turned automatically prior each transmission (slave mode only). current will ramped slowly avoid false voltage pulses AS-I line. amount circuitry between ASI+ ASI- pins minimized allow high impedance values. When transmitter turned receiver turned reduce power consumption.
Digital Logic
digital logic block performs analysis received signal, controls reaction transmits slave response, switches I/O-ports, controls internal EEPROM. principal function described detail section
Protection Circuitry
device several protection cells that prevent disruption malfunction complete AS-i line. thermal detection shuts down power supply case over-heating condition (silicon temperature 140°C typically more than seconds) when UOUT shorted more than seconds. device only reactivated power-on reset. over-heating condition occur overloading output pin. Therefore, circuit monitors operating conditions power supply (effectively monitors UOUT) measures temperature silicon.
Infrared Diode Input
photo current input used alternative communication slave mode. circuitry will turned when communication been switched AS-i line. Slave mode logic sets input photo-detector mode disables CMOS mode. this photo-detector mode, signals external photo diode amplified. CMOS mode (master/repeater mode only), input signals have CMOS levels between VU5R.
Power-Fail Detection
power-fail detector consists comparator that generates logic signal case power supply drops below 22VDC (Power-Fail) time more than tLoff (0.8 ms). power fail signal will presented master mode only. Power-fail detection monitors value ASIP voltage. will activate logic signal power fails more than 1ms. device then buffered external capacitor UOUT internal circuitry will reset when supply voltage fails
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
UOUT
U5RD
OSC1/2
A2SI
POWERFAIL DETECTION
ELECTRONIC INDUCTOR
POWER-ON
POWER SUPPLY
OSCILLATOR
OUTPUT STAGE
DO(3:0)
SHUT-DOWN
POWER-FAIL
DATA-OUT
RESET
P-PULSE
DATA-IN
INPUT STAGE
DI(3:0)
ASIP
RECEIVE
N-PULSE
RESET
STAGE
REC-RESET
DIGITAL LOGIC
DATA-STRB
PARAM STRB
ASIN
SEND-D
OUTPUT STAGE
PARAM
TRANSMIT
SEND-SBY
Logic
PARAM
THERMAL PROTECTION
OVER-HEAT
FAULT
INPUT STAGE P(3:0) OUTPUT STAGE
CMOS INPUT Current STAGE INPUT
OUTPUT STAGE
INPUT STAGE
GND2
Figure Functional Block Diagram
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
Description Digital Logic
digital logic structured four parts (see Figure UART, which analyses incoming signal from AS-i line ensures correct timing output signals; STATE MACHINE, which controls reaction PORTS, which contain registers digital I/O's; finally which contains non-volatile data circuit.
Digital Logic
P-PULSE N-PULSE P-Pulse -REG -REG -REG -REG -REG SEND-D SEND-SBY -REG -REG DO-REG DO-REG DO-REG DO-REG DATA-OUT-0 DATA-OUT-1 DATA-OUT-2 DATA-OUT-3
STATE MACHINE
DI-REG DI-REG DI-REG DI-REG PO-REG PO-REG PO-REG PO-REG PI-0 PI-1 PI-2 PI-3
DATA-STRB RESET DATA-IN-0 DATA-IN-1 DATA-IN-2 DATA-IN-3
UART
-REG -REG -REG -REG -STRB SEND -REG SEND -REG SEND -REG SEND -REG SEND -STRB
REC-RESET
PORTS
PARAM-OUT-0 PARAM-OUT-1 PARAM-OUT-2 PARAM-OUT-3 PARAM-STRB PARAM-IN-0 PARAM-IN-
E2PROM
ADD-CLK ADD-OUT ADD-IN POWER-FAIL POWER-ON RESET
PARAM-IN-2 PARAM-IN-3 IRD-IN FAULT-IN LED-OUT OVER-HEAT SHOUTDOWN
Figure Digital Logic
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
7.7.1.
Operational Modes
Master/Repeater Mode
Input (CMOS Input)
7.1.1.
sends signals retrieved from AS-i line AS-i telegram. input signal Manchestercoded active low. falling edge signal, which conducted ADD-IN, starts receiving process triggers Activity-Checker. Receive-Muxer selects input receive data signal connected with Send-Muxer SEND-D ADD-IN. signal latched every long there activity input pin. there high level input longer then ActivityChecker will recognize this activity Receive-Muxer returning idle state. information transported SEND-D with delay sender always non-standby mode. SEND-SBY signal constant there generation ADD-CLK.
P-PULSE N-PULSE ADD-IN
PULSE ENCODER
UART
-REG-0
RECEIVE MUXER ACTIVITY CHECKER
-REG-1 -REG-2 -REG-3 -REG-4
CODE CHECKER
RECEIVE REGISTER
-REG-5 -REG-6 -REG-7 -REG-8 -REG-9
SEND-REG-0 SEND-REG-1 SEND-REG-2 SEND-REG-3
SEND REGISTER
EC-R EG-10
SEND-D
STROBE UNIT
SEND-STRB
SEND MUXER
ADD-OUT REC-STRB
CONTROL UNIT
ADD-CLK SEND-SBY REC-RESET
Figure UART Block Diagram
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
7.1.1.2
AS-i Input
signal AS-i-line generates signals receiver output that pulse coded with minimal pulse width pulse AS-i line starts receiver triggers Activity-Checker through N-PULSE P-PULSE. Receive-Muxer selects AS-i-line pins input receive data. NPULSE P-PULSE signals latched every long there activity input pins. there pulse distance AS-i-line inputs longer then receiver will recognize this activity Receive-Muxer going idle state. Pulse-Encoder used convert active high pulse-coded signal active Manchester-II-coded (MAN) signal. will also check pulse stream timing pulse errors (e.g. alternation error). Master/Repeater mode Pulse-Encoder additionally resynchronizes error-free telegram into proper time base. This eliminate pulse jitter transformed AS-i telegram. synchronized signal sent ADD-OUT through Send-Muxer. ADD-OUT connected LED-OUT higher hierarchy level. all, information AS-i-line pins transported LED-OUT with delay Master/Repeater mode sender never standby mode, hence SEND-SBY signal always low. generation ADD-CLK provided simplify external processing Manchester-coded data. rising edge ADD-CLK signal middle second half Manchester data assuring that correct binary data clocked into shift register. ADD-CLK starts with rising edge after falling edge start ADD-OUT with period ratio 1:1. last rising edge ADD-CLK signal occurs after falling edge ADD-OUT. received signal Master Mode valid slave answer with start bit, four data bits, parity, pause following with length greater than UART generates active high REC-STRB signal with pulse width REC-STRB signal connected Parameter Output this mode. appears 10.0 10.5 after rising edge AS-i-line. 7.1.1.3 Ports
Functional assignments some ports depend operational mode Thus, these ports perform multiple functions that related particular mode Master Mode, following signals ports connected: Slave Function Parameter output port Parameter output port Parameter output port Fault indicator output/addressing channel output Addressing channel input Master REC-CLK POWERFAIL REC-STRB MAN-OUT Repeater REC-CLK MAN-OUT
MAN-IN
MAN-IN
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
7.1.2
Slave Mode
After IC-reset, Receive-Muxer watching input channels (AS-i-line pin) depending multiplex select signal MPX. frequency about kHz. low, Receive-Muxer selects AS-i-line vice versa high, selects data input. channel, from which valid master call received first, will locked until next IC-reset occurs. 7.1.2.1 Input Mode (Photo Diode Input)
photo diode current input Manchester-coded active (ref. 8.2.2 Addressing Channel Input IRD). level signal starts receiver triggers Activity-Checker. Control-Unit enabling Receive-Register received information clocked every into Receive-Register. there high level input longer then Control-Unit will recognize this activity Receive-Register will disabled. received information correct master call with Start-Bit, eleven Data-Bits, Parity-Bit, End-Bit, following pause either greater than (Synchronous Mode) 18.0 (Asynchronous Mode), UART generates internal active high REC-STRB signal with pulse width received telegram contained error, Control-Unit will generate REC-STRB signal asynchronous state waiting pause input. After pause detected, UART ready receive next telegram from input. REC-STRB signal generated, occurs 10.0 (Synchronous Mode) 21.0 21.5 (Asynchronous Mode), respectively, after rising edge End-Bit signal. slave asynchronous state, transforms synchronous state. Rec-Muxer locked input until next IC-reset. After generation REC-STRB signal Control-Unit waiting about SEND-STRB generated Main-State-Machine. Control-Unit receives active high SEND-STRB signal, starts transmission Send-Register data. Therefore, Send-Register data will converted active Manchester II-coded (MAN) signal which sent LED-OUT ADD-OUT. first falling edge signal occurs 11.75 (Synchronous Mode) 12.25 (Asynchronous Mode) after rising edge REC-STRB signal. Hence, delay from rising edge End-Bit master call (IRD input) first falling edge slave response (LED output) 21.25 21.75 (Synchronous Mode) 33.25 33.75 (Asynchronous Mode). After pause detected, UART ready receive next telegram from input. case Control-Unit will receive SEND-STRB signal within given time frame (for instance, this slave addressed), will check activity input. Otherwise, will just wait response time µs). both cases Control-Unit stays synchronous. Once slave pause detected, UART ready receive next telegram from input 7.1.2.2 AS-i Input Mode
signal AS-i-line generates pulse-coded signals (N-PULSE, P-PULSE) receiver output with minimum pulse width pulse AS-i line starts receiver triggers ActivityChecker through N-PULSE P-PULSE. Pulse-Encoder used convert active high pulse coded signal active Manchester-II-coded (MAN) signal. will also check pulse stream timing pulse errors (e.g. alternation error). ControlUnit enables Receive-Register that received information clocked every there pulse distance AS-i-line input longer than Control-Unit recognizes this activity disables Receive-Register. received information correct master call with Start-Bit, eleven (11) Data-Bits, Parity-Bit, End-Bit, following pause either greater than (Synchronous Mode) 18.0 (Asynchronous Mode), UART generates internal active high REC-STRB signal. received telegram contained error, ControlUnit will generate REC-STRB signal asynchronous state waiting pause AS-i line input. After pause detected UART ready receive next telegram from AS-i line input.
Data Sheet, Rev. 2.4, March 2002
Advanced AS-Interface
REC-STRB signal generated, occurs 10.0 10.5 (Synchronous Mode) 21.5 (Asynchronous Mode), respectively, after rising edge (receiver comparator switching point) End-Bit AS-i line input. slave asynchronous state, transforms synchronous state. RecMuxer locked AS-i line input until next IC-reset. After generation REC-STRB signal Control-Unit waiting about SEND-STRB generated Main-State-Machine. Control-Unit receives active high SEND-STRB signal (pulse width ns), starts transmission Send-Register data. Therefore, Send-Register data will converted active Manchester IIcoded (MAN) signal which sent AS-i line transmitter SEND-D. first falling edge signal occurs 11.75 (Synchronous Mode) 12.25 (Asynchronous Mode) after rising edge RECSTRB signal. Hence, delay from rising edge End-Bit master call (AS-i input) first falling edge slave response (AS-i output) 21.75 22.25 (Synchronous Mode) 33.75 34.25 (Asynchronous Mode). SEND-SBY will always after rising edge REC-STRB. This turn transmitter settle operation point. small offset current, which required operate transmitter, will ramped slowly avoid false voltage pulses AS-i line. data sent, Control-Unit sets sender standby mode (SEND-SBY high) checks slave pause AS-i line input. After pause detected, UART ready receive next telegram from AS-i line input. case Control-Unit will receive SEND-STRB signal within given time frame (for instance, this slave addressed), will check activity AS-i line. activity detected time frame about (another slave transmitting data), Control-Unit will wait next pause (slave pause). Otherwise, will just wait response time µs). both cases Control-Unit stays synhronus. Once slave pause detected, UART ready receive next telegram from AS-i line input. 7.1.2.3 Ports
Although still store AS-i Slave IO-Configuration Code does decode value configure direction Data-Port signals. rather distinctive Data-Out Data-In ports which always work parallel. bidirectional Data desired single Data-Port only (for backwards compatibility), Data-Out pins Data-In pins need shorted circuit board respectively nonvololatile Multiplex flag TRUE. that case output ports will switch high impedance state certain time following rising edge Data-Strobe allow input data Data-Port. input data will read inverted nonvolotile Invert_Data_In flag TRUE. This feature will simplify circuitry NPN-inputs. Note: Multiplex Invert_Data_In flags Configuration flags which stored Firmware region internal complete overview content please Application Notes. parameter port always bidirectional mode. input data result wired-AND between open drain output drivers application drivers. 7.1.2.4 Watchdog
Compliant AS-i Complete Specification, contains independent watchdog which generally enabled setting Watchdog_Active flag TRUE.
Data Sheet, Rev. 2.4, March 2002
10/3
Advanced AS-Interface
watchdog will activated slave address uneven zero after reception Write_Parameter Request particular Slave Address. will deactivated circuit Reset after reception Delete_Address Request. When activated, Watchdog will reset every Write_Parameter Data_Exchange Request received Slave. such request received particular Slave within 40ms, Hardware Reset will performed Data Parameter Outputs switched inactive. 7.1.2.5 Output
active (logic high) signal causes flashing status (frequency approx. 2Hz) AS-i Slave Status-Register (S1) well. active (logic low), cleared. that case status operation depends Data-Exchange-Disable flag. Data-Exchange-Disable TRUE each Reset becomes cleared (set FALSE) after first reception Write_Parameter Request. Data-Exchange-Disable flag set, data exchange performed through Data Ports which indicated steady-on LED. Note: active priority will cause flashing even Data-Exchange-Disable flag set. UART selected input channel, output again overriden Addressing Channel output. this mode does operate indicator output periphery failures status information signaled. 7.1.2.6 Overtemp shutdown continuously observes silicon temperature. temperature rises above 140°C will into shut-down stay there until next power-on reset occurs. 7.1.2.7 State Machine
so-called Main-State-Machine performs central control terms operation mode selection, EEPROM access control, processing master requests control ports. MainState-Machine interfaces with UART through Receive- Send-Register well certain strobe signals. avoid situation which slave gets locked allowed state (i.e imission strong electromacnetic radiation) thereby would jeopardize entire system, prohibited states state machine will lead RESET which comparable AS-i call "Reset Slave (RES)".
Summary Master Calls
following diagram Master Calls that will decoded listed. "Enter Program Mode" call intended factory programming only. order achieve EEPROM firmware protection comply complete AS-i specification, call "Enter Program Mode" deactivated before shipment slave.
Data Sheet, Rev. 2.4, March 2002
11/3
Advanced AS-Interface
Table Master Calls Related Save Responses
Instruction Data Exchange Write Parameter DEXG WPAR Master Request ~Sel ~Sel ~Sel ~Sel Slave Response
Address Assignment ADRA Write Extented Code-1 Delete Address Reset Slave Read Configuration Read Code Read Code-1 Read Code-2 Read Status Broadcast (Reset) WID1 DELA RDIO RDID RID1 RID2 RDST
slave response slave response
Enter Program Mode PRGM
Note:
extended address mode "Select Bit" defines whether A-Slave B-Slave being addressed. Dependent type master call carries select information (Sel) inverted select information (~Sel).
Program Mode
Provided that non-volatile configuration flag, Program-Mode-Disable, been set, device transferred program mode utilizing "Enter Program Mode" call. Please refer Application Notes details programming process. AS-i Complete Specification compliance note: order ensure full compliance with AS-i Complete Specification, Program-Mode-Disable flag must final manufacturing configuration process before AS-i slave device being delivered field application users.
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
Electrical Specification
Absolute Maximum Ratings
stress above listed Absolute Maximum Ratings cause permanent damage device. given conditions represent stress rating only. Functional operation device those conditions other stress above Operational Limits implied. Exposure maximum rating conditions extended times effect device performance, functionality, reliability.
Table Absolute Maximum Ratings
SYMBOL ,VGND VASIP VASIN VASIP-ASIN VASIPP VUIN VUINPV Vinputs1 Vinputs2 VHBM1 VHBM2 VEDM qSTG Ptot
PARAMETER Voltage reference Positive AS-i supply voltage Negative AS-i supply voltage Voltage difference from ASIP ASIN (VASIP VASIN) AS-i supply pulse voltage, voltage difference between pins ASIP ASIN (from ASIP ASIN) Aux. power supply input voltage Aux. power supply input voltage pulse Voltage pins DI0, DO0, DSR, PST, LED, FID, UOUT Voltage pins OSC1, OSC2, IRD, CAP, U5R, U5RD Input current into except supply pins Humidity non-condensing Electrostatic discharge human body model (HBM1) Electrostatic discharge human body model (HBM2) Electrostatic discharge equipment discharge model (EDM) Storage temperature Total power dissipation
MIN. -0.3 -0.3 -0.3
MAX.
UNITS
NOTE
-0.3
-0.3 -0.3
VUIN
Vinputs1
4000 2000 0.85
ASIN-pin shall shorted 0V-pin PCB. Reverse polarity protection performed externally. Pulse with 50µs, repetition rate Level according JEDEC-020A guaranteed HBM1: 100pF charged VHBM1 with resistor 1.5kW series, valid ASIP-ASIN only. HBM2: 100pF charged VHBM2 with resistor 1.5kW series, valid pins except ASIP-ASIN. EDM: 200pF charged VEDM with resistor series, valid ASIP-ASIN only. maximum operating temperature, allowed total power dissipation depends additional thermal resistance from case ambient operation ambient temperature (see Figure
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Data Sheet, Rev. 2.4, March 2002
13/3
Advanced AS-Interface
Ptot (Ta); layer layer
Figure Maximum Power Dissipation, PTOT f(Ambient Temperature)
Ptot (2L) Ptot (1L)
Table Operating Conditions
SYMBOL VUIN VASIN V0V, VGND IASI ICL1 ICL2 qamb
PARAMETER Positive supply voltage Negative AS-i supply voltage Negative supply voltage Supply current VASI Max. output sink current pins DO0, Max. output sink current pins Ambient temperature range, operating range
MIN.
MAX. 33.1
UNITS
NOTE
voltage ASIN shall shorted with ensure proper functionality transmitter circuit. 8.000 MHz, load without reaction circuit, ASIP short-cut ASIN respectively.
Characteristics
parameters valid recommended range VASIP VASIN, VUIN V0V, qamb. devices tested within recommended range VASIP VASIN, V0V, qamb +25°C 85°C 25°C sample base only) unless otherwise stated. Unused input pins shall connected suitable potential within application circuit because there internal pull-up/down resistors. recommended connect these pins either resistor UOUT respectively. With external signal data strobe (pull-down open drain driver) more than 44µs, will execute reset procedure. During power procedure data parameter ports will stay highimpedance state. been initialization procedure external reset DSR, should toggled externally avoid that control logic transfers test mode.
Data Sheet, Rev. 2.4, March 2002
14/3
Advanced AS-Interface
8.2.
Digital Input Output Pins
Table Input/Output Voltage Current
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
Pins DI3, DSR, FID,
VICH VHYST IICH IIHV VOL1 VOL2
Voltage range input "low" level, Voltage range input "low" level, only Voltage range input "high" level Hysteresis switching level Current range input "low" level Current range input "high" level Current range high voltage input
0.25
VUOUT
IOL1 10mA IOL2 4.5V
Pins DO3, DSR,
Voltage range output "low" level Voltage range output "low" level Output leakage current Capacitance
Voltage range output "low" level Output leakage current
IOL1 10mA
Switching level approximately i.e. VHYST. higher capacitive load external pull-up resistor connected UOUT necessary reach 3.5V less than after beginning pulse, otherwise reset will executed. output driver sends "low" (LED on). output driver sends "high" (equivalent tri-state, off).
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
Table Timing Parameter Port
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
tsetup tPST tPI-latch tCYCLE
Valid output data; PST-H/L pulse width PST-H/L parameter input latch Next cycle
13.5
Figure
parameter input data must stable within period that defined minimum maximum tPI-latch.
tCYCLE
tsetup
keep stable
aram eter port output data
I-latch
parameter input value parameter output value wired with external signal source value
Figure Timing Diagram Parameter Port
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
Table Timing Data Port Outputs
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
tsetup thold tDSTR tDI-latch tCYCLE
Valid output data; DSR-H/L Valid output data; DSR-L/H pulse width DSR-H/L data input latch Next cycle
13.5
Figure
data input must stable within period that defined minimum maximum tDI-latch.
tCYCLE
tsetup
tDSR
data remains, multiplex flag hi-z, multiplex flag
DO0-DO3
Data port output data keep stable
thold
DI0-DI3
Data port input data
tDI-latch
Figure Timing Diagram Data Port
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
Table Timing Reset Signal
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
tALM1 tALM2 tRESET
Ext. reset) Ext. Hi-Z Reset time after external transition
tRESET
DO0-DO3 PO0-PO3
hi-z
Data port output data
hi-z
Parameter port output data
tALM1 tALM2
Figure Timing Diagram External Reset
Data Sheet, Rev. 2.4, March 2002
18/3
Advanced AS-Interface
8.2.2
Addressing Channel Input
addressing channel input dedicated photo-diode input. photo-diode connected pins directly. input current input. valid signal current input have certain amplitude (range) should exceed certain offset value (see Figure Table logic "low" input will detected, present signal value drops below IIRDO, "high" will detected, present value greater than IIRDO IIRDA.
input current IIRDA
IIRDA
IIRDO time
Figure Photo Current Waveform
Table Current Amplitude Diode Input Slave Mode
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
IIRDO IIRDA
Input current offset Input current amplitude
µAPP µAPP
Table Digital Input Master/Repeater Mode
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
VICH
Voltage range input "low" level Voltage range input "high" level Rise/fall time
VU5R
order avoid jittery AS-i line, rise/fall time input signal should possible.
8.2.3
Fault Indication Input,
fault indication input digital input dedicated periphery fault messaging signal (for properties Table status equivalent input signal. transition will occur with certain delay, because synchronizer circuit between.
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
Voltage Outputs
Table Properties Voltage Output Pins UOUT
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
VUOUT VUOUTp tUOUTp VDROP VU5R IUOUT IUOUTS CLUOUT CL5V
UOUT output supply voltage UOUT output voltage pulse deviation UOUT output voltage pulse deviation width Voltage drop from UOUT supply voltage UOUT output supply current output supply current Total voltage output current IUOUT Short circuit output current Load capacitance UOUT Load capacitance
VUINVDROPmax
VUINVDROPmin
IUOUT 30mA
VUIN IU5R IUOUT
COUT output current switches from vice versa. 11.0V VOUT 27.6V.
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
8.3.
AS-i Load
following parameters determined with short-cut between pins ASIP pins ASIN respectively.
Table AS-i Interface Properties (Pins ASIP/ASIN UIN)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
VUIN ILIN VSIG ISIG CZener RIN1 LIN1 CIN1 RIN2 LIN2 CIN2
Input AS-i voltage Input current limit Input signal voltage difference between ASIP ASIN Modulated output peak current from ASIP ASIN Parasitic capacitance external overvoltage protection diode (zener diode) Equivalent resistor device Equivalent inductor device Equivalent capacitor device Equivalent resistor device Equivalent inductor device Equivalent capacitor device
VUOUTmin+ VDROPmax
VUOUTmax VDROPmin
(L-12mH)*2.5pF/mH
Parameter equivalent circuit slave (which calculated from impedance device paralleled external over-voltage protection diode (zener diode)) satisfy Complete AS-i-Specification v.2.1 concerning requirements extended address range. Subtracting maximum parasitic capacitance external over voltage protection diode (20pF) either triple RIN1, LIN1 CIN1 triple RIN2, LIN2 CIN2 committed device fulfil Complete AS-i-Specification v2.1.
8.3.2
Input Impedance Control
Table
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
RCAP CCAP
External filter resistor External filter capacitor
Recommended values optimal impedance are:
RCAP CCAP RCAP CCAP chapter Package Marking, details distinguish different versions.
Revision Revision
de-coupling capacitor serial resistor define internal low-pass filter time constant; lower values decrease impedance improve turn-on time. Higher values improve impedance increase turn-on time. turn-on time also depends load capacitor UOUT. After connecting slave power capacitor charged with maximum current IUOUT. impedance will increase when voltage allows analog circuitry fully operate.
Data Sheet, Rev. 2.4, March 2002
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Advanced AS-Interface
8.3.3
Oscillator
Table Oscillator Pins (OSC1 OSC2)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
COSC VICH
External parasitic capacitor oscillator pins OSC1, OSC2 Input "low" voltage Input "high" voltage
VU5R
external clock applied OSC1 only.
Development Information Data
Table Information Data Conditions: Asynchronous mode, reset default comparator level ,,line pause".
Symbol VLSIGon
PARAMETER
MIN.
MAX.
UNITS
NOTE
Receiver comparator threshold level (see Figure Reset time after Master Call ,,Reset AS-i-Slave" external transition Reset time after power Reset time after power with high capacitive load VASIP voltage detect power fail (master mode only) Power supply break down time (master mode only) VU5R voltage trigger internal reset procedure, falling voltage VU5R voltage trigger INIT procedure, rising voltage Power-on reset pulse width Chip temperature thermal shut down (overheating)
Related amplitude pulse
treset1 treset2 treset3 VASIP-PF tLoff VPOR1F VPOR1R tLow TShut
1000 21.5 23.5
Guaranteed design only. `Power_on' starts latest VUIN 18V, external capacitor UOUT 10µF. CUOUT 470µF, treset3 guaranteed design only. CUOUT 10µF, power fail generated VASIP VASIP-PF tLoff master mode only).
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Advanced AS-Interface
level"
VLSIGon (0.45 0.50) VSIG
determines amplitude first negative pulse AS-i telegram. This amplitude asserted VSIG
VLSIGon VSIG
First negative pulse AS-i telegram
Figure Receiver Comparator
MASTER MODE only
VASIP VASIP-PF VUIN
Modes
tLoff
VASIN
VU5R VPOR1F VPOR1R
tLow
(active low) reset, break down time exceeds tLoff, power-fail signal will generated Power-on Reset will active, VU5R drops below VPOR1F Reset will initalized
Figure Power-Fail Generation Master Mode) Reset Behavior (All Modes)
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Application Circuits
following figures show typical application cases Figure shows application circuit which replacing ASI3+ circuit. Finally, Figure shows circuit used perform analog/digital interface between AS-i-line master electronics. Furthermore this figure shows that used repeater applications well.
10.1 Precautions
Precaution must taken avoid radio frequency interference. recommended keep input lines short possible connect unused inputs UOUT through pull-up resistor. Furthermore, supply pins should de-coupled with ceramic capacitors addition normal de-coupling capacitors. Also, recommended connect pull-up resistor from (pin UOUT order avoid unintentional reset under difficult conditions.
10.2 Typical Slave Application
A2SI
GREEN
DI_0 DI_1 DI_2 DI_3 DO_0 DO_1 DO_2 DO_3 DS&Reset Fault Input
OSC2
39V/1W
ASIP
U5RD ASIN
+24V
2.2µF
Figure Typical Application, Slave Mode
Note: Figure Figure show digital (data parameter) ports without application specific connections. correct function, important consider that output drivers open drain stages hence each port must connected with appropriate pull-up resistor.
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10.3 Typical ASI3+ Compatible Application
OSC1 39V/1W ASIN U5RD DIO-0 DIO-1 DIO-2 DIO-3 DS&Reset
A2SI
OSC2
ASIP
+24V
RCAP CCAP
2.2µF
Figure Typical ASI3+ Compatible Application
Note: Depending I/O-configuration, DI-ports connected Multiplex-Flag set.
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10.4 Typical Master/Repeater Application
ISOLATION REC-CLK (optional)
A2SI
REC-STRB (optional)
OSC2 ASIP
RECEIVE DATA
ASI+
/POWER-FAIL
ASI-
U5RD ASIN 2.2µF
SEND
RCAP CCAP
Figure Master/Repeater Application
further information also Application Note.
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Package Outline
Figure SSOP Package
Figure Package Dimensions
Table Package Dimensions (mm)
Symbol Nominal Maximum Minimum
1.86 1.99 1.73
0.13 0.21 0.05
1.73 1.78 1.68
0.30 0.38 0.25
0.15 0.20 0.13
10.20 10.33 10.07
5.30 5.38 5.20
0.65
7.80 7.90 7.65
0.75 0.95 0.55
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Package Marking
VIEW BOTTOM
A2SI
R-XXXXYZZ
LLLLLL
Figure Package Marking
Marking:
RXXXX LLLLLL
Product name Manufacturer Revision code Date code (year week) Assembly location Traceability Number
Bottom Marking:
yellow indicating pre-programmed Master function printed marking Note: Revision have revision code marking. without Revision Code equivalent Revision Revision shows "B-"
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Advanced AS-Interface
Evaluation boards Evaluation board equipped with ordered from Bihl+Wiedeman GmbH (www.bihl-wiedemann.de)
Figure Evaluation board dimensions H):(34
Ordering Information
Ordering Code A2SI-ST A2SI-SR A2SI-MT A2SI-MR Description Operating Temperature Range Package Type Device Marking Shipping Form
Standard version Standard version Pre-programmed master function Pre-programmed master function
-25°C 85°C -25°C 85°C -25°C 85°C -25°C 85°C
28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP
yellow yellow
Tubes parts/tube) Tape-and-Reel (1500 parts/reel) Tubes parts/tube) Tape-and-Reel (1500 parts/reel)
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Advanced AS-Interface
Application Support
15.1 AS-International Association
Documentation promotional materials well datailed technical specifications regarding AS-Interface Standard available from:
AS-International Association Contact Rolf Becker Taubengarten D-63571 Gelnhausen 1103 (63551) Tel: 6051 Fax: 6051 4732 Email: as-interface@t-online.de http://www.as-interface.net
Refer Association's website hereabove contact info nine local AS-Interface associations which provide local support within Europe, Japan.
15.2
Application Note found under www.zmd.de www.zmda.com device related application support requests addressed asi@zmd.de
15.3 Application Support Partners
Bihl+Wiedemann Flosswoerthstrasse D-68199 Mannheim, Germany Tel.: 3996 Fax: 3922 Email: mail@bihl-wiedemann.de http://www.bihl-wiedemann.de fieldbus specialists Colchester Road, Kilsyth 3137 Victoria, Australia Tel.: 9761 4653 Fax: 9761 5525 Email: fs_sales@fieldbus.com.au http://www.fieldbus.com.au
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Sales Contacts
Sales Office Dresden Sales Office Long Island
Zentrum Mikroelektronik Dresden D-01109 Dresden Germany Phone +49-351-8822-370 +49-351-8822-337 sales@zmd.de
America Inc. Country Road Melville, 11747 Phone +1-631-549-2666 +1-631-549-2882 info@zmda.com
Life Support Policy products designed, intended, authorised components systems intended surgical implant into body, other applications intended support sustain life, other application which failure product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorised such purpose. Limited Warranty information this document been carefully checked believed reliable. However Zentrum Mikroelektronik Dresden (ZMD) makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. does guarantee that information contained herein will infringe patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent ZMDs warranty product beyond that forth standard terms conditions sale. reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice. 2002 Zentrum Mikroelektronik Dresden rights reserved.
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Features AS-i Complete Specification V2.11 compliant Integrated E

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