2.5V flowthrough burst synchronous SRAM Features Organization: 1,

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2.5V flowthrough burst synchronous SRAM Features Organization: 1,

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AS7C251MFT18A
2.5V flowthrough burst synchronous SRAM Features
Organization: 1,048,576 words bits Fast clock data access: 8.5/10 Fast access time: 3.5/3.8 Fully synchronous flow-through operation Asynchronous output enable control Available 100-pin TQFP 165-ball packages Individual byte write global write Multiple chip enables easy expansion 2.5V core power supply Linear interleaved burst control Snooze mode reduced power-standby Boundary scan using IEEE 1149.1 JTAG function NTDTM1 flow-through mode architecture available (AS7C251MNTD18A, AS7C25512NTD32A/ AS7C25512NTD36A)
NTDis trademark Alliance Semiconductor Corporation. trademarks mentioned this document property their respective owners.
Logic block diagram
ADSC ADSP A[19:0]
Burst logic
Address register
Memory array
Byte Write registers Byte Write registers
Enable register
Output buffers
Input registers
Power down
Enable
delay register
DQ[a,b]
Selection guide
Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) Units
4/12/04,
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Copyright Alliance Semiconductor. rights reserved.
AS7C251MFT18A
ball designations configuration 100-pin TQFP
VDDQ VSSQ DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb VSSQ VDDQ
ADSC ADSP
TQFP 20mm
VDDQ VSSQ DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 VSSQ VDDQ
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AS7C251MFT18A
Ball assignments 165-ball
DQPb
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ADSC
ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQPa
least significant bits (LSB) address field internal burst counter burst desired.
4/12/04,
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AS7C251MFT18A
Functional description
AS7C251MFT18A high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized 1,048,576 words bits. Fast cycle times 10/12 with clock access times (tCD) 8.5/10 Three chip enable (CE) inputs permit easy memory expansion. Burst operation initiated ways: controller address strobe (ADSC), processor address strobe (ADSP). burst advance (ADV) allows subsequent internally generated burst addresses. Read cycles initiated with ADSP (regardless ADSC) using external address clocked into on-chip address register when ADSP sampled LOW, chip enables sampled active, output buffer enabled with read operation, data accessed current address registered address registers positive edge carried data-out buffers. ignored clock edge that samples ADSP asserted, sampled subsequent clock edges. Address incremented internally next access burst when sampled both address strobes HIGH. Burst mode selectable with input. With unconnected driven HIGH, burst operations interleaved count sequence. With driven LOW, device uses linear count sequence. Write cycles performed disabling output buffers with asserting write command. global write enable writes bits regardless state individual BW[a,b] inputs. Alternately, when HIGH, more bytes written asserting appropriate individual byte signals. ignored clock edge that samples ADSP LOW, sampled subsequent clock edges. Output buffers disabled when sampled LOW, regardless Data clocked into data input register when sampled LOW. Address incremented internally next burst address sampled LOW. Read write cycles also initiated with ADSC instead ADSP. differences between cycles initiated with ADSC ADSP follow. ADSP must sampled HIGH when ADSC sampled initiate cycle with ADSC. signals sampled clock edge that samples ADSC (and ADSP HIGH).
Master chip enable blocks ADSP, ADSC.
AS7C251MFT18A family operates from core 2.5V power supply. These devices available 100-pin TQFP 165-ball BGA.
TQFP capacitance
Parameter Input capacitance capacitance Symbol CI/O Test conditions VOUT Unit
TQFP thermal resistance
Description Thermal resistance (junction ambient)1 Thermal resistance (junction case)1
This parameter sampled.
Symbol layer layer
Typical
Units °C/W °C/W °C/W
Conditions Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51
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AS7C251MFT18A
Signal descriptions
Signal A,A0,A1 DQ[a,b] CE1, ADSP ADSC BW[a,b] Properties Description CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC SYNC SYNC SYNC SYNC ASYNC Clock. inputs except synchronous this clock. Address. Sampled when chip enables active when ADSC ADSP asserted. Data. Driven output when chip enabled when active. Master chip enable. Sampled clock edges when ADSP ADSC active. When inactive, ADSP blocked. Refer "Synchronous truth table" more information. Synchronous chip enables. Active HIGH active LOW, respectively. Sampled clock edges when ADSC active when ADSP active. Address strobe processor. Asserted load address enter standby mode. Address strobe controller. Asserted load address enter standby mode. Advance. Asserted continue burst read/write. Global write enable. Asserted write bits. When HIGH, BW[a,b] control write enable. Byte write enable. Asserted with HIGH enable effect BW[a,b] inputs. Write enables. Used control write individual bytes when HIGH LOW. BW[a,b] active with HIGH LOW, cycle write cycle. BW[a,b] inactive, cycle read cycle. Asynchronous output enable. pins driven when active chip read mode.
Selects Burst mode. When tied left floating, device follows interleaved Burst order. When driven LOW, device follows linear Burst order. This signal internally pulled High.
Serial data-out JTAG circuit. Delivers data negative edge (BGA only). Serial data-in JTAG circuit. Sampled rising edge (BGA only). This controls Test Access Port state machine. Sampled rising edge (BGA only). Serial data-out JTAG circuit. Delivers data negative edge (BGA only). Sleep. Places device power mode; data retained. Connect unused. connects
Write enable truth table (per byte)
Function Write bytes Write byte Write byte Read
Key: don't care; low; high; BWE, internal write signal
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AS7C251MFT18A
Burst sequence table
Interleaved burst address Address
Linear burst address Address
Address
Address
Address Address
Address Address
Synchronous truth table
CE01 ADSP ADSC WRITE[2] Address accessed Operation
External External External External Next Next Current Current Next Next Current Current External Next Next Current Current
Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
don't care, low, high WRITE, means more byte write enable signals (BWa BWb) LOW. WRITE HIGH BWx, BWE, HIGH. "Write enable truth table (per byte)," page more information. write operation following READ, must HIGH before input data time held HIGH throughout input hold time
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AS7C251MFT18A
Absolute maximum ratings
Parameter Power supply voltage relative Input voltage relative (input pins) Input voltage relative (I/O pins) Power dissipation output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ IOUT Tstg Tbias -0.3 -0.3 -0.3 +3.6 VDDQ +150 +135 Unit
Note: Stresses greater than those listed this table cause permanent damage device. This stress rating only, functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect reliability.
Recommended operating conditions
Parameter Supply voltage inputs Supply voltage Ground supply Symbol VDDQ 2.375 2.375 Nominal 2.625 2.625 Unit
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electrical characteristics
Parameter Input leakage current Output leakage current Input high (logic voltage Input (logic voltage Output high voltage Output voltage
|ILI| |ILO|
Conditions Max, VIH, Max, VOUT VDDQ Address control pins pins Address control pins pins VDDQ 2.375V VDDQ 2.625V
-0.3
VDD+0.3 VDDQ+0.3
Unit
-0.3*
-1.5 pulse width less than tCYC
operating conditions maximum limits
Parameter Operating power supply current1 Standby power supply current ISB1 ISB2 Conditions VIL, VIH, VIL, fMax, IOUT Deselected, fMax, Deselected, 0.2V, 0.2V 0.2V Deselected, fMax, VDD, VDDQ) 0.2V, Unit
given with output loading. increases with faster cycle times greater output loading
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Timing characteristics over operating range
Parameter Cycle time Clock access time Output enable data valid Clock high output Data output invalid from clock high Output enable output Output enable high output high Clock high output high Output enable high invalid output Clock high pulse width Clock pulse width Address setup clock high Data setup clock high Write setup clock high Chip select setup clock high Address hold from clock high Data hold from clock high Write hold from clock high Chip select hold from clock high setup clock high ADSP setup clock high ADSC setup clock high hold from clock high ADSP hold from clock high ADSC hold from clock high
"Notes" page
Unit 2,3,4 2,3,4 2,3,4 2,3,4 Notes1
tCYC tLZC tLZOE tHZOE tHZC tOHOE tCSS tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH
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AS7C251MFT18A
IEEE 1149.1 serial boundary scan (JTAG)
SRAM incorporates serial boundary scan test access port (TAP). port operates accordance with IEEE Standard 1149.1-1990 does have functions required full 1149.1 compliance. inclusion these functions would place added delay critical speed path SRAM. controller functionality does conflict with operation other devices using 1149.1 fully compliant TAPs. uses JEDEC-standard 2.5V logic levels. SRAM contains controller, instruction register, boundary scan register, bypass register, register.
Disabling JTAG feature
JTAG function being implemented, should tied VSS, left unconnected, device will come reset state which will interfere with operation device. should left unconnected.
controller state diagram
TEST-LOGIC RESET RUN-TEST/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELECT IR-SCAN CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR EXIT2-IR UPDATE-IR
controller block diagram
Bypass Register
Selection Circuitry
Instruction Register Identification Register
Selection Circuitry
Boundary Scan Register1
Controller
configuration, configuration.
Note: next each state represents value rising edge TCK.
Test access port (TAP) Test clock (TCK)
test clock used with only controller. inputs captured rising edge TCK. outputs driven from falling edge TCK.
Test mode select (TMS)
controller receives commands from input. sampled rising edge TCK. leave this pin/ball unconnected used. pin/ball pulled internally, resulting logic high level.
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Test data-in (TDI)
pin/ball serially inputs information into registers connected input registers. register between chosen instruction that loaded into instruction register. information loading instruction register, Controller State Diagram. internally pulled unconnected unused application. connected most significant (MSB) register. (See Controller Block Diagram.)
Test data-out (TDO)
output pin/ball serially clocks data-out from registers. output active depending upon current state state machine. output changes falling edge TCK. connected least significant (LSB) register. (See Controller State Diagram.)
Performing RESET
perform RESET forcing high (VDD) five rising edges TCK. This RESET does affect operation SRAM performed while SRAM operating.
registers
Registers connected between pins/balls. They allow data scanned into SRAM test circuitry. Only register selected time through instruction register. Data serially loaded into pin/ball rising edge TCK. Data output pin/ball falling edge TCK.
Instruction register
serially load three-bit instructions into instruction register. register loaded when placed between pins/balls shown Controller Block Diagram. instruction register loaded with IDCODE instruction power also controller placed reset state, described previous section. When controller Capture-IR state, least significant bits loaded with binary "01" pattern allow fault isolation board-level series test data path.
Bypass register
save time when serially shifting data through registers, sometimes advantageous skip certain chips. bypass register singlebit register that placed between pins/balls. This allows data shifted through SRAM with minimal delay. bypass register (Vss) when BYPASS instruction executed.
Boundary scan register
boundary scan register connected input bidirectional pins/balls SRAM. configuration 72-bit-long register configuration 53-bit-long register. boundary scan register loaded with contents ring when controller Capture-DR state then placed between pins/balls when controller moved Shift-DR state. EXTEST, SAMPLE/RELOAD, SAMPLE instructions used capture contents ring. boundary scan order table shows order which bits connected. Each corresponds bumps SRAM package. most significant (MSB) register connected TDI, least significant (LSB) connected TDO.
Identification (ID) register
register vendor code other information described Identification Register Definitions table. register loaded with vendor-specific, 32-bit code during Capture-DR state when IDCODE command loaded instruction register. IDCODE hardwired into SRAM shifted when controller Shift-DR state.
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AS7C251MFT18A
instruction
Eight different instructions possible with 3-bit instruction register. combinations listed Instruction Codes table. Three these instructions reserved should used. Note that controller used this SRAM fully compliant 1149.1 convention because some mandatory 1149.1 instructions fully implemented. controller cannot used load address, data, control signals into SRAM cannot preload buffers. SRAM does implement 1149.1 commands EXTEST INTEST PRELOAD portion SAMPLE/ PRELOAD. Instead, performs capture ring when these instructions executed. Instructions loaded into controller during Shift-IR state when instruction register placed between TDO. During this state, instructions shifted through instruction register through pins/balls. execute instruction once shifted controller needs moved into Update-IR state.
EXTEST
EXTEST instruction, which executes whenever instruction register loaded with implemented this SRAM controller. controller, however, does recognize all-0 instruction. When EXTEST instruction loaded into instruction register, SRAM responds SAMPLE/PRELOAD instruction been loaded. Unlike SAMPLE/PRELOAD instruction, EXTEST places SRAM outputs high-Z state. EXTEST mandatory 1149.1 instruction. this device, therefore, compliant with 1149.1.
IDCODE
IDCODE instruction loaded into instruction register upon power-up whenever controller given test logic reset state. IDCODE instruction causes vendor-specific, 32-bit code loaded into instruction register. also places instruction register between pins/balls allows IDCODE shifted device when controller enters Shift-DR state.
SAMPLE
SAMPLE instruction causes boundary scan register connected between pins/balls when controller Shift-DR state. also places SRAM outputs into high-Z state.
SAMPLE/PRELOAD
When SAMPLE/PRELOAD instruction loaded into instruction register controller Capture-DR state, snapshot data inputs bidirectional pins/balls captured boundary scan register. Note that SAMPLE/PRELOAD 1149.1 mandatory instruction, PRELOAD portion this instruction implemented this device. controller, therefore, fully 1149.1 compliant. aware that controller clock operate only frequency Mhz, while SRAM clock operates more than order magnitude faster. Because there large difference clock frequencies, possible that during Capture-DR state, input output undergo transition. then capture signal while transition (metastable state). This will harm device, there guarantee value that will captured. Repeatable results possible. guarantee that boundary scan register captures correct value signal, SRAM signal must stabilized long enough meet controller's capture setup plus hold time (tCS plus tCH). SRAM clock input might captured correctly there design stop slow) clock during SAMPLE/PRELOAD instruction. this issue, possible capture other signals ignore value captured boundary scan register. Once data captured, possible shift data putting into Shift-DR state. This places boundary scan register between pins. Note that since PRELOAD part command implemented, putting Update-DR state while performing SAMPLE/PRELOAD instruction will have same effect Pause-DR command.
BYPASS
advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board. When BYPASS instruction loaded instruction register placed Shift-DR state, bypass register placed between TDO. 4/12/04,
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AS7C251MFT18A
Reserved
reserved instruction.These instructions implemented reserved future use.
timing diagram
Test Clock (TCK) tTHTL Test Mode Select (TMS) tMVTH tTHMX Test Data-In (TDI) tDVTH tTHDX Test Data-Out (TDO)
Don't care Undefined
tTLTH
tTHTH
tTLOV tTLOX
electrical characteristics
notes +10oC +110oC +2.4V +2.6V.
Description Clock Clock cycle time Clock frequency Clock high time Clock time Output Times unknown valid valid high high invalid Setup Times setup Capture setup Hold Times hold Capture hold
Symbol
Units
THTH
THTL TLTH
TLOX TLOV
tDVTH
THDX
tMVTH
THMX
refer setup hold time requirements latching data from boundary scan register.
Test conditions specified using load figure output load equivalent.
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AS7C251MFT18A
test conditions
Input pulse levels. 2.5V Input rise fall times. Input timing reference levels. 1.25V Output reference levels 1.25V Test load termination supply voltage. 1.25V
output load equivalent
1.25V ZO=50 20pF
electrical characteristics operating conditions
(+10oC +110oC +2.4V +2.6V unless otherwise noted)
Description Input high (logic voltage Input (logic voltage Input leakage current Output leakage current Output voltage Output voltage Output high voltage Output high voltage
voltage referenced VSS(GND).
Conditions
Symbol
-0.3 -5.0 -5.0
Units
Notes
Outputs disabled, VDDQ(DQx) IOLC 100µA IOLT IOHS -100µA IOHT -2mA
VOL1 VOL2 VOH1 VOH2
Overshoot: VIH(AC) 1.5V tKHKH/2 Undershoot: VIL(AC) -0.5 tKHKH/2 Power-up: +2.6V 2.4V VDDQ 1.4V 200ms
During normal operation, VDDQ must exceed VDD. Control input signals (such R/W, etc.) have pulsed widths less than tKHKL(Min) operate frequencies exceeding fKF(Max).
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Identification register definitions
Instruction field Revision number (31:28) Device depth (27:23) Device width (22:18) Device (17:12) JEDEC code (11:1) register presence indicator xxxx xxxxx xxxxx xxxxxx Description Reserved version number. Defines depth words. Defines width bits. Reserved future use. Indicates presence register.
00001010010 Allows unique identification SRAM vendor.
Scan register sizes
Register name Instruction Bypass Boundary scan x18:53 size x36:72
Instruction codes
Instruction EXTEST IDCODE SAMPLE Reserved SAMPLE/ PRELOAD Reserved Reserved BYPASS Code Description Captures ring contents. Places boundary scan register between TDO. Forces SRAM outputs high-Z state. This instruction 1149.1-compliant. Loads register with vendor code places register between TDO. This operation does affect SRAM operations. Captures ring contents. Places boundary scan register between TDO. Forces SRAM output drivers high-Z state. use. This instruction reserved future use. Captures ring contents. Places boundary scan register between TDO. Does affect SRAM operation. This instruction does implement 1149.1 preload function therefore 1149.1-compliant. use. This instruction reserved future use. use. This instruction reserved future use. Places bypass register between TDO. This operation does affect SRAM operations.
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165-ball boundary scan order (x18)
Signal Name
DQPb
Ball
Signal Name ADSC ADSP DQPa
Ball
Note: don't care
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switching waveforms
Rising input Falling input Undefined/don't care
Timing waveform read cycle
tADSPS tADSPH ADSP tADSCS tADSCH ADSC Address GWE, tCSS tCSH CE0, LOAD ADDRESS tCYC
tADVS tADVH inserts wait states
tLZOE DOUT
Q(A1)
tHZOE
Q(A3)
Read Q(A1) Suspend Read Q(A1) Read Q(A2)
tHZC
DSEL
Burst Burst Suspend Burst Read Burst Burst Burst Read Read Read Read Q(A3) Read Read Read
Note: when high/no connect; when low. BW[a:b] don't care.
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Timing waveform write cycle
tADSPS tADSPH ADSP tADSCS tADSCH ADSC Address ADSC loads address tCSS tCSH CE0, tCYC
BW[a:d]
suspends burst tADVS tADVH
Data
Read Q(A1)
D(A1) D(A2) D(A3)
Suspend Write D(A1)
Read Q(A2)
Suspend Write
Suspend Burst Write Burst Burst Write Write Write
Write
Burst Write
Burst Write
Note: when high/no connect; when low.
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Timing waveform read/write cycle
tADSPS tADSPH ADSP Address tCYC
CE0,
tADVS tADVH
D(A2)
DOUT tLZC
DSEL Read Q(A1) Suspend Read Q(A1)
Q(A1)
tHZOE tLZOE
Read Q(A2) Suspend Write Read Q(A3)
Burst Read
Burst Read
Burst Read
Suspend Read
Note: when high/no connect; when low.
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test conditions
Output load: tLZC, tLZOE, tHZOE, tHZC, Figure others, Figure Input pulse level: 2.5V. Figure Input rise fall time (measured 0.25V 2.25V): Figure Input output timing reference levels: 1.25V. +2.5V DOUT Figure Output load VDDQ/2 DOUT 353/1538 Thevenin equivalent: +2.5V 319/1667 *including scope capacitance
Figure Input waveform
Figure Output load(B)
Notes
test conditions, Test Conditions", Figures This parameter measured with output load condition Figure This parameter sampled 100% tested. tHZOE less than tLZOE, tHZC less than tLZC given temperature voltage. measured high above VIH, measured below VIL. This synchronous device. addresses must meet specified setup hold times rising edges CLK. other synchronous inputs must meet setup hold times rising edges when chip enabled. Write refers GWE, BWE, BW[a,b]. Chip select refers CE0, CE1, CE2.
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Package dimensions 100-pin TQFP (quad flat pack)
TQFP
0.05 1.35 0.22 0.09 13.90 19.90 15.85 21.80 0.45
0.15 1.45 0.38 0.20 14.10 20.10 16.15 22.20 0.75
0.65 nominal
1.00 nominal
Dimensions millimeters
165-ball (ball grid array)
View
corner index area 13.00±0.10
Bottom View
1.00
15.00±0.10 15.00±0.10 14.00 1.00
measurements 0.40 0.45 0.30 12.90 14.90 1.00 15.00 14.00 13.00 10.00 0.26 0.35 0.40 1.20 0.50
0.50
15.10 13.10
10.00 13.00±0.10 0.20 0.12 0.35±0.05
0.26
1.20
0.45±0.05 (165X)
0.15 0.08
Detail Solder Ball
Side View
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Ordering information
Package &Width
10AS7C251MFT18A-85TQC AS7C251MFT18A-85TQI AS7C251MFT18A-85BC AS7C251MFT18A-85BI
AS7C251MFT18A-10TQC AS7C251MFT18A-10TQI AS7C251MFT18A-10BC AS7C251MFT18A-10BI
TQFP
Note: above part numbers Lead Free Parts (Ex. AS7C251MFT18A-85TQCN)
Part numbering guide
AS7C
Alliance Semiconductor SRAM prefix Operating voltage: 2.5V Organization: Flow-through mode Organization: Production version: first production version Clock speed Package type: TQFP; Operating temperature: commercial industrial (-40°
Lead Free Part
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AS7C251MFT18A
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Copyright Alliance Semiconductor Rights Reserved Part Number: AS7C251MFT18A Document Version:
Copyright 2003 Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights; mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

2.5V flowthrough burst synchronous SRAM Features Organization: 1,

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