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TitlePage 80A3010_MA001_03
Universe IIVME-to-PCI Bridge Manual User Manual
Document Number: 80A3010_MA001_03 Document Status: Final Release Date: November 2002
This document discusses features, capabilities, configuration requirements Universe intended hardware software engineers designing system interconnect applications with Universe
Tundra Semiconductor Corporation
Trademarks
TUNDRA registered trademark Tundra Semiconductor Corporation (Canada, U.S., U.K.). TUNDRA, Tundra logo, Universe Silicon Behind Network, trademarks Tundra Semiconductor Corporation. other registered unregistered marks (including trademarks, service marks logos) property their respective owners. absence mark identifier representation that particular product name mark.
Copyright
Copyright November 2002 Tundra Semiconductor Corporation. rights reserved. Published Canada This document contains information which proprietary Tundra used non-commercial purposes within your organization support Tundra products. other transmission part this document permitted without written permission from Tundra, must include copyright other proprietary notices. transmission part this document violation applicable Canadian other legislation hereby expressly prohibited. User obtains rights information product, process, technology trademark which includes describes, expressly prohibited from modifying information creating derivative works without express written consent Tundra.
Disclaimer
Tundra assumes responsibility accuracy completeness information presented which subject change without notice. event will Tundra liable direct, indirect, special, incidental consequential damages, including lost profits, lost business lost data, resulting from reliance upon information, whether Tundra been advised possibility such damages. Mention non-Tundra products services information purposes only constitutes neither endorsement recommendation.
Corporate Profile
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation (TSE:TUN) designs, develops, markets advanced System Interconnect world's leading Internet communications infrastructure vendors. Tundra chips provide latest interface throughput features help these vendors design deliver more powerful equipment shorter timeframes. Tundra products essential range applications, including telecommunications, data communications, wireless communications, industrial automation, ruggedized systems. Tundra headquarters located Kanata, Ontario, Canada, sales offices based Mountain View, California Maidenhead, U.K. Tundra sells products worldwide through network direct sales personnel, independent distributors, manufacturers' representatives. More information available online www.tundra.com.
Greater Demand, Greater Opportunity
increasingly complex requirements placed Internet, intranets extranets have created insatiable demand higher speed greater capacity communications networks. evolution converging communications networks requires higher levels security increasingly sophisticated network intelligence. These network demands, user expectations that drive them, have created global need well-managed ever-increasing bandwidth. Tundra helps meet those demands creating underlying technology that enables accelerated flow voice, data, video information over communications networks. Tundra products found broad range applications, including telecommunications, data communications, wireless communications, industrial automation, avionics. Communications infrastructure vendors rely Tundra off-the-shelf, standards-based, easy-to-deploy highly scalable System Interconnect products.
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Tundra System Interconnect
Tundra System Interconnect. Tundra uses term System Interconnect refer technology used connect components sub-systems almost embedded system. This concept applies interfacing functional elements (CPU, memory, complexes, etc.) within single-board system, interfacing multiple boards larger system. System Interconnect vital enabling technology networked world. convergence voice, video, data traffic, need more secure communications, exploding demand high-speed network access putting communications infrastructure vendors under intense pressure provide faster, well-managed bandwidth that also integrates smoothly with existing technology. Tundra System Interconnect helps these vendors address their customer needs. enables them build standards-based network equipment that scale multi-gigahertz speeds also integrate with existing infrastructure.
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Fundamental success Tundra partnerships with leading manufacturers, including Motorola, Compaq Texas Instruments. result these alliances, Tundra devices greatly influence design customers' architectures. Customers changing their designs incorporate Tundra products. This highlights commitment Tundra holds significant part customers' success. Tundra design philosophy which number strategic customers invited participate definition, design, test, early silicon supply phases product development. Close working relationships with customers clear product roadmaps ensure that Tundra anticipate meet future directions needs communications systems designers manufacturers.
Tundra Customers
Tundra semiconductor products used world's leading communications infrastructure vendors, including Cisco, Motorola, Ericsson, Nortel, Lucent, IBM, Xerox, Hewlett-Packard, 3Com, Nokia, Siemens, Alcatel, Matsushita, OKI, Fujitsu, Samsung, LGS.
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Tundra respected throughout industry outstanding commitment customer support. Tundra ensures that customers take immediate advantage company's products through Applications Engineering Group, unmatched Design Support Tools (DST), full documentation. Customer support also includes Web-based telephone access in-house technical resources. Tundra System Interconnect Silicon Behind Network
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Contact Information
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Design Support Tools (DST)
database
Sales support
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Technical support
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Universe VME-to-PCI Bridge Manual
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Contents
Functional Overview.
1.1.1 1.1.2 1.1.3 1.2.1 1.2.2 1.2.3 1.2.4 Universe Features Universe Benefits. Universe Typical Applications VMEbus Interface Interface Interrupter Interrupt Handler Controller
Main Interfaces.
VMEbus Interface
VMEbus Requester 2.2.1 2.2.2 2.2.3 2.3.1 2.3.2 2.3.3 Internal Arbitration VMEbus Requests Request Modes VMEbus Release Addressing Capabilities. Data Transfer Capabilities Cycle Terminations
Universe VMEbus Master
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Contents
Universe VMEbus Slave. 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 Coupled Transfers Posted Writes Prefetched Block Reads VMEbus Lock Commands (ADOH Cycles) VMEbus Read-Modify-Write Cycles (RMW Cycles). Register Accesses. Location Monitors Generating Configuration Cycles First Slot Detector VMEbus Register Access Power-up Auto Slot VME64 Specified Auto-ID: Proprietary Tundra Method System Controller Functions IACK Daisy-Chain Driver Module VMEbus Time-out BI-Mode
VMEbus Configuration. 2.5.1 2.5.2
Automatic Slot Identification 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6
Interface
Cycles 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3.1 3.3.2 3.3.3 3.3.4 32-Bit Versus 64-Bit Request Parking Address Phase Data Transfer Termination Phase Parity Checking Command Types Burst Transfers Termination Parity
Universe Master.
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Contents
Universe Target. 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 Command Types Data Transfer Coupled Transfers Posted Writes. Special Cycle Generator Using VOWN Terminations
Slave Image Programming.
Slave Image Programming 4.2.1 4.2.2 4.2.3 4.3.1 4.3.2 4.3.3 VMEbus Fields Fields Control Fields Fields VMEbus Fields Control Fields
Target Images
Special Target Image
Registers Overview.
Register Access from 5.2.1 5.2.2 5.2.3 5.3.1 5.3.2 5.3.3 Configuration Access Memory Access Locking Register Block from bus. VMEbus Register Access Image (VRAI) CR/CSR Accesses ADOH Register Access Cycles
Register Access from VMEbus
Mailbox Registers Semaphores
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Contents
Controller.
Registers 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 Source Destination Addresses Non-incrementing Mode Transfer Size Transfer Data Width. Command Packet Pointer Control Status
Direct Mode Operation Linked-list Mode. 6.4.1 6.5.1 6.5.2 Linked-list Updating PCI-to-VMEbus Transfers VMEbus-to-PCI Transfers FIFO Operation Ownership
Interrupts. Channel Interactions with Other Channels. Error Handling 6.8.1 6.8.2 6.8.3 Software Response Error Hardware Response Error Resuming Transfers
Interrupt Generation Handling
Interrupt Generation 7.2.1 7.2.2 7.3.1 7.3.2 7.3.3 7.3.4 Interrupt Generation VMEbus Interrupt Generation Interrupt Handling. VMEbus Interrupt Handling Internal Interrupt Handling VME64 Auto-ID
Interrupt Handling.
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Contents
Error Handling.
Errors Coupled Cycles Errors Decoupled Transactions 8.3.1 8.3.2 8.3.3 8.3.4 Posted Writes. Prefetched Reads Errors. Parity Errors.
Resets, Clocks Power-up Options
Resets 9.2.1 9.2.2 9.3.1 9.3.2 9.3.3 9.4.1 9.4.2 Universe Reset Circuitry Reset Implementation Cautions. Power-up Option Descriptions Power-up Option Implementation Hardware Initialization (Normal Operating Mode). Auxiliary Test Modes JTAG support
Power-Up Options
Test Modes
Clocks.
Signals Pinout
10.2 VMEbus Signals. 10.3 Signals 10.4 Pin-out 10.4.1 List 313-pin Plastic Package (PBGA) 10.4.2 DBGA List
Electrical Characteristics.
11.1 Characteristics 11.1.1 Non-PCI Characteristics 11.1.2 Characteristics 11.2 Operating Conditions 11.2.1 Absolute Maximum Ratings 11.3 Power Dissipation 11.4 Power Sequencing
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Contents
Registers
12.2 Register Map.
Packaging Information
PBGA Package DBGA Package
Performance
Overview. Slave Channel B.2.1 B.2.2 B.3.1 B.3.2 B.4.1 B.4.2 B.4.3 B.5.1 B.5.2 Coupled Cycles Decoupled Cycles Coupled Cycles Decoupled Cycles VMEbus Ownership Modes. Transfers. Transfers Overview U2SPEC Register Adjustable Timing Parameters
Slave Channel
Channel Relative FIFO Sizes.
Universe Specific Register
Performance Summary
Reliability Prediction
Overview. Physical characteristics Thermal characteristics Universe Ambient Operating Calculations Thermal vias
Endian Mapping
Overview. Little-endian Mode
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Contents
Typical Applications
Overview Interface E.2.1 E.2.2 E.2.3 E.3.1 E.3.2 Transceivers. Direction control Power-up Options Resets. Local Interrupts
Interface
Manufacturing Test Pins Decoupling Universe
Ordering Information
Ordering Information
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Contents
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Universe Block Diagram Universe Single Board Computer Application Universe Data Flow Diagram. VMEbus Slave Channel Dataflow Timing Auto-ID Cycle Target Channel Dataflow Address Translation Mechanism VMEbus Transfers Address Translation Mechanism VMEbus Transfers Memory Mapping Special Target Image
Figure Universe Control Status Register Space Figure Access UCSR Memory Space Figure UCSR Access from VMEbus Register Access Image Figure UCSR Access VMEbus CR/CSR Space Figure Direct Mode transfers Figure Command Packet Structure Linked List Operation Figure Linked List Operation Figure Universe Interrupt Circuitry. Figure STATUS/ID Provided Universe Figure Sources Internal Interrupts. Figure Reset Circuitry Figure Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration Figure Power-up Options Timing Figure UCSR Access Mechanisms Figure PBGA Bottom View. Figure PBGA Side View Figure DBGA Notes.
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List Figures
Figure DBGA View Figure DBGA Bottom View. Figure Coupled Read Cycle Universe Master Figure Several Coupled Read Cycles Universe Master. Figure Coupled Write Cycle Universe Master Figure Several Non-Block Decoupled Writes Universe Master Figure Decoupled Write Universe Master Figure Coupled Read Cycle Universe Slave Figure Coupled Write Cycle Universe Slave (bus parked Universe Figure Non-Block Decoupled Write Cycle Universe Slave Figure Decoupled Write Cycle Universe Slave Figure MBLT Decoupled Write Cycle Universe Slave. Figure Pre-fetched Read Cycle Universe Slave Figure Read Transactions During Operation Figure Multiple Read Transactions During Operation. Figure Universe Connections VMEbus Through Buffers Figure Universe Connections VMEbus Through Buffers Figure Power-up Configuration Using Passive Pull-ups Figure Power-up Configuration Using Active Circuitry Figure Analog Isolation Scheme Figure Noise Filter Scheme
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List Tables
Table Table Table Table Table Table Table Table Table VMEbus Address Modifier Codes Address Line Asserted Function VA[15:11] Command Type Encoding Transfer Type Register Fields Special Cycle Generator VMEbus Fields VMEbus Slave Image. Fields VMEbus Slave Image Control Fields VMEbus Slave Image. Fields Target Image VMEbus Fields Target Image
Table Control Fields Target Image Table Fields Special Target Image Table VMEbus Fields Special Target Image Table Control Fields Special Target Image Table Programming VMEbus Register Access Image. Table Settings Non-Inc Mode Table Interrupt Sources Enable Bits Table Source, Enabling, Mapping, Status Interrupt Output. Table Source, Enabling, Mapping, Status VMEbus Interrupt Outputs. Table Internal Interrupt Routing. Table Hardware Reset Mechanisms Table Software Reset Mechanism Table Functions Affected Reset Initiators. Table Power-Up Options Table VRAI Base Address Power-up Options Table Manufacturing Requirements Normal Operating Mode Table Test Mode Operation
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List Tables
Table VMEbus Signals Table Signals Table List DBGA. Table DBGA List (continued) Table DBGA List (continued) Table DBGA List (continued) Table Ground, Power Table Non-PCI Electrical Characteristics. Table AC/DC Electrical Characteristics Table Operating Conditions Table Absolute Maximum Ratings Table Power Dissipation Table Universe Register Table Configuration Space Register (PCI_ID). Table Configuration Space Control Status Register (PCI_CSR) Table Configuration Class Register (PCI_CLASS) Table Configuration Miscellaneous Register (PCI_MISC0) Table Configuration Base Address Register (PCI_BS0). Table Configuration Base Address Register (PCI_BS1) Table Configuration Miscellaneous Register (PCI_MISC1) Table Target Image Control (LSI0_CTL) Table Target Image Base Address Register (LSI0_BS) Table Target Image Bound Address Register (LSI0_BD) Table Target Image Translation Offset (LSI0_TO) Table Target Image Control (LSI1_CTL) Table Target Image Base Address Register (LSI1_BS) Table Target Image Bound Address Register (LSI1_BD) Table Target Image Translation Offset (LSI1_TO) Table Target Image Control (LSI2_CTL) Table Target Image Base Address Register (LSI2_BS) Table Target Image Bound Address Register (LSI2_BD) Table Target Image Translation Offset (LSI2_TO) Table Target Image Control (LSI3_CTL) Table Target Image Base Address Register (LSI3_BS) Table Target Image Bound Address Register (LSI3_BD)
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List Tables
Table Target Image Translation Offset (LSI3_TO) Table Special Cycle Control Register (SCYC_CTL). Table Special Cycle Address Register (SCYC_ADDR) Table Special Cycle Swap/Compare Enable Register (SCYC_EN) Table Special Cycle Compare Data Register (SCYC_CMP). Table Special Cycle Swap Data Register (SCYC_SWP). Table Miscellaneous Register (LMISC) Table Special Target Image (SLSI). Table Command Error Register (L_CMDERR) Table Address Error (LAERR) Table Target Image Control Register (LSI4_CTL) Table Target Image Base Address Register (LSI4_BS) Table Target Image Bound Address Register (LSI4_BD). Table Target Image Translation Offset (LSI4_TO) Table Target Image Control Register (LSI5_CTL) Table Target Image Base Address Register (LSI5_BS) Table Target Image Bound Address Register (LSI5_BD). Table Target Image Translation Offset (LSI5_TO) Table Target Image Control Register (LSI6_CTL) Table Target Image Base Address Register (LSI6_BS) Table Target Image Bound Address Register (LSI6_BD). Table Target Image Translation Offset (LSI6_TO) Table Target Image Control Register (LSI7_CTL) Table Target Image Base Address Register (LSI7_BS) Table Target Image Bound Address Register (LSI7_BD). Table Target Image Translation Offset (LSI7_TO) Table Transfer Control Register (DCTL) Table Transfer Byte Count Register (DTBC) Table Address Register (DLA) Table VMEbus Address Register (DVA) Table Command Packet Pointer (DCPP) Table General Control/Status Register (DGCS) Table Linked List Update Enable Register (D_LLUE) Table Interrupt Enable Register (LINT_EN) Table Interrupt Status Register (LINT_STAT).
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List Tables
Table Interrupt Register (LINT_MAP0) Table Interrupt Register (LINT_MAP1) Table VMEbus Interrupt Enable Register (VINT_EN) Table VMEbus Interrupt Status Register (VINT_STAT). Table Interrupt Register (VINT_MAP0) Table Interrupt Register (VINT_MAP1) Table 100: Interrupt STATUS/ID Register (STATID) Table 101: VIRQ1 STATUS/ID Register (V1_STATID) Table 102: VIRQ2 STATUS/ID Register (V2_STATID) Table 103: VIRQ3 STATUS/ID Register (V3_STATID) Table 104: VIRQ4 STATUS/ID Register (V4_STATID) Table 105: VIRQ5 STATUS/ID Register (V5_STATID) Table 106: VIRQ6 STATUS/ID Register (V6_STATID) Table 107: VIRQ7 STATUS/ID Register (V7_STATID) Table 108: Interrupt Register (LINT_MAP2) Table 109: Interrupt Register (VINT_MAP2) Table 110: Mailbox Register (MBOX0) Table 111: Mailbox Register (MBOX1) Table 112: Mailbox Register (MBOX2) Table 113: Mailbox Register (MBOX3) Table 114: Semaphore Register (SEMA0) Table 115: Semaphore Register (SEMA1) Table 116: Master Control Register (MAST_CTL) Table 117: Miscellaneous Control Register (MISC_CTL). Table 118: Miscellaneous Status Register (MISC_STAT). Table 119: User Codes Register (USER_AM) Table 120: Universe Specific Register (U2SPEC) Table 121: VMEbus Slave Image Control (VSI0_CTL) Table 122: VMEbus Slave Image Base Address Register (VSI0_BS) Table 123: VMEbus Slave Image Bound Address Register (VSI0_BD) Table 124: VMEbus Slave Image Translation Offset (VSI0_TO) Table 125: VMEbus Slave Image Control (VSI1_CTL) Table 126: VMEbus Slave Image Base Address Register (VSI1_BS) Table 127: VMEbus Slave Image Bound Address Register (VSI1_BD) Table 128: VMEbus Slave Image Translation Offset (VSI1_TO)
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List Tables
Table 129: VMEbus Slave Image Control (VSI2_CTL). Table 130: VMEbus Slave Image Base Address Register (VSI2_BS) Table 131: VMEbus Slave Image Bound Address Register (VSI2_BD) Table 132: VMEbus Slave Image Translation Offset (VSI2_TO) Table 133: VMEbus Slave Image Control (VSI3_CTL). Table 134: VMEbus Slave Image Base Address Register (VSI3_BS) Table 135: VMEbus Slave Image Bound Address Register (VSI3_BD) Table 136: VMEbus Slave Image Translation Offset (VSI3_TO) Table 137: Location Monitor Control Register (LM_CTL). Table 138: Location Monitor Base Address Register (LM_BS) Table 139: VMEbus Register Access Image Control Register (VRAI_CTL) Table 140: VMEbus Register Access Image Base Address Register (VRAI_BS) Table 141: Power-up Option behavior field VRAI_CTL Table 142: VMEbus Control Register (VCSR_CTL) Table 143: VMEbus Translation Offset (VCSR_TO) Table 144: VMEbus Code Error (V_AMERR). Table 145: VMEbus Address Error (VAERR) Table 146: VMEbus Slave Image Control (VSI4_CTL). Table 147: VMEbus Slave Image Base Address Register (VSI4_BS) Table 148: VMEbus Slave Image Bound Address Register (VSI4_BD) Table 149: VMEbus Slave Image Translation Offset (VSI4_TO) Table 150: VMEbus Slave Image Control (VSI5_CTL). Table 151: VMEbus Slave Image Base Address Register (VSI5_BS) Table 152: VMEbus Slave Image Bound Address Register (VSI5_BD) Table 153: VMEbus Slave Image Translation Offset (VSI5_TO) Table 154: VMEbus Slave Image Control (VSI6_CTL). Table 155: VMEbus Slave Image Base Address Register (VSI6_BS) Table 156: VMEbus Slave Image Bound Address Register (VSI6_BD) Table 157: VMEbus Slave Image Translation Offset (VSI6_TO) Table 158: VMEbus Slave Image Control (VSI7_CTL). Table 159: VMEbus Slave Image Base Address Register (VSI7_BS) Table 160: VMEbus Slave Image Bound Address Register (VSI7_BD) Table 161: VMEbus Slave Image Translation Offset (VSI7_TO) Table 162: VMEbus Clear Register (VCSR_CLR) Table 163: VMEbus Register (VCSR_SET)
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List Tables
Table 164: VMEbus Base Address Register (VCSR_BS) Table 165: Slave Channel Performance. Table 166: Slave Channel Performance Table 167: Channel Performance Table 168: Ambient Junction Thermal Impedance. Table 169: Maximum Universe Junction Temperature. Table 170: Mapping 32-bit Little-Endian 32-bit VMEbus Table 171: Mapping 32-bit Little-Endian 64-bit VMEbus Table 172: VMEbus Signal Drive Strength Requirements Table 173: VMEbus Transceiver Requirements Table 174: Reset Signals. Table 175: Standard Ordering Information.
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About this Document
This chapter discusses general document information about Manual. following topics described: "Revision History" page "Document Conventions" page "Related Documents" page
Revision History
80A91142_MA001_03, Final Manual, November 2002
This final version Universe VME-to-PCI Bridge Manual. This document information applies both Universe Universe devices. Universe recommended designs. more information about devices, refer UniverseIID UniverseIIB Differences Summary Tundra website www.tundra.com. following chapter updated release this manual: "Reliability Prediction" page
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80A91142_MA001_02, Final Manual, October 2002
This final version Universe VME-to-PCI Bridge Manual. This document information applies both Universe Universe devices. Universe recommended designs. more information about devices, refer UniverseIID UniverseIIB Differences Summary Tundra website www.tundra.com. There erratum found DBGA package drawing. following section document been updated: "361 DBGA Package" page
80A91142_MA001_01, Final Manual, June 2002
This final version Universe VME-to-PCI Bridge Manual. This document information applies both Universe Universe devices. Universe recommended designs. more information about devices, refer Universe Universe Differences Summary Tundra website www.tundra.com.
Document Conventions
This section explains document conventions used this manual.
Signal Notation
Signals either active high active low. Active signals defined true (asserted) when they logic low. Similarly, active high signals defined true logic high. Signals considered asserted when active negated when inactive, irrespective voltage levels. voltage levels, indicates voltage while indicates high voltage. voltage levels, indicates voltage while indicates high voltage. voltage levels, indicates voltage while indicates high voltage. Each signal that assumes logic state when asserted followed underscore sign, "_". example, SIGNAL_ asserted indicate active signal. Signals that followed underscore asserted when they assume logic high state. example, SIGNAL asserted high indicate active high signal. asterisk sign used this manual show that signal asserted that used VMEbus backplane. example, SIGNAL* asserted indicate active signal VMEbus backplane.
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Ordering Notation
This document adopts convention that most significant always largest number (also referred Little-Endian ordering). example, address/data consists AD[31:0], where AD[31] most significant AD[0] least-significant field.
Object Size Notation
following object size conventions used: byte 8-bit object. word 16-bit byte) object. doubleword 32-bit byte) object. quadword 64-bit byte) object. Kword 1024 16-bit words.
Numeric Notation
following numeric conventions used: Hexadecimal numbers denoted prefix example, 0x04. Binary numbers denoted suffix example, 10b.
Typographic Notation
following typographic conventions used this manual: Italic type used following purposes: Book titles: example, Local Specification. Important terms: example, when device granted access called master. Undefined values: example, device supports four channels depending setting PCI_Dx register. Courier type used represent file name text that appears computer display. example, "run load.exe typing command prompt."
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Symbols Used
following symbols used this manual.
This symbol indicates basic design concept information considered helpful. This symbol indicates important configuration information suggestions. This symbol indicates procedures operating levels that result misuse damage device.
Document Status Information
Tundra technical documentation classified either Advance, Preliminary, Final: Advance: Advance manual contains information that subject change exists until prototypes available. This type manual downloaded from website www.tundra.com. Preliminary: Preliminary manual contains information about product that near production-ready, revised required. Preliminary manual exists until product released production. This type manual downloaded from website www.tundra.com. Final: Final manual contains information about final, customer-ready product. This type manual downloaded from website. also ordered print format calling 613-592-0714 1-800-267-7231 (please customer service), email docs@tundra.com.
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Related Documents
following documents useful reference purposes when using this manual. Local Specification (Revision 2.2) This specification defines hardware environment including protocol, electrical, mechanical configuration specification local components expansion boards. more information, www.pcisig.com. This specification defines VME64 hardware environment including protocol, electrical, mechanical, configuration specification. more information, www.vita.com
VME64 Specification
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Functional Overview
This chapter outlines functionality Universe This chapter discusses following topics: "VMEbus Interface" page "PCI Interface" page "Interrupter Interrupt Handler" page "DMA Controller" page
Overview
Tundra Universe industry's leading high performance PCI-to-VMEbus interconnect. Universe fully compliant with VME64 standard, tailored next-generation advanced processors peripherals. With zero-wait state implementation, multi-beat transactions, support bus-parking, Universe provides high performance bus. Universe eases development multi-master, multi-processor architectures VMEbus systems. device ideally suited boards functioning both master slave VMEbus system, that require access systems. Bridging accomplished through decoupled architecture with independent FIFOs inbound, outbound, traffic. With this architecture, throughput maximized without sacrificing bandwidth either bus. With Universe know that your system becomes more complex, have proven silicon that continues provide everything need PCI-to-VME bridge.
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Functional Overview
Figure Universe Block Diagram
Four location Fixed priority, montiors support VMEbus Round robin, broadcast capability Single level modes
Location Monitor
VMEbus Arbiter
VMEbus Slave Channel
Posted Writes, Prefetched Reads, Coupled Reads 32-bit Address 64-bit Data VMEbus
32-bit Address 64-bit Data
Channel
VMEbus Interface
8091862_BK001_03
Interface
Bidirectional FIFO, Direct/Linked List Mode
Register Channel
Configuration Registers, Mailbox Registers, Semaphores
Interrupt Channel
Interrupt Handler, Interrupter
Target Channel
Posted Writes, Coupled Read
JTAG
IEEE1149.1 Boundary Scan
1.1.1
Universe Features
Universe following features: Industry-proven, high performance 64-bit VMEbus interconnect Fully compliant, 32-bit 64-bit, interconnect Integral FIFOs write posting maximize bandwidth utilization Programmable controller with Linked-List mode (Scatter/Gather) support Flexible interrupt logic Sustained transfer rates 60-70 Mbytes/s Extensive suite VMEbus address data transfer modes Automatic initialization slave-only applications
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Functional Overview
Flexible register set, programmable from both VMEbus ports Full VMEbus system controller Support RMWs, ADOH, LOCK_ cycles, semaphores Commercial, industrial, extended temperature variants IEEE 1149.1 JTAG Available packaging: 25mm 25mm, 361-contact dimpled ceramic (DBGA) 35mm 35mm, 313-contact plastic (PBGA) package
1.1.2
Universe Benefits
Universe offers following benefits designers: Conserves board space with 25mm 25mm, 361-contact dimpled ceramic (DBGA) Industry proven device Reliable customer support with experience hundreds customer designs
1.1.3
Universe Typical Applications
Universe targeted today's technology demands, such following: Single-board computers Telecommunications equipment Test equipment Command control systems Factory automation equipment Medical equipment Military Aerospace
1.1.3.1
Typical Application Example: Single Board Computers Universe widely used VME-based Single Board Computers (SBC) that employ their local backplane bus, shown accompanying diagram. These cards support variety applications including telecom, datacom, medical, industrial, military equipment.
Universe high performance architecture seamlessly bridges busses, industry's standard single board computer interconnect device.
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Functional Overview
Figure Universe Single Board Computer Application
Memory
Connection
Processor
Processor
Processorto-PCI Bridge
32-bit 64-bit Data
Controller
Universe
64-bit Data
VMEbus
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Functional Overview
Main Interfaces
Universe main interfaces: Interface VMEbus Interface. Each interfaces, VMEbus bus, there three functionally distinct modules: master module, slave module, interrupt module. These modules connected different functional channels operating Universe device following channels: VMEbus Slave Channel Target Channel Channel Interrupt Channel Register Channel
Figure shows Universe terms different modules channels.
Figure Universe Data Flow Diagram
Channel
Interface
bidirectional FIFO
VMEbus Interface
VMEbus Slave Channel
Master
posted writes FIFO prefetch read FIFO coupled read
Slave
Slave Channel
Slave
posted writes FIFO coupled read logic
Master
VMEbus
Interrupt Channel
Interrupts
Interrupt Handler Interrupter
Interrupts
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Register Channel
Mailbox Registers Semaphores
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Functional Overview
1.2.1
1.2.1.1
VMEbus Interface
Interface VME64 Specification compliant interface.
Universe VMEbus Slave Universe VMEbus Slave Channel accepts addressing data transfer modes documented VME64 Specification except those intended augment applications. Incoming write transactions from VMEbus treated either coupled posted, depending upon programming VMEbus slave image (see "VME Slave Image Programming" page 84). With posted write transactions, data written Posted Write Receive FIFO (RXFIFO), VMEbus master receives data acknowledgment from Universe Write data transferred resource from RXFIFO without involvement initiating VMEbus master (see "Posted Writes" page full explanation this operation). With coupled cycle, VMEbus master only receives data acknowledgment when transaction complete bus. This means that VMEbus unavailable other masters while transaction executed.
Read transactions either prefetched coupled. prefetched read initiated when VMEbus master requests block read transaction (BLT MBLT) this mode enabled. When Universe receives block read request, begins fill Read Data FIFO (RDFIFO) using burst transactions from resource. initiating VMEbus master then acquires block read data from RDFIFO instead directly from resources. VMEbus slave, Universe does assert RETRY* termination transaction.
1.2.1.2
Universe VMEbus Master Universe becomes VMEbus master when VMEbus Master Interface internally requested Target Channel, Channel, Interrupt Channel. Interrupt Channel always priority over other channels. Several mechanisms available configure relative priority that Target Channel Channel have over ownership VMEbus Master Interface.
Universe II's VMEbus Master Interface generates addressing data transfer modes documented VME64 Specification except those intended augment applications. Universe also compatible with VMEbus modules conforming pre-VME64 specifications.
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Functional Overview
VMEbus master, Universe supports Read-Modify-Write (RMW), Address-Only-with-Handshake (ADOH) does accept RETRY* termination from VMEbus slave. ADOH cycle used implement VMEbus Lock command allowing master lock VMEbus resources.
1.2.2
1.2.2.1
Interface
Interface Specification compliant interface
Universe Target Read transactions from always processed coupled transactions. Write transactions either coupled posted, depending upon setting target image (see "PCI Target Images" page 87). With posted write transaction, write data written Posted Write Transmit FIFO (TXFIFO) master receives data acknowledgment from Universe with zero wait-states. Meanwhile, Universe obtains VMEbus writes data VMEbus resource independent initiating master (see "Posted Writes" page full description this operation).
Universe Special Cycle Generator that enables masters perform ADOH cycles. Special Cycle Generator must used combination with VMEbus ownership function guarantee masters exclusive access VMEbus resources over several VMEbus transactions (see "Special Cycle Generator" page "Using VOWN bit" page full description this functionality).
1.2.2.2 Universe Master Universe becomes master when Master Interface internally requested VMEbus Slave Channel Channel. There mechanisms provided which allow user configure relative priority VMEbus Slave Channel Channel.
1.2.3
1.2.3.1
Interrupter Interrupt Handler
Universe both interrupt generation interrupt handling capability.
Interrupter Universe Interrupt Channel provides flexible scheme interrupts VMEbus Interface. Interrupts generated from hardware software sources (see "Interrupt Generation" page "Interrupt Handling" page full description hardware software sources). Interrupt sources mapped VMEbus interrupt output pins. Interrupt sources mapped VMEbus interrupts generated VMEbus interrupt output pins VIRQ_ [7:1]. When software hardware source assigned same VIRQ_ pin, software source always higher priority.
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Functional Overview
Interrupt sources mapped interrupts generated INT_ [7:0] pins. fully compliant, interrupt sources must routed single INT_ pin. VMEbus interrupt outputs, Universe interrupter supplies 8-bit STATUS/ID VMEbus interrupt handler during IACK cycle. interrupter also generates internal interrupt this situation SW_IACK bit, Interrupt Status (LINT_STAT) register, (see "VMEbus Interrupt Generation" page 133). Interrupts mapped outputs serviced interrupt controller. determines which interrupt sources active reading interrupt status register Universe source negates interrupt when been serviced (see "PCI Interrupt Generation" page 131).
1.2.3.2 VMEbus Interrupt Handling VMEbus interrupt triggers Universe generate normal VMEbus IACK cycle generate specified interrupt output. When IACK cycle complete, Universe releases VMEbus interrupt vector read resource servicing interrupt output. Software interrupts ROAK, while hardware, internal interrupts RORA.
1.2.4
Controller
Universe internal controller high performance data transfer between VMEbus. operations between source destination decoupled through single bidirectional FIFO (DMAFIFO). Parameters transfer software configurable Universe registers (see "DMA Controller" page 103). principal mechanism transfers same operations either direction (PCI-to-VMEbus, VMEbus-to-PCI), only relative identity source destination changes. transfer, Universe gains control source reads data into DMAFIFO. Following specific rules DMAFIFO operation (see "FIFO Operation Ownership" page 121), then acquires destination writes data from DMAFIFO. controller programmed perform multiple blocks transfers using linked-list mode. works through transfers linked-list following pointers each linked-list entry. Linked-list operation initiated through pointer internal Universe register, linked-list itself resides memory.
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VMEbus Interface
This chapter explains operation VMEbus Interface.This chapter discusses following topics: "VMEbus Requester" page "Universe VMEbus Master" page "Universe VMEbus Slave" page "VMEbus Configuration" page "Automatic Slot Identification" page "System Clock Driver" page
Overview
VMEbus Interface incorporates operations associated with VMEbus. This includes master slave functions, VMEbus configuration system controller functions.
VMEbus Requester
There different channels Universe which require VMEbus. They referred VMEbus requesters described following sections.
2.2.1
Internal Arbitration VMEbus Requests
Different internal channels within Universe require VMEbus: Interrupt Channel, Target Channel, Channel. These three channels directly request VMEbus, instead they compete internally ownership VMEbus Master Interface.
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2.2.1.1
Interrupt Channel Interrupt Channel (refer Figure page always highest priority access VMEbus Master Interface. Target Channel requests handled fair manner. channel awarded VMEbus mastership maintains ownership VMEbus until completed transaction. definition complete transaction each channel "VMEbus Release" page
Interrupt Channel requests VMEbus master when detects enabled VMEbus interrupt line asserted must interrupt acknowledge cycle acquire STATUS/ID.
2.2.1.2 Target Channel Target Channel requests VMEbus Master Interface service following conditions:
2.2.1.3
TXFIFO contains complete transaction coupled cycle request.
Channel Channel requests VMEbus Master Interface following instances:
DMAFIFO bytes available reading from VMEbus) bytes FIFO writing VMEbus), block complete (see "DMA Controller" page 103).
case Channel, user optionally Channel VMEbus-off-timer further qualify requests from this channel. VMEbus-off-timer controls long remains VMEbus before making another request (see "PCI-to-VMEbus Transfers" page 121). Universe provides software mechanism VMEbus acquisition through VMEbus ownership (VOWN MAST_CTL register, Table 116). When VMEbus ownership set, Universe acquires VMEbus sets acknowledgment (VOWN_ACK MAST_CTL register, Table 116) optionally generates interrupt (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 80). Universe maintains VMEbus ownership until ownership cleared. During VMEbus tenure initiated setting ownership bit, only Target Channel Interrupt Channel access VMEbus Master Interface.
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2.2.2
Request Modes
Universe configurable request modes operation, described following sections.
2.2.2.1
Request Levels Universe software configurable request four VMEbus request levels: BR3*, BR2*, BR1*, BR0*. default setting level VMEbus request. request level global programming option through VMEbus Release Mode (VRL) field Master Control (MAST_CTL) register (Table 116). programmed request level used VMEbus Master Interface regardless channel (Interrupt Channel, Channel, Target Channel) currently accessing VMEbus Master Interface. Fair Demand Modes Universe requester programmed either Fair Demand mode. request mode global programming option through VMEbus Request Mode (VRM) bits MAST_CTL register (Table 116).
2.2.2.2
Fair mode, Universe does request VMEbus until there other VMEbus requests pending programmed level. This mode ensures that every requester equal level access bus. default setting Demand mode, requester asserts request regardless state BRn* line. requesting frequently, requesters down daisy chain prevented from ever obtaining ownership. This referred starving those requesters. Note that order achieve fairness, requesters VMEbus system must fair mode.
2.2.3
VMEbus Release
Universe VMEbus requester configured either (release when done) (release request) using VREL MAST_CTL register (Table 116). default setting RWD. means Universe releases BBSY* only request pending from another VMEbus master once channel that current owner VMEbus Master Interface done. Ownership assumed another channel without re-arbitration there pending requests level VMEbus. When RWD, VMEbus Master Interface releases BBSY* when channel accessing VMEbus Master Interface done (see below). Note that MYBBSY status MISC_STAT register (Table 118) when Universe asserts BBSY*.
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mode, VMEbus released when channel (for example, Channel) done, even another channel request pending (for example, Target Channel). re-arbitration VMEbus required pending channel requests. Each channel rules that determine when `done' with VMEbus transaction.
2.2.3.1 Transaction Complete interrupt complete when single interrupt acknowledge cycle complete.
Target Channel complete under following conditions: when TXFIFO empty, TXFE clear (the TXFE Universe MISC_STAT register, Table 118), when maximum number bytes Target Channel tenure been reached programmed with PWON field MAST_CTL register, Table 116)1, after each posted write, PWON equal 0b1111, programmed MAST_CTL register, Table when coupled cycle complete Coupled Window Timer expired, Coupled Request Timer (page expires before coupled cycle retried master, when VMEbus ownership acquired with VOWN MAST_CTL register then VOWN cleared other words, VMEbus acquired through VOWN bit, Universe does release BBSY* until VOWN cleared-see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 80).
Channel complete under following conditions: DMAFIFO full during VMEbus transfers, DMAFIFO empty during VMEbus transfers, error encountered during operation, VMEbus Tenure Byte Counter expired, block complete.
Refer "FIFO Operation Ownership" page "DMA Error Handling" page more information.
This setting overridden VOWN mechanism used.
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Universe ownership VMEbus affected assertion BCLR* because does monitor BCLR*.
Universe VMEbus Master
Universe becomes VMEbus master under following circumstances: master accesses Universe target image (leading VMEbus access) Channel initiates transaction, Either Universe Target Channel Channel wins access VMEbus Master Interface through internal arbitration Universe Master Interface requests obtains ownership VMEbus
Universe also becomes VMEbus master VMEbus ownership (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page role VMEbus interrupt handling (see "VMEbus Interrupt Handling" page 136). following sections describe function Universe VMEbus master terms different phases VMEbus transaction: addressing, data transfer, cycle termination, release.
2.3.1
Addressing Capabilities
Depending upon programming target image (see "PCI Target Images" page 87), Universe generates A16, A24, A32, CR/CSR address phases VMEbus. address mode type (supervisor/non-privileged program/data) also programmed through target image. Address pipelining provided, except during MBLT cycles. VMEbus Specification does permit pipelining during MBLT cycles. address Address Modifier (AM) codes that generated Universe functions address target image programming (see "PCI Target Images" page through programming. Table shows codes used VMEbus.
Table VMEbus Address Modifier Codes
Address Modifier 0x3F 0x3E 0x3D Address Bits Description supervisory block transfer (BLT) supervisory program access supervisory data access
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Table VMEbus Address Modifier Codes
Address Modifier 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x35 0x34 0x32 0x2F 0x2D 0x2C 0x29 0x21 0x20 0x10 0x1F Address Bits Undefined Description supervisory 64-bit block transfer (MBLT) non-privileged block transfer (BLT) non-privileged program access non-privileged data access non-privileged 64-bit block transfer (MBLT) A40BLT [MD32] lock command (LCK) access lock command CR/CSR supervisory access lock command non-privileged access 2eVME modules (address size code) 2eVME modules (address size code) User-defined supervisory block transfer (BLT) supervisory program access supervisory data access supervisory 64-bit block transfer (MBLT) non-privileged block transfer (BLT) non-privileged program access non-privileged data access non-privileged 64-bit block transfer (MBLT) lock command lock command
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Table VMEbus Address Modifier Codes
Address Modifier Address Bits Description block transfer (BLT) single transfer access 64-bit block transfer (MBLT)
Universe generates Address-Only-with-Handshake (ADOH) cycles support lock commands A16, A24, spaces. ADOH cycles only generated through Special Cycle Generator (see "Special Cycle Generator" page 78). There User Defined codes that programmed through USER_AM register (Table 119). USER_AM register only used generate accept codes 0x10 through 0x1F. default USER_AM code 0x10. These codes designated USERAM codes VMEbus Specification. After power-up, values USER_AM register default same VME64 User-defined code. USER_AM code used with VMEbus Slave Interface, cycles must 32-bit addressing, only single cycle accesses used. BLTs MBLTs with USER_AM codes will lead unpredictable behavior.
2.3.2
Data Transfer Capabilities
VMEbus protocols have different data transfer capabilities. maximum data width VMEbus data transfer programmed with VMEbus Maximum Datawidth (VDW) field Target Image control (see Table page 213). example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled will broken into 16-bit cycles VMEbus. target image also programmed with block transfers enabled, 32-bit data beat will result block transfer VMEbus. Write data unpacked VMEbus read data packed data width. data width data beat same maximum data width target image, then Universe maps data beat equivalent VMEbus cycle. example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled translated single 32-bit cycle VMEbus.
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VMEbus Interface
general rule, data width less than VMEbus data width then there packing unpacking between buses. only exception this during 32-bit multi-data beat transactions target image programmed with maximum VMEbus data width bits. this case, packing/unpacking occurs make maximum full bandwidth both buses. Only aligned VMEbus transactions generated, requested data beat unaligned, non-, byte enables, then broken into multiple aligned VMEbus transactions wider than programmed VMEbus data width. example, consider three-byte data beat 32-bit bus) accessing target image with bits. three-byte data beat broken into three aligned VMEbus cycles: three single-byte cycle (the ordering cycles depends arrangement byte enables data beat). above example target image 8-bit, then three-byte data beat broken into three single-byte VMEbus cycles. BLT/MBLT cycles initiated VMEbus target image been programmed with this capacity (see "PCI Target Images" page 87). length BLT/MBLT transactions VMEbus determined initiating transaction. example, single data beat transaction queued TXFIFO results single data beat block transfer VMEbus. With PWON field, user specify transfer byte count that queued from TXFIFO before VMEbus Master Interface relinquishes VMEbus. PWON field specifies minimum tenure Universe VMEbus. However, tenure extended VOWN MAST_CTL register (see "Using VOWN bit" page 81). During operations, Universe attempts block transfers maximum length permitted VMEbus specification (256 bytes BLT, Kbytes MBLT) limited counter (see "DMA VMEbus Ownership" page 110). Universe provides indivisible transactions with VMEbus lock commands VMEbus ownership (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 80).
2.3.3
Cycle Terminations
Universe accepts BERR* DTACK* cycle terminations from VMEbus slave. does support RETRY*. assertion BERR* indicates that some type system error occurred transaction complete properly. assertion BERR* during IACK also causes error logged.
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VMEbus Interface
VMEbus BERR* received Universe during coupled transaction communicated master Target-Abort. information logged Universe receives BERR* coupled transaction. error occurs during posted write VMEbus during IACK cycle, Universe uses V_AMERR register (Table 144) code transaction (AMERR [5:0]), state IACK* signal (IACK bit, indicate whether error occurred during IACK cycle). current transaction FIFO purged. V_AMERR register also records multiple errors have occurred (with M_ERR bit), although actual number errors given. error qualified value V_STAT bit. address errored transaction latched V_AERR register (Table 144). When Universe receives VMEbus error during posted write, generates interrupt VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Interrupt Handling" page 136, Table Table 96). DTACK* signals successful completion transaction.
Universe VMEbus Slave
This section describes VMEbus Slave Channel other aspects Universe VMEbus slave. Universe becomes VMEbus slave when eight programmed slave images register images accessed VMEbus master. Depending upon programming slave image, different possible transaction types result (see "VME Slave Image Programming" page 84). Universe cannot reflect cycle VMEbus access itself.
reads, transaction coupled prefetched. Write transactions coupled posted. type read write transaction allowed slave image depends programming that particular VMEbus slave image (see Figure below "VME Slave Image Programming" page 84). ensure sequential consistency, prefetched reads, coupled reads, coupled write operations only processed once previously posted write operations have completed (the RXFIFO empty).
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Figure VMEbus Slave Channel Dataflow
PREFETCHED READ DATA RDFIFO
MASTER INTERFACE
COUPLED READ DATA
COUPLED WRITE DATA POSTED WRITE DATA RXFIFO
VMEbus SLAVE INTERFACE
Incoming cycles from VMEbus have data widths 8-bit, 16-bit, 32-bit, 64-bit. Although supports only port sizes (32-bit 64-bit), byte lanes individually enabled, which allows each type VMEbus transaction directly mapped data bus. order VMEbus slave image respond incoming cycle, Master Interface must enabled (bit PCI_CSR register, Table 38). data queued VMEbus Slave Channel FIFO cleared, FIFO empties additional transfers received.
2.4.1
Coupled Transfers
coupled transfer means that FIFO involved transaction handshakes relayed directly through Universe Coupled mode default setting VMEbus slave images. Coupled transfers only proceed once posted write entries RXFIFO have completed (see "Posted Writes"). coupled cycle with multiple data beats (such block transfers) VMEbus side always mapped single data beat transactions bus, where each data beat VMEbus mapped single data beat transaction regardless data beat size. packing unpacking performed. only exception this when VMEbus transaction mapped bus. data width depends programming VMEbus slave image (32-bit 64-bit, "VME Slave Image Programming" page 84). Universe enables appropriate byte lanes required VMEbus transaction. example, VMEbus slave image programmed generate 32-bit transactions accessed VMEbus read transaction (prefetching enabled this slave image). transaction mapped single data beat 32-bit transfers with only byte lane enabled.
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Target-Retry from target communicated VMEbus master. transactions terminated with Target-Abort Master-Abort terminated VMEbus with BERR*. Universe sets R_TA R_MA bits PCI_CSR register (Table when receives Target-Abort Master-Abort.
2.4.2
Posted Writes
posted write involves VMEbus master writing data into Universe II's RXFIFO, instead directly address. Write transactions from VMEbus processed posted PWEN VMEbus slave image control register (see "VME Slave Image Programming" page 84). cleared (default setting) transaction bypasses FIFO performed coupled transfer. Incoming posted writes from VMEbus queued 64-entry deep RXFIFO. Each entry RXFIFO contain address bits, data bits. Each incoming VMEbus address phase, whether 16-bit, 24-bit, 32-bit, constitutes single entry RXFIFO followed subsequent data entries. address entry contains translated address space command information mapping relevant particular VMEbus slave image that been accessed (see "VME Slave Image Programming" page 84). this reason, reprogramming VMEbus slave image attributes only reflected RXFIFO entries queued after reprogramming. Transactions queued before re-programming delivered with VMEbus slave image attributes that were before reprogramming. RXFIFO same structure RDFIFO. different names used FIFO's roles. each FIFO, only role, either RXFIFO RDFIFO, used time.
2.4.2.1
FIFO Entries Incoming non-block write transactions from VMEbus require entries RXFIFO: address entry (with accompanying command information) data entry. size data entry corresponds data width VMEbus transfer. Block transfers require least entries: entry address command information, more data entries. VMEbus Slave Channel packs data received during block transfers full 64-bit width RXFIFO. example, data phase transfer bytes total) does require data entries RXFIFO. Instead, eight data phases bits data phase total bits) packed into 64-bit data entries RXFIFO. final data phases bits combined) queued next RXFIFO entry. When address entry added three data entries, this VMEbus block write been stored total five RXFIFO entries.
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Unlike Target Channel (see "Universe Target"), VMEbus Slave Channel does retry VMEbus RXFIFO does have enough space hold incoming VMEbus write transaction. Instead, DTACK* response from VMEbus Slave Interface delayed until space becomes available RXFIFO. Since single transfers require entries RXFIFO, entries must available before VMEbus Slave Interface asserts DTACK*. Similarly, VMEbus Slave Channel requires available RXFIFO entries before acknowledge first data phase MBLT transfer (one entry address phase first data phase). RXFIFO available space subsequent data phases block transfer, then VMEbus Slave Interface delays assertion DTACK* until single entry available next data phase block transfer. Master Interface uses transactions queued RXFIFO generate transactions bus. address phase deletion performed, length transaction corresponds length queued VMEbus transaction. Non-block transfers generated single data beat transactions. Block transfers generated more burst transactions, where length burst transaction programmed (PABS field MAST_CTL register, Table 116). Universe always packs unpacks data from VMEbus transaction data width programmed into VMEbus slave image (with byte lanes enabled). data width VMEbus transaction programmed LD64EN VMEbus Slave Image Control register (see Table 121). LD64EN enables 64-bit transactions example, consider VMEbus slave image programmed posted writes that accessed with VMEbus block write transaction. VMEbus write transactions mapped write transactions with byte lanes enabled. (However, single transaction from VMEbus mapped with only byte lanes enabled). During block transfers, Universe packs data full negotiated width bus. This imply that block transfers that begin addresses aligned width different byte lanes enabled during each data beat.
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2.4.2.2
Errors error occurs during posted write bus, Universe uses L_CMDERR register (Table command information transaction (CMDERR [3:0]). L_CMDERR register also records multiple errors have occurred (with M_ERR bit) although actual number errors given. error qualified with L_STAT bit. address errored transaction latched LAERR register (Table 68). interrupt generated VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Error Handling" page "Interrupt Generation Handling" page 129).
2.4.3
Prefetched Block Reads
Prefetching read data occurs VMEbus block transfers (BLT, MBLT) those slave images that have Prefetch Enable (PREN) (see "VME Slave Image Programming" page 84). VMEbus Slave Channel, prefetching supported non- BLT/MBLT transfers. Without prefetching, block read transactions from VMEbus master handled VMEbus Slave Channel coupled reads. This means that each data phase block transfer translated single data beat transaction bus. addition, only amount data requested during relevant data phase fetched from bus. example, block read transaction with data phases VMEbus maps transactions, where each transaction only byte lanes enabled. VMEbus lies idle during arbitration time required each transaction, resulting performance degradation.
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VMEbus Interface
With prefetching enabled, VMEbus Slave Channel uses 64-entry deep RDFIFO provide read data VMEbus with minimum latency. RDFIFO 64-bit, with additional bits control information. VMEbus slave image programmed prefetching (see "VME Slave Image Programming" page 84), then block read access that image causes VMEbus Slave Channel generate aligned burst read transactions (the size burst read transactions determined setting aligned burst size, PABS MAST_CTL register). These burst read transaction queued RDFIFO data then delivered VMEbus. first data phase provided VMEbus master essentially coupled read, subsequent data phases VMEbus block read delivered from RDFIFO decoupled (see "Prefetched Reads" page impact error handling). RXFIFO same structure RDFIFO. different names used FIFO's roles. each FIFO, only role, either RXFIFO RDFIFO, used time.
2.4.3.1 FIFO Entries When there transactions from Universe Slave Universe Master, data width transaction (32-bit 64-bit) depends setting LD64EN VMEbus Slave Image Control register (see Table 121) capabilities accessed target.
Internally, prefetched read data packed 64-bit, regardless width data width original VMEbus block read address information stored with data). Once entry queued RDFIFO, VMEbus Slave Interface delivers data VMEbus, unpacking data necessary with data width original VMEbus block read (D16, D32). VMEbus Slave Interface continuously delivers data from RDFIFO VMEbus master performing block read transaction. Because data transfer rates exceed those VMEbus, unlikely that RDFIFO will unable deliver data VMEbus master. this reason, block read performance VMEbus similar that observed with block writes. However, RDFIFO unable deliver data VMEbus master (which happen there considerable traffic target slow response) VMEbus Slave Interface delays DTACK* assertion until entry queued available VMEbus block read.
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bus, prefetching continues long there room another transaction RDFIFO initiating VMEbus block read still active. space required RDFIFO another burst read transaction determined setting aligned burst size (PABS MAST_CTL register, Table 116). PABS bytes, there must four entries available RDFIFO; aligned burst size bytes, eight entries must available, aligned burst size bytes, there must entries available. When there insufficient room RDFIFO hold another burst read, read transactions terminated only resume room becomes available another aligned burst original VMEbus block read still active. When VMEbus block transfer terminates, remaining data RDFIFO removed. Reading does cross 2048-byte boundary. Master Interface releases FRAME_ VMEbus Slave Channel relinquishes internal ownership Master Interface when reaches this boundary. VMEbus Slave Channel re-requests internal ownership Master Interface soon possible, order continue reading from external target. PABS setting determines much data must available RDFIFO before VMEbus Slave Channel continues reading. Regardless read request, data width prefetching side full width with byte lanes enabled. LD64EN VMEbus Slave image, Universe requests asserting REQ64_ during address phase. target does respond with ACK64_, subsequent data beats D32.
2.4.3.2 Errors error occurs bus, Universe does translate error condition into BERR* VMEbus; Universe does directly error. doing nothing, Universe forces external VMEbus error timer expire.
2.4.4
VMEbus Lock Commands (ADOH Cycles)
Universe supports VMEbus lock commands described VME64 Specification. Under specification, ADOH cycles used execute lock command (with special code, Table page 39). purpose Lock command lock resources card master card cannot modify resource. resource locked VMEbus cannot accessed other resource during tenure VMEbus master.
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When Universe receives VMEbus lock command, asserts LOCK_ addressed resource bus. Master Interface processes this 32-bit read transfer with byte lanes enabled data). subsequent slave VMEbus transactions coupled while Universe owns LOCK_. Universe holds lock until VMEbus lock command terminated negating BBSY*). VMEbus Slave Channel dedicated access Master Interface during locked transaction. Universe accepts ADOH cycles slave images when Universe Master Interface enabled PCI_CSR register) images programmed transactions into Memory Space.
2.4.4.1 Errors error occurs bus, error will occur VMEbus because they coupled. event error occurs VMEbus once LOCK_ been established, VMEbus master which locked VMEbus must terminate LOCK_ negating BBSY*. Access Once external VMEbus masters locks bus, Universe does perform transfers until unlocked.
2.4.4.2
LOCK_ negated when negated VMEbus. LOCK_ negated when negated LOCK_ asserted ADOH/lock command.
2.4.5
VMEbus Read-Modify-Write Cycles (RMW Cycles)
read-modify-write (RMW) cycle allows VMEbus master read from VMEbus slave then write same resource without relinquishing tenure between operations. Each Universe slave images programmed transactions locked transactions. LLRMW enable selected VMEbus slave image control register (Table page 316), then every non-block slave read mapped coupled locked read. LOCK_ held until negated VMEbus. Every non-block slave read assumed since there possible indication from VMEbus master that single cycle read just read beginning RMW. cycles supported with unaligned cycles.
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LLRMW enable Universe receives VMEbus cycle, read write portions cycle treated independent transactions read followed write). write coupled decoupled depending state PWEN accessed slave image. There adverse performance impact reads that processed through RMW-capable slave image This increased LOCK_ currently owned another master. When external VMEbus Master begins cycle, some point read cycle appears bus. During time between when read cycle occurs when associated write cycle occurs bus, transfers occurs bus.
2.4.6
Register Accesses
"Registers" page full description register mapping register access.
2.4.7
Location Monitors
Universe four location monitors support VMEbus broadcast capability. location monitors' image 4-Kbyte image A16, space VMEbus. enabled, access location monitor causes Master Interface generate interrupt. Location Monitor Control Register (LM_CTL, Table 137) controls Universe II's location monitoring. field LM_CTL register enables capability. PGM[1:0] field sets Program/Data code. SUPER[1:0] field LM_CTL register sets Supervisor/User code which Universe responds. VAS[3:0] field LM_CTL register specifies address space that monitored. BS[31:12] field location monitor Base Address Register (LM_BS, Table 138) specifies lowest address Kbyte range that decoded location monitor access. While Universe four location monitors, they share same LM_CTL LM_BS registers. address spaces A16, respective upper address bits ignored. When access location monitor detected, interrupt generated bus. VMEbus address bits [4:3] determine which Location Monitor used, hence which four interrupts generate (see "Location Monitors" page 144). location monitors store write data. Read data from location monitors undefined. Location monitors support MBLT transfers.
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Each Universe VMEbus must programmed monitor same Kbytes addresses VMEbus. Universe accesses (enabled) location monitor, same Universe generates DTACK* VMEbus terminates cycle. This removes necessity system integrator ensuring that there another card enabled generate DTACK*. generation DTACK* happens after Universe decoded responded cycle. location monitor accessed different master, Universe does respond with DTACK*.
2.4.8
Generating Configuration Cycles
Configuration cycles generated accessing VMEbus slave image whose Local Address Space field (LAS) Configuration Space. ADOH, MBLT cycles must attempted when field image programmed Configuration Space. Both Type Type cycles generated handled through same mechanism. Once VMEbus cycle received mapped configuration cycle, Universe compares bits [23:16] incoming address with value stored MAST_CTL Register's Number field (BUS_NO[7:0] Table 116). bits same BUS_NO field, then TYPE access generated. they same, Type configuration access generated. bus-generated address then becomes unsigned addition incoming VMEbus address VMEbus slave image translation offset.
2.4.8.1
Generating Configuration Type Cycles Universe asserts AD[31:11] select device during configuration Type access. perform configuration Type cycle bus, following steps must completed:
Program field VSIx_CTL Configuration Space Program VSIx_BS, VSIx_BD registers some suitable value Program VSIx_TO register Program BUS_NO field MAST_CTL register some value
Perform VMEbus access where: VA[7:2] identifies Register Number will mapped directly AD[7:2] VA[10:8] identifies Function Number will mapped directly AD[10:8]
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VA[15:11] selects device will mapped AD[31:12] according Table VA[23:16] matches BUS_NO MAST_CTL register Other address bits important-they mapped
Table Address Line Asserted Function VA[15:11]
Address Line Assertedb
VA[15:11]a 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100
other values VA[15:11] defined must used.
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Only AD[31:11] asserted; other address lines AD[31:11] negated.
ADOH, MBLT cycles must attempted when image programmed Configuration space.
2.4.8.2 Generating Configuration Type Cycles following steps used generate configuration Type cycle VMEbus:
Program field VSIx_CTL Configuration Space Configuration cycles only generated when field appropriate VSIx_CTRL register programmed either A32, USER1, USER2.
Program VSIx_BS, VSIx_BD registers some suitable value Program VSIx_TO register Program BUS_NO field MAST_CTL register some value
Perform VMEbus access where: VMEbus Address[7:2] identifies Register Number, VMEbus Address[10:8] identifies Function Number, VMEbus Address[15:11] identifies Device Number, VMEbus Address[23:16] does match BUS_NO MAST_CTL register, VMEbus Address[31:24] mapped directly through bus.
VMEbus Configuration
Universe provides following functions assist initial configuration VMEbus system: First Slot Detector Register Access Power-up Auto Slot (two methods)
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2.5.1
First Slot Detector
specified VME64 Specification First Slot Detector module Universe samples BG3IN* immediately after reset determine whether Universe II's host board resides slot VME64 Specification requires that BG[3:0]* lines driven high after reset. This means that card preceded another card VMEbus system, always sample BG3IN* high after reset. BG3IN* only sampled after reset first card system there preceding card drive BG3IN* high. BG3IN* sampled logic immediately after reset (due Universe II's internal pull-down), then Universe II's host board slot Universe becomes SYSCON: otherwise, SYSCON module disabled. This mechanism overridden software through clearing setting SYSCON MISC_CTL register (Table 117). Universe monitors IACK*, instead IACKIN*, when configured SYSCON. This permits operate SYSCON VMEbus chassis slot other than slot provided there only empty slots left. slot with SYSCON becomes virtual slot
2.5.2
VMEbus Register Access Power-up
Universe provides VMEbus slave image that allows access Universe registers. base address slave image programmed through VRAI_BS register (Table 139). power-up, Universe program VRAI_BS VRAI_CTL (Table 139) registers with information specifying Universe Control/Status (UCSR) register slave image (see "Power-Up Options" page 160). Register access power-up used systems where Universe II's card CPU, where register access that card needs independent local CPU.
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Automatic Slot Identification
Universe supports types Auto-ID functionality. type uses Auto Slot technique described VME64 Specification. other type uses proprietary method developed Systems implemented Tundra SCV64 Universe Neither system identifies geographical addressing, only relative position amongst boards present system, example, fourth board versus fourth slot. Both VME64 Auto Slot method automatic slot identification activated through power-up option. Refer "Power-Up Options" page more information. Auto-ID prevents need jumpers uniquely identify cards system. This feature benefits designers following reasons: increase speed system level repairs field reduce possibility incorrect configurations reduce number unique spare cards that must stocked
2.6.1
Auto Slot VME64 Specified
VME64 auto cycle, described VME64 Specification, requires power-up that Auto slave takes following actions: generate IRQ2* negate SYSFAIL*
When Auto slave responds Monarch's IACK cycle, following actions taken: enable accesses CR/CSR space provide Status/ID Monarch indicating interrupt Auto-ID request assert DTACK* release IRQ2*
Universe participates VME64 auto cycle either automatic semi-automatic mode. fully automatic mode, holds SYSFAIL* asserted until SYSRST* negated. When SYSRST* negated, Universe asserts IRQ2* releases SYSFAIL*. semi-automatic mode, Universe still holds SYSFAIL* asserted until SYSRST* negated. However, when SYSRST* negated, local performs diagnostics local logic sets AUTOID MISC_CTL register (Table 117). This asserts IRQ2* releases SYSFAIL*.
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After SYSFAIL* released Universe detects level IACK cycle, responds with STATUS/ID stored STATID register. default value 0xFE. Universe programmed that does release SYSFAIL* until SYSFAIL VCSR_CLR register (Table 162) cleared local logic (SYSFAIL* asserted SYSFAIL VCSR_SET register, Table 162, power-up). Since system Monarch does service Auto-ID slave until after SYSFAIL* negated, clearing SYSFAIL allows Auto-ID process delayed until completes local diagnostics. Once local diagnostics complete, clears SYSFAIL Auto-ID cycle proceeds. Monarch perform CR/CSR reads writes A[23:19]= 0x00 CR/CSR space re-locate Universe II's CR/CSR base address.
2.6.1.1 Universe Auto-ID Monarch power-up Auto-ID Monarch waits IACK cycle until after SYSFAIL* goes high. After IACK cycle performed received Status/ID indicating Auto-ID request, monarch software does following:
masks IRQ2* that will service other interrupters that interrupt level until current Auto-ID cycle completed) performs access 0x00 CR/CSR space information about Auto-ID slave moves CR/CSR base address location unmasks IRQ2* allow service next Auto-ID slave)
Universe supports monarch activity through capability level interrupt handler. other activity must handled through software residing board.
2.6.2
Auto-ID: Proprietary Tundra Method
Universe uses proprietary Auto-ID scheme when enabled through power-up option (see "Auto-ID" page 162). Tundra proprietary Auto-ID function identifies relative position each board system, without using jumpers on-board information. number generated Auto-ID then used determine board's base address. After system reset (assertion SYSRST*), Auto-ID logic responds first level IACK cycle VMEbus.
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After level IACK* signal been asserted (either through IRQ1* with synthesized version), Universe slot counts five clocks from start cycle then asserts IACKOUT* second board system (see Figure other boards continue counting until they receive IACKIN*, then count four more clocks assert IACKOUT* next board. Finally, last board asserts IACKOUT* pauses until data transfer time-out circuit ends cycle asserting BERR*.
Figure Timing Auto-ID Cycle
SYSCLK IACK IACKOUT (CARD IACKOUT (CARD IACKOUT (CARD COUNTER VALUE
Because boards four clocks wide, value clock counter divided four identify slot which board installed; remainder discarded. Note that since start IACK cycle synchronized SYSCLK, count variation from theoretical value board occur. However, cases value board greater than that board lower slot number. result placed DY4AUTOID [7:0] field DY4DONE (both located MISC_STAT register, Table 118).
2.6.3
System Controller Functions
When located Slot VMEbus system (see "First Slot Detector" page 55), Universe assumes role SYSCON sets SYSCON status MISC_CTL register (Table 117). accordance with VME64 Specification, SYSCON Universe provides following functions: system clock driver arbitration module IACK Daisy Chain Driver (DCD) timer
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2.6.3.1
System Clock Driver Universe provides SYSCLK signal derived from CLK64 when configured SYSCON. VMEbus Arbiter When Universe SYSCON, Arbitration Module enabled. Arbitration Module supports following arbitration modes:
2.6.3.2
Fixed Priority Arbitration Mode (PRI) Round Robin Arbitration Mode (RRS) (default setting)
These modes selected with VARB MISC_CTL register (Table 117).
2.6.3.3 Fixed Priority Arbitration Mode (PRI) this mode, order priority VRBR_[3], VRBR_[2], VRBR_[1], VRBR_[0] defined VME64 Specification. Arbitration Module issues Grant (VBGO [3:0]_) highest requesting level.
Request higher priority than current owner asserted, Arbitration Module asserts VBCLR_ until owner releases (VRBBSY_ negated).
2.6.3.4 Round Robin Arbitration Mode (RRS) This mode arbitrates levels round robin mode, scanning from levels Only grant issued level owner never forced from favor another requester (VBCLR_ never asserted).
Since only grant issued level each round robin cycle, several scans required service queue requests level.
2.6.3.5 VMEbus Arbiter Time-out Universe II's VMEbus arbiter programmed time-out requester does assert BBSY* within specified period. This allows BGOUT negated that arbiter continue with other requesters. timer programmed using VARBTO field MISC_CTL register (Table 117), disabled. default setting timer arbitration time-out timer granularity setting timer means timer timeout little
2.6.4
IACK Daisy-Chain Driver Module
IACK Daisy-Chain Driver module enabled when Universe becomes system controller. This module guarantees that IACKIN* stays high least specified rule VME64 specification.
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2.6.5
VMEbus Time-out
programmable timer allows users select VMEbus time-out period. time-out period programmed through VBTO field MISC_CTL register (Table 117) 16µs, 32µs, 64µs, 1024 disabled. default setting timer VMEbus Timer module asserts VXBERR_ VMEbus transaction times (indicated VMEbus data strobes remaining asserted beyond time-out period).
2.6.6
BI-Mode
BI-Mode (Bus Isolation Mode) mechanism logically isolating Universe from VMEbus. This mechanism useful following purposes:
Implementing hot-standby systems system have identically configured boards, BI-Mode. board that BI-Mode fails, BI-Mode while spare board removed from BI-Mode. System diagnostics routine maintenance Fault isolation event card failure faulty board isolated
While BI-Mode, Universe data channels cannot used communicate between VMEbus (Universe mailboxes provide means communication). only traffic permitted Universe registers either through configuration cycles, register image, VMEbus register image, CR/CSR space. IACK cycles generated responded activity occurs. access other images result Target-Retry. Access other VMEbus images ignored. Entering BI-Mode following effects: VMEbus Master Interface becomes inactive Target Channel coupled accesses retried. Target Channel Posted Writes FIFO continues accept transactions eventually fills further posted writes accepted. FIFO eventually empties fills further activity takes place bus. Universe VMEbus Master does service interrupts while BI-Mode.
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Universe does respond VMEbus slave Except accesses register image CR/CSR image. Universe does respond interrupt outstanding. VMEbus outputs from Universe tri-stated, that Universe driving VMEbus signals. only exception this IACK daisy chains which must remain operation before.
There four ways cause Universe enter BI-Mode. Universe into BI-Mode following reasons: BI-Mode power-up option selected (See "Power-Up Options" page Table page 160) when SYSRST* RST_ asserted time after Universe been powered-up BI-Mode when VRIRQ_ asserted, provided that ENGBI MISC_CTL register (Table page 308) been when MISC_CTL register
Either following actions remove Universe from BI-Mode: Power-up Universe with BI-Mode option (see "BI-Mode" page 163), clear MISC_CTL register. This effective only source BI-Mode longer active. VRIRQ_ still being asserted while ENGBI MISC_CTL register set, then attempting clear MISC_CTL register does work.
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Peripheral Component Interconnect (PCI) protocol that defines devices communicate peripheral with host processor. device referred compliant must compliant with Local Specification (Revision 2.1). Universe supports frequencies MHz, 32-bit 64-bit transfers. This chapter describes Universe II's Interface. This chapter discusses following topics: "PCI Cycles" page "Universe Master" page "Universe Target" page
Overview
Universe Interface directly connected bus. information concerning different types accesses available, "PCI Target Images" page
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Cycles
Interface Universe operates compliant port with 64-bit multiplexed address/data bus. Universe Interface configured little-endian using address invariant translation when mapping between VMEbus bus. Address invariant translation preserves byte ordering data structure little-endian memory big-endian memory (see "Endian Mapping" page Specification). Universe signals described Specification) with exception SBO_ SDONE (since Universe does provide cache support). Universe cycles synchronous, meaning that control input signals externally synchronized clock (CLK). cycles divided into four phases: Request Address phase Data transfer Cycle termination
3.2.1
32-Bit Versus 64-Bit
Universe configured with 32-bit 64-bit data power-up (see "PCI Width" page 164). Each Universe II's VMEbus slave images programmed that VMEbus transactions mapped 64-bit data Interface through LD64EN bit, Transfer Control (DCTL) register (see Table page 263). VMEbus slave image programmed with 64-bit data width Universe powered-up 64-bit environment, Universe asserts REQ64_ during address phase transaction. REQ64_ asserted LD64EN 64-bit system independent whether Universe full 64-bit transfer. This result performance degradation because extra clocks required assert REQ64_ sample ACK64_. Also, there some performance degradation when accessing 32-bit targets with LD64EN set. this unless there 64-bit targets slave image window. VMEbus slave images programmed 64-bit wide data bus, then Universe operates transparently 32-bit environment.
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Independent setting LD64EN bit, Universe never attempts 64-bit cycle powered-up 32-bit device.
3.2.2
Request Parking
Universe supports parking. Universe requires asserts REQ_ only GNT_ currently asserted. When Master Module ready begin transaction GNT_ asserted, transfer begins immediately. This eliminates possible clock cycle delay before beginning transaction which would exist Universe implement parking. Refer Specification more information
3.2.3
Address Phase
transactions initiated asserting FRAME_ driving address command information onto bus. VMEbus Slave Channel, Universe calculates address transaction adding translation offset VMEbus address (see "Universe VMEbus Slave" page 43).
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command signals C/BE_ lines) contain information about Memory space, cycle type whether transaction read write. Table shows command type encoding implemented with Universe
Table Command Type Encoding Transfer Type
C/BE_ [3:0] PCI, C/BE_ [7:4] non-multiplexed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Command Type Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate
Universe Capability Target/Master Target/Master Target/Master Target/Master Target/Master Target/Master (See Text) (See Text) (See Text)
Memory Read Multiple Memory Read Line transactions aliased Memory Read transactions when Universe accessed target with these commands. Likewise, Memory Write Invalidate aliased Memory Write. master, Universe generate Memory Read Multiple Memory Read Line.
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targets must assert DEVSEL_ they have decoded access. During Configuration cycle, target selected particular Select (IDSEL). target does respond with DEVSEL_ within clocks, Master-Abort generated. role configuration cycles described Specification.
3.2.4
Data Transfer
Acknowledgment data phase occurs first rising clock edge after both IRDY_ TRDY_ asserted master target, respectively. REQ64_ driven during address phase indicate that master wishes initiate 64-bit transaction. target asserts ACK64_ able respond 64-bit transaction. Wait cycles introduced either master target deasserting IRDY_ TRDY_. write cycles, data valid first rising edge after IRDY_ asserted. Data acknowledged target first rising edge with TRDY_ asserted. read cycles, data transferred acknowledged first rising edge with both IRDY_ TRDY_ asserted. single data transfer cycle repeated every time IRDY_ TRDY_ both asserted. transaction only enters termination phase when FRAME_ deasserted (master-initiated termination) STOP_ asserted (target-initiated). When both FRAME_ IRDY_ deasserted (final data phase complete), defined idle.
3.2.5
Termination Phase
Interface permits following types terminations: Master-Abort: master negates FRAME_ when target responds (DEVSEL_ asserted) after clock cycles. Target-Disconnect: termination requested target (STOP_ asserted) because unable respond within latency requirements specification requires address phase. Target-Disconnect with data: means that transaction terminated after data transferred. Universe deasserts REQ_ least clock cycles receives STOP_ from target. Target-Disconnect without data: means that transaction terminated before data transferred. Universe deasserts REQ_ least clock cycles receives STOP_ from target.
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Target-Retry: termination requested (STOP_ asserted) target because cannot currently process transaction. Retry means that transaction terminated after address phase without data transfer. Target-Abort: modified version target-disconnect where target requests termination (asserts STOP_) transaction which will never able respond during which fatal error occurred. Although there fatal error initiating application, transaction completes gracefully, ensuring normal operation other resources.
3.2.6
Parity Checking
Universe both monitors generates parity information using signal. Universe monitors when accepts data master during read target during write. Universe drives when provides data target during read master during write. Universe also drives during address phase transaction when master monitors during address phase when target. both address data phases, signal provides even parity C/BE_[3:0] AD[31:0]. Universe continues with transaction independent parity error reported during transaction. Universe also programmed report address parity errors. does this asserting SERR_ signal setting status registers. interrupt generated, regardless whether assertion SERR_ enabled, Universe does respond errored access. When Universe powered-up 64-bit environment, uses PAR64 same PAR, except AD[63:32] C/BE[7:4]. Universe reports parity errors during transactions with PERR_ signal. Universe drives PERR_ high within clocks receiving parity error incoming data, holds PERR_ least clock each errored data phase.
Universe Master
Universe requests mastership through Master Interface. Master Interface available either VMEbus Slave Channel (access from remote VMEbus master) Channel. VMEbus Slave Channel makes internal request Master Interface when following conditions met: RXFIFO contains complete transaction,
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sufficient data exists RXFIFO generate transaction length defined programmable aligned burst size (PABS) there coupled cycle request
Channel makes internal request Master Interface when following conditions met: DMAFIFO room bytes read from DMAFIFO queued bytes written block completely queued during write
Arbitration between channels Master Interface follows round robin protocol. Each channel given access single transaction. Once that transaction completes, ownership Master Interface granted other channel requires bus. VMEbus Slave Channel Channel each have rules that determine when transaction complete channels longer need Master Interface. VMEbus Slave Channel done under following conditions: entire transaction greater length than programmed aligned burst size) emptied from RXFIFO coupled cycle complete
Channel finished with Master Interface when following conditions met: boundary programmed into aligned burst size emptied from DMAFIFO during writes boundary programmed into aligned burst size queued DMAFIFO during reads from
Access from VMEbus either coupled decoupled. full description operation these data paths, "Universe VMEbus Slave" page
3.3.1
Command Types
Master Interface generate following command types: Read Write Memory Read Memory Read Multiple Memory Write
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Configuration Read (Type Configuration Write (Type
type cycle Universe generates depends which VMEbus slave image accessed programmed. example, slave image might programmed space, another Memory space another Configuration space (see "VME Slave Image Programming" page 84). When generating memory transaction, addressing either 32-bit 64-bit aligned, depending upon target. When generating transaction, addressing 32-bit aligned incoming transactions coupled.
3.3.2
Burst Transfers
Universe generates aligned burst transfers some maximum alignment, according programmed aligned burst size (PABS field MAST_CTL register, Table 116). aligned burst size programmed bytes. Burst transfers cross programmed boundaries. example, when programmed 32-byte boundaries, burst begins XXXX_XX20, XXXX_XX40, etc. necessary, burst begins address with programmed alignment. optimize usage, Universe always attempts transfer data aligned bursts full width bus. Universe perform 64-bit data transfer over [63:0] lines, operated 64-bit environment against 64-bit capable target master. LD64EN must access being made through VMEbus slave image; LD64EN must access being performed with DMA. Universe generates burst cycles performing following tasks: when RXFIFO emptying, TXFE MISC_STAT register clear filling RDFIFO receives block read request from VMEbus master appropriately programmed VMEbus slave image performing transfers
other accesses treated single data beat transactions bus. During burst transactions, Universe dynamically enables byte lanes changing signals during each data phase.
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3.3.3
Termination
Universe performs Master-Abort target does respond within clock cycles. Coupled transactions terminated with Target-Abort Master-Abort terminated VMEbus with BERR*. R_TA R_MA bits PCI_CS register (Table when Universe receives Target-Abort generates Master-Abort independent whether transaction coupled, decoupled, prefetched, initiated DMA. Universe receives retry from target, then relinquishes re-requests within three clock cycles. other transactions processed Master Interface until retry condition cleared. Universe programmed perform maximum number retries using MAXRTRY field MAST_CTL register (Table 116). When this number retries been reached, Universe responds same does Target-Abort bus. Universe issue BERR* signal VMEbus. VMEbus slave coupled transactions decoupled transactions encounter delayed DTACK once FIFO fills until condition clears either success retry time-out. error occurs during posted write (see also "Error Handling" page 147), Universe uses L_CMDERR register (Table command information transaction (CMDERR [3:0]) address errored transaction latched LAERR register (Table 68). L_CMDERR register also records multiple errors occur (with M_ERR bit) although number errors given. error qualified with L_STAT bit. rest transaction purged from RXFIFO some portion write encounters error. interrupt generated VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Interrupt Generation Handling" page 129). error occurs bus, Universe does translate error condition into BERR* VMEbus; Universe does directly error. taking action, Universe forces external VMEbus error timer expire.
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3.3.4
Parity
Universe monitors when accepts data master during read drives when provides data master during write. Universe also drives during address phase transaction when master. both address data phases, signal provides even parity C/BE_[3:0] AD[31:0]. When Universe powered-up 64-bit environment, uses PAR64 same PAR, except AD[63:32] C/BE[7:4]. PERESP PCI_CS register (Table determines whether Universe responds parity errors master. Data parity errors reported through assertion PERR_ PERESP set. Regardless setting these bits, D_PE (Detected Parity Error) PCI_CS register Universe encounters parity error master. DP_D (Data Parity Detected) same register only parity checking enabled through PERESP Universe detects parity error while master (i.e. asserts PERR_ during read transaction receives PERR_ during write). interrupts generated Universe response parity errors reported during transaction. Parity errors reported Universe through assertion PERR_ setting appropriate bits PCI_CS register. PERR_ asserted Universe while master, only action takes DP_D. Universe continues with transaction independent parity errors reported during transaction. master, Universe does monitor SERR_. expected that central resource monitors SERR_ take appropriate action.
Universe Target
Universe becomes target when nine programmed target images, registers, accessed master. Universe cannot access images registers master bus. Refer "Registers" page more information register accesses. When target images accessed, Universe responds with DEVSEL_ within clocks FRAME_. This makes Universe medium speed device, reflected DEVSEL field PCI_CS register).
3.4.1
Command Types
target, Universe responds following command types: Read
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Write Memory Read Memory Write Configuration Read (Type Configuration Write (Type Memory Read Multiple (aliased Memory Read) Memory Line Read (aliased Memory Read) Memory Write Invalidate (aliased Memory Write)
Type Configuration accesses only made Universe II's configuration registers. target images accept Type accesses. Address parity errors reported both PERESP SERR_EN PCI_CS register (Table 38). Address parity errors reported Universe asserting SERR_ signal setting S_SERR (Signalled SERR_) PCI_CS register. Assertion SERR_ disabled clearing SERR_EN PCI_CS register. interrupt generated, regardless whether assertion SERR_ enabled not, Universe does respond access with DEVSEL_. Typically, master transaction times with Master-Abort. Universe accessed with REQ64_ Memory space 64-bit target, then responds with ACK64_ powered 64-bit device.
3.4.2
Data Transfer
Read transactions always coupled, opposed VMEbus slave reads which pre-fetched (see "Universe VMEbus Slave" page 43). Write transactions coupled posted (see Figure "PCI Target Images" page 87). ensure sequential consistency, coupled operations (reads writes) only processed once previously posted write operations have completed (the TXFIFO empty).
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Figure Target Channel Dataflow
POSTED WRITE DATA TXFIFO
SLAVE INTERFACE
COUPLED READ DATA
COUPLED WRITE DATA
VMEbus MASTER INTERFACE
VMEbus have different data width capabilities. maximum VMEbus data width programmed into target image through Target Image Control register (Table page 213). example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled will broken into 16-bit cycles VMEbus. target image also programmed with block transfers enabled, 32-bit data beat will result block transfer VMEbus. Write data unpacked VMEbus read data packed data width. data width data beat same maximum data width target image, then Universe maps data beat equivalent VMEbus cycle. example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled translated single 32-bit cycle VMEbus. data width less than VMEbus data width then there packing unpacking between buses. only exception this during 32-bit multi-data beat transactions target image programmed with maximum VMEbus data width bits. this case, packing/unpacking occurs make maximum full bandwidth both buses. Only aligned VMEbus transactions generated, requested data beat unaligned non-contiguous byte enables, then broken into multiple aligned VMEbus transactions wider than programmed VMEbus data width. example, consider three-byte data beat 32-bit bus) accessing target image with 16-bit. three-byte data beat will broken into three aligned VMEbus cycles: three single-byte cycles. above example target image 8-bit, then three-byte data beat will broken into three single-byte VMEbus cycles.
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3.4.3
Coupled Transfers
Target Channel supports coupled transfers. coupled transfer through Target Channel transfer between where Universe maintains ownership VMEbus from beginning transfer bus, where termination cycle VMEbus relayed directly master normal manner (Target-Abort Target Completion), rather than through error-logging interrupts. default, target images coupled transfers. Coupled transfers typically cause Universe through three phases: Coupled Data-Transfer Phase, then Coupled Wait Phase. When external Master attempts data transfer through slave image programmed coupled cycles, Universe currently owns VMEbus, Target Channel moves directly Coupled Data-Transfer Phase
3.4.3.1
Coupled Data-Transfer Phase beginning Coupled Data-Transfer Phase, Universe latches command, byte enable, address case write) data. Regardless state FRAME_, Universe retries1 master, then performs transaction VMEbus. Universe continues signal Target-Retry external master until transfer completes VMEbus.
transfer completes normally VMEbus then, case read, data transmitted master. data phase coupled transfer requires packing unpacking VMEbus, acknowledgment transfer given master until data been packed unpacked VMEbus. Successful termination signalled bus-the data beat acknowledged with Target-Disconnect, forcing multi-beat transfers into single beat. this point, Universe enters Coupled Wait Phase. error signalled VMEbus error occurs during packing unpacking, then transaction terminated with Target-Abort. more information refer "Data Transfer" page
latency requirements described revision Specification) require that only clock cycles elapse between first second data beat transaction. Since Universe cannot guarantee that data acknowledgment will received from VMEbus time meet these latency requirements, Universe performs target-disconnect after first data beat every coupled write transaction.
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3.4.3.2
Coupled Wait Phase Coupled Wait Phase entered after successful completion Coupled Data-Transfer phase. Coupled Wait Phase allows consecutive coupled transactions occur without releasing VMEbus. coupled transaction attempted while Universe Coupled Wait Phase, Universe moves directly Coupled Data-Transfer Phase.
Coupled Window Timer determines maximum duration Coupled Wait Phase. When Universe enters Coupled Wait Phase, Coupled Window Timer starts. period this timer specified clocks programmable through field LMISC register (Table 65). this field programmed 0000, Universe does early release BBSY* during coupled transfer VMEbus will enter Coupled Wait Phase. this case, VMEbus ownership relinquished immediately Target Channel after each coupled cycle. Once timer associated with Coupled Wait Phase expires, Universe releases VMEbus release mode RWD, release mode there pending (external) request VMEbus.
3.4.4
Posted Writes
Posted writes enabled target image setting PWEN control register target image (see "PCI Target Images" page setting Write transactions relayed from VMEbus through 64-entry deep TXFIFO. TXFIFO allows each entry contain address bits (with extra bits provided command information), full 64-bit width. each posted write transaction received from bus, Target Interface queues address entry FIFO. This entry contains translated address space mapped VMEbus attributes information relevant particular target image that been accessed (see "PCI Target Images" page 87). this reason, reprogramming target image attributes will only reflected TXFIFO entries queued after reprogramming. Transactions queued before re-programming delivered VMEbus with target image attributes that were before reprogramming. Care must taken before reprogramming target images. ensure FIFO empty there following possible options: Perform coupled read. coupled read does complete until posted-write data been queued Read MISC_STAT register until TXFE value
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3.4.4.1
FIFO Entries Once address phase queued TXFIFO entry, Target Interface pack subsequent data beats full 64-bit width before queuing data into entries TXFIFO.
32-bit transfers Universe TXFIFO accepts single burst address phase data phases when empty. 64-bit PCI, TXFIFO accepts single burst address phase data phases when empty. improve utilization, TXFIFO does accept address phase does have room burst address phase bytes data. TXFIFO does have enough space aligned burst, then posted write transaction terminated with Target-Retry immediately after address phase. When external Master posts writes Target Channel Universe Universe issues disconnect address crosses 256-byte boundary. Before transaction delivered VMEbus from TXFIFO, Target Channel must obtain ownership VMEbus Master Interface. Ownership VMEbus Master Interface granted different channels round robin basis (see "VMEbus Release" page 37). Once Target Channel obtains VMEbus through VMEbus Master Interface, manner which TXFIFO entries delivered depends programming VMEbus attributes target image (see "PCI Target Images" page 87). example, VMEbus data width programmed 16-bit, block transfers disabled, then each data entry TXFIFO corresponds four transactions VMEbus. block transfers enabled target image, then each transaction queued TXFIFO, independent length, delivered VMEbus block transfer. This means that single data beat transaction queued TXFIFO, appears VMEbus single data phase block transfer. master attempting coupled transactions retried while TXFIFO contains data. posted writes continually written Target Channel another master, FIFO does empty, coupled transactions requested first master Target Channel does proceed continually retried. This presents potential starvation scenario. This functionality intended support earlier versions PCI-to-PCI bridges.
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3.4.5
Special Cycle Generator
Special Cycle Generator Target Channel Universe used conjunction with Target Images generate Read-Modify-Write (RMW) Address Only With Handshake (ADOH) cycles. address programmed into SCYC_ADDR register (Table 61), address space specified field SCYC_CTL register (Memory I/O), must appear during address phase transfer Special Cycle Generator perform function. Whenever this address (bits [31:2]) used matches address SCYC_ADDR register, Universe does respond with ACK64_ (since Special Cycle Generator only processes 32-bit cycles). cycle that produced VMEbus uses attributes programmed into Image Control Register image that contains address programmed SCYC_ADDR register. Special Cycle Generator configured through register fields shown Table
Table Register Fields Special Cycle Generator
Field 32-bit address Address Space Special cycle 32-bit enable Register Bits ADDR Table Table Description Specifies target image address Specifies whether address specified ADDR field lies memory space Disabled, ADOH mask select bits modified VMEbus read data during cycle Data which compared VMEbus read data during cycle Data which swapped with VMEbus read data written original address during cycle
SCYC[1:0] Table [31:0] Table
32-bit compare
[31:0] Table
32-bit swap
[31:0] Table
following sections describe specific properties each transfer types: ADOH.
Universe VME-to-PCI Bridge Manual
80A3010_MA001_03
Interface
3.4.5.1
Read-Modify-Write When SCYC field RMW, read access specified address (SCYC_ADDR register) results cycle VMEbus (provided constraints listed below satisfied). cycles VMEbus consist single read followed single write operation. data from read portion VMEbus returned read data bus.
cycles make three 32-bit registers (see Table enable field mask which lets user specify which bits read data compared modified cycle. This enable setting completely independent cycle data width, which determined data width initiating transaction. During RMW, VMEbus read data bitwise compared with SCYC_CMP SCYC_EN registers. valid compared enabled bits then swapped using SCYC_SWP register. Each enabled that compares equal swapped with corresponding 32-bit swap field. false comparison results original being written back. Once cycle completes, VMEbus read data returned waiting master cycle terminates.
Constraints Certain restrictions apply cycles. write transaction initiated VMEbus address when special cycle field (SCYC Table RMW, then standard write occurs with attributes programmed target image other words, special cycle generator used). Universe performs packing unpacking data VMEbus during operation. following constraints must also met.
Special Cycle Generator only generates accessed with 8-bit, aligned 16-bit, aligned 32-bit read cycle. Special Cycle Generator only generates size request less than equal programmed VMEbus Maximum Data width. destination VMEbus address space mu
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