Preliminary Data Sheet 06.99 24911 Revision History: Previous Ver
|
|
|
Top Searches for this datasheet
Quad ISDN 2B1Q Echocanceller Digital Front DFE-Q V2.1 24911 Version
Preliminary Data Sheet 06.99
24911 Revision History: Previous Version: Page previous Version) Page current Version) Subjects (major changes since last revision) Current Version: 06.99
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
ABM®, AOP® ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC® -LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S ISAC®-P ITAC®, MUSAC® OCTAT®-P, QUAT®-S, SICAT® SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI® registered trademarks Infineon Technologies ASMTM, POTSWIRE QuadFALCTM, SCOUTare trademarks Infineon Technologies Edition 06.99 Published Infineon Technologies Gr., 81541 Infineon Technologies i.Gr. 1999. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Infineon Technologies only used life-support devices systems2 with express written approval Infineon Technologies critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
24911
Preface
This document describes interfaces, functions behavior QUAD ISDN 2B1Q Echocanceller Digital Front (DFE-Q V2.1). 24911 digital part two-chip solution featuring four times ISDN basic rate access 144kbit/s. DFE-Q V2.1 supersedes existing versions, DFE-Q V1.1, V1.2 V1.3. corresponding Analog Front End, V2.1 (PEF 24902) described detail Data Sheet V1.1, Delta Sheet V1.2 Delta Sheet V2.1. Organization this Document This Preliminary Data Sheet divided into chapters. organized follows: Chapter Introduction Gives general description product family, lists features, presents some typical applications. Chapter Description Lists locations with associated signals, categorizes signals according function, describes signals. Chapter Functional Description Gives functional overview device, shows block diagram, specifies various interfaces describes provided U-transceiver functions. Chapter Operational Description Describes reset power-down behavior, illustrates activation deactivation procedures, shows device tested maintenance data retrieved. Chapter Monitor Commands Lists available Monitor Commands that applied. Chapter Register Description Lists register functions that addressable MON-12 protocol which behaves like serial microprocessor interface. Chapter Electrical Characteristics Denotes operating conditions gives exact interface timing. Chapter Package Outlines Chapter Appendix Standards Specifications
Preliminary Data Sheet
06.99
24911
Chapter Glossary Chapter Index
Related Documentation DFE-Q V2.1 Delta Sheet 05.98 V1.1 Data Sheet 05.96 V1.2 Delta Sheet 06.97 V2.1 Delta Sheet 09.98
Your Comments welcome your comments this document continuously aiming improving documentation. Please send your remarks suggestions e-mail sc.docu_comments@infineon.com Please provide subject your e-mail: device name (DFE-Q V2.1), device number (PEF 24911), device version (Version 2.1), body your e-mail: document type (Preliminary Data Sheet), issue date (06.99) document revision number
Preliminary Data Sheet
06.99
24911
Table Contents 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.9.1 3.9.2 3.9.3 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.17.1 3.17.2 3.17.3
Page
Introduction Features Logic Symbol System Integration Operational Overview Descriptions Diagram Definitions Functions Pinning Changes from DFE-Q V1.3 DFE-Q V2.1 Functional Description Functional Overview Block Diagram IOM®-2 Interface IOM®-2 Interface Frame Structure Superframe Marker Function IOM®-2 Command/ Indicate Channel IOM®-2 Monitor Channel MON-12 Protocol 3-12 Interface Analog Front 3-14 General Purpose I/Os 3-17 Clock Generation 3-18 U-Transceiver Functions 3-19 2B1Q Frame Structure 3-19 Maintenance Channel 3-21 Reporting State Machine 3-26 Control Mechanisms 3-27 Start Maintenance Evaluation 3-29 Embedded Operations Channel (EOC) 3-29 Processor 3-31 Cyclic Redundancy Check 3-33 Scrambling/ Descrambling 3-35 Encoding/ Decoding (2B1Q) 3-36 Codes (2B1Q) 3-37 State Machine Notation 3-39 Mode State Diagram 3-41 Inputs U-Transceiver LT-Mode 3-42 Outputs U-Transceiver LT-Mode 3-46 LT-States 3-48 Operational Description Reset Power Down
06.99
Preliminary Data Sheet
24911
Table Contents 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.1.4 4.4.1.5 4.4.2 4.4.3 4.4.3.1 4.4.3.2 4.4.4 4.4.4.1 4.4.4.2 4.4.4.3 4.4.4.4 4.4.4.5 4.4.4.6 4.4.4.7 4.4.4.8 4.4.4.9 4.4.5 4.4.5.1 4.4.6 4.6.1 4.6.2 4.6.3 4.6.4
Page
Layer Activation/ Deactivation Procedures Complete Activation Initiated Activation with ACT-Bit Status Ignored Exchange Side Complete Activation Initiated Complete Deactivation 4-11 Partial Activation Only) 4-13 Activation Initiated with Active 4-15 Activation Initiated with Active 4-17 Deactivating S/T-Interface Only 4-20 Maintenance Test Functions 4-22 Test Loopbacks 4-22 Analog Loopback (No.1) 4-23 Loopback No.2 Overview 4-24 Loopback No.2 Complete Loopback 4-25 Loopback No.2 Single Channel Loopbacks 4-27 Local Loopbacks Featured Register LOOP 4-28 Error Rate Counter 4-30 Block Error Counters 4-30 Near-End Far-End Block Error Counter 4-30 Testing Block Error Counters 4-33 System Measurements 4-35 Single-Pulses Test Mode (SSP) 4-35 Data Through Mode (DT) 4-35 Master Reset Mode 4-35 Pulse Mask Measurement 4-36 Power Spectral-Density Measurement 4-36 Total Power Measurement 4-36 Return-Loss Measurement 4-36 Quiet Mode Measurement 4-37 Insertion Loss Measurement 4-37 Retrieving Data 4-38 Reading Coefficient Values 4-40 Boundary Scan 4-42 D-Channel Arbitration 4-47 Operation RITL/WLL Systems 4-48 Alignment Synchronization U-Superframes 4-48 Propagation Delay Measurement 4-49 Measurement Data Interpretation 4-50 Synchronization Base Stations 4-52 Monitor Commands MON-0 Exchanging Information MON-2 Exchanging Overhead Bits
06.99
Preliminary Data Sheet
24911
Table Contents 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 7.4.1 7.4.2 7.4.3 7.4.4 7.6.1 7.6.2
Page
MON-8 Local Functions Register Description Register Summary Reset U-Transceiver Functions State 'Deactivated' Mode Register Evaluation Timing Detailed Register Description LP_SEL Line Port Selection Register OPMODE Operation Mode Register MFILT M-Bit Filter Options EOC_CR Control Register 6-12 M4RMASK Read Mask Register 6-13 M4WMASK Write Mask Register 6-15 TEST Test Register 6-17 LOOP Loop Back Register 6-19 FEBE Block Error Counter Register 6-21 NEBE Near Block Error Counter Register 6-21 BERC Error Rate Counter Register 6-22 Propagation Delay Register 6-22 Phase Information Register 6-23 Registers 6-24 Electrical Characteristics Absolute Maximum Ratings Operating Range Characteristics Characteristics Reset Timing IOM®-2 Interface Timing Interface Analog Front Boundary Scan Timing Capacitances Power Supply Supply Voltage Power Consumption Package Outlines Appendix Standards Specifications Glossary 10-1 Index 11-1
Preliminary Data Sheet
06.99
24911
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 4-10 Figure 4-11 Figure 4-12
Page
DFE-Q/ Generation Chip Logic Symbol 16-Line Card Application with DELPHI Solution 16-Line Card Application with ELIC®/ IDEC® Solution Connecting AFE/DFE-Q Chip Sets Recommended Clocking Scheme More Than DFE-Q/AFE Chip Sets Configuration used) Data Flow Diagram (DFE-Q V2.1 AFE) DFE-Q V2.1 Block Diagram Clock Supply Data Exchange between Master Slave Multiplexed Frame Structure IOM®-2 Interface Superframe Marker Handshake Protocol with 2-Byte Monitor Message/Response Abortion Monitor Channel Transmission 3-10 Monitor Access with Enabled 3-11 Interface Analog Front 3-14 Frame Structure SDX/SDR 3-15 U-Superframe Structure. 3-19 U-Basic Frame Structure 3-19 MON-0/2 M-Bit Correspondence 3-22 Maintenance Channel Filtering Options. 3-25 Report Timing 3-26 Control Transmit Direction 3-28 Control Receive Direction 3-28 EOC-Procedure Auto- Transparent Mode. 3-32 CRC-Process 3-34 Scrambler/ Descrambler Algorithms 3-35 Explanation State Diagram 3-39 State Transition Diagram LT-Mode 3-41 Complete Activation Initiated Activation with ACT-Bit Status Ignored Exchange Complete Activation Initiated Complete Deactivation. 4-11 Only Activation 4-14 Initiated Activation with U-Interface Active 4-15 TE-Activation with Active Exchange Control (case 4-17 TE-Activation with Active Exchange Control (case 4-19 Deactivation Only 4-20 Test Loopbacks 4-22 Complete Loopback Options 4-25 Loopbacks Featured Register LOOP 4-29
06.99
Preliminary Data Sheet
24911
Figure 4-13 Figure 4-14 Figure 4-15 Figure 4-16 Figure 4-17 Figure 4-18 Figure 4-19 Figure 4-20 Figure 4-21 Figure 4-22 Figure Figure Figure Figure Figure Figure
Block Error Counter Test 4-34 Total Power Measurement Set-Up 4-36 Data Transfer Synchronization Handshake Signals 4-38 Provided Registers Access Coefficient Data 4-40 Passing D-channel arbitration Terminal EOC-Channel 4-47 U-Frame Alignment/Synchronization RITL/WLL Mode 4-48 Measurement Principle 4-49 Sources Measurement Tolerances 4-51 Transmission Synchronizing Pattern Channel 4-53 IOM®-2 Terminal Mode 4-53 DFE-Q V2.1 Register Input/Output Waveform Tests. Reset Timing IOM®-2 Interface Timing Dynamic Input Output Requirements Analog Interface. Boundary Scan Timing
Preliminary Data Sheet
06.99
24911
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
Operating Modes Definitions Functions Pinning Changes IOM®-2 Data Rates Assignments IOM® Channels Time-Slots SDX/SDR Line Ports 3-15 2B1Q Coding Table 3-16 2B1Q U-Frame Structure 3-20 Supported EOC-Commands 3-30 2B1Q Coding Table 3-36 Command Indicate Codes (2B1Q). 3-37 Timers Used LT-Modes 3-45 U-Interface Signals Boundary Scan Cells. 4-42 Controller Instructions: 4-44 MON-0 Functions. MON-2 Overhead Bits MON-8-Local Function Commands Register Reference Table IOM®-2 Dynamic Input Characteristics IOM®-2 Dynamic Output Characteristics Dynamic Input Characteristics Dynamic Output Characteristics Boundary Scan Dynamic Timing Requirements Power Consumption.
Preliminary Data Sheet
06.99
24911
Introduction
Introduction
Quad ISDN 2B1Q Echocanceller Digital Front (DFE-Q) digital part optimized two-chip solution featuring ISDN basic rate access 144kbit/s. 24911 designed provide conjunction with Quad ISDN Echocanceller Analog Front (PEF 24902 V2.1) full duplex data transmission U-reference point according ANSI T1.601 (1992), ETSI (1998) ITU-T G.961 standards. DFE-Q generation been completely reengineered guarantee availability well proved DFE-Q/AFE solution over year 2000. 24911 V2.1 downwards compatible functionally equivalent DFE-Q V1.x. Thus, line card manufacturers make most advanced process technology without need change their current design (besides changeover 3.3V power supply). software changes required DFE-Q V2.1 deployed existing DFE-Q V1.x solutions. Some features provided such free programmable filteing options maintenance bits (M1-6) enhanced monitoring test functions. data rate programmable from 1Mbit/s 4Mbit/s.
15.36MHz
+\EULG +\EULG
+\EULG +\EULG
chipset.vsd
Figure
DFE-Q/ Generation Chip
output input pins throughout compatible although 24911 processed advanced 3.3V CMOS technology. power down state with very power consumption featured. 24911 comes P-MQFP-64 package.
Preliminary Data Sheet
06.99
Quad ISDN 2B1Q Echocanceller Digital Front DFE-Q V2.1
24911
Version
CMOS
Features
U-Interface Digital part two-chip solution featuring full duplex data transmission reception over twowire metallic subscriber loops providing ISDN basic rate access kbit/s Conforms P-MQFP-64 ANSI T1.601-1992 ETSI (1998) Recommendation ITU-T G.961 2B1Q-block code binary, quaternary) 80-kHz symbol rate mode Data rate clock master/slave configuration system interface independently programmable from selected operating mode (LT/NT) Activation/ deactivation controller start-up guard timer (T1) disabled repeater applications Adaptive echo cancellation equalization Automatic gain control polarity adaptation Clock recovery (frame synchronization) applications Built-in wake-up unit activation from power-down state. System Interface IOM®-2 interface with programmable data rates Mbit/s Mbit/s) controlled ports relay driver power feeder control relay driver pins port status pins port
Type 24911
Preliminary Data Sheet
Package P-MQFP-64
06.99
24911
Introduction Others Software compatible 24911 V1.2 (Quad DFE-Q) Inputs outputs compatible DOUT (open drain) accepts pull-up 3.3V +3.3V ±0.3V Power Supply Sophisticated power management restricted power mode Advanced power CMOS technology Extended temperature range 40.to 85°C) available Boundary-Scan, JTAG IEEE 1149.1
Add-On Features Differences with Respect DFE-Q V1.3/V1.2/V1.1 Max. IOM®-2 data rate 4Mbit/s (DCL= 8MHz) +3.3V instead power supply Dedicated pins test modes DOUT configurable either open drain push-pull (tristate) output Monitor Time-Out (MTO) procedure MON-12 class features internal register access Coefficients retrievable MON-12 commands instead MON-8 commands Information RANGE receiver phase requested MON-12 instead MON-8 'AST' introduced V1.3 Advanced filter options MON-0 MON-2 messages Error Rate measurement port Additional digital local loops codes 'LTD' 'HI' more supported Optimized LT-state machine JTAG Boundary-Scan with dedicated reset line TRST (replaces power-on reset functionality)
Addressed Applications ISDN Line Cards Central Office ISDN Line Cards Access Networks ISDN Line Cards Systems Suited applications Constant delay Propagation delay measurement transmission line Means synchronization Base Stations
Preliminary Data Sheet
06.99
24911
Introduction
Logic Symbol
USTU
9PVU
TGPU TGPU
')(4
T`I8
8GT! 8GT"
8S8PI
96S7
6VUP
logsym.vsd
Figure
Logic Symbol
06.99
Preliminary Data Sheet
24911
Introduction
System Integration
This paragraph shows DFE-Q V2.1 integrated systems using other Infineon ISDN devices. 24911 DFE-Q optimized following applications: Digital Line Cards Central Office Digital Line Cards Access Networks mode only) applications mode only) Figure Figure illustrate line card solutions with various Infineon line card controllers. DELPHI (PEB 20570) supersedes ELIC® (PEB 20550) will feature HDLC controllers on-chip.
')(4
DPH!
'(/3+,/&
Tvthyyvt
4,+3&
appl_delphi.vsd
Figure
16-Line Card Application with DELPHI Solution
Preliminary Data Sheet
06.99
24911
Introduction
Cvtuh
(/,&
')(4
Tvthyyvt
,'(&
4,+3&
appl_elic.vsd
Figure
16-Line Card Application with ELIC®/ IDEC® Solution
Figure shows channel line card application realized AFE/ DFE-Q chip sets: AFE-PLL generates synchronized 15.36MHz clock provides master clock CL15 other devices. internal first synchronizes 15.36 master clock onto reference clock either 2048 kHz. Infineon recommends feed clock input DFE-Q V2.1 reference clock input (pin CLOCK) from same clock source. second deactivated. 15.36 master clock applied CL15. CL15 configured input clamped either VSS. XOUT left open CLOCK shall tied GND.
Preliminary Data Sheet
06.99
24911
Introduction
15.36MHz
2048kHz Reference Cock
+\EULG +\EULG
;287
&/2&.
'287
+\EULG +\EULG
0%LWV
+\EULG +\EULG
+\EULG +\EULG
;287
&/2&.
clkchain1.vsd
Figure
Connecting AFE/DFE-Q Chip Sets
DFE-Q devices supplied first CL15 with synchronized 15.36MHz clock. IOM®-2 channels DFE-Q devices assigned programmed slot pins. Starting from channel 0/4/8/12 always four subsequent channels occupied. Alternatively clocking scheme shown Figure applied more than devices clocked (e.g. 16-channel line card application). Instead supply with master clock CL15, here 15.36MHz master clock input XIN. Thereby CL15 configured output passes 15.36MHz clock attached DFE-Q. clock chain extended same another AFE/DFE-Q chip sets 16-channel line card application realized with just single crystal. Note that 15.36MHz clock inverted once input output CL15. This duty cycle recovered again.
Preliminary Data Sheet
06.99
24911
Introduction
15.36MHz
2048kHz Reference Cock
+\EULG +\EULG
;287
&/2&.
'287
+\EULG +\EULG
0%LWV
+\EULG +\EULG
;287
&/2&.
+\EULG +\EULG
+\EULG +\EULG
;287
&/2&.
+\EULG +\EULG
clkchain2.vsd
Figure
Recommended Clocking Scheme More Than DFE-Q/AFE Chip Sets
Preliminary Data Sheet
06.99
24911
Introduction
Operational Overview
DFE-Q V2.1 operates always mode. operating modes known from former versions DFE-Q further supported activated setting given Table 1-1. cross reference corresponding pins V1.x additional denoted.
Table
Operating Modes
T`I8
96S7
mode without WLL/RITL synchronization D-channel arbitration disabled mode without WLL/RITL synchronization, D-channel arbitration enabled LT-PBX-mode with WLL/RITL synchronization, D-channel arbitration disabled
periodic signal*) periodic signal*)
periodic signal*)
periodic LT-PBX-mode with WLL/RITL signal*) synchronization, D-channel arbitration enabled
must multiples 12ms
System Interface Configurations following parameters system interface configurable: Open Drain/ Push-Pull Mode Configured open drain output DOUT floating pull-up resistor required. push-pull mode output high impedance outside active time slots. IOM®-2 Channel Assignment IOM®-2 channels always assigned blocks four.
SLOT1
SLOT0
Assigned IOM®-2 Channels
Preliminary Data Sheet
06.99
24911
Introduction
IOM®-2 Data Rates
Frequency [kHz] 2048 3072 4096 6144 8192
Data Rate [kBit/s] 1024 1536 2048 3072 4096
IOM®-2 Channels
Preliminary Data Sheet
1-10
06.99
24911
Introduction Send Single Pulses Test Mode test mode 'Send Single Pulses' +/-3 pulses spaced 1.5ms transmitted lines. test mode activated SSP= '1'. test function well stimulated C/I= besides fact that selection impacts line ports while selection impacts only chosen line. Data Through Mode test mode 'Data Through' U-transceiver forced enter 'Transparent' state issue independently wake-up protocol. test mode activated '1'. test function well stimulated C/I= besides fact that selection impacts line ports while selection impacts only chosen line.
Preliminary Data Sheet
1-11
06.99
24911
Descriptions
Descriptions
Diagram
(top view)
&5&21 6<1& 6/27 '$5% $872 7567
304)3
pinning.vsd
Figure
Configuration used)
06.99
Preliminary Data Sheet
24911
Descriptions
Definitions Functions
Definitions Functions Symbol Input Output Function
Table
IOM®-2 Interface Frame Synchronization Clock (8kHz) start first B1-channel time-slot marked, expected least periods. Data Clock clock rate ranges from 2048 8192kHz (1024 4096kBit/s) Data input IOM®-2 data synchronous clock Data output IOM®-2 data synchronous clock
DOUT
(OD/ PuP)
Mode Selection Pins Reset triggers asynchronous reset, Schmitt trigger input '1'= inactive '0'= active IOM®-2 Channel Slot Selection assigns IOM®-2 channels blocks SLOT1, '00'= IOM®-2 channels '01'= IOM®-2 channels '10'= IOM®-2 channels '11'= IOM®-2 channels SLOT1 (PD) IOM®-2 Channel Slot Selection assigns IOM®-2 channels blocks
SLOT0
Preliminary Data Sheet
06.99
24911
Descriptions Table Definitions Functions Symbol Input Output (PD) Function Monitor Channel Time-Out activated Monitor channel reset every '1'= enables time-out '0'= disables time-out Push Pull Mode push pull mode actively driven during occupied time slot, outside active time slots DOUT high impedance (tristate) '1'= configures DOUT push/pull output '0'= configures DOUT open drain output CRCON (PD) Check On/Off defines condition which MON-2 messages will passed setting effect ports '1'= Check MON-2 messages issued while violations U-interface were detected (MFILT= 0001 0xxx) '0'= Check MON-2 messages issued every time change least overhead bits (M4,5,6) U-interface detected, regardless checksum status (MFILT= 0000 0xxx) SYNC Synchronization Signal input RITL/WLL sync signal which causes alignment U-superframes first edge= RITL/WLL synchronization enabled '1'= RITL/WLL synchronization disabled
Preliminary Data Sheet 06.99
(PD)
24911
Descriptions Table Definitions Functions Symbol DARB Input Output Function D-Channel Arbitration Signal enables/disables D-channel arbitration '1'= D-channel arbitration enabled '0'= D-channel arbitration disabled AUTO Auto Mode selects auto transparent mode channel processing, setting effect ports '1'= auto mode (MFILT= xxxx x100) '0'= transparent mode (MFILT= xxxx x001) Send Single Pulses (SSP) Test Mode '1'= alternating +/-3 pulses issued line ports 1.5ms intervals '0'= deactivated, clamp used
Note: This function corresponds selection C/I= besides fact that selection impacts line ports while selection impacts only chosen line
Data Through (DT) Test Mode enables/disables test mode '1'= test mode enabled, U-transceiver forced line ports enter 'Transparent' state '0'= test mode disabled
Note: This function corresponds selection C/I= besides fact that selection impacts line ports while selection impacts only chosen line
Interface Analog Front
Preliminary Data Sheet 06.99
24911
Descriptions Table Definitions Functions Symbol CL15 PDM0 Input Output Function 15.36MHz Master Clock Input Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Pulse Density Modulated Receive Data Line Port pulse density modulated stream from 24902 Quad that output from second-order sigma-delta Serial Data Receive Line interface signal from 24902 Quad that transports level detect information wake-up recognition lines Serial Data Transmit Line interface 24902 Quad transmit control data. Transmission based clock CL15 (15.36 Mbit/s). each line port following bits exchanged: TD0, TD1: Transmit data RANGE: Range select LOOP: Analog loopback switch PDOW: Power down/power Synchronization information
06.99
PDM1
PDM2
PDM3
Preliminary Data Sheet
24911
Descriptions Table Definitions Functions Symbol Input Output Function
Relay Driver/ Status Pins Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 0/4/8/12. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 1/5/9/13. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 2/6/10/14. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Relay Driver Pins Line Port addressable MON-8 command IOM®-2 channel 3/7/11/15. logic values positions A,B,C, MON-8 command 'SETD' determine output setting. Default value after pin-reset low. C/I-code reset does affect current status. Status Line Port change status passed IOM®-2 channel 0/4/8/12 MON-8 message 'AST' positions Connect either used.
ST00 ST01
Preliminary Data Sheet
06.99
24911
Descriptions Table Definitions Functions Symbol ST10 ST11 Input Output Function Status Line Port change status passed IOM®-2 channel 1/5/9/13 MON-8 message 'AST' positions Connect either used. Status Line Port change status passed IOM®-2 channel 2/6/10/14 MON-8 message 'AST' positions Connect either used. Status Line Port3 change status passed IOM®-2 channel 3/7/11/15 MON-8 message 'AST' positions Connect either used.
ST20 ST21
ST30 ST31
Test Pins CLS0 CLS1 CLS2 CLS3 80kHz Transmit Baud Clock Port used monitoring test purposes 80kHz Transmit Baud Clock Port used monitoring test purposes 80kHz Transmit Baud Clock Port used monitoring test purposes 80kHz Transmit Baud Clock Port used monitoring test purposes
JTAG Boundary Scan (PU) (PU) Test Clock Test Mode Select internal pullup resistor (160k) Test Data Input internal pullup resistor (160k) Test Data Output
Preliminary Data Sheet
06.99
24911
Descriptions Table Definitions Functions Symbol TRST Input Output (PU) Function JTAG Boundary Scan Disable resets controller state machine (asynchronous reset), active low, internal pullup (160k)
Note: Clamp TRST Boundary Scan logic used
'1'= reset inactive '0'= reset active Power Supply Pins
PuP: Open Drain Push Pull Internal Pull Down Internal Pull
3.3V ±0.3V supply voltage ground
Pinning Changes from DFE-Q V1.3 DFE-Q V2.1
Pinning Changes V2.1 N.C. SLOT1 SYNC V1.3 N.C. DSYNC N.C. Comment activates Monitor Time-Out procedure additional push-pull mode DOUT eases interface adaptation obsolete, replaced signal 'SYNC' increased data rate requires additional SLOT input signal used RITL/WLL synchronization, dedicated mode obsolete
06.99
Table
Preliminary Data Sheet
24911
Descriptions Table Pinning Changes V2.1 SLOT0 DARB TRST V1.3 SLOT Comment renamed dedicated 'Send Single Pulses' test mode renamed dedicated 'Data Through' test mode BScan power-on-reset replaced dedicated reset line
Preliminary Data Sheet
06.99
24911
Functional Description
Functional Description
Functional Overview
functional overview DFE-Q V2.1 given Figure 3-1. Besides signal processing frame formatting blocks 24911 features on-chip activation/ deactivation controller programmable general purpose pins control test relays power feeding circuits. application specific core services four Ulines cuts chip size minimum.
@pqr
8hpryyr
@hyvr 9rpqr
rshpr
DPH!
)LOWHU
Srpr 6pvhv9rhpvhv 8yyr
7hqth
8ypx
Brrhy
dataflow.vsd
Figure
Data Flow Diagram (DFE-Q V2.1 AFE)
Preliminary Data Sheet
06.99
24911
Functional Description
Block Diagram
8yyr
Drshpr
Drshpr
8ypx 8ypx Brrhv Tphiyr 8qvt
8uhry
EU6B
8yyr
7T86I
Sryh
block_ds.emf
Figure
DFE-Q V2.1 Block Diagram
Preliminary Data Sheet
06.99
24911
Functional Description
IOM®-2 Interface
IOM®-2 interface four-wire serial interface providing symmetrical full-duplex communication link layer-1 layer-2 backplane devices. transports user data, control/programming status information dedicated time multiplexed channels. structure used follows D-channel structure ISDN. ISDN-user data rate kbit/s U-interface transmitted transparently both directions IOM®) over interface.
6ODYH
0DVWHU
Last Frame Frame Frame Frame
iomif.emf
Figure
Clock Supply Data Exchange between Master Slave
Frame Sync Signal signal delimiting frames. This signal used determine start frame. data clocked Data Clock (DCL) which operates twice data rate. data clock square wave signal with duty cycle ratio typically 1:1. Incoming data sampled falling edge DCL-clock. Data carried over Data Upstream (DD) Data Downstream (DU) signals. upstream downstream directions always defined with respect exchange: Downstream refers information flowing from exchange subscriber, upstream defined vice versa. output line operating either open drain push-pull output. Both modes selected signal "PUP". open drain mode external pull-up resistor required. absence pull-up resistor automatically recognized (i.e. push-pull detection).
Preliminary Data Sheet
06.99
24911
Functional Description Within FSC-period, transmitted, corresponding DCLfrequencies ranging from 2048 8192 kHz. following table shows possible operating frequencies IOM®-2-interface. Table IOM®-2 Data Rates Data Rate [kBit/s] 1024 1536 2048 3072 4096 IOM®-2 Channels
Frequency [kHz] 2048 3072 4096 6144 8192
3.3.1
IOM®-2 Interface Frame Structure
typical IOM®-2 line card application comprises DCL-frequency 4096 with nominal rate 2048 kbit/s. Therefore eight channels available, each consisting basic frame with nominal data rate kbit/s. downstream data (DD) transferred signal DIN, upstream data (DU) signal DOUT. IOM®-2 channel assignment programmable strapping (SLOT1,0). basic IOM®-2 frame clocking structure consists
channel bits
Monitor
Command Indicate
64-kbit/s channels monitor channel transferring maintenance information between layer-1 layer-2 devices bits 16-kbit/s D-channel Four command indication (C/I) bits controlling layer-1 functions (activation/ deactivation additional control functions) layer-2 controller bits handling monitor channel
Preliminary Data Sheet
06.99
24911
Functional Description
Figure
Multiplexed Frame Structure IOM®-2 Interface
3.3.2
Superframe Marker Function
start superframe programmed high-phase lasting single DCL-period. high-phase more) DCL-periods transmitted other IOM®-2-frame starts. optional include superframe markers every 96th "frame synchronization" signal. remaining FSC-clocks must least DCL-periods duration. superframe marker used high-phases need least DCLperiods duration. With function enabled next outgoing basic frame defines start superframe inverted sync word (see Figure 3-5). This positions IOM®-2 superframe more arbitrary definite within tolerance 1.5ms.
Preliminary Data Sheet
06.99
24911
Functional Description
sf_pos.emf
Figure
Superframe Marker
superframe marker used, high-phases need least DCL-periods duration. relationship between IOM®-2-superframe LT-side, U-frame IOM®-2-superframe NT-side fixed after activation U-interface. I.e. data inserted LT-side first B1-channel after IOM®-2-slave superframe marker will always appear NT-side with fixed offset, e.g. B1-channel after master superframe marker. After activation this relationship (offset) different.
3.3.3
IOM®-2 Command/ Indicate Channel
Command/Indication (C/I) channel carries real-time control status information between DFE-Q V2.1 layer-1 control device. code must detected consecutive IOM®-2 frames considered valid (double last look criterion). indication issued permanently DFE-Q V2.1 DOUT until indication needs forwarded. code wide located positions 27-30 each time-slot. listing explanation U-transceiver codes found page 3-37.
3.3.4
IOM®-2 Monitor Channel
Monitor channel represents second method initiating reading U-transceiver specific information. Features monitor channel supplementary command/indicate channel. Unlike command/indicate channel with emphasis status control, monitor channel provides access internal bits (maintenance, overhead) test functions (local loop-backs, block error counter etc).
Preliminary Data Sheet
06.99
24911
Functional Description Besides known MON-0/2/8 commands class, MON-12 introduced DFE-Q V2.1: MON-12 Class MON-12 commands DFE-Q V2.1 provides ability address parts device internal register thus address functions that have been added with version 2.1. MON-12 commands always prioritized processed first other Monitor commands outstanding. Chapter 3.3.5 details. This means that Monitor commands split into four categories. Each category derives name from first nibble bits) byte long message. These are: MON-12 MON-0 MON-2 MON-8 (Internal Register Map) (Transparent Channel) (Overhead Bits) (Local Functions)
order list above corresponds priority attributed each category. MON12 commands always processed first. MON-0 messages will transmitted before MON-2 messages case several messages initiated simultaneously. various MON-0, MON-2 MON-8-commands discussed detail chapter "Monitor Commands" page 5-1. Structure structure Monitor channel wide, located position every time-slot. Monitor commands/messages sent to/from U-transceiver always bytes long. Transmission multiple monitor bytes specified IOM®-2 (see next section "Handshake Procedure" details). handshake control multiple byte transfers, monitor read "MR", monitor transmit "MX", every time-slot used. Verification double last-look criterion implemented monitor channel. monitor message that received consecutively after change been detected identical message that received before message will aborted. Handshake Procedure IOM®-2 provides sophisticated handshake procedure transfer monitor messages. handshake control bits, assigned each IOM®-2 frame DOUT). monitor transmit (MX) indicates when byte
Preliminary Data Sheet 06.99
24911
Functional Description been issued monitor channel (active low). transmitter postpones transmitting next information until correct reception been confirmed. correct reception will confirmed setting monitor read (MR) low. monitor channel full duplex operates pseudo-asynchronous base, i.e. while data transfer takes place synchronized frame synchronization, flow monitor data controlled MX-bits. Monitor data will transmitted repeatedly until reception acknowledged. Figure illustrates monitor transfer maximum speed. transmission 2-byte monitor command followed 2-byte response requires minimum IOM®-2 frames (reception frames transmission frames 1.875 ms). case controller able confirm receipt first response byte frame immediately following MX-transition DOUT from high (i.e. frame byte saved frames frames). Transmission reception monitor messages performed simultaneously U-transceiver. procedure depicted Figure would possible Utransceiver transmit monitor data frames (excluding EOM-indication) receive monitor data from frame onwards.
1/2: 1/2:
Monitor message byte Monitor response byte
Figure
Handshake Protocol with 2-Byte Monitor Message/Response
Preliminary Data Sheet
06.99
24911
Functional Description Idle State After bits have been held inactive (i.e. high) more successive IOM®-frames, channel considered idle this direction. Standard Transmission Procedure first byte monitor data placed external controller line DFE-Q V2.1 activated (low; frame DFE-Q V2.1 reads data monitor channel acknowledges setting MR-bit DOUT active transmitted bytes identical received frames (frame because data already read compared while MX-bit activated). second byte monitor data placed controller MX-bit inactive single IOM®-frame. This performed time convenient controller. DFE-Q V2.1 reads data byte monitor channel after rising edge been detected. frame immediately following MX-transition activeto-inactive, MR-bit DOUT inactive. MR-transition inactive-to-active exactly IOM®-frame later regarded acknowledgment external controller (frame 4-5). acknowledgment DFE-Q V2.1 will always sent IOM®-frames after activation data byte. After both monitor data bytes have been transferred DFE-Q V2.1, controller transmits "End Message" (EOM) setting MX-bit inactive more IOM®-frames (frame 5-6). frame following transition MX-bit from active inactive, DFE-Q V2.1 sets MR-bit inactive case step detects EOM, keeps MR-bit inactive (frame transmission monitor command controller complete. DFE-Q V2.1 requested return answer will commence with response soon possible. case "monitor time out" function enabled have postpone answer until after internal reset (see section Monitor Procedure Time-out details). Figure illustrates case where response sent immediately. procedure response similar that described points except transmission direction. assumed that controller does latch monitor data. this reason additional frame will required acknowledgment. Transmission monitor byte will started DFE-Q V2.1 frame immediately following acknowledgment first byte. U-transceiver does delay monitor transfer.
Preliminary Data Sheet
06.99
24911
Functional Description Transmission Abortion detected after first monitor bytes, received bytes identical first received frames, transmission will aborted through receiver setting MR-bit inactive more IOM®-2-frames. controller reacts with EOM. This situation illustrated Figure 3-7.
Figure
Abortion Monitor Channel Transmission
MONITOR Procedure Time-Out (MTO) DFE-Q offers internal reset (monitor procedure "Time-out") monitor routine. This reset function transfers monitor channel into idle state high) thereby resolving possible lock-up situations. therefore used systems where capable detecting solving hang-up situations monitor procedure. reset procedure started intervals. order avoid loss transmitted received data DFE-Q V2.1 commences monitor transfer only when enough time available before next reset will initiated. this case transmission postponed until after reset. Once message been issued IOM®, transfer needs completed before next reset. this accomplished, message lost without notice. this reason control software should able transfer monitor messages quickly possible. Signal "MTO" enables MTO-function, signal "MTO" disables
Preliminary Data Sheet
3-10
06.99
24911
Functional Description With MTO-function enabled, monitor routine reset twice U-superframe. resets performed start 49th IOM®-2-frame (see Figure 3-8). relationship reset timing U-frame reset procedure only executed active states (Line Active, Pend. Transparent, Transparent, Deactivated). Every reset sets both handshake bits DOUT idle state high) thereby preventing lock-up situations. DFE-Q-transmitter -receiver reset synchronously. With MTO-function disabled internal resets performed. This eliminates restrictions described following paragraphs, requires however external controller prevent lock-up situations monitor channel.
Figure
Monitor Access with Enabled
DFE-Q V2.1 operates Transmitter with Enabled transmitter reset intervals frames shown above. case transmission monitor message been completed before transmitter reset, complete message will lost. message that been lost interruption monitor reset will retransmitted. prevent this loss monitor messages, DFE-Q V2.1 will only commence monitor transmission more than IOM®-2 frames will available transmission before next reset occurs. Transmission thus does start during frame numbers ensure correct transmission receiver must delay receive procedure more than following value: 2-byte transmission: max. speed frames max. controller (receive) delay frames
Preliminary Data Sheet
3-11
06.99
24911
Functional Description DFE-Q V2.1 operates Receiver with Enabled receiver reset intervals frames shown above. case reception monitor message been completed before receiver reset, complete message lost because generation abort request guaranteed. prevent this loss monitor messages DFE-Q will only commence monitor reception (i.e. acknowledge received byte) more than IOM®-2 frames will available reception before next reset occurs. Reception thus does start during frame numbers ensure correct reception, transmitter must delay receive procedure more than following value: 2-byte reception: max. speed frames max. controller (transmit) delay frames
3.3.5
MON-12 Protocol
MON-12 commands feature direct access device internal register Monitor channel. This means that although DFE-Q V2.1 features microcontroller interface internal register functions directly addressed MON-12 commands. MON-12 read request command must first acknowledged DFE-Q V2.1 before subsequent read request triggered. case failure condition DFE-Q V2.1 repeats last outstanding MON-12 answer. MON-12 commands prioritized over other classes. U-interface functions addressed then value register LP_SEL determines register bank channel that referred result desired line port number must programmed first register LP_SEL before U-interface register accessed. this reason MON-12 commands issued simultaneously different IOM®-2 channels, must issued consecutively they address U-interface functions. registers that addressable MON-12 commands please refer register Chapter page 6-6. MON-12 commands following format: MON-12 write command comprises bytes, first byte contains MON-12 header, second byte register address, third byte register value.
Byte 1100 MON-12 Byte AAAA AAAA Byte DDDD DDDD
Register Address
Register Value
Preliminary Data Sheet
3-12
06.99
24911
Functional Description MON-12 read request command comprises bytes, first byte contains MON-12 header, second byte register address data that requested.
Byte 1100 MON-12 Byte AAAA AAAA
Register Address
After read request DFE-Q V2.1 reacts with 3-byte message. MON-12 read answer comprises bytes, first byte contains MON-12 header, second byte register address, third byte register value.
Byte 1100 MON-12 Byte AAAA AAAA Register Address Byte DDDD DDDD Register Value
Preliminary Data Sheet
3-13
06.99
24911
Functional Description
Interface Analog Front
interface 24902 V2.1 6-wire interface (see Figure 3-9). transmit receive data exchanged well control information start-up procedure means time division multiplexing. transmit data, power-up/down information, range function analog loopback requests transferred. level status information received line ports. PDM0.PDM3 output data from transferred DFE-Q V2.1. timing signals based 15.36MHz master clock which provided AFE.
dfe_afe_if.vsd
Figure
Interface Analog Front
available bits (related 15.36 clock) SDR/SDX during period divided into time-slots. time-slots bits long reserved data transmission, time-slot bits long used synchronization purposes. DFE-Q V2.1 uses four them, time-slots Table shows assignment IOM®-2 channels time-slots SDX/SDR assignment time-slots line ports.
Preliminary Data Sheet
3-14
06.99
24911
Functional Description
Table
Assignments Channels Time-Slots SDX/SDR Line Ports Time-Slot Line Port
IOM®-2 Channel 0/4/8/12 1/5/9/13 2/6/10/14 3/7/11/15
status synchronized SDX. Each time-slot carries corresponding during last bits slot.
Figure 3-10 Frame Structure SDX/SDR data interpreted follows: NOP: no-operation-bit none control bits (PDOW, RANGE LOOP) shall changed. values control bits assigned line port latched. states control bits ignored, they should reduce digital cross-talk analog signals. NOPQ least control bits shall changed. this case control bits transmitted with their current values. PDOW: PDOW '1', assigned line port switched power-down. Otherwise switched power-up.
RANGE: RANGE activates range function which attenuates received U-signal '1'= RANGE function activated (short line) '0'= RANGE function deactivated (long line)
Preliminary Data Sheet
3-15
06.99
24911
Functional Description LOOP: "0": LOOP activates loop function, i.e. loop closed. Otherwise line port normal operation. First time-slots with transmission data. synchronization allocation SDX, SDR. Reserved bit. Reserved bits currently defined shall '0'. Some these bits used test purposes assigned function later versions.
2B1Q data coded with bits TD2, TD1, TD0:
Table
2B1Q Coding Table care care
2B1Q Data
data interpreted follows: level detect information communicated DFE-Q V2.1 SDR. signal amplitude reaches wake-up level, toggles with signal frequency. input signal U-interface below wake-up level, tied either high. First time-slots with transmission data. synchronization allocation SDX, SDR.
Preliminary Data Sheet
3-16
06.99
24911
Functional Description
General Purpose I/Os
DFE-Q V2.1 features general purpose pins line port. This transparent control test relays power feeding circuits possible IOM®-2 Monitor channel. Four pins outputs, inputs. Setting Relay Driver Pins Four relay driver output pins (where denotes line port specifies pin) available line port. logic state four relay driver outputs which assigned same line port single MON-8 command, called 'SETD'. value latched long other SETD command with different relay driver settings received. state relay driver pins affected software reset (C/I= RES). state relay driver pins after hardware reset ,,low". Reading Status Pins Each line port owns status pins (where 0,1, denotes line port specifies pin) whose logical value reported associated Monitor channel. signal change status pins ST1.4 causes automatically issue two-byte MON-8 message 'AST' whose least significant bits reflect status STij. However, this automatic mechanism only enabled again, previous status message been transferred acknowledged correctly according Monitor channel handshake protocol. takes DFE-Q V2.1 least IOM®-2 frames (1ms) transmit 2-byte MON-8 message. Thus, repeated changes within periods shorter than IOM®-2 frames will overwrite status register information. this reason only value last recent status change will reported. Note that MON-8 transfer time depends also reaction time (acknowledge MR-bit) DFE-Q counterpart. Besides this automatic report DFE-Q V2.1 will issue status Monitor message 'AST' upon MON-8 request 'RST' STij pins have tied either GND, they used.
Preliminary Data Sheet
3-17
06.99
24911
Functional Description
Clock Generation
U-transceiver synchronize onto externally provided PTT-master clock. phase locked loop (PLL) integrated (PEF 24902) generate 15.36MHz system clock. synchronized system clock guarantees that U-interface transmission will synchronous PTT-master clock. able synchronize onto 2048 system clock. Infineon recommends however feed clock input DFE-Q V2.1 reference clock input (pin CLOCK) from same clock source. Please refer 24902 Data Sheet further details PLL. connection clock output line with DFE-Q V2.1 clock input line (CL15) please refer page 1-5.
Preliminary Data Sheet
3-18
06.99
24911
Functional Description
U-Transceiver Functions
U-interface establishes direct link between exchange terminal side. consists copper wires. Quad uses four differential outputs (AOUT, BOUT) four differential inputs (AIN, BIN) transmission reception. These differential signals coupled four hybrids four transformers four two-wire U-interfaces. nominal peak values correspond chip output U-interface. Direct access U-interface possible. user data inserted extracted IOM®-2 interface. Control maintenance bits partly provided IOM®-2 monitor commands. remaining maintenance bits fully controlled DFE-Q V2.1 itself allow external influence (e.g. CRC-checksum).
2B1Q Frame Structure
Transmission over U2B1Q-interface performed symbol rate kBaud. code used reduces binary informations quaternary symbol (2B1Q) resulting total rate kbit/s. kbit/s user data kbit/s used maintenance synchronization information. Data grouped together into U-superframes each. beginning superframe marked inverted synchronization word (ISW). Each superframe consists eight basic frames (1.5ms) which begin with standard synchronization word (SW) contain bits information. structure U-superframe illustrated Figure 3-11 Figure 3-12.
Basic Frame
Basic Frame
Basic Frame
Figure 3-11 U-Superframe Structure
(Inverted) Synch Word Quat)
User Data Bits (108 Quat)
Maintenance Data Bits Quat)
Figure 3-12 U-Basic Frame Structure information bits contain data from IOM®-frames, remaining bits used transmit maintenance information. Thus maintenance bits available U-superframe. They used transmit EOC-messages bit), Maintenance (overhead) bits checksum bit).
Preliminary Data Sheet
3-19
06.99
24911
Functional Description
Table
2B1Q U-Frame Structure
Framing Overhead Bits
Quat Positions Positions Super Frame Basic Frame 2,3.
Sync Word
ACT/
CRC1 CRC3 CRC5 CRC7 CRC9
FEBE CRC2 CRC4 CRC6 CRC8
EOCa1 EOCa2 EOCa3 EOCd EOCi3 EOCi6 EOCd EOCi3 EOCi6 EOCi1 EOCi4 EOCi7 EOCi1 EOCi4 EOCi7 EOCi2 EOCi5 EOCi8 EOCi2 EOCi5
EOCa1 EOCa2 EOCa3
EOCi8 CRC11 CRC12
dir. Inverted Synchronization Word (quad): Synchronization Word (quad): Cyclic Redundancy Check Embedded Operation Channel Activation Deactivation Colt Start Only U-Only Activation S-Activity Indicator Far-end Block Error FEBE Power Status Primary Source Power Status Secondary Source NT-Test Mode NAlarm Indication Network Indication
dir.
-3-3+3+3+3-3+3-3-3 +3+3-3-3-3+3-3+3+3 address data message information (data message) Layer ready communication informs that will turn NT-activation with cold start only U-only activated S-interface deactivated Far-end block error occurred Primary power supply Secondary power supply busy test mode Interruption (according ANSI) function (reserved)
FEBE NAIB
Preliminary Data Sheet
3-20
06.99
24911
Functional Description
Maintenance Channel
last three symbols bits) form 4kbit/s M(Maintenance)-channel used exchange operations maintenance data between network Approved M-bit data first processed then reported system Monitor channel messages (MON-0, MON-2). MON-0/ MON-2 mapping M1-3 bits over four basic frames constitute complete word. words exchanged across IOM®-2 interface MON-0 messages. overhead bits (M4,M5,M6) U-superframe collected transported MON-2 message. Figure 3-13 shows detail maintenance bits received U-superframe mapped MON-0 MON-2 messages. M1-6 Filtering Options reduce processor load DFE-Q V2.1 provides several programmable filters issue MON-0 MON-2 messages. following paragraphs various verification algorithms provided control mechanism overhead bits (M4,M5,M6) presented. verification method received M-channel data programmed MFILT register using MON-12 protocol. following options provided:
Preliminary Data Sheet
3-21
06.99
24911
Functional Description
Super Frame
Basic Frame
CRC1 CRC3 CRC5 CRC7 CRC9 CRC11
FEBE CRC2 CRC4 CRC6 CRC8 CRC10 CRC12
DEA/PS1 SCO/PS2 1/N1/CSO
UOA/SAI AIB/NIB
Super Frame
Basic Frame
CRC1 CRC3 CRC5 CRC7 CRC9 CRC11
CRC2 CRC4 CRC6 CRC8 CRC10 CRC12
6qqr
HPI!
HPI!
mon02corrsp.emf
Figure 3-13
MON-0/2 M-Bit Correspondence
3-22 06.99
Preliminary Data Sheet
24911
Functional Description (M1-M3) Filtering first three M-bits (M1-M3) each basic U-frame constitute command/ message. different commands their meaning next paragraph. register MFILT following operating modes set: Automode (MFILT.EOC= '100' default setting) automode received messages checked 'triple-last-look' (TLL) before they signalled system MON-0 message. Return Message Reception Function activated (see "EOC Auto Mode" page 3-31). Transparent mode (MFILT.EOC= '001') transparent mode received messages forwarded MON-0 system interface. This means that every MON-0 message issued. Transparent mode with Change function active (MFILT.EOC= '010') Only change message been detected received message reported MON-0 message. Transparent mode with active (MFILT.EOC= '011') change only reported MON-0 command been detected least three consecutive messages. more details commands messages processing please refer chapter 3.10 page
Overhead (M4, Filtering bits used communicate status maintenance functions between transceivers. meaning position depends direction transmission (upstream/downstream) operation mode (NT/LT). Table different meaning bits. reflect change system status value bits shall repeated least three consecutively transmitted superframes. overhead bits binary when leaving power-down state. further processing performed Utransceiver. Four different validation modes selected take effect base. Only received change been approved programmed filter algorithm corresponding MON-2 message issued. following filter algorithms provided: Change (MFILT.M4= 'X00') Triple-Last-Look (TLL) coverage (MFILT.M4= 'X01') coverage (MFILT.M4= 'X10' default setting) coverage (MFILT.M4= 'X11')
Some bits, ACT, UOA, have destinations, state machine system interface. Regarding these bits Triple-Last-Look (TLL) applied default before changed status input state machine. MFILT
Preliminary Data Sheet 3-23 06.99
24911
Functional Description register user decide whether bits which input state machine shall approved (MFILT.M4= '0XX') (default setting, since Bellcore requirement) same verification mode (MFILT.M4= '1XX') selected issue MON2 message. spare bits M51, default unless they explicitly MON-2 commands otherwise. default changes reported MON2 messages only violation been detected (same mode bits). However user choice program following options: Same validation algorithm applied bits programmed bits (MFILT.M56= 'X0' default setting) Note that unlike bits bits included generation! Change (MFILT.M56= 'X1')
Note: issue corresponding Monitor messages delayed 12ms Usuperframe) received M-bits covered. This M-bit data checked with actual which received U-superframe later.
Filter Setting AUTO CRCON Besides MFILT register verification method maintenance bits well programmed AUTO CRCON. setting AUTO determines operational mode Embedded Operations Channel: AUTO selects automode line ports corresponds following register setting MFILT xxxx x100. AUTO selects transparent mode line ports corresponds following register setting MFILT xxxx x001. CRCON mode overhead bits activated deactivated: CRCON enables mode line ports corresponds following register setting MFILT 0001 0xxx. CRCON disables mode line ports corresponds following register setting MFILT 0000 0xxx. Note that setting only evaluated once after reset. This fact allows reprogram verification modes later MON-12 command. MFILT register setting evaluated each time U-transceiver enters DEACTIVATED state.
Preliminary Data Sheet
3-24
06.99
24911
Functional Description Figure 3-14 summarizes various filtering options that provided several bits Maintenance channel
8uhtr
HADGU@P87v"!
Hhpuvr
HADGUH#7v$ HADGUH#7v#"
HPI! HPI!
8uhtr
8uhtr
HADGUH$%7v%
m456_filter.emf
Figure 3-14 Maintenance Channel Filtering Options
Preliminary Data Sheet
3-25
06.99
24911
Functional Description
3.9.1
Reporting State Machine
Figure 3-15 illustrates point time when detected change reported system interface when reported state machine: towards system interface MON-2 messages might sent after complete U-superframe received, whereas towards state machine M4-bit changes (ACT, SAI) instantly passed soon they were approved (default setting register register MFILT, "MFILT M-Bit Filter Options" page 6-8). context Figure 3-15 this means that verified change already reported basic frame instead basic frame
Super Frame Basic Frame
n+1. Super Frame Basic Frame
Basic Frame
hyvqhrq HPI!
Hhpuvr
Drshpr
m4tim2sm.emf
Figure 3-15
Report Timing
However, same filter selected towards state machine programmed towards system interface Bit5= register MFILT) user aware that mode active state machine informed next Usuperframe.
Preliminary Data Sheet
3-26
06.99
24911
Functional Description
3.9.2
Control Mechanisms
Figure 3-16 Figure 3-17 show control mechanisms that provided data: M4WMASK register user selectively program which bits externally controlled which internal state machine. M4WMASK then value U-transmit frame determined value corresponding position MON-2 command. Note that MON-8 command PACE/PACA corresponds M4WMASK register. selected whether state machine MON2 commands. M4RMASK register user selectively program which changes shall cause MON-2 message. With respect corresponding (no. M4RMASK decides addition whether value received reported state machine SAI= signalled. Access M4WASK M4RMASK provided MON-12 protocol. MON-2 commands bits that sent with next available U-superframe. MON-2 messages status last validated data reported. Also default values spare bits, M51, overwritten time MON-2 command. MON-2 messages reports last received verified data.
Preliminary Data Sheet
3-27
06.99
24911
Functional Description
HPI!
Hhpuvr
I@7@
A@7@
PQHP9@A@7@
H#XH6TF
m456_lt_tx.emf
Figure 3-16
Control Transmit Direction
HADGUH#
HADGUH$%
A@7@
H#SH6TF
Hhpuvr
8uhry 8yyr
HPI!
m456_lt_rx.emf
Figure 3-17
Control Receive Direction
3-28 06.99
Preliminary Data Sheet
24911
Functional Description
3.9.3
Start Maintenance Evaluation
MON-0/2 messages will issued only receiver synchronized. This done avoid meaningless MON-0/2 messages data transmission synchronized. other words, MON-0/2 messages will issued only following states:
States Line Active Pending Transparent Deactivated Pending Deactivation Transparent
3.10
Embedded Operations Channel (EOC)
Embedded Operations Channel (EOC) used transfer data from exchange terminal side vice versa without occupying D-channels. used transmit diagnostic functions signaling information. EOC-data inserted into U-frame positions thereby permitting transmission complete EOC-messages 12bits) within U-superframe. With MON-0-command complete EOC-message (address field, data/message indicator information field) passed U-transceiver. contains address field, data/message indicator eight-bit information field. With address field destination transmitted message/data defined. Addresses defined repeater stations broadcasting. data/message indicator needs indicate that information field contains message. (0), numerical data transferred Currently numerical data transfer from required. From codes possible information field reserved non-standard applications, reserved internal network eight defined ANSI diagnostic loopback functions. remaining free codes available future standardization.
Preliminary Data Sheet
3-29
06.99
24911
Functional Description
Table
Supported EOC-Commands
Address Field
Data/ Message Indicator
Information (rigin) (estination)
Message
Broadcast Repeater stations Data Message
LBBD
protocol operates repetitive command/response mode. Three identical properly-addressed consecutive messages shall received before action initiated. order cause desired action Line Card controller continues send message until receives three identical consecutive frames from that agree with transmitted frame. response echo received frame. reply echoed frame sent upstream next available returning frame. actions initiated shall latching, permitting multiple EOC-initiated actions effect simultaneously. Latched functions resolved (return-to-normal) command.
Preliminary Data Sheet
3-30
06.99
24911
Functional Description Access only possible when superframe transmitted. This case following states: Line Active Pend. Transparent Deactivated Pend. Deactivation Transparent
other states than listed above EOC-bits U-interface clamped high.
3.11
Processor
on-chip EOC-processor responsible correct insertion extraction EOC-data U-interface. MON-0-messages provide access device internal EOC-registers. processor performs code repitition. This means that MON-0 message transporting command needs transferred only once EOC-processor programmed automode transparent mode: Auto Mode Acknowledgment: There acknowledgment mode. Latching: latching performed. Transfer IOM®: 'Return Message Reception Function' enabled soon transmitted command. causes U-transceiver mode compare received verified TLL) messages with last downstream transmitted command. MON-0 message issued they prove equal. this particular received message 'different from previous' rule applied. This means that MON-0 message even issued received message different previously accepted. other incoming messages besides echo transmitted downstream will evaluated 'different from previous' verification. received messages will passed independently address used, i.e. only messages addressed with (000) (111) received EOC-messages will transmitted with MON-0-messages indicated interrupt request. Execution: execution mode
Preliminary Data Sheet
3-31
06.99
24911
Functional Description Transparent Mode Every MON-0-message issued IOM®. contains last received EOCmessage. This occurs even change occurred EOC-channel. "triple-lastlook" performed before MON-0-message sent. Figure 3-18 summarizes different processing EOC/MON-0 commands/messages mode.
Figure 3-18
EOC-Procedure Auto- Transparent Mode
Preliminary Data Sheet
3-32
06.99
24911
Functional Description
3.12
Cyclic Redundancy Check
error monitoring function implemented covering data transmission U-superframe Cyclic Redundancy Check (CRC). computed polynomial
modulo addition)
check digits (CRC bits CRC1, CRC2, CRC12) generated transmitted U-superframe. receiver will compute received data compare with received CRC-bits generated transmitter. CRC-error will indicated both sides U-interface, NEBE (Near-end Block Error) side where error detected, FEBE (Far-end Block Error) remote side. FEBE-bit will placed next available U-superframe transmitted originator. Far-end near-end error indications increment corresponding block error counters exchange terminal side. Figure 3-19 illustrates CRC-process.
Preliminary Data Sheet
3-33
06.99
24911
Functional Description
G(u)
SFR(n)
G(u)
CRC1. CRC12
CRC1. CRC12
SFR(n SFR(n 1.0625) FEBE FEBE Error Counter
(MON-8)
(MON-1) NEBE (MON-8) NEBE Error Counter
SFR(n 1.0625) FEBE
G(u)
SFR(n 0.0625)
G(u)
SFR(n 1.0625) FEBE Error Counter
(MON-8) (MON-1) FEBE
SFR(n FEBE SFR(n FEBE
NEBE Error Counter
(MON-8)
crc.emf
Figure 3-19
CRC-Process
3-34 06.99
Preliminary Data Sheet
24911
Functional Description
3.13
Scrambling/ Descrambling
scrambling algorithm ensures that sequences permanent binary transmitted. defined ETSI ANSI T1.601. algorithms used scrambling descrambling NT-mode given Figure 3-20. Note that wrong decision receiver automatically leads least three errors. Whether these recorded error counter depends fact whether faulty bits part monitored channels not.
Figure 3-20 Scrambler/ Descrambler Algorithms
Preliminary Data Sheet
3-35
06.99
24911
Functional Description
3.14
Encoding/ Decoding (2B1Q)
2B1Q line code 4-level pulse amplitude modulation (PAM) code without redundancy. 2B1Q stands Binary, Quaternary. transmit direction two-bit binary pairs converted into quaternary symbols that called quats. each pair bits first called sign second called magnitude bit. Table shows relationship bits quats.
Table
2B1Q Coding Table Second (magnitude) Quaternary Symbol (quat)
First (sign)
four values listed under 'Quaternary symbol' table above should understood symbol names, numerical values. receiver, each quaternary symbol converted pair bits reversing table, descrambled finally formed into original stream.
Preliminary Data Sheet
3-36
06.99
24911
Functional Description
3.15
Codes (2B1Q)
operational status DFE-Q V2.1 controlled Control/Indicate channel (C/I-channel). four channels operate completely independently. Table presents existing codes. command indication will recognized valid after been detected successive IOM®-frames (double last-look criterion). Indications strictly state oriented. Refer state diagrams following sections commands indications applicable various states. Commands have applied continuously until command validated DFE-Q V2.1 desired action been initiated. Afterwards command changed. indication issued permanently DFE-Q V2.1 DOUT until indication needs forwarded. Because number states issue identical indications possible identify every state individually. Table
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RES1 Activation Indication Activation Request Activation Request with
Command Indicate Codes (2B1Q)
LT-Mode DOUT DEAC 3-37 Error Indication (error S/T) Loss Signal Level Deactivation Confirmation 06.99
Preliminary Data Sheet
24911
Functional Description
DEAC Activation Request Local Loop Activation Request Maintenance bits Activation Request without limit Deactivation Request Deactivation Accepted Deactivation Indication Data-Through test mode Error Indication (time-out error RES1 Reset Reset receiver Loss Synchronization Send-Single-Pulses test mode U-Activation Indication U-Activation Request Frame Jump
Preliminary Data Sheet
3-38
06.99
24911
Functional Description
3.16
State Machine Notation
state machines control sequence signals U-interface that generated during start-up procedure. informations contained following state diagrams are:
State name U-signal transmitted Overhead bits transmitted C/I-code transmitted Transition criteria Timers
Figure 3-21 shows interpret state diagrams.
Figure 3-21 Explanation State Diagram
following example explains state diagram extract LT-state diagram. state explained "Deactivated" state LT-mode.
Preliminary Data Sheet
3-39
06.99
24911
Functional Description state entered either three methods: From state "Receive Reset" after time expired Expired) From state "Tear Down" after internal transition criterion "LSU" fulfilled From state "Reset" "Test" after C/I-command "DR" been sent following information transmitted: sent U-interface overhead bits sent C/I-message "DI" issued DOUT state left either following methods: Leave state "Awake" after wake tone (TN) detected C/I-code present Leave state "Alerting" after C/I-commands "AR", "ARX", "AR0" "UAR" were received Leave state "Reset Loop" after C/I-command "ARL" received Combinations transition criteria possible. Logical "AND" indicated DC), logical "OR" written "or" negation used. start timer indicated with "TxS" ("x" being equivalent timer number). Timers always started when entering state. action resulting after timer expired indicated path labelled "TxE". sections following state diagram contain detailed information states signals used. These details mode dependent differ identically named signals/states. They therefore listed each mode.
Preliminary Data Sheet
3-40
06.99
24911
Functional Description
3.17
Mode State Diagram
Pin-RES C/I= 'RES'
9@68
TN&DC
9rhpvhrq
T1S*) T1S*),
Pin-SSP C/I= 'SSP' RES1
9@68
6yrvt
RES1
T9S,
(Loop) T4S, LSEC T1S,
6hxr
LSEC
LSEC
@8Uhvvt
6yrvtf@
RES1
LSEC
h2q2 @88rtrq
h2q2
RES1
h2q2
h2q2
RES1
@RUhvvt
(BBD0 BBD1 CRCOK) LSUE
TG"U TG"U
h2q2
QrqUhhr
/AR0
LSUE
V6DAE
State Pin-DT LSUE act=1
TG"U
sai=0 act=0 act=0 sai=1
TG"U h2q2
LSUE
Uhhr 6DAE @D!AE
6SAE V6DAE
sai=0 LSUE
TG"U h2q2 TG"U
h2q2 TG"U
T10S
h2q2
9@68
RES1
RES1
T10E
9@68
started case applied
state Line Active entered from state 'EQTraining 2B+D data must clamped until act= been received from
LT_SM_2B1Q_cust.emf
Figure 3-22 State Transition Diagram LT-Mode
Preliminary Data Sheet 3-41 06.99
24911
Functional Description
3.17.1
Inputs U-Transceiver LT-Mode
transition criteria described following sections. They grouped into: C/I-commands settings Events related U-interface Timers
C/I-Commands
Activation Request U-transceiver requested enter power-up state start activation procedure sending wake-up signal case U-transceiver state "Deactivated" recommended always apply before resolve situation tone been detected before. Activation Request with "ACT" U-transceiver requested enter power-up state start activation procedure sending wake-up signal After Training" state "Line Active" will entered independent "ACT" bit. Evaluation "ACT" disabled when received enabled when received. case U-transceiver state "Deactivated" recommended always apply before resolve situation tone been detected before. Activation Request Local Loop-back U-transceiver requested operate analog loop-back (close U-interface) start start-up sequence sending wake-up tone This command issued only after U-transceiver been "Deactivated" state (C/I-channel code issued DOUT) issued continuously long loop-back requested. Activation Request Extended DFE-Q requested enter power-up state start activation procedure sending wake-up signal difference command that Timer disabled. activation duration exceed sec. case U-transceiver state "Deactivated" recommended always apply before resolve situation tone been detected before. Deactivation Confirmation 'DC' applied state "Deactivated" DFE-Q transitions state "AWAKE" soon receives wake-up tone from 'DR' applied state "Deactivated" wake request acknowledged. This linecard able reject activation attempt e.g. during service procedure. means 'DC' command also during U-only activation capable control point time when complete transmission line transparent case terminal initiated activation request occurred. state 'S/T Deactivated' with applied code 'UAR' DFE-Q issues 'UOA= receives 'SAI= from deactivated interface. terminal requests activation with 'AR' issued
Preliminary Data Sheet
3-42
06.99
24911
Functional Description
indication 'UAI' switches 'AR'. soon 'DC' applied instead 'UAR' side line transparent, since reflects polarity thus '1'. Deactivation Request This command requests U-transceiver start deactivation procedure setting cease transmission afterwards. DR-code conditional command causing U-transceiver only react states "Reset", "Test", "S/T Deactivated", "Line Active", "Pending Transparent" "Transparent", i.e. when C/Ichannel codes DEAC, UAI, issued DOUT. Data Through This unconditional command used test purposes only forces U-transceiver into transparent state independent wake-up protocol. far-end transceiver needs connected; case far-end transceiver present assumed same condition. Reset Unconditional command which resets whole chip; note that contrary reset clock signal must provided code processing. Reset reset command resets receiver functions; especially EQ-coefficients zero. RES1-code does reset other than receiver functions (e.g. IOM®-functions relay driver settings). RES1-code should used when U-transceiver entered failure condition (expiry timer loss framing loss signal level) indicated C/I-channel EI3, DOUT. Besides resetting receiver, this command stops transmission U-interface. RES1. Send Single Pulses Unconditional command which requests transmission single pulses U-interface. pulses issued intervals have duration 12.5 chip transferred "Test" state; receiver will reset. Partial Activation Request only) U-transceiver requested enter power-up state start activation procedure U-interface only.
RES1
Pins
Pin-RES Pin-Reset function this same C/I-code RES. C/I-message DEAC will issued. duration reset pulse must minimum. Send Single Pulses function this same C/I-code SSP. C/I-message DEAC will issued. high level needs applied continuously transmission single pulses. Data Through function identical with C/I-code
Pin-SSP
Pin-DT
Preliminary Data Sheet
3-43
06.99
24911
Functional Description U-Interface Events
"ACT" received from NT-side. signals that detected INFO3 S/T-interface indicates that complete basic access system synchronized both directions transmission. LT-side requested provide transparency transmission both directions respond with setting ACT-bit "1". case loopbacks (loop-back single-channel loop-back NT), however, transparency required even when sending Transparency achieved following manner: U-transceiver performs transparency both directions transmission after receiver achieved synchronization (state EQ-training left) independent status received ACT-bit. status "ready sending" reached when state transparent entered i.e. when C/I-channel indication issued. This valid case normal activation procedure call control. case loop-backs (loop-back single-channel loop-back analog loop-back however, status "ready sending" reached when state line active entered i.e. when C/I-channel indication issued. Until status "ready sending" reached, binary "0s" have passed D-channels DIN. indicates loss transparency NT-side (loss framing loss signal level S/T-interface). U-transceiver informs LT-side issuing C/I-channel indication EI2, performs state change other actions. CRCOK Cyclic Redundancy Check This input used criterion that receiver acquired frame synchronization both coefficients have converged. Loss Framing U-interface This condition fulfilled framing lost upper limit. correlation between synchronization word input signal optimal, issued earlier. Loss Signal Level behind Echo Canceler "Awake" state, this input used indication that ceased transmission signal SN1. EC-training state, this input used internal signal indicating that converged. Loss Signal Level U-interface This signal indicates that loss signal level duration been detected U-interface. This short response time relevant cases where waits response signal level) from NT-side, i.e. after deactivation procedure been started after loss framing occurred. Loss Signal Level U-interface (error condition) After loss signal level been noticed, timer started. After this timer elapsed, LSUE-criterion fulfilled. This long response time (see also LSU) valid cases where prepared lose signal level. Note that 3-44 06.99
LSEC
LSUE
Preliminary Data Sheet
24911
Functional Description
represent minimum value; actual loss signal might have occurred earlier, e.g. when long loop LT-side, echo coefficients need readjusted parameters. Only after adjusted coefficient cancel echo completely, loss signal detected timer started long loop remote end, coefficients still correct loss signal will detected immediately). Signal Level behind echo canceler This signal indicates that signal level corresponding from been detected U-interface. Superframe Detected Tone (wake-up signal) received from When "Deactivated" state, U-transceiver requested start activation procedure inform LT-side making C/I-channel code When "Wait state, signal sent acknowledges receipt wake-up signal from When analog loop-back operated, wake-up signal sent LT-transmitter detected LT-receiver. TN-criteria fulfilled when consecutive periods wake-up tone were detected. Binary "1s" detected D-channels This internal signal indicates that period time 6-12 continuous stream binary "0s" "1s" been detected. used criterion that receiver acquired frame synchronization both EQ-coefficients have converged. BBD1 corresponds signals case normal activation BBD0 corresponds internally received signal case analog loop-back possibly loop-back
BBD0/1
Timers
start timers indicated TxS, expiry TxE. following Table shows which timers used LT-modes:
Table
Timer
Timers Used LT-Modes
Duration (ms) Function 15000 6000 1000 6000 Supervisor start-up TL-transmission Receiver reset Re-transmission Supervisor detect Supervisor converge Supervisor detect Hold time Alerting Reset loop Wait Awake training converge Receiver reset State
Preliminary Data Sheet
3-45
06.99
24911
Functional Description
Timer Duration (ms) Function Delay time detection Hold time "DEA" transmission State Pend. transparent Awake error Pend. Deactivation
3.17.2
Outputs U-Transceiver LT-Mode
Signals indications issued IOM®-2-interface (C/I-codes) U-interface (predefined U-signals).
C/I-Indications
Activation Indication This indication signals that "ACT" been received that timer elapsed. This indication issued case applied DOUT analog loop-back operated. Activation Request AR-code signals that wake-up signal been received that start-up procedure commenced. Receiver synchronization been achieved. When already partially active only activation), indicates that "SAI" (1), i.e. S/T-interface become active. Deactivation This indication issued response DR-code (Pend. Deactivation, Tear Down) "Reset" "Test" states. Deactivation Indication Idle code IOM®-interface. Normally U-transceiver stays "Deactivated" state unless activation procedure started NT-side. Error Indication issued received ACT-bit (0). receiver indicates loss signal framing S/T-interface setting upstream ACT-bit (0). Utransceiver remains "Transparent" state. After signal level framing detected again, C/I-indication will issued anew. Error Indication This indication issued when U-transceiver been able activate successfully (expiry timer T1). Loss Signal Level U-transceiver entered failure condition after loss signal level (LSUE). Re-Synchronization indication after loss framing (LOF) EI3, indication LT-side should react applying C/I-channel code RES1 allow U-transceiver enter "Receive reset" state reset receiver functions. 3-46 06.99
DEAC
Preliminary Data Sheet
24911
Functional Description
Frame Jump This indication signals that either data buffer overflow/underflow been detected phase jump IOM®-timing signals occurred. FJ-code issued period U-Activation Indication UAI-code signals that line system synchronized both directions transmission (see also input Maintenance bits transmitted normally. Activation Request Maintenance Transmission maintenance bits possible.
Signals U-Interface
signals SLx, transmitted U-interface defined Table page polarity overhead bits indicated follows: corresponds binary "0/1". corresponds binary "0/1". polarity transmitted UOA-bit depends received C/I-channel code: sets UOA-bit binary sets UOA-bit binary other C/I-codes sets same value received bit. After deactivation UOA-bit binary until valid SAI-bit received.
Preliminary Data Sheet
3-47
06.99
24911
Functional Description
3.17.3
LT-States
This section describes functions states defined LT-mode.
Alerting wake-up signal transmitted (T2) response activation request from side ARL). case analog loop-back, signal forwarded internally wake-up signal detector stored. Alerting Error When timer (15s) expired state "Alerting" before been detected then DFE-Q transits from state "Alerting" state "Alerting Error". Once "Alerting Error" been entered receiver must reset RES1. Awake "Awake" state entered upon receipt wake-up acknowledge signal from case activation started LT-side, timer restarted when "Awake" state entered. Awake Error "Awake Error" state equivalent "Awake" state, entered only when wake-up signal received while being "Receive reset" state. "Receive reset" state entered upon application C/I-channel code RES1, "Awake error" state assures that minimum amount time elapses between application RES1-code U-transceiver entering state training) which again reacts RES1-code. LT-side requested stop issuing command RES1 within after receipt C/I-channel code DOUT replace another command such idle code instance. Deactivated (Full Reset) "Deactivated" state device enter power consumption condition. powerdown mode entered monitor messages expected. power-down receiver parts interface deactivated while functions related IOM®-2-interface wakeup detector still active. signal sent U-interface, differential outputs AOUT BOUT Utransceiver waits wake-up signal from NT-side activation request (AR, AR0, ARL) from LT-side start activation procedure. Note that state "Deactivated" activation initiated ARX, tone been recognized before. This situation only resolved applying Therefore recommended apply always before ARX, UAR. recognition wake-up signal following procedure applies: detected periods transfer within "Deactivated" state into power-up power-up both differential outputs, AOUTx BOUTx, common mode level VDDmin/2
Preliminary Data Sheet
3-48
06.99
24911
Functional Description
detected total consecutive periods transition criterion fulfilled, change next state, addition C/I-command given DIN. detected more than less than periods return power-down input sensitivity stated V1.1 Data Sheet. There minimum level required specified meet transition criterion. power-up condition thus already entered lower level. Converged Upon EC-coefficients having converged, U-transceiver starts transmission signal waits receipt signal from (SEC). signal detected within nevertheless start-up procedure will continued. case analog loop-back, this state left immediately because compensates looped back transmit signal. EC-Training signal transmitted U-interface allow LT-receiver update EC-coefficients. "EC-training" state left when converged (LSEC) when timer elapsed. Timer allows start-up procedure proceed even LSEC high noise level U-interface instance, could detected. EQ-Training state "EQ-Training" equalizer coefficients trained minimum period 3ms. Upon expiry timer state "EQ-Training entered. EQ-Training "EQ-Training state left after receiver achieved synchronization superframe indication been detected (SFD). case RES1 applied "EQ-Training U-transceiver transits "Tear Down Error" finally gets reset. Refer state "EQ-Training case error condition occurred. EQ-Training Error Upon expiry timer DFE-Q leaves state "EQ-Training enters state "EQ-Training Error" issues C/I-channel indication EI3. error condition only resolved applying RES1. Line Active "Line Active" state, U-transceiver transmits transparently both directions. UInterface synchronized maintenance channel operational. U-transceiver stays line-active state during normal activation procedure while "ACT" received when analog loop-back established while C/I-command applied
Preliminary Data Sheet
3-49
06.99
24911
Functional Description
case normal activation with call control, binary "0s" have applied channels IOM®-interface. After C/I-channel indication been issued, layer-2 receiver should fully operational prevent first layer-2 message issued NT-side upon receipt AI-code lost. Loss Signal "Loss Signal" state entered upon detection failure condition i.e. loss receive signal (LSUE). C/I-channel indication issued. Utransceiver waits C/I-channel command RES1 enter "Receive Reset" state. Loss Synchronization "Loss Synchronization" state entered upon detection failure condition i.e. loss framing LT-receiver (LOF). ACT-bit C/I-channel indication issued. U-transceiver waits C/I-channel command RES1 enter "Tear Down Error" state subsequently "Receive Reset" state. Pending Deactivation "Pending Deactivation" transient state entered after receipt DR-code. DEA-bit "0". Timer assures that DEA-bit least three consecutive superframes before transmit level turned off. Pending Transparent "Pending Transparent" transient state entered upon detection left ACT-bit "1". purpose this state issue C/I-channel indication (corresponding "ready sending") after ACT-bit been LT-transceiver. This assures that under normal operating conditions AI-indication issued first TE-side only afterwards LT-side. Thus layer-2 receiver already operational when first layer-2 message issued LT-side. Reset "Reset" state entered with unconditional command RES, respectively Pin-RES. left when RESQ inactive C/I-channel code received. DEAC output "Reset" state. U-transceiver does react receipt wake-up signal Reset Loop "Reset Loop" resets receiver order guarantee correct adaption echo- equalizer coefficients. Receive Reset "Receive Reset" state assures that period signal, especially wake-up signal sent U-interface, i.e. activation procedure started from LT-side. wake-up signal however, from NT-side acknowledged.
Preliminary Data Sheet
3-50
06.99
24911
Functional Description
Deactivated state "S/T Deactivated" will entered received ACT- SAI-bits (0). this state signal SL3T, (0), transmitted downstream. IOM®-2-bus C/I-code issued while received (0). order initiate complete activation from deactivation state, needs UOA-bit (1). This will occur either following three conditions met: AR(LT-activation) AR(TE-activation with exchange control [DIN UAR]) (1)(TE-activation without exchange control [DIN DC]) "S/T deactivated" will left received (1), code applied. Tear Down "Tear Down" state, transmission ceases order deactivate basic access, Utransceiver waits response signal level, LSU) from NT-side. Tear Down Error "Tear Down Error" state entered after loss framing been detected. Transmission ceases order deactivate basic access U-transceiver waits response signal level, LSU) from NT-side. EI3-indication transmitted after transition forced RES1 from waitfor-TN EQ-training states. case transition from "Loss synchronization" state sent. Test This "Test" mode entered when unconditional commands Pin-SSP applied. left when inactive again C/I-channel code RES1 received. Single pulses (SP) DEAC output "Test" state. U-transceiver does react receipt wakeup signal Transparent This "Transparent" state corresponds fully active state case normal activation call control. also entered case loop-back issues case single-channel loop-back LT-side informed that status "ready sending" reached (indication AI). NT-side loses transparency (receipt LT-side informed making C/I-channel indication EI2, state change performed. Upon reception ACT= indication issued again. S/T-interface deactivated (SAI (0)), device transferred deactivated state. Wait "Wait U-transceiver waits response (tone from tone case analog loop-back) transmission wake-up signal response received within state left re-transmission wake-up tone This procedure repeated until detection tone until expiry timer this case C/I-channel indication issued, state change performed. Preliminary Data Sheet 3-51 06.99
24911
Operational Description
Operational Description
scope this section describe DFE-Q V2.1 works behaves system environment. Activation/ deactivation control procedures exemplary given programmers reference.
Reset
There different ways apply reset, either hardware reset setting software reset applying 'C/I= RES' Hardware Reset hardware reset affects design components takes effect immediately (asynchronous reset style). clock signal other than 15.36MHz master clock required reset execution. Software Reset 'RES' resets receiver activation/deactivation state machine. Transmission stopped. unconditional command therefore applicable state. Unlike hardware reset, software reset triggered 'C/I= RES' 'C/I= RES1' only effect addressed line port. C/I= resets receiver activation/deactivation state machines. unconditional command. C/I= RES1 resets receiver functions. Transmission stopped. EC-, EQcoefficients zero. conditional command. remaining line ports, system interface, relay driver/ status pins other global functions affected. Note that clock signal must provided code processing.
Power Down
Each building block DFE-Q V2.1 optimized with respect power consumption support power down mode. chapter 7.6.2 page specified max. power consumption. DFE-Q V2.1 goes power down mode U-transceiver state DEACTIVATED. DFE-Q V2.1 leaves power down mode when wake tone (TN) been detected U-interface least 800µs.
Preliminary Data Sheet
06.99
24911
Operational Description internal control logic activation/deactivation procedures event driven power saved soon four lines transits 'Deactivated' state Regarding DFE-Q V2.1 power down mode means that clock turned digital circuits (excluding IOM®-2 interface) power down mode timing signals delivered (CLS0, CLS3) internal control logic activation/deactivation procedures event driven power saved soon four lines transits DEACTIVATED state
Regarding connected power down mode means that signal sent U-interface only functions that necessary detect wake conditions kept active transmit path, receive path auxiliary functions analog line port switched power consuming mode when power down function activated. This implies following: ADC, relevant output tied GND. output buffer; outputs AOUTx/ BOUTx tied GND. internal voltage reference switched off. range loop functions deactivated.
Preliminary Data Sheet
06.99
24911
Operational Description
Layer Activation/ Deactivation Procedures
This chapter illustrates interactions during activation deactivation between station. activation initiated either stations involved. deactivation procedure initiated only exchange. This chapter shows user activate deactivate device under various circumstances. types start-up procedures supported U-transceiver: cold starts warm starts. Cold starts performed after reset require echo equalizer coefficients recalculated. This procedure typically completed after seconds depending line characteristic. Cold starts recommended activations where line characteristic changed considerably since last deactivation. warm start procedure uses coefficient saved during last deactivation. therefore completed much faster (maximum 300ms). Warm starts however restricted activations where line characteristic changed significantly since last deactivation. Both start-up procedures differ only fact that device been transferred into RESET state cold start) prior activation. Activation initialization procedure both cases identical. following sections thus apply both warm cold startups. table below summarizes existing U-interface signals specified ETSI/ ANSI. Table
Signal
U-Interface Signals
Synch. Word (SW) signal present present present present signal present present Superframe (ISW) NT-Modes signal absent absent present present LT-Modes signal absent present M-Bits
SN3T
signal normal signal
signal normal normal signal normal
Preliminary Data Sheet
06.99
24911
Operational Description
Signal SL3T
Synch. Word (SW) present present
Superframe (ISW) present present Test Mode
normal
M-Bits normal normal
signal
signal
signal
Notes:1) Alternating symbols
Must generated exchange state 'Line Active' entered from state 'EQ-Training 2B+D data must clamped exchange until act= been received from NT-side Alternating single pulses 12.5 duration spaced
Preliminary Data Sheet
06.99
24911
Operational Description
4.3.1
Complete Activation Initiated
Figure depicts procedure activation been initiated exchange side.
TI"U
TG"U
TUhprvr
VUhprvr
8yyr
actbyLT_2b1q.emf
Figure
Complete Activation Initiated
06.99
Preliminary Data Sheet
24911
Operational Description activation protocol user interactions summarized below:
IOM®-2 <----- -----> <----- <----- <----- -----> <----- (1111B) (1111B) (0111B) (1111B) (1000B) (1100B) (1100B)
IOM®-2 CI/DC C/IDI (1111B) (1111B) (1000B) (1000B) (1001B) (0111B) <----- -----> <----- -----> -----> -----> Initial state "Deactivated" Start activation Activation proceeds Confirm that terminal active Activation complete
(1100B)
----->
4.3.2
Activation with ACT-Bit Status Ignored Exchange Side
ignores ACT-bit transmitted upstream from LT-activation been initiated with ,,AR0" instead ,,AR". Activation with C/I-command "AR0" forces state machine into state "Line Active" independently ACT-bit status transmitted upstream from network. Because activation with performed with UOA-bit "0", initially only partial activation started. setting MON-2 message S-interface activated well. Activation completed after ACT-bit evaluation been enabled with C/I-command "AR".
Preliminary Data Sheet
06.99
24911
Operational Description
TI"U
TG"U
TUhprvr
VUhprvr
8yyr
actbyLT_ignact_2b1q.emf
Figure
Activation with ACT-Bit Status Ignored Exchange
Preliminary Data Sheet
06.99
24911
Operational Description activation protocol user interaction summarized below:
IOM®-2 <----- -----> (1111B) (1111B) IOM®-2 MON8 PACE MON2 (1111B) (1111B) (1101B) (1000B) (1001B) (0111B) BEH) FFH) <----- Initial state "Deactivated" -----> <----- -----> -----> -----> <----- <----- Start activation Enable control UOA-bit
<----- <-----
(0111B) (1111B)
<----- -----> <----- <-----
(1000B) (1100B) (1000B) (1100B) (1100B) (1000B) (1100B) (1101B) (0111B) -----> <----- -----> Confirm that terminal active ACT-bit status ignored Enable ACT-bit evaluation Activation complete
<-----
(1000B)
<----- Disable ACT-bit evaluation -----> ACT-bit status ignored
Preliminary Data Sheet
06.99
24911
Operational Description
4.3.3
Complete Activation Initiated
Figure depicts procedure activation been initiated terminal side.
actbyNT_2b1q.emf
Figure
Complete Activation Initiated
Preliminary Data Sheet
06.99
24911
Operational Description When initiating activation from terminal side, must DEACTIVATED state. initiated activation successful downstream C/I-code must This case DEACTIVATED state been entered from RESET TEST state (the last code this case).
IOM®-2 <----- -----> -----> <----- -----> -----> <----- <----- -----> <----- (1111B) (1111B) (0000B) (0111B)
IOM®-2 (1111B) (1111B) <----- -----> Initial state "Deactivated"
Start IOM®-clocks U-transceiver power-up Start activation (1000B) (1001B) (0111B) -----> -----> -----> Activation proceeds Confirm that terminal active Activation complete
(1000B) release (1111B) (1000B) (1100B) (1100B)
(1100B)
----->
Preliminary Data Sheet
4-10
06.99
24911
Operational Description
4.3.4
Complete Deactivation
9@68
TUhprvr
VUhprvr
8yyr
deac_2b1q.emf
Figure
Complete Deactivation
Preliminary Data Sheet
4-11
06.99
24911
Operational Description Deactivating U-interface initiated only exchange. deactivation started when device states LINE ACTIVE, PEND. TRANSPARENT TRANSPARENT.
IOM®-2
IOM®-2 DEAC (0000B) (0001B) (1111B) <----- -----> -----> Start deactivation Deactivation proceeds Deactivation complete Power down Deactivation complete
<-----
(0000B)
-----> <-----
(1111B) (1111B)
Preliminary Data Sheet
4-12
06.99
24911
Operational Description
4.3.5
Partial Activation Only)
U-transceiver only partially activated S-interface remains deactivated. When partial activation initiated LT-side, exchange options: First, case C/I-command issued after partial activation complete, exchange issue before terminal initiated complete activation request accepted. This allows exchange retain full control, even case terminal initiated activation requests. Secondly exchange issue after been received. This allows terminal activate S-interface independently exchange. this case exchange control S-interface activation procedure. U-transceiver "Synchronized state after successful partial activation. DOUT C/I-message "DC" well LT-user data sent. While C/I-messages "DI" (1111B) "TIM" (0000B) received DIN, Utransceiver will transmit "SAI" upstream. other code results "SAI" sent. U-interface signal (i.e. (1)) will transmitted continuously regardless data DIN. will transmit user data transparently downstream (signal SL3T). case last C/I-command applied "UAR", retains activation control when activation request comes from terminal (confirmation with "AR" required. With "DC" applied DIN, initiated activations will completed without necessity exchange confirmation.
IOM®-2 <----- -----> (1111B) (1111B)
IOM®-2 [C/I (1111 (1111 (0111 (1000 (1001 (0111 (1111B)] <----- -----> <----- -----> -----> -----> <----- Initial state "Deactivated"
<----- <-----
(0111B) (1111B)
Start partial activation Activation proceeds Partial activation complete Exchange retains control S-interface activation
Preliminary Data Sheet
4-13
06.99
24911
Operational Description
TUhprvr
VUhprvr
8yyr
actbyLT_uar_2b1q.emf
Figure
Only Activation
4-14 06.99
Preliminary Data Sheet
24911
Operational Description
4.3.6
Activation Initiated with Active
When already active, S-interface activated either exchange terminal. first case described here, second next section.
TI"U
TG"U
TUhprvr
VUhprvr
8yyr
actbyLT_uactiv_2b1q.emf
Figure
Initiated Activation with U-Interface Active
Preliminary Data Sheet
4-15
06.99
24911
Operational Description S-interface activated from exchange with command "AR". "UOA" changes requesting S-interface activation.
IOM®-2 <----- -----> (1111B) (1111B)
IOM®-2 [DC] (0111B) (1000B) <----- -----> <----- only activated [exchange retains control] Start complete activation
<----- -----> ----->
(1000B) (1100B) (1100B) (0111B) (1100B) -----> -----> (1000B) -----> Activation proceeds Confirm that terminal active Activation complete
<-----
(1100B)
Preliminary Data Sheet
4-16
06.99
24911
Operational Description
4.3.7
Activation Initiated with Active
When terminal requests activate S-interface (U-interface already active) cases occur: first case exchange retained control over S-interface activation. Then S-activation proceed only after explicit permission exchange with This situation discussed this section under "case second case exchange requested send order continue activation. This situation described "case this section. initiates complete activation with INFO leading "SAI" (1). Case requires exchange side acknowledge TE-activation sending "AR", Case activates completely without LT-confirmation. recognizes difference between types, procedure NT-side consequently identical both cases.
TI"U
TG"U
TUhprvr
VUhprvr
8yyr
actbyNT_uactiv1_2b1q.emf
Figure
TE-Activation with Active Exchange Control (case
Preliminary Data Sheet
4-17
06.99
24911
Operational Description Case (controlled exchange)
IOM®-2 <----- -----> -----> (1111B) (1111B) (1000B) IOM®-2 (0111B) (0111B) <----- -----> only activated Terminal requests activation Exchange notified request Exchange permits S-activation
<----- -----> (1000B) (1100B)
(1000B) (1000B)
-----> <-----
Confirm that terminal active (0111B) (1100B) -----> -----> Activation complete
<-----
(1100B)
Preliminary Data Sheet
4-18
06.99
24911
Operational Description
TI"U
TG"U
TUhprvr
VUhprvr
8yyr
actbyNT_uactiv2_2b1q.emf
Figure
TE-Activation with Active Exchange Control (case
Case control exchange)
IOM®-2 <----- -----> -----> (1111B) (0011B) (1000B)
IOM®-2 <----- -----> only activated
(0111
<----- -----> (1000B) (1100B)
(1000
----->
Terminal requests activation Exchange notified proceeding S-activation Confirm that terminal active
<-----
(1100B)
(0111 (1100
-----> ----->
Activation complete
Preliminary Data Sheet
4-19
06.99
24911
Operational Description
4.3.8
Deactivating S/T-Interface Only
following shows procedure deactivating S-interface only while leaving U-interface active. Deactivation S-interface only initiated from exchange setting "UOA" (0).
TUhprvr
VUhprvr
8yyr
deacST_2b1q.emf
Figure
Deactivation Only
Preliminary Data Sheet
4-20
06.99
24911
Operational Description
IOM®-2 <----- -----> <----- -----> <----- (1100B) (1100B) (0000B) (1111B) (1111B)
IOM®-2 [C/I (1100B) (1000B) (0111B) (0111B) (1111B)] -----> <----- <----- -----> <----- Initial state: layer activated
Deactivate S-interface only S-interface deactivated Exchange retains control
Preliminary Data Sheet
4-21
06.99
24911
Operational Description
Maintenance Test Functions
This chapter summarizes features provided DFE-Q V2.1 support maintenance functions system measurements. Three main groups distinguished: maintenance functions close open test loopbacks features facilitating recognition transmission errors test modes required system measurements next sections describe these test maintenance functions implemented used applications.
4.4.1
Test Loopbacks
Test loopbacks specified national PTTs order facilitate location defect systems. Four different loopbacks defined. position each loopback illustrated Figure 4-10.
S-BUS Loop S-Transceiver
IOM®-2
Loop U-Transceiver
IOM®-2
Loop U-Transceiver U-Transceiver Loop U-Transceiver
IOM®-2
Loop Layer-1 Controller U-Transceiver
IOM®-2
Repeater (optional)
Exchange
IOM-2
Loop Layer-1 Controller U-Transceiver
loop_2b1q.emf
Figure 4-10 Test Loopbacks Loopbacks controlled exchange. Loopbacks closed DFE-Q V2.1 itself whereas loopbacks remote controlled closed repeater Loopback closed controlled terminal. four loopback types transparent. This means bits that looped back will also passed onwards normal manner. propagation delay D-channel data identical loopbacks.
Preliminary Data Sheet 4-22 06.99
24911
Operational Description Beside remote loopback stimulation EOC- MON-channel DFE-Q V2.1 features also direct loopback control register set. next sections describe these loopbacks closed opened using C/I- MON-commands.
4.4.1.1
Analog Loopback (No.1)
Loopback closed DFE-Q V2.1 near U-interface possible. this reason called analog loopback. range attenuation receive path active. Transparent analog signals will still passed U-interface. result NT-station will activated well. Only internal loopback signal processed. Signals receive pins ignored. this reason device stays "Line Active" state (upstream ACT-bit cannot received). Loopback Activation Before analog loopback closed device should have been reset into state "Deactivated" first before Loop-back closed. Then C/I-command (activation request loopback) must applied continuously long loopback requested. Loopback Deactivation order open analog loopback again device should reset applying I-command reset). This ensures that echo coefficients equalizer coefficients will converge correctly when activating next time. example below demonstrates control loopbacks
IOM®-2 <-----
IOM®-2 (1111B) (1000B) (1111B) -----> (1010B) <----- Close loopback (1000B) -----> Activation proceeds (1001B) -----> (0111B) -----> Activation complete, closed (0001B) <----- Open loopback reset U-transceiver
<-----
Preliminary Data Sheet
4-23
06.99
24911
Operational Description
4.4.1.2
Loopback No.2 Overview
loopback several alternatives exist. Both type loopback location vary. Three loopback types belong loopback category: Complete loopback, U-transceiver downstream device B1-channel loopback, always performed U-transceiver B2-channel loopback, always performed U-transceiver loop variations closed near IOM®-interface possible. Complete Loopback complete loopback comprises both B-channels D-channel. closed either U-transceiver itself downstream device. propagation delay D-channel data identical. Single Channel Loopback Single channel loopbacks always performed within U-transceiver. this case digital data DOUT will directly back into DIN. This also applies complete loopback closed U-transceiver. Normally loopback controlled from exchange MON-0 commands LBBD, LB2. loop requests recognized executed automatically U-transceiver automode selected. loopback functions latched This allows channel channel looped back simultaneously. loopbacks opened again upon reception command RTN. Transparency Data sent downstream will passed transparent independently closed loopbacks.
Preliminary Data Sheet
4-24
06.99
24911
Operational Description
4.4.1.3
Loopback No.2 Complete Loopback
Upon receiving EOC-command LBBD automode, U-transceiver does close loopback immediately. Because intention this loopback test complete U-transceiver passes complete loopback request next downstream device (e.g. S-Transceiver). This achieved issuing C/I-code "Transparent" state states different than "Transparent". downstream device able close complete loopback, MON-8-message LBBD returned U-transceiver. This turn will close complete loopback within U-transceiver itself D-channels). remaining IOM®-information (monitor, C/I-channel well bits still read from IOM®-2-interface. this reason still possible layer-2 device deactivate despite fact that loopbacks controlled exchange. Figure 4-11 illustrates these options.
S-Transceiver 2B+D
AIL/ARL
U-Transceiver
Auto-Mode
EOC= "LBBD"
MON-8 "LBBD"
Layer-1 Controller
lp2bymon8.emf
Figure 4-11
Complete Loopback Options
complete loopback opened again U-transceiver (e.g. IEC-Q, 2091) when command MON-8-command NORM received. reset required loopback line stays active ready data transmission. typical procedure closing opening complete loopback demonstrated examples below. There always operated automode.
Complete Loopback Automode (NT-side):
IOM®-2
IOM®-2
(1000B) <---- (0111B) ----> U-interface activated without terminal confirmation with
<---- (--->
(1000B) (1100B)
Preliminary Data Sheet
4-25
06.99
24911
Operational Description IOM®-2
<---- (1100B)
IOM®-2
MON-0 LBBD (1100B) ----> (50H) <---- terminal confirmation) Close complete loop (EOC) Request downstream device close complete loopback Receive acknowledgment
<---- <----
MON-0 LBBD
(1110B) (50H) MON-0 LBBD (50H) ---->
---->
MON-8 LBBD
(F1H)
MON-0 <---- MON-0 (FFH) MON-0
(FFH)
<----
downstream device can't close, loop closed U-transceiver Open loopbacks loopbacks opened Receive acknowledgment
(FFH)
---->
Complete Loopback Transparent Mode side): IOM®-2
---> <---
IOM®-2
(1100 (1100 MON-0 LBBD (1000B) <---- (1100B) ----> (50H) <---- U-interface activated
Close complete loop (EOC) Request passes transparently U-transceiver Transmit acknowledgment Close complete loop
<----
MON-0 LBBD MON-0 LBBD MON-8 LBBD MON-0 MON-0 MON-8 NORM
(50H)
---> ---> <---- ---> --->
(50H) (F1H) (FFH) (FFH) (FFH)
MON-0 LBBD (50H)
---->
MON-0 MON-0
(FFH) (FFH)
<---- ---->
Request open loops Receive acknowledgment Open loopbacks
Preliminary Data Sheet
4-26
06.99
24911
Operational Description
4.4.1.4
Loopback No.2 Single Channel Loopbacks
Single channel loopbacks always performed directly U-transceiver. difference between B1-channel B2-channel loopback control procedure exists. They therefore discussed together. automode B1-channel closed EOC-command LB1. causes channel loopback. Becau
Other recent searches
ZFM-15+ - ZFM-15+ ZFM-15+ Datasheet
XCR3256XL - XCR3256XL XCR3256XL Datasheet
X76F041 - X76F041 X76F041 Datasheet
MIC2569 - MIC2569 MIC2569 Datasheet
IL8190N - IL8190N IL8190N Datasheet
HM00-07863LF - HM00-07863LF HM00-07863LF Datasheet
DI-75 - DI-75 DI-75 Datasheet
CA5130 - CA5130 CA5130 Datasheet
CA5130A - CA5130A CA5130A Datasheet
2SK3727-01 - 2SK3727-01 2SK3727-01 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
