Proprietary Confidential Preliminary Issue February 2002 Propriet

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RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Proprietary Confidential Preliminary Issue February 2002
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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Data Sheet
RM5261AMicroprocessor with 64-Bit System
RM5261A
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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Tel: (604) 415-6000 Fax: (604) 415-6200
PMC-Sierra, Inc. 8555 Baxter Place Burnaby, Canada
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Contacting PMC-Sierra
RM5261A trademark PMC-Sierra, Inc.
Trademarks
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None information contained this document constitutes express implied warranty PMCSierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement.
Disclaimer
PMC-2002240 (P3)
information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc.
2002 PMC-Sierra, Inc. rights reserved.
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Legal Information
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Issue Date
January 2002
Details Change
Added RM5261A-400-H valid combinations.
March 2001
Applied PMC-Sierra template existing (QED) FrameMaker document. Revised features list, Absolute Maximum Ratings table, Recommended Operating Conditions table, Electrical Characteristics table, Power Consumption table, Clock Parameters table System Interface Parameters table.
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Modified SysClock Frequency SysClock Period values Clock Parameters table.
Added reference VccInt Power Consumption table. Changed standby modes 350. Changed maximum worst case instruction 1250. Modified Note
August 2001
Added feature: 1.65 core with (p9). Changed recommended operating conditions VccInt 1.57 1.85 VccP 1.57 1.85 Added VssP commercial industrial values. Modified Note
Modified recommended operating conditions table (page 31), power consumption table (page 33), clock parameters table (page 34), system interface parameters table (page include values operation.
Modified system interface description (page read peak rate GByte/ with SysClock.
Modified features include operating frequency, Dhrystone MIPS, MFLOPS.
Issue
Revision History
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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signal, pin, names described text, such ExtRqst*, boldface typeface. field names described text, such Interrupt Mask, italic-bold typeface. instruction names, such MFHI, serif typeface.
following conventions used this datasheet:
Document Conventions
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Legal Information Revision History Table Contents List Figures Document Conventions
Integer Unit Pipeline
3.10 Floating-Point General Register File 3.12 System Control Co-Processor Registers 3.13 Virtual Physical Address Mapping 3.14 Joint 3.16 Data 3.18 Instruction Cache 3.20 Write buffer 3.21 System Interface 3.22 System Address/Data 3.23 System Command
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3.24 Handshake Signals 3.25 Non-overlapping System Interface 3.26 Enhanced Write Modes 3.27 External Requests 3.28 Interrupt Handling 3.29 Standby Mode 3.30 JTAG Interface
3.19 Data Cache
3.17 Cache Memory
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3.15 Instruction
3.11 System Control Co-processor (CP0)
Floating-Point Unit
Floating-Point Co-Processor
Integer Multiply/Divide
Register File
Registers
Superscalar Dispatch
Hardware Overview
Block Diagram
Features
List Tables
Table Contents
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
3.32 Boot-Time Modes Absolute Maximum Ratings
Power Consumption Electrical Characteristics Capacitive Load Deration System Interface Parameters Boot-Time Interface Parameters
Timing Diagrams Packaging Information RM5261A 208-QFP Package Alphabetical Pinout Ordering Information
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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RM5261A 208-QFP Package Numerical Pinout
10.1 System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
Clock Parameters
Electrical Characteristics
Recommended Operating Conditions
Descriptions
3.31 Boot-Time Options
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Figure Block Diagram Figure Registers Figure Registers Figure Kernel Mode Virtual Addressing (32-bit) Figure Pipeline
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Figure Output Timing
Figure Input Timing
Figure Clock Timing
Figure Processor Block Write
Figure Processor Block Read
Figure
Typical Embedded System Block Diagram
List Figures
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Table Integer Multiply/Divide Operations Table Floating-Point Instruction Cycles Table Boot-Time Mode Stream Table System Interface Table Cache Attributes
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Table Power Supply
Table Initialization Interface
Table JTAG Interface
Table Interrupt Interface
Table Clock/Control Interface
List Tables
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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High-performance floating-point unit: MFLOPS Single cycle repeat rate common single-precision operations some double-precision operations cycle repeat rate double-precision multiply double precision combined multiply-add operations Single cycle repeat rate single-precision combined multiply-add operation MIPS instruction Floating point multiply-add instruction increases performance signal processing graphics applications Conditional moves reduce branch frequency Index address modes (register register) Embedded application enhancements Specialized integer Multiply-Accumulate instructions 3-operand multiply instruction cache locking Optional dedicated exception vector interrupts Fully static 0.18 micron CMOS design with power down logic Standby reduced power mode with WAIT instruction 1.65 core with 208-pin package
Dual Issue superscalar microprocessor 250, 300, 350, operating frequencies Dhrystone MIPS High-performance system interface 64-bit multiplexed system address/data optimum price/performance High-performance write protocols maximize uncached write bandwidth Processor clock multipliers 2.5, 3.5, 4.5, IEEE 1149.1 JTAG boundary scan Integrated on-chip caches instruction data associative locking Virtually indexed, physically tagged Write-back write-through page basis Pipeline restart first doubleword data cache misses Integrated memory management unit Fully associative joint (shared translations) dual entries pages Variable page size increments)
Features
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
DTLB
ITLB
Store Buffer Write Buffer Read Buffer
Buffer Address Buffer
Instruction Dispatch Unit Integer Instruction Register
Instruction Register
Floating-Point Control
Floating-Point Load/Align Floating-Point Register File Packer/Unpacker
Joint Coprocessor System/Memory Control
Load Aligner
Integer Control
Integer Register File Integer Address/Adder Shifter/Store Aligner Logic Unit
Branch Adder ITLB Virtual DTLB Virtual PLL/Clocks Mult, Div, Madd
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Program Counter
Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt
Incrementer
Primary Data Cache 2-way Associative
DTag
ITag
Primary Instruction Cache 2-way Associative
Integer
Figure
Block Diagram
Block Diagram
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
General Purpose Registers
Multiply/Divide Registers
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Program Counter
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
Integer Unit
RM5261A implements MIPS Instruction Architecture therefore fully upward compatible with applications that processors implementing earlier generation MIPS IIII instruction sets. Additionally, RM5261A includes implementation specific instructions found baseline MIPS that useful embedded market place. These instructions integer multiply-accumulate (MAD) 3-operand integer multiply (MUL).
Figure Registers
RM5261A contains general purpose registers, special purpose registers integer multiplication division, program counter, condition code bits. Figure shows user visible state.
Registers
RM5261A asymmetric superscalar dispatch unit which allows issue integer instruction floating-point computation instruction simultaneously. Integer instructions include alu, branch, load/store, floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, convert. combination with high-throughput fully pipelined floating-point execution unit, superscalar capability RM5261A provides unparalleled price/performance computationally intensive embedded applications.
Superscalar Dispatch
RM5261A offers high-level integration targeted high-performance embedded applications. elements RM5261A briefly described below.
Hardware Overview
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Figure Pipeline
Figure shows RM5261A integer pipeline. illustrated figure, five integer instructions executing simultaneously.
RM5261A multiplies input SysClock 2.5, 3.5, 4.5, produce pipeline clock.
cycle
Register File
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
RM5261A consists integer adder/subtractor, logic unit, shifter. adder performs address calculations addition arithmetic operations. logic unit performs logical zero shift data moves. shifter performs shifts store alignment operations. Each these units optimized perform operations single processor cycle.
RM5261A thirty-two general purpose registers with register location (r0) hard-wired zero value. These registers used scalar integer operations address calculation. register file read ports write port fully bypassed minimize operation latency pipeline.
1I-1R: Instruction cache access Instruction virtual physical address translation Register file read, Bypass calculation, Instruction decode, Branch address calculation Issue slip decision, Branch decision Data virtual address calculation 1A-2A: Integer add, logical, shift Store Align 2A-2D: Data cache access load align Data virtual physical address translation Register file write
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integer operations, loads, stores, other non-floating-point operations, RM5261A implements 5-stage integer pipeline. addition integer pipeline, RM5261A implements extended 7-stage pipeline floating-point operations.
Pipeline
RM5261A integer unit includes thirty-two general purpose 64-bit registers, load/store architecture with single cycle operations (add, sub, logical, shift) autonomous multiply/divide unit. Additional register resources include: HI/LO result registers twooperand integer multiply/divide operations, program counter (PC).
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
DMULT, DMULTU DIV, DIVD DDIV, DDIVU
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
RM5261A incorporates high-performance fully pipelined floating-point co-processor which includes floating-point register file autonomous execution units multiply/add/convert divide/square root. floating-point coprocessor tightly coupled execution unit, decoding executing instructions parallel with, case floating-point loads stores, cooperation with integer unit. superscalar capabilities RM5261A allow floatingpoint computation instructions issue concurrently with integer instructions.
Floating-Point Unit
RM5261A floating-point execution unit supports single double precision arithmetic, specified IEEE Standard 754. execution unit broken into separate divide/square root
Floating-Point Co-Processor
multiply-add instructions, MADU, multiply operands resulting product current contents registers. multiply-accumulate operation core primitive almost signal processing algorithms, allowing RM5261A eliminate need separate engine many embedded applications.
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addition baseline MIPS integer multiply instructions, RM5261A also implements 3-operand multiply instruction, MUL. This instruction specifies that multiply result directly integer register file rather than register. portion multiply that would have normally gone into register discarded. applications where known that upper half multiply result required, using instruction eliminates necessity executing explicit MFLO instruction.
baseline MIPS specifies that results multiply divide operation placed registers. These values then transferred general purpose register file using Move-from-Hi Move-from-Lo (MFHI/MFLO) instructions.
MULT/U, MAD/U
Opcode
Operand Size Latency
Repeat Rate
Stall Cycles
Table Integer Multiply/Divide Operations
RM5261A dedicated integer multiply/divide unit optimized high-speed multiply multiply-accumulate operations. Table shows performance multiply/divide unit each operation.
Integer Multiply/Divide
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Floating-point operations include: subtract multiply divide square root reciprocal reciprocal square root conditional moves conversion between fixed-point floating-point format conversion between floating-point formats floating-point compare
Table gives latencies floating-point instructions internal processor cycles.
Table Floating-Point Instruction Cycles
fadd fsub fmult fmadd fmsub fdiv fsqrt frecip frsqrt
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21/36 21/36
21/36 38/68
fcvt.s.d
fcvt.s.w fcvt.s.l
fcvt.d.s fcvt.d.w
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
Operation
Latency
Repeat Rate
19/34 19/34 19/34 36/66
RM5261A maintains fully precise floating-point exceptions while allowing both overlapped pipelined operations. Precise exceptions extremely important object-oriented programming environments highly desirable debugging environment.
unit pipelined multiply/add unit. Overlap divide/square root multiply/add operations supported.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
fcvt.d.l fcvt.w.s fcvt.w.d fcvt.l.s fcvt.l.d fcmp fmov fmovc fabs fneg
Numbers represented single/double precision format.
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
memory management unit controls virtual memory system page mapping. consists instruction address translation buffer, ITLB, data address translation buffer, DTLB, Joint instruction data address translation buffer, JTLB, co-processor registers used virtual memory mapping sub-system.
system control coprocessor, also called coprocessor MIPS architecture, responsible virtual memory sub-system, exception control system, diagnostics capability processor. MIPS architecture, system control co-processor (and thus kernel software) implementation dependent.
3.11 System Control Co-processor (CP0)
floating-point control register space contains registers; determining configuration revision information coprocessor, control status information. These primarily used diagnostic software, exception handling, state saving restoring, control rounding modes. support superscalar operation, four read ports write ports, fully bypassed minimize operation latency pipeline. Three read ports write port used support combined multiply-add instruction while fourth read second write port allows concurrent floating-point load store.
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floating-point general register file (FGR) made thirty-two 64-bit registers. With floating-point load store double instructions (LDC1 SDC1) floating-point unit take advantage 64-bit wide data cache issue floating-point coprocessor load store doubleword instruction every cycle.
3.10 Floating-Point General Register File
Notes:
Operation
Latency
Repeat Rate
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
RM5261A incorporates system control co-processor (CP0) registers on-chip. These registers provide path through which virtual memory system's page mapping examined modified, exceptions handled, operating modes controlled (kernel user mode, interrupts enabled disabled, cache features). addition, RM5261A includes registers implement real-time cycle counting facility cache diagnostic testing assist data error detection.
Figure Registers
PageMask EntryHi EntryLo0 EntryLo1
Figure shows registers.
Context Count Status
BadVAddr Compare Cause
Random Wired PRId Config
Index
(entries protected from TLBWR)
LLAddr TagLo
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TagHi
Register number
3.13 Virtual Physical Address Mapping
user mode kernel mode supervisor mode
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This mechanism allows system software provide secure environment user processes. Bits register Status determine which virtual addressing mode used. user mode, RM5261A provides single, uniform virtual address space 32-bit mode). When operating kernel mode, four distinct virtual address spaces, totalling over 32-bit mode), simultaneously available differentiated high-order bits virtual address.
RM5261A provides three modes virtual addressing:
Used memory management
XContext CacheErr ErrorEPC
Used exception processing
3.12 System Control Co-Processor Registers
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Figure shows address space layout 32-bit operation
Figure Kernel Mode Virtual Addressing (32-bit)
0xFFFFFFFF Kernel virtual address space (kseg3) 0xE0000000 Mapped, 0.5GB
(ksseg) 0xC0000000 Mapped, 0.5GB
0xA0000000
0x9FFFFFFF Cached kernel physical address space (kseg0) 0x80000000 Unmapped, 0.5GB
3.14 Joint
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fast virtual-to-physical address translation, RM5261A uses large, fully associative that maps virtual pages their corresponding physical addresses. indicated name, joint (JTLB) used both instruction data translations. JTLB organized pairs even-odd entries, maps virtual address address space identifier into large, physical address space. mechanisms provided assist controlling amount mapped space replacement characteristics various memory regions. First, page size configured, per-entry basis, page sizes range multiples Page Mask register loaded with desired page size mapping, that size stored into
0x00000000
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Mapped, 2.0GB
(kuseg)
0x7FFFFFFF User virtual address space
Unmapped, 0.5GB
(kseg1)
0xBFFFFFFF Uncached kernel physical address space
0xDFFFFFFF Supervisor virtual address space
When RM5261A configured 64-bit microprocessor, virtual address space layout upward compatible extension 32-bit virtual address space layout.
RM5261A processors also support supervisor mode which virtual address space over (2.5 32-bit mode), divided into three regions based high-order bits virtual address.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
3.16 Data
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RM5261A implements 4-entry data (DTLB) same reasons cited above ITLB. Each DTLB entry maps page. DTLB improves performance allowing data address translation occur parallel with instruction address translation. When miss occurs data address translation DTLB, DTLB filled from JTLB. DTLB refill pseudo-LRU: least recently used entry least recently used pair entries filled. operation DTLB completely transparent user.
RM5261A implements 2-entry instruction (ITLB) minimize contention JTLB, eliminate timing critical path translating through large associative array, save power. Each ITLB entry maps page. ITLB improves performance allowing instruction address translation occur parallel with data address translation. When miss occurs instruction address translation ITLB, least-recently used ITLB entry filled from JTLB. operation ITLB completely transparent user.
3.15 Instruction
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coherency attributes generate coherent transaction types system interface. However, RM5261A cache coherency supported. Hence coherency attributes should never used.
non-coherent protocols used both code data RM5261A, with data using write-back write-through depending application.
uncached non-coherent write-back non-coherent write-through with write-allocate non-coherent write-through without write-allocate sharable exclusive update
JTLB also contains information that controls cache coherency protocol each page. Specifically, each page attribute bits determine whether coherency algorithm following:
second mechanism controls replacement algorithm when miss occurs. RM5261A provides random replacement algorithm select entry written with mapping; however, processor also provides mechanism whereby system specific number mappings locked into TLB, thereby avoiding random replacement. This mechanism uses Wired register allows operating system guarantee that certain pages always mapped performance reasons deadlock avoidance. This mechanism also facilitates design real-time systems allowing deterministic access critical software.
along with virtual address when entry written. Thus, operating systems create special purpose maps; example, entire frame buffer memory mapped using only entry.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
3.18 Instruction Cache
Cache miss refill writes bits cycle minimize cache miss penalty. line size eight instructions bytes) maximize performance communication between processor memory system. RM5261A supports cache locking. contents cache locked setting coprocessor Status register. Locking prevents contents from being overwritten subsequent cache miss. Refills occur only into This mechanism allows programmer lock critical code into cache, thereby guaranteeing deterministic behavior locked code sequence.
Uncached
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Data loads instruction fetches from uncached memory space brought from main memory register file execution unit, respectfully. caches accessed. Data stores uncached memory space directly main memory without updating data cache.
Write-back Loads instruction fetches first search cache, reading main memory only desired data cache resident. data store operations, cache first searched determine
Cache protocols supported data cache are:
data cache protected with byte parity protected with single parity bit. virtually indexed physically tagged allow simultaneous address translation data cache access.
fast, single cycle data access, RM5261A includes on-chip data cache that twoway associative with fixed 32-byte (eight words) line size.
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3.19 Data Cache
instruction cache 64-bits wide accessed each processor cycle. Accessing bits cycle allows instruction cache supply instructions cycle superscalar dispatch unit. typical code sequences where floating-point load store floating-point computation instruction being issued together loop, entire bandwidth available from instruction cache consumed.
Since cache virtually indexed, virtual-to-physical address translation occurs parallel with cache access, further increasing performance allowing these operations occur simultaneously. cache contains 24-bit physical address, valid bit, single parity bit.
RM5261A incorporates two-way associative on-chip instruction cache. This virtually indexed, physically tagged cache size protected with word parity.
RM5261A incorporates on-chip instruction data caches that accessed single processor cycle. Each cache 64-bit data path both caches accessed simultaneously. cache subsystem provides integer floating-point units with aggregate bandwidth second internal clock frequency MHz.
3.17 Cache Memory
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
most commonly used write policy write-back, where store cache line does immediately cause main memory updated. This increases system performance reducing traffic eliminating bottleneck waiting each store operation finish before issuing subsequent memory operation. Software can, however, select write-through perpage basis when appropriate, such frame buffers. Associated with data cache store buffer. When RM5261A executes store instruction, this single-entry buffer gets written with store data while comparison performed. matches, then data written into data cache next cycle that data cache accessed (the next non-load cycle). store buffer allows RM5261A execute store every processor cycle perform back-to-back stores without penalty. event store immediately followed load same address, combined merge cache write occurs such that penalty incurred. RM5261A cache attributes both instruction data caches summarized Table
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Loads instruction fetches first search cache, reading main memory only desired data cache resident. data store operations, cache first searched determine target address cache resident. resident, cache contents updated main memory written, leaving write-back cache line unchanged. cache lookup misses, then only main memory written.
Write-through without write allocate
Loads instruction fetches first search cache, reading main memory only desired data cache resident. data store operations, cache first searched determine target address cache resident. resident, cache contents updated main memory written, leaving write-back cache line unchanged. cache lookup misses, target line first brought into cache then write performed above.
Write-through with write allocate
target address cache resident. resident, cache contents updated, cache line marked later write-back. cache lookup misses, target cache line first brought into cache then write performed above.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Characteristics
Size Organization Line size Index Write policy Read order Write order miss restart after transfer Parity Cache locking
Instruction
32KB 2-way associative vAddr11.0 pAddr31.12 n.a. sub-block sequential entire line per-word
Data
32KB
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system interface consists 64-bit Address/Data with parity check bits 9-bit command bus. addition, there handshake signals interrupt inputs. interface capable transferring data between processor memory peak rate GB/sec with SysClock.
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3.21 System Interface
Writes external memory, whether cache miss write-backs stores uncached write-through addresses, on-chip write buffer. write buffer holds four 64-bit address data pairs. entire buffer used data cache write-back allows processor proceed parallel with memory update. uncached write-through stores, write buffer significantly increases performance decoupling SysAD transfers from instruction execution stream.
3.20 Write buffer
sub-block sequential
first double per-byte
write-back/write-through
pAddr31.12
vAddr11.0
2-way associative
Table Cache Attributes
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Control DRAM Address Flash/ Boot
RM5261A
Memory Controller
Latch
3.23 System Command
RM5261A interface 9-bit System Command (SysCmd) bus. command indicates whether SysAD carries address data information per-clock basis. SysAD carries address, SysCmd indicates what type transaction take place (for example, read write). SysAD carries data, SysCmd provides information about data (for example, this last data word transmitted, data contains error). SysCmd bidirectional support both processor requests external requests RM5261A. Processor requests initiated RM5261A responded external device. External requests issued external device require RM5261A respond.
3.24 Handshake Signals
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RM5261A supports one- eight-byte transfers well block transfers SysAD bus. case sub-double word transfer, three low-order address bits give byte address transfer, SysCmd indicates number bytes being transferred.
There handshake signals system interface. these, RdRdy* WrRdy*, used external device indicate RM5261A whether accept read write
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Block Write data rate, Non-block Write protocol, Output Drive strength programmable Boot time Mode Control bits. rate which processor receives data also fully controlled external device.
64-bit System Address Data (SysAD) used transfer addresses data between RM5261A rest system. protected with 8-bit parity check (SysADC). system interface configurable allow easy interfacing memory systems varying frequencies.
3.22 System Address/Data
Figure
Typical Embedded System Block Diagram
Figure shows typical embedded system using RM5261A. this example, bank DRAMs memory controller ASIC share processor's SysAD while memory controller provides separate ports boot system.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
SysCmd ValidOut* ValidIn*
Read
SysAD
Addr
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SysClock
Figure Processor Block Read
Figure shows processor block read request external agent read response. read latency cycles (ValidOut* ValidIn*), response data pattern DDDD, indicating that data transferred every clock with wait states in-between.
Data0 NData
processor reads RM5261A asserts ValidOut* simultaneously drives address read command SysAD SysCmd buses respectively. system interface RdRdy* asserted, then processor tristates drivers releases system interface slave state asserting Release*. external device then begin sending data RM5261A.
Data1 NData
Data2 NData
RdRdy* WrRdy*
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Release*
RM5261A implements non-overlapping system interface, meaning that only processor request outstanding time that request must serviced external device before RM5261A issues another request. RM5261A issue read write requests external device, whereas external device issue null write requests RM5261A.
Data3 NEOD
3.25 Non-overlapping System Interface
ValidOut* ValidIn* used RM5261A external device respectively indicate that there valid address, command, data SysAD SysCmd buses. RM5261A asserts ValidOut* when driving these buses with valid address, command, data, external device drives ValidIn* when control buses driving valid address, command, data.
ExtRqst* Release* used transfer control SysAD SysCmd buses from processor external device. When external device needs control interface, asserts ExtRqst*. RM5261A responds asserting Release* release system interface slave state.
transaction. RM5261A samples these signals before deasserting address read write requests.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Figure
SysClock
Processor Block Write
ValidOut* ValidIn*
WrRdy*
Release*
External Request pin, ExtRqst*, asserted external agent when requires mastership system interface, either perform independent transfer write interrupt register within RM5261A. independent transfer data transfer between external agents between external agent memory peripheral system interface. Following asserting ExtRqst*, RM5261A tri-states drivers allowing external agent system interface buses complete independent transfer. external agent responsible returning mastership system interface RM5261A when completed independent transfer does executing External Null cycle.
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3.27 External Requests
write reissue mode, write rate write every cycles achieved. Pipelined writes have same cycle write repeat rate, issue additional write following deassertion WrRdy*.
Write reissue mode enhancement pipelined write mode allows processor reissue missed write cycles. WrRdy* deasserted during issue phase write operation, cycle aborted processor reissued later time.
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Pipelined write mode eliminates these wait states allowing processor drive write address onto immediately after previous write data cycle. This allows higher SysAD utilization. However, high frequencies processor drive subsequent write onto prior time external agent deasserts WrRdy*, indicating that accept another write cycle. This cause write cycle missed.
RM5261A implements enhancements original R4000 write mechanism: Write Reissue Pipeline Writes. original R4000 allowed write address cycle SysAD only once every four SysClock cycles. Hence non-block write, this meant that every four cycles were wait states.
3.26 Enhanced Write Modes
RdRdy*
SysCmd
Write
NData
NData
NData
NEOD
SysAD
Addr
Data0
Data1
Data2
Data3
Figure shows processor block write using write response pattern DDDD, code boottime mode select options.
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
3.29 Standby Mode
3.30 JTAG Interface
3.31 Boot-Time Options
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boot-time serial mode stream defined Table presented processor first stream when VCCOK asserted. last transferred.
3.32 Boot-Time Modes
Immediately after VCCOK signal asserted, processor reads serial stream bits initialize fundamental operational modes. ModeClock runs continuously from assertion VCCOK.
Fundamental operational modes processor initialized boot-time mode control interface. This serial interface operates very frequency (SysClock divided 256). frequency operation allows initialization information kept cost EPROM system interface ASIC.
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RM5261A interface supports JTAG Test Access Port (TAP) boundary scan conformance with IEEE 1149.1 specification. JTAG interface especially helpful checking integrity processors connections.
Executing WAIT instruction enables interrupts causes processor enter Standby Mode. SysAD idle when wait instruction completes pipe stage, internal processor clock stops pipeline suspended. phase lock loop, PLL, internal timer/ counter, "wake input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, ColdReset* continue operate their normal fashion. SysAD idle when WAIT instruction completes pipe-stage, then WAIT treated until operation completed. Once processor Standby, interrupt, including internally generated timer interrupt, causes processor exit Standby mode resume operation where left off. WAIT instruction typically inserted idle loop operating system real time executive.
RM5261A provides means reduce amount power consumed internal core when performing useful operations. This state known Standby Mode.
RM5261A supports dedicated interrupt vector. When enabled real time executive setting Cause register), interrupts vector specific address that shared with other exception types. This capability eliminates need through normal software routine exception decode dispatch, thereby lowering interrupt latency.
3.28 Interrupt Handling
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Pclock SysClock Multiplier Mode Bits Mode 20=0 Multiply Multiply Multiply Multiply Multiply Multiply Multiply Multiply
19:18
DDDD DDxDDx DDxxDDxx DxDxDxDx DDxxxDDxxx DDxxxxDDxxxx DxxDxxDxxDxx DDxxxxxxDDxxxxxx DxxxDxxxDxxxDxxx 9-15 reserved
10:9
Non-Block Write Protocol R4000 compatible reserved pipelined write re-issue
ilic
Little endian endian
Specifies byte ordering. Logically ORed with BigEndian input signal.
Multiply Multiply Multiply
Mode 20=1
Timer Interrupt Enable/Disable
Enable timer interrupt Int5* Disable timer interrupt Int5*
Reserved: Must zero Output driver strength 100% fastest strength strength 100% strength strength
255:23 Reserved: Must zero
14:13
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Reserved: Must zero
Select Pclock SysClock Multiply Mode Integer Multipliers Half-Integer Multipliers External Width 64-bit 32-bit
VccIO Setting VccIO 3.3V VccIO 2.5V
Write-back data rate
17:16
System configuration identifiers software visible Config[21.20] register
reserved (must zero)
Reserved: Must zero
Mode Description
Mode Description
Table Boot-Time Mode Stream
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Name
ExtRqst*
Type
Input
Description
External Request
RdRdy*
Input
Read Ready
ValidOut*
Output
Valid Output
SysAD[63:0]
Input/Output
ilic
SysADC[7:0]
Input/Output
SysCmd[8:0]
Input/Output
SysCmdP
Input/Output
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Signals that processor driving valid address data SysAD valid command data identifier SysCmd bus. System Address/Data 64-bit address data communication between processor external agent. System Address/Data check
8-bit containing parity check bits SysAD during data cycles. System Command/Data identifier 9-bit command data identifier transmission between processor external agent. Reserved system Command/Data identifier parity RM5261A, unused input zero output.
Signals that external agent driving valid address data SysAD valid command data identifier SysCmd bus.
ValidIn*
Input
Valid Input
Signals that external agent accept processor write request.
WrRdy*
Input
Write Ready
Signals that external agent accept processor read.
Signals that processor releasing system interface slave state.
Release*
Output
Release Interface
Signals that system interface submitting external request.
Table System Interface
following list interface, interrupt, miscellaneous pins available RM5261A. asterisk signal name denotes active-low.
Descriptions
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Name
SysClock
Type
Input
Description
System Clock
Master clock input used system interface reference clock. output timings relative this input clock. Pipeline operation frequency derived multiplying this clock factor selected during boot initialization.
Int[5:0]*
Input
Interrupt
NMI*
Input
Non-maskable interrupt
JTDI
Input
ilic
Name
Type
JTCK
Input
JTDO
Output
JTMS
Input
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Table JTAG Interface
Description
JTAG data JTAG serial data JTAG clock input JTAG serial clock input. JTAG data JTAG serial data out. JTAG command JTAG command signal, signals that incoming serial data command data.
Non-maskable interrupt, ORed with interrupt register.
general processor interrupts, bit-wise ORed with bits interrupt register.
Name
Type
Description
Table Interrupt Interface
Quiet internal phase locked loop. Must connected through filter circuit.
VSSP
Input
Quiet
Quiet internal phase locked loop. Must connected VccInt through filter circuit.
VccP
Input
Quiet
Table Clock/Control Interface
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Name
BigEndian VCCOK
Type
Input Input
Description
Reset*
Input
Reset
ModeClock
Output
Boot mode clock
VCCIO
Input
VCCInt
Input
ilic
Name
Type
Input
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
Table Power Supply
Description
Power supply core. Power supply I/O. Ground return.
Serial boot-mode data input.
ModeIn
Input
Boot mode data
Serial boot-mode data clock output system clock frequency divided 256.
This signal must asserted reset sequence. asserted synchronously asynchronously cold reset, synchronously initiate warm reset. Reset must de-asserted synchronously with SysClock.
This signal must asserted power reset cold reset. ColdReset must de-asserted synchronously with SysClock.
ColdReset*
Input
Cold reset
When asserted, this signal indicates RM5261A that both power supplies been above recommended value more than milliseconds will remain stable. assertion VCCOK initiates reading boot-time mode control serial stream.
Allows system change processor addressing mode without rewriting mode ROM.
Table Initialization Interface
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Symbol
VTERM TCASE
Rating
Terminal Voltage with respect Operating Temperature Commercial Industrial
Limits
-0.52 +3.9
IOUT
Input Current Output Current
±203 ±204
TSTG
Storage Temperature
+125
Notes:
When VCCIO
more than output should shorted time. Duration short should exceed seconds.
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
ilic
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. minimum -2.0 pulse width less than should exceed Volts.
Unit
Absolute Maximum Ratings1
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Grade
Commercial
Speed
VCCIO
Case Temperature VCCInt
+85°C +70°C
VCCP
VSSP
3.15 3.45
Recommended Operating Conditions
1.57 1.85 3.15 3.45 1.57 1.85
Industrial
-40°C +85°C
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
ilic
specified IEEE 1149.1 (JTAG), JTMS must held high during reset avoid entering JTAG test mode. VCCP must connected VCCInt through passive filter circuit. VSSP must connected through passive filter circuit. RM5200 User's Manual recommended filter circuit.
Applying logic high state before VCCInt becomes stable recommended.
VCCIO should exceed VCCInt greater than during power-up sequence.
Notes:
1.57 1.85 3.15 3.45 1.57 1.85
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
VccIO
-0.3
VccIO
VCCIO
Parameter
Minimum
Maximum
|IOUT|
VccIO
|IOUT|=
|IOUT|
-0.3
ilic
|IOUT|
VccIO VccIO
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
|IOUT|=
Conditions
Parameter
Minimum
Maximum
Conditions
VCCIO
3.15 3.45
Electrical Characteristics
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
ilic
Dhrystone instruction mix. VCCIO supply power application dependant, typically <20% VCCInt.
Maximum supply voltage (VCCInt) with maximum temperature (TCase).
Notes:
Maximum worst case instruction 1250
1400
VCCInt Power (mWatts)3
standby active Maximum with operation2
1150
1350
Parameter
Conditions
Max1
Max1
Max1
Max1
1800
1450
1600
Speed
2100
Power Consumption
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Speed Test Parameter
SysClock High SysClock SysClock Frequency1 SysClock Period Clock Jitter SysClock SysClock Rise Time SysClock Fall Time tSCP
tSCH tSCL
Transition Transition
Symbol
Conditions
Clock Parameters
Load Derate
Parameter
Symbol
Capacitive Load Deration
Units
±150
±150
±150
Units
ns/25pF ±150 tSCP tSCP
Electrical Characteristics
Notes:
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
Operation RM5261A only guaranteed with Phase Lock Loop Enabled.
JTAG Clock Period
tJTAGCKP
ilic
ModeClock Period tModeCKP
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
Data Output2,3
mode14.13 105,6 (fastest) mode14.13 015,6 (slowest)
Parameter1
Symbol Conditions
Units
4.75 5.75
Units
Boot-Time Interface Parameters
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
Mode Data Hold
ilic
Mode Data Setup
Parameter
Symbol
Capacitive load maximum output timings Minimum output timings theoretical load condition-untested. Data Output timing applies signal pins whether tristate output only. Setup Hold parameters apply signal pins whether tristate input only. Only mode 14:13 tested guaranteed. Data shown I/O. (250 speeds only) derate times
Timings measured from 0.425 VCCIO clock 0.425 VCCIO signal 3.3V I/O. Timings measured from 0.48 VCCIO clock 0.48 VCCIO signal 2.5V I/O.
Notes:
Data Hold4
tfall above table
Data Setup4
tDS6
trise above table
SysClock cycles SysClock cycles
Speed
System Interface Parameters1
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
tRise
tFall
±tJitterIn
Figure Input Timing
SysClock
Figure Output Timing
SysClock
Data
Data
tDOmin Data Data
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
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Data
tDOmax
10.1 System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
tHigh
tLow
SysClock
Figure Clock Timing
Timing Diagrams
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
(19.80) -D1.25 (0.049) 0.20 (0.008)
C0.864 (4X) (1.25 (0.049)) 28.10 (1.106) 27.90 (1.098) 0.20 (0.008) 0.05 (0.002) -D0.27 (0.011) 0.17 (0.007) 0.08 (0.003)
0.20 (0.008) 0.05 (0.002)
28.10 (1.106) 27.90 (1.098)
VIEW
(25.50 (1.004)) 30.85 (1.215) 30.35 (1.195)
4.07 (0.160 MAX. 3.60 (0.142) 3.20 (0.126) BASE PLANE -C0.102 (0.003) SEATING PLANE 5°-16° SIDES
MIN. R0.13 (0.005) MIN. R0.13 (0.012) 0.13 (0.005) 0°-7° GAGE PLANE 0.25 (1.30 (0.051)) DETAIL 0.75 (0.029) (208X) 0.50 (0.020)
DETAIL
AFTER PLATING 0.20 (0.008) 0.09 (0.004) 0.25 (0.010) MIN.
Notes
Controlling dimensions: millimeters. Dimensions inches shown parentheses. Dimensions tolerancing ANSI Y14.5 1982. Datum plane located mold parting line coincident with lead exits plastic body bottom parting line. Datums "A-B" determined datum plane "H". determined seating plane "C". These dimensions determined datum plane "H". Dimensions include mold protrusion. Allowable protrusion 0.25/0.10" side. Lead width does include damber protrusion. Allowable damber protrusion shall 0.08 mm/0.003" total excess this dimension maximum material condition. Dambar cannot located lower radius foot.
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
numbers start with continue counter-clockwise when viewed from top.
Package dimensions conform JEDEC MS-029(FA-1).
ilic
0.50 (0.020) (204X)
DATUM PLANE
-HDATUM PLANE
30.85 (1.215) 30.35 (1.195) (25.50 (1.004))
0.20 (0.008)
Packaging Information
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
VCCIO SysAD4 SysAD36 SysAD5 SysAD37 VCCInt SysAD6 SysAD38 VCCIO SysAD7 SysAD39 SysAD8 SysAD40 VCCInt
ModeClock JTDO JTDI JTCK JTMS VCCIO VCCIO
VCCInt VCCInt VCCIO Int0*
SysAD52
VCCIO
SysCmdP
SysAD20
VCCIO
SysAD53
SysAD21
SysAD22 SysAD54 VCCInt SysAD23 SysAD55 SysAD24 SysAD56 VCCIO SysAD25 SysAD57 VCCInt SysAD26 SysAD58 SysAD27 SysAD59 VCCIO
Int2*
Int1*
Int3* Int4*
Int5* VCCIO VCCIO NMI* ExtRqst* Reset* ColdReset* VCCOK BigEndian
ModeIn
ilic
RdRdy*
WrRdy* ValidIn*
ValidOut* Release* VCCP VSSP SysClock VCCInt VCCIO
SysAD9
SysAD41 VCCIO
SysAD10 SysAD42
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VCCIO
SysAD47
SysCmd8
Function
Function
Function
Function
Function
SysAD30 SysAD62 VCCIO SysAD31
SysAD63 SysADC2 SysADC6 VCCInt SysADC3 SysADC7 VCCIO SysADC0 SysADC4 VCCInt SysADC1 SysADC5 SysAD0 SysAD32 VCCIO SysAD1 SysAD33 VCCInt
RM5261A 208-QFP Package Numerical Pinout
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
SysAD11 SysAD43 VCCInt SysAD12 SysAD44 VCCIO SysAD13 SysAD45 SysAD14 SysAD46 VCCInt SysAD15
SysCmd0 SysCmd1 SysCmd2 SysCmd3 VCCIO SysCmd4 SysCmd5 VCCIO SysCmd6 SysCmd7
SysAD16 SysAD48 VCCInt SysAD17 SysAD49 SysAD18 SysAD50
VCCIO
SysAD28 SysAD60 SysAD29 SysAD61 VCCInt
VCCIO
SysAD19
SysAD51 VCCInt
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ilic
VCCInt
VCCIO
SysAD2
SysAD34 SysAD3 SysAD35 VCCIO VCCIO
Function
Function
Function
Function
Function
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
ColdReset* ExtRqst* Int0* Int1* Int2* Int3* Int4* Int5* JTCK JTDI JTDO JTMS ModeClock ModeIn
SysAD5 SysAD6 SysAD7 SysAD8 SysAD9 SysAD10 SysAD11 SysAD12 SysAD13 SysAD14 SysAD15 SysAD16 SysAD17 SysAD18 SysAD19 SysAD20
SysAD47 SysAD48 SysAD49 SysAD50 SysAD51 SysAD52 SysAD53 SysAD54 SysAD55 SysAD56 SysAD57
VCCInt VCCInt VCCInt VCCInt
VCCInt
BigEndian
SysAD4
SysAD46
VCCInt
Function
Function
Function
Function
Function
RM5261A 208-QFP Package Alphabetical Pinout
VCCInt
VCCInt VCCInt
VCCInt VCCInt VCCInt VCCInt VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
SysAD58
SysAD59
SysAD60 SysAD61 SysAD62 SysAD63 SysADC0 SysADC1 SysADC2 SysADC3 SysADC4 SysADC5 SysADC6 SysADC7 SysClock
ilic
SysAD21
SysAD22 SysAD23 SysAD24 SysAD25 SysAD26 SysAD27 SysAD28 SysAD29 SysAD30
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
NMI* RdRdy* Release* Reset* SysAD0 SysAD1 SysAD2 SysAD3
SysAD31 SysAD32 SysAD33 SysAD34 SysAD35 SysAD36 SysAD37 SysAD38 SysAD39 SysAD40 SysAD41 SysAD42 SysAD43 SysAD44 SysAD45
SysCmd0 SysCmd1 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysCmd6 SysCmd7 SysCmd8 SysCmdP ValidIn* ValidOut* VCCInt VCCInt
VCCIO VCCIO VCCIO VCCIO VCCIO
VSSP WrRdy*
VCCIO
VCCIO
Function
Function
Function
Function
Function
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
ilic
VCCInt
VCCIO VCCIO
VCCIO VCCIO
VCCOK VCCP
RM5261AMicroprocessor with 64-Bit System Data Sheet Preliminary
RM5261A -123
Temperature Grade: (blank) commercial Industrial Package Type: MQFP with internal heat spreader
Device Maximum Speed Device Type 0.18 micron process geometry
Valid Combinations
RM5261A-250-H
RM5261A-400-H
Proprietary Confidential PMC-Sierra, Customer's Internal Document PMC-2002240, Issue
ilic
RM5261A-350-H
RM5261A-300-HI (contact sales prior design)
RM5261A-300-H
Ordering Information

Proprietary Confidential Preliminary Issue February 2002 Propriet

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