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CRSU4x2488 Telecom Standard Product Data Sheet Released
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Quad Clock Recovery Synthesis Unit 2488 Mbit/s
Data Sheet
Released Issue December, 2002
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
CRSU4x2488
PM5395
CRSU4x2488 Telecom Standard Product Data Sheet Released
Legal Informati
Patents
technology discussed this document protected more patent grants.
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information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc.
2002 PMC-Sierra, Inc.
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, Canada Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Revision History
December 2002
2001
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March 2000
Document created
Added Patent informati
Added more details. Removed note that indicated automatic insertion (mechanism provided insertion automatic).
2002
Document ported template. System side SFI-4 interface referenced QSFI-4.
November 2002
Master register 000DH Swing Bits longer reserved updated looptime settings.
Updated power numbers. Added reference Bellcore spec GR253 -CORE 1995 2000 release. Note added QSFI-4 Common Electrical Interface Overview, detailing QSFI-4 IEEE LVDS compliant when channel reset. Added Jitter Tolerance plot. Typical Intrinsic Jitter number added. LCRUTO pins documented. reset period added.
Issue
Issue Date
Details Change
CRSU4x2488 Telecom Standard Product Data Sheet Released
Table Contents
Legal Information.2 Disclaimer.2 Patents Contacting PMC-Sierra.3 Table Contents.5 List Registers.10 List Tables.15 Features SONET Section Line Regenerator Multiplexer Section List Figures Definitions Revision History.4
Description Serial Line Side Interface Signals (33).34 Clocks Alarms (12).35
9.10 Summary
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System Side Interface Signals (100).36 JTAG Test Access Port (TAP) Signals
Microprocessor Interface Signals (36)
Analog Miscellaneous Signals (32).43 Analog Power (120) Digital Power (56).48 Ground (186).50
Diagram
Description
Block Diagram.25
Application Examples.22
References.21
Applications.20
SONET In-band Forward Error Correction.19
General
Trademarks
Copyright
CRSU4x2488 Telecom Standard Product Data Sheet Released
10.1 Receive Line Interface (RXLI).56 10.2 SONET/SDH Receive Line Interface (SRLI).57 10.4 Receive In-band Forward Error Correction Decoder (RIFD) 10.4.2 Performance Monitors 10.6 Receive QSFI-4 Interface QSFI-4 I/F).61 10.7 Transmit QSFI-4 Interface QSFI-4 I/F) 10.8 Receive Section Overhead Processor (RSOP) 10.3 Receive Regenerator Multiplexor Processor (RRMP)
10.9.2 Encoder.63 10.11 SONET/SDH Transmit Line Interface (STLI) 10.12.1 Transmit Line Interface Clock Synthesis Unit Line CSU) 10.14 Microprocessor Interface 11.1 Channel Register .127 Register 1056H: TRSP Reserved .154 Register 1057H: TRSP Reserved .155 Register 1058H: TRSP Reserved .156
Test Features Description .228 12.1 Master Test Test Configuration Registers .228 12.2 JTAG Test Port .234 12.3 Boundary Scan Cells .238 12.4 JTAG Control.241 12.4.1 Controller .242
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Register 1059H: TRSP Reserved .157 Register 105B-105FH: unused.158
Normal Mode Register Description.83
10.13 JTAG Test Access Port Interface
10.12 Transmit Line Interface (TXLI)
10.10 Transmit Regenerator Section Processor (TRSP).63
10.9.1 Compensation.62
10.9 Transmit In-band Forward Error Correction Encoder (TIFE)
10.7.1 Transmit QSFI-4 Clock Synthesis Unit QSFI-4 CSU)
10.6.1 Receive QSFI-4 Clock Output.61
10.5 SONET/SDH Error Rate Monitor (SBER).61
10.4.1 Decoder.60
Functional Description
CRSU4x2488 Telecom Standard Product Data Sheet Released
12.4.3 Instructions .245 13.1 Initialization Settings .246 13.2 System side interface issues .246 13.2.2 Line side data frequency specification issues.246 13.3.1 LVDS Receiver (RXLVDS) .248 13.3.2 Serial-In Parallel-Out (SIPO).248 13.3.4 Parallel-In Serial-Out (PISO).248 13.3.3 LVDS Transmitter (TXLVDS) .248 13.3.5 LVDS Transmit Reference (TXLVREF) .248 13.5 SBER Error Rate Monitor .250 13.7 Looptime Operation.254 Register 10A1H: TXLI Control .254 Register RXLI 1102H: Control .255 Register RXLI 1102H: Control .255 Register 000CH: Diagnostic Bypass Modes .255 Register 000DH: Diagnostic Bypass Modes .256 13.10 Line Side Parallel Loopback Operation.256
Operation .246 13.1.1 TRSP Register settings: .246 13.2.1 Byte Recalculated .246 13.3 QSFI-4 Common Electrical Interface Overview .246
13.11 Line Side, same Channel Loopback Operation .257 Register 000DH: Diagnostic Loopback control.257 Register 10A1H: TXLI Control .257 Register 000FH: Bypass Loop-across .257
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Register 000DH: Diagnostic Loopback control.256 Register 10A1H: TXLI Control .256 Register TXLI 10A0H: TXLI Control .256 Register RXLI 1103H: RXLI clock training Configuration .256
13.9 System side Parallel Loopback operation.255
13.8 System side serial Loopback Operation .254
Register 000DH: Diagnostic Loopback control.254
13.6 Clocking Operations.254
13.4 Transport Overhead Bytes .248
12.4.2 States.244
CRSU4x2488 Telecom Standard Product Data Sheet Released
Register 000DH: Diagnostic Loopback control.258
Register 10A1H: TXLI Control .258 Register 000FH: Bypass Loop-across .258 13.14 Using Performance Monitoring Features .259 13.15 Transmit Encoder Error Insertion.260 14.1 Interfacing CRSU 4x2488 S/UNI-9953 SPECTRA-9953.262 14.2.1 QSFI-4 Interface Power Supply Decoupling Recommendations .263
14.3.1 Output Levels .263 Functional Timing.267 Absolute Maximum Ratings .269 17.1 Power Requirements.270 D.C. Characteristics .273 A.C. Timing Characteristics.276 19.1 Microprocessor Interface Timing Characteristics.276 19.2 Reset Timing .279 19.3 JTAG Timing.279 19.5 OC-48 Interface Timing Characteristics .282
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Thermal Information.284 Mechanical Information.285 Notes .286
Ordering Information .283
19.4 QSFI-4 Timing .281
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17.2 Power Sequencing .271
Power Information.270
15.1 QSFI-4 Interface Timing.267
14.3.2 Termination Scheme .265
14.3 Interfacing Devices .263
14.2.2 2.488 Line Side Power Supply Decoupling Recommendations
14.2 Power Supplies .263
Board Design Recommendations .262
13.14.1 Required Reset Sequence .259
13.13 Interrupt Service Routine .259
Register 12A1H: TXLI Control .258
13.12 Line side, Channel Channel Loopback Operation .257
CRSU4x2488 Telecom Standard Product Data Sheet Released
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CRSU4x2488 Telecom Standard Product Data Sheet Released
List Registers
Register 0000H: Identity Global Performance Monitor Update Trigger Register 0002H: Master Interrupt Status Register 0004H: Master Interrupt Status Register 0005H: Master Interrupt Status Register 0007H: Master Interrupt Status CH1.98 Register 0008H: Master Interrupt Status CH2.100 Register 000AH: Channel Interrupt Status .104 Register 000CH: Bypass fiber order.107 Register 000EH: Clock Control .111 Register 0010H: Diagnostics#1.115 Register 0012H: Channel SALM ENABLES .120 Register 0014H: Device Number.126 Register 1000H: QSFIM_2488 Status.128 Register 1001H: QSFIM_2488 Control .129 Register 1002H: QSFIM_2488 Reserved.131 Register 1030H: RSOP Control.132 Register 1040H: TIFE Configuration .134 Register 1042H: TIFE Error Insertion Byte .137 Register 1043H: TIFE Error Insertion Byte .139 Register 1044H: TIFE Error Insertion Byte .141 Register 1045H: TIFE Error Insertion Byte .143 Register 1031H: RSOP Interrupt Status.133 Register 1041H: TIFE Control .135 Register 0009H: Master Interrupt Status CH3.102 Register 000BH: Configuration.106 Register 0006H: Master Interrupt Status CH0.96
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Channel Register Map:.128
Register 0013H: TXENB Control.124
Register 0011H: Channel SALM Enables .116
Register 000FH: Bypass Loop-across .113
Register 000DH: Diagnostic Loopback control .109
Register 0003H: Master Interrupt Status
Register 0001H: Master Reset
CRSU4x2488 Telecom Standard Product Data Sheet Released
Register 1051H: TRSP Register Insertion.147
Register 1052H: TRSP Error Insertion .149 Register 1054H: TRSP Transmit .152 Register 105AH: TRSP Transmit B1Mask .158 Register 1070H: TRSP Aux2 Configuration .159 Register 1061H: TRSP Aux1 Register Insertion .160 Register 1081H: TRSP Aux3 Register Insertion .160
Register 1082H: TRSP Aux3 Error Insertion.161 Register 1073H: TRSP Aux2 Transmit .162 Register 1064-106AH: TRSP Aux1 Reserved .163 Register 1074-107AH: TRSP Aux2 Reserved .163 Register 1084-108AH: TRSP Aux3 Reserved .164 Register 108BH- 108FH unused .164 Register 1090H: STLI Clock Configuration .165 Register 10A0H: TXLI Control/Status.166 Register 10A1H: TXLI Control .169 Register 1100H: RXLI Interrupt Status.173 Register RXLI 1102H: Control .178 Register 1103H: RXLI Clock Training Configuration Status.180 Register 1104H: RXLI PRBS Control .183 Register 1105H: RXLI Pattern.185
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Register 1101H: RXLI Interrupt Control .176
Register 10A2H: TXLI Pattern Register .172
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Register 107BH- 107FH unused .164
Register 106BH- 106FH unused .163
Register 1083H: TRSP Aux3 Transmit .162
Register 1063H: TRSP Aux1 Transmit .162
Register 1072H: TRSP Aux2 Error Insertion.161
Register 1062H: TRSP Aux1 Error Insertion.161
Register 1071H: TRSP Aux2 Register Insertion .160
Register 1080H: TRSP Aux3 Configuration .159
Register 1060H: TRSP Aux1 Configuration .159
Register 1055H: TRSP Transmit D1D3.153
Register 1053H: TRSP Transmit Z0.151
Register 1050H: TRSP Configuration .145
CRSU4x2488 Telecom Standard Product Data Sheet Released
Register 1110H: SRLI Clock Configuration .186 Register 1120H: RRMP Configuration .187 Register 1122H: RRMP Interrupt Enable .192 Register 1124H: RRMP Receive APS.196 Register 1126H: RRMP Enable.198 Register 1128H: RRMP Line Error Counter (LSB) .201
Register 1146H: RRMP Enable (Slave) .203 Register 1160H: RIFD Configuration.204 Register 1162H: RIFD Interrupt Enable .207 Register1164H: RIFD correctable error count LSB.211 Register 1166H: RIFD line error count .213 Register 1167H: RIFD line error count .214 Register 1180H: SBER Configuration .215 Register 1181H: SBER Status .217 Register 1182H: SBER Interrupt Enable .218 Register 1184H: SBER BERM Accumulation Period (LSB) .220 Register 1186H: SBER BERM Saturation Threshold (LSB).221 Register 1187H: SBER BERM Saturation Threshold (MSB).221 Register 1188H: SBER BERM Declaring Threshold (LSB) .222 Register 1189H: SBER BERM Declaring Threshold (MSB) .222
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Register 1185H: SBER BERM Accumulation Period (MSB) .220
Register 1183H: SBER Interrupt Status .219
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Register 1165H: RIFD correctable error count MSB.212
Register 1163H: RIFD Interrupt Status .209
Register 1161H: RIFD Status .206
Register 1156H: RRMP Enable (Slave) .203
Register 1136H: RRMP Enable (Slave) .203
Register 112BH: RRMP Line Error Counter (MSB) .202
Register 112AH: RRMP Line Error Counter (LSB) .202
Register 1129H: RRMP Line Error Counter (MSB) .201
Register 1127H: RRMP Section Error Counter .200
Register 1125H: RRMP Receive .197
Register 1123H: RRMP Interrupt Status .193
Register 1121H: RRMP Status.190
Register 1106H 110FH: RXLI Reserved .186
CRSU4x2488 Telecom Standard Product Data Sheet Released
Register 118BH: SBER BERM Clearing Threshold (MSB) .223 Register 118CH: SBER BERM Accumulation Period (LSB) .224 Register 118DH: SBER BERM Accumulation Period (MSB) .224
Register 1194-11FFH: Unused .227 Register 2001H: CRSU-4X2488 Test Mode Address Force Enable.231
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Register 2003H: CRSU-4X2488 Reserved Test Register.233
Register 2002H: CRSU-4X2488Test Mode Address Force Value.232
Register 2000H: CRSU 4x2488 Master Test .229
Register 1193H: SBER BERM Clearing Threshold (MSB) .227
Register 1192H: SBER BERM Clearing Threshold (LSB) .227
Register 1191H: SBER BERM Declaration Threshold (MSB) .226
Register 1190H: SBER BERM Declaration Threshold (LSB) .226
Register 118FH: SBER BERM Saturation Threshold (MSB) .225
Register 118EH: SBER BERM Saturation Threshold (LSB) .225
Register 118AH: SBER BERM Clearing Threshold (LSB) .223
CRSU4x2488 Telecom Standard Product Data Sheet Released
List Figures
Figure 2.488 Gbit/s Stream Pure SERDES Application Figure STS-48 (STM-16) Line Regeneration Equipment (LRE) Application.24 Figure Normal Operation.25 Figure Loop-back Bypass Operation Modes.26 Figure STS-48 (STM-16) SOH, Master TRSP Figure Z0/National Growth Bytes Definition #1.65 Figure Input Observation Cell (IN_CELL) .239 Figure Bidirectional Cell (IO_CELL) .240 Figure Boundary Scan Architecture .241 Figure Controller Finite State Machine.243 Figure Generic LVDS Link Block Diagram .247 Figure CRSU 4x2488 S/UNI-9953 Interface .262 Figure PECL Levels (100K Characteristics).264 Figure CRSU 4x2488 Termination Scheme #2.266 Figure CRSU 4x2488 Termination Scheme .266 Figure Receive Side Timing Diagram .267 Figure Transmit Side Timing Diagram .267 Figure Intel Microprocessor Interface Read Timing .276 Figure System Miscellaneous Timing Diagram Timing .279 Figure QSFI-4 Master Interface Timing.281 Figure QSFI-4 Error Indication Timing Diagram.268 Figure Intel Microprocessor Interface Write Timing .278 Figure JTAG Port Interface Timing.280 Figure CRSU 4x2488 Termination Scheme #1.266 Figure Output Cell (OUT_CELL) .239 Figure Layout Output Enable Bidirectional Cells.240 Figure Typical STS-48c (STM-16c) Jitter Tolerance.57 Figure Insertion Priority
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Figure STS-48 (STM-16) SERDES Application
CRSU4x2488 Telecom Standard Product Data Sheet Released
List Tables
Table Abbreviations Used this Document Table CRSU 4x2488 Left Corner Pin-Out.30 Table CRSU 4x2488 Right Corner Pin-Out Table CRSU 4x2488 Bottom Right Corner Pin-Out Table Register Memory Table CRSU 4x2488 Channel Register .127 Table Test Mode Register Memory .228 Table Identification Register.234 Table Recommended BERM settings different data rates, meeting Bellcore Objectives .251 Table TX2488 Mode Control .167 Table Instruction Register (Length bits) .234 Table Functional Block Mode
Table Power Requirements.270 Table D.C. Characteristics (CMOS/TTL)1.273 Table Microprocessor Interface Read Access .276 Table Microprocessor Interface Write Access.278 Table JTAG Port Interface (Figure .279 Table OC-48 Interface Timing .282 Table Ordering Information .283 Table Outside Plant Thermal Information .284 Table System Miscellaneous Timing.279 Table QSFI-4 Interface Timing .281
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Table Device Compact Model .284 Table Heat Sink Requirements .284
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Table Absolute Maximum Ratings.269
Table CRSU 4x2488 Amplitudes .264
Table Recommended BERM settings different data rates, meeting Bellcore requirements .252
Table Boundary Scan Register .234
Table CRSU 4x2488 Bottom Left Corner Pin-Out.31
Table CRSU 4x2488 Modes Operation.28
CRSU4x2488 Telecom Standard Product Data Sheet Released
Definitions
AIS-L ASSP ABER CMOS ERDI FEBE FIFO HDLC LVDS
Alarm Indication Signal Line overhead Automatic Protection Switching Application Specific Standard Product Asynchronous Transfer Mode Error Rate Interleaved Parity Complementary Metal Oxide Semiconductor Cyclic Redundancy Check Clock Synthesis Unit Data Communication Channel Data Recovery Unit Emitter Controlled Logic Electrostatic Discharge Far-End Block Error First-In First-Out Clock Recovery Unit
Enhanced Remote Defect Indication Frame Check Sequence
Generic Flow Control High-level Data Link Layer Current Controlled Oscillator Jitter Attenuator Loss Cell Delineation Loss Frame Loss Pointer Loss Signal Voltage Differential Signaling Connect, indicates Unused Data Flag Network-Network Interface Optical Data Link Frame Pseudo-ECL
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PECL
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Header Check Sequence
Alarm Indication Signal
Table Abbreviations Used this Document
following table defines abbreviations CRSU4x2488.
CRSU4x2488 Telecom Standard Product Data Sheet Released
PRBS QSFI-4 RDI-L RRMP RIFD RSOP RXLI SBER SONET SRLI STLI STSI TIFE TRSP TXLI VCXO
Phase-Locked Loop Packet Over SONET Point-to-Point Protocol Pseudo-Random Sequence Quad Serdes/Framer Electrical Interface Line Remote Defect Indication Receive Regenerator Multiplexor Processor Remote Defect Indication Receive In-band Decoder Receive Section Overhead Processor Receive Line Interface SONET/SDH Error Rate Monitor Signal Degrade Synchronous Digital Hierarchy Signal Fail Synchronous Optical Network Synchronous Payload Envelopes
SONET/SDH Receive Line Interface Space Timeslot Interchange Transport Overhead
SONET/SDH Transmit Line Interface Transmit In-band Encoder Transmit Regenerator Section Processor Transmit Line Interface Unit Interval User-Network Interface Voltage Controlled Crystal Oscillator Virtual Path Indicator Wide Area Network Exclusive logic operator
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Virtual Connection Indicator
PISO
Parallel Serial Converter
CRSU4x2488 Telecom Standard Product Data Sheet Released
Features
Implements In-band Forward Error Correction (FEC) line regeneration equipment (LRE) function according ANSI Committee Letter Ballot LB812. Provides performance monitoring SONET Section, Line layer entities Regenerator Section, Multiplexer Section entities. Interfaces with downstream SONET/SDH framer devices over four 4-bit, ports that conforms timing characteristics defined Optical Internetworking Forum, contribution OIF-SFI4-01.0. Supports line loop-back from line side receive stream transmit stream system side loop-back from QSFI-4 transmit interface QSFI-4 receive stream interface.
Provides generic 16-bit microprocessor interface configuration, control, status monitoring. power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs digital outputs. PECL inputs outputs 3.3V compatible.
SONET Section Line Regenerator Multiplexer Frames SONET/SDH receive stream inserts framing bytes (A1, into transmit stream; unscrambles received stream scrambles transmit stream.
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35mmx35mm UBGA package.
Industrial temperature range (-40oC +85oC Ambient, 125oC Maximum Junction Temperature).
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Provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes.
Supports Internal Channel-to-Channel loop Function. Channel internally connected Channel Channel connected Channel
Supports loop-timing transmit stream from associated receive stream.
Implements In-band Forward Error Correction (FEC) source sink function according ANSI Committee Letter Ballot LB812.
Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer intrinsic jitter criteria.
Processes four independent bit-serial 2488.32 Mbit/s STS-48 (STM-16) data streams with onchip clock data recovery clock synthesis.
Single chip Clock Recovery Synthesis Unit supporting four SONET/SDH links operating 2488.32 Mbit/s.
General
CRSU4x2488 Telecom Standard Product Data Sheet Released
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Support Line Regeneration Equipment function with maximum delay 15.36µs looping receive stream transmit stream after error correction.
Implements In-band Forward Error Correction source function with maximum delay 15µs. Optionally inserts checksum bytes into transmit stream. Line (B2) bytes compensated inserted byte values.
Counts corrected errors software readable registers.
Implements In-band Forward Error Correction sink function with maximum delay 15µs. Frames status indication signal (FSI), optionally outputs corrected data onto receive system side interface.
SONET In-band Forward Error Correcti
Configurable force Line transmit stream.
Provides mechanism insert automatic line insertion following detection various received alarms QSFI-4 system side receive interface.
Detects loss signal (LOS), frame (OOF), loss frame (LOF), line remote defect indication (RDI-L), line alarm indication signal (AIS-L), protection switching byte failure alarms receive stream.
Extracts filters synchronization status message (S1) byte into internal register receive stream.
Extracts filters automatic protection switch (APS) channel (K1, bytes into internal registers.
Calculates compares interleaved parity (BIP) error detection codes (B1, receive stream. Calculates inserts transmit stream. Accumulates near errors (B1, errors (M1).
CRSU4x2488 Telecom Standard Product Data Sheet Released
Applications
SONET/SDH Add/Drop Multiplexers with data processing capabilities SONET/SDH ATM/POS Test Equipment
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Aand Multi-service Switches, routers, switch/routers
DWDM Terminal Multiplexers.
CRSU4x2488 Telecom Standard Product Data Sheet Released
References
Recommendation G781, "Structure Recommendations Equipment Synchronous Design Hierarchy (SDH)", January 1994.
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IEEE 1596.3-1996, "IEEE Standard Low-Voltage Differential Signals (LVDS) scaleable Coherent Interface (SCI)", March 1996
OIF-SFI4-01.0, "SFI-4: Common electrical interface between framers serializer/deserializer parts STS-192/STM-64 interfaces". September 2000.
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ITU, Recommendation G.783 "Characteristics Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks", 1996.
ITU, Recommendation G.707 "Network Node Interface Synchronous Digital Hierarchy", 1996.
ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipment Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July 1995.
ITU-T Recommendation G.703 "Physical/Electrical Characteristics Hierarchical Digital Interfaces", 1991.
417-1-1, "Generic Functional Requirements Synchronous Digital Hierarchy (SDH) Equipment", January 1996.
ANSI Letter Ballot LB812, "In-band SONET", October 1999.
ANSI T1.105-1995, "Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, Formats", 1995.
Telcordia GR-436-CORE "Digital Network Synchronization Plan", Issue Revision June 1996.
Telcordia GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue December 1995.
Telcordia GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue September 2000.
Applicable Recommendations Standards. designer required read these references during Design Planning task. Device Design Procedure, PMC1940424.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Application Examples
Optical Data Link Optical Data Link Optical Data Link Optical Data Link
rxd_n[0]/rxd_p[0] txd_n[0]/txd_p[0] rxd_n[1]/rxd_p[1] txd_n[1]/txd_p[1] rxd_n[2]/rxd_p[2] txd_n[2]/txd_p[2] rxd_n[3]/rxd_p[3] txd_n[3]/txd_p[3]
rxdata0[3:0] txdata0[3:0]
CRSU-4x2488
Figure 2.488 Gbit/s Stream Pure SERDES Applicati
PM5395 CRSU 4x2488 applicable many types equipment that implement 2.488 Gbit/s serial interfaces. When device configured pass through mode CRSU 4x2488 bridges between optical module Protocol Processor. higher level processing data done after data extracted from serial stream. this mode, CRSU 4x2488 serve SERDES data streams arbitrary formats provided optical line-side data rates 2.488Gbit/s. CRSU 4x2488 provides clock data recovery functions receive direction clock synthesis functions transmit direction. four interfaces optical module serial 2.488 Gbit/s serial streams interface Protocol Processor quad 4-bit version Optical Internetworking Forum SFI-4 Specification. Figure shows simplified connection diagram illustrate example CRSU 4x2488 connected Protocol Processor.
rxdata[3:0] txdata[3:0] rxdata[7:4] txdata[11:8] rxdata[11:8] txdata[7:4] rxdata[15:12] txdata[15:12]
rxdata1[3:0] txdata1[3:0] rxdata2[3:0] txdata2[3:0] rxdata3[3:0] txdata3[3:0]
a[13:0]
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Microprocessor
d[15:0]
Protocol Processor
CRSU4x2488 Telecom Standard Product Data Sheet Released
Figure STS-48 (STM-16) SERDES ApplicatiCRSU-4x2488
Optical Data Link Optical Data Link Optical Data Link Optical Data Link rxd_n[0]/rxd_p[0] txd_n[0]/txd_p[0] rxd_n[1]/rxd_p[1] txd_n[1]/txd_p[1] rxd_n[2]/rxd_p[2] txd_n[2]/txd_p[2] rxd_n[3]/rxd_p[3] txd_n[3]/txd_p[3] a[13:0] d[15:0] rxdata0[3:0] txdata0[3:0] rxdata1[3:0] txdata1[3:0]
rxdata1[3:0] txdata1[3:0] rxdata2[3:0] txdata2[3:0] rxdata3[3:0] txdata3[3:0] rxdata4[3:0] txdata4[3:0]
S/UNI-9953
PM5395 CRSU 4x2488 applicable equipment implementing SONET OC-48 STM-16 interfaces. Figure shows CRSU 4x2488 connected S/UNI-9953 OC-192 Physical Layer Device. CRSU 4x2488 also directly connects SPECTRA-9953 SONET/SDH Payload Extractor Aligner channelized OC-192 applications. addition bridging between optical module SONET/SDH framer devices, CRSU 4x2488 optionally performs SONET section line layer regenerator multiplex section performance monitoring. provides clock data recovery functions receive direction clock synthesis functions transmit direction. interfaces optical module serial 2.488 Gbit/s streams interface SONET/SDH framers quad 4-bit version Optical Internetworking Forum SFI-4 Specification.
txdata2[3:0]
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typical In-band Forward Error Correction (FEC) Line Regeneration Equipment (LRE) application shown Figure CRSU 4x2488 performs clock data recovery receive direction loop timed transmit direction line interface. Errors received data stream corrected using checksum bytes embedded SONET transport overhead section overhead bytes transmitted transmit line interface
typical In-band Forward Error Correction (FEC) termination application, CRSU 4x2488 performs clock data recovery receive direction clock synthesis transmit direction line interface. addition, receive direction, errors received data stream corrected using checksum bytes embedded SONET transport overhead section overhead bytes. transmit direction, checksum bytes inserted into overhead bytes.
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Microprocessor
rxdata3[3:0] txdata3[3:0]
rxdata2[3:0]
PL-4 Interface
CRSU4x2488 Telecom Standard Product Data Sheet Released
CRSU-4x2488
Optical Data Link Optical Data Link Optical Data Link Optical Data Link rxd_n[0]/rxd_p[0] txd_n[0]/txd_p[0] rxd_n[1]/rxd_p[1] txd_n[1]/txd_p[1] rxd_n[2]/rxd_p[2] txd_n[2]/txd_p[2] rxd_n[3]/rxd_p[3] txd_n[3]/txd_p[3] d[15:0] a[13:0] rxdata0[3:0] txdata0[3:0] rxdata1[3:0] txdata1[3:0] rxdata2[3:0] txdata2[3:0] rxdata3[3:0] txdata3[3:0]
Connecti
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Microprocessor
Connecti
Connecti
Connecti
Figure STS-48 (STM-16) Line Regeneration Equipment (LRE) Applicati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Block Diagram
RCLK[3:0]
SALM[3:0]
RXD[3:0]+/-
REFCLK[3:0]+/-
C0[3:0] C1[3:0]
Line
TXD[3:0]+/-
TXLI
STLI
TRSP (16)
TXENB[3:0]
TIFE
RSOP
RXLI
SRLI
RRMP (16)
RIFD
SD[3:0]
SBER
PHASE_INIT[3:0]
Microprocessor
JTAG
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TCLK[3:0]
TRSTB
D[15:0] A[13:0] RSTB INTB
Figure Normal Operati
CRSU4x2488 Telecom Standard Product Data Sheet Released
RCLK[3:0]
SALM[3:0]
SD[3:0] RXD[3:0]+/RXLI SRLI
RX_BYPASS
RRMP (16) RIFD
SDLE
REFCLK[3:0]+/-
SPLE
RSOP
SBER
PHASE_INIT[3:0]
TXD[3:0]+/C0[3:0] C1[3:0]
Microprocessor
Line
TXLI LPLE_TX LPLE_RX
TXENB[3:0]
STLI
TRSP (16)
TIFE
LBEN CHLBEN
TX_BYPASS
JTAG
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TCLK[3:0]
TRSTB
D[15:0] A[13:0] RSTB INTB
Figure Loop-back Bypass Operation Modes
CRSU4x2488 Telecom Standard Product Data Sheet Released
Descripti
CRSU 4x2488 receives SONET/SDH streams using serial interface, recovers clock data processes section line overhead. CRSU 4x2488 performs framing (A1, A2), de-scrambling, detects alarm conditions, monitors section line interleaved parity (B1, B2), accumulating error counts each level performance monitoring purposes. Line remote error indications (M1) also accumulated. Optionally, CRSU 4x2488 frames in-band forward error correction status indication byte processes checksum bytes. Detected errors accumulated corrected. Processing delay limited less than 15µs. CRSU-4x2488 transmits SONET/SDH streams using serial interface. CRSU 4x2488 synthesizes transmit clock from 155.52MHz frequency reference performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, creates section interleaved parity codes (B1) required allow performance monitoring end. Optionally, CRSU 4x2488 supports In-band functions. status indication bytes, checksum bytes inserted into transport overhead bytes line bytes compensated reflect inserted checksum bytes. Processing delay limited less than 15µs. CRSU 4x2488 also supports insertion large variety errors into transmit stream, such framing pattern errors, interleaved parity errors which useful system diagnostics tester applications. modes line rate clocks required directly CRSU-4x2488 synthesizes transmit clock recovers receive clock using 155.52 reference clock. CRSU 4x2488 outputs four differential PECL line data (TXD[3:0]+/-). CRSU-4x2488 configured, controlled monitored generic 16-bit microprocessor interface. CRSU-4x2488 also provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes. CRSU-4x2488 implemented power, +1.8 Volt, CMOS technology. compatible digital inputs TTL/CMOS compatible digital outputs. High speed inputs outputs support 3.3V compatible pseudo-ECL (PECL) CML, respectively. CRSU- 4x2488 packaged UBGA package. CRSU 4x2488 provides three main modes operation, SERDES mode, PMON mode Regenerator modes shown Table In-band optional feature that used both PMON Regenerator modes.
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PM5395 CRSU 4x2488 Quad Clock Recovery Synthesis Unit Interface monolithic integrated circuit that bridges between optical module SONET/SDH framer devices. provides clock data recovery functions receive direction clock synthesis functions transmit direction. interfaces optical module serial 2.488 Gbit/s streams interface SONET/SDH framers quad 4-bit version Optical Internetworking Forum SFI-4 Specification.
CRSU4x2488 Telecom Standard Product Data Sheet Released
SERDES Mode PMON Mode
Quad 2.488 Gbit/s serializer/deserializer
PMON Mode
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CRSU-4x2488 transmits SONET/SDH streams using serial interface. CRSU- 4x2488 synthesizes transmit clock from 155.52 frequency reference performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, creates section interleaved parity codes (B1) required allow performance monitoring end. Optionally, CRSU-4x2488 supports In-band functions. status indication bytes, checksum bytes inserted into transport overhead bytes line bytes compensated reflect inserted checksum bytes. Processing delay limited less than 15µs. CRSU-4x2488 also supports insertion large variety errors into transmit stream, such framing pattern errors, interleaved parity errors which useful system diagnostics tester applications.
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CRSU 4x2488 provides PMON Mode support DWDM other applications that require optimized devices perform SONET/SDH compliant data recovery well overhead performance monitoring. CRSU-4x2488 receives SONET/SDH streams using serial interface, recovers clock data processes section line overhead. CRSU 4x2488 performs framing (A1, A2), de-scrambling, detects alarm conditions, monitors section line interleaved parity (B1, B2), accumulating error counts each level performance monitoring purposes. Line remote error indications (M1) also accumulated. Optionally, CRSU-4x2488 frames in-band forward error correction status indication byte processes checksum bytes. Detected errors accumulated corrected. Processing delay limited less than
SERDES Mode, CRSU 4x2488 provides clock recovery synthesis four independent bit-serial streams. this mode, CRSU 4x2488 used bridge between SONET/SDH framer other devices such emerging G.709 framers. CRSU 4x2488 connects framer higher layer device quad 4-bit version SFI-4 specification.
SERDES Mode
Performance monitoring (PMON Mode) Forward Error Correction optional this mode.
channel channel
channel channel
Regenerator Mode
Quad 2.488 Gbit/s serializer/deserializer with internal regenerator connection between
Quad OC-48 (2.488 Gbit/s) serializer/deserializer with SONET/SDH overhead performance monitoring optional Forward Error Correcti
Operational Mode
Mode Descripti
Table CRSU 4x2488 Modes Operati
CRSU4x2488 Telecom Standard Product Data Sheet Released
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Both PMON Regenerator modes CRSU 4x2488 support in-band according ANSI-T1 letter ballot LB812. In-band checksum bytes inserted into SONET Transport section overhead bytes transmit direction. receive direction, errors received data stream corrected using checksum bytes embedded SONET transport overhead section overhead bytes.
CRSU 4x2488 provides Regenerator Mode support dense regenerator applications. this mode, CRSU 4x2488 provides internal connection between channel channel from channel channel CRSU 4x2488 performs clock data recovery receive direction loop timed transmit direction line interface. While regenerator mode, performance monitoring capability (PMON Mode) Forward Error Correction functions utilized. These functions flexibly configured allow conversion from OC-48 SONET/SDH streams side while supporting in-band forward error correction other side, processing delay limited less than 15.36µs.
Regenerator Mode
CRSU4x2488 Telecom Standard Product Data Sheet Released
Diagram
avdl_qs
rxdata0 rxdata0 txclk_s rxdata1 rxdata1 txclk_s rxdata2 rxdata2 txclk_s [1][2]cr0[1][2]rc1[1][2]rc2-
resk
avdh_qs
rxdata0 rxclk0+ rxdata0 rxdata1 rxclk1+ rxdata1 rxdata2 rxclk2+ rxdata2 rxdata3 [0]+ [3]+ [0]+ [3]+ [0]+ [3]+ [0]+
avdh_qs avdl_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs
vddo
vddo
vddo
vddo
vddo
d[15]
d[14]
d[13]
vddo
vddi
d[8]
d[7]
d[5]
d[6]
vddi
d[4]
d[3]
d[1]
d[2]
vddo
d[0]
vddi
a[0]
vddo
a[2]
a[1]
a[3]
a[4]
a[6]
a[5]
vddi
vddo
a[12]
rstb
a[13]
intb
vddi
lcruto[
vddo
vddo
vddo
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vddo
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a[7]
a[8]
a[11]
a[10]
a[9]
vddi
vddo
d[12]
d[11]
d[9]
vddo
d[10]
rxdata0 rxclk0- rxdata0 rxdata1 rxclk1- rxdata1 rxdata2 rxclk2- rxdata2 rxdata3 [0][3][0][3][0][3][0]-
avdl_qs
rxdata0 rxdata0 txclk_s rxdata1 rxdata1 txclk_s rxdata2 rxdata2 txclk_s [1]+ [2]+ rc0+ [1]+ [2]+ rc1+ [1]+ [2]+ rc2+
Table CRSU 4x2488 Left Corner Pin-Out
CRSU4x2488 Telecom Standard Product Data Sheet Released
Table CRSU 4x2488 Bottom Left Corner Pin-Out
c0[0] c1[0] avdh_cr avdh_cr avdh_cr
rxd[0]+
avdh_cr avdh_cr avdh_cr
rxd[0]-
avdl_0
txd[0]-
avdl_0
txd[0]+
avdl_0
refclk[ avdh_cs avdh_cs
avdl_0
avdl_0
avdl_0
avdl_0
avdl_0
vddi
vddi
avdh_cr avdl_1
avdh_cr avdl_1
refclk[ avdh_cs avdh_cs 0]u_0
avdh_tx avdl_1
avdl_1
avdh_tx avdh_tx avdh_tx
avdh_cs avdh_cs vddo
vddi
avdh_cr
avdh_cr qavd
avdh_cr
avdh_tx
avdh_cs avdh_cs avdl_1
lcruto[ avdh_cr avdh_tx refclk[ refclk[ avdl_1 1]lcruto[ c1[1] avdl_1 c0[1] rxd[1]+ rxd[1]- txd[1]- txd[1]+ avdl_1
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qavd
avdl_0
CRSU4x2488 Telecom Standard Product Data Sheet Released
Table CRSU 4x2488 Right Corner Pin-Out
vddi
rxdata3 rxdata3 [1]+ [2]+
txdata0 txdata0 txdata1 txclk1+ txdata1 txdata2 txdata2 txdata3 txclk3+ [1]+ [2]+ [0]+ [3]+ [1]+ [2]+ [0]+
rxdata3 rxdata3 vddi [1][2]-
vddi
txdata0 txdata0 txdata1 txclk1- txdata1 txdata2 txdata2 txdata3 txclk3- [1][2][0][3][1][2][0]-
avdl_qs avdh_qs avdl_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs avdh_qs avdl_qs
rxclk3+ rxdata3 txclk_s txdata0 txclk0+ txdata0 txdata1 txdata1 txdata2 txclk2+ txdata2 txdata3 txdata3 txdata3 [3]+ rc3[0]+ [3]+ [1]+ [2]+ [0]+ [3]+ [1]+ [2]+ [3]-
rxclk3- rxdata3 txclk_s txdata0 txclk0- txdata0 txdata1 txdata1 txdata2 txclk2- txdata2 txdata3 txdata3 txdata3 [3]rc3+ [0][3][1][2][0][3][1][2][3]+
vddo
vddo
vddo
vddo
vddo
vddo
sync_er sync_er sync_er r[3] r[2] r[1]
vddo
sync_er phase_i vddo r[0] nit[3]
phase_i nit[2]
phase_i phase_i vddo nit[1] nit[0]
phase_e phase_e rr[3] rr[2]
vddi
phase_e phase_e rclk[3] rr[1] rr[0]
rclk[2] vddi
rclk[1] rclk[0]
tclk[3] tclk[2] tclk[1] vddi
tclk[0]
salm[3] salm[2] vddi
salm[1]
vddo
salm[0]
vddi
trstb
vddi
lcruto[
vddo
vddo
vddo
vddo
vddo
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Table CRSU 4x2488 Bottom Right Corner Pin-Out
avdl_3 avdl_3 avdl_3
avdl_3
avdl_3
avdh_cs avdh_cs refclk[
avdh_cs avdh_cs refclk[
avdl_3
txd[3]+
avdl_3
txd[3]-
avdh_tx avdh_tx avdh_tx
avdl_3
rxd[3]-
avdh_cr avdh_cr avdh_cr
rxd[3]+
avdl_3
qavd
avdh_cr avdh_cr avdh_cr c1[3]
c0[3]
vddi
vddi
vddi
sd[1]
vddi
avdh_cr avdl_2
avdh_cr avdl_2
avdh_tx avdl_2
avdl_2 avdh_cs avdh_cs avdl_2
vddi
sd[2]
sd[3]
txenb[3 avdh_cr
avdh_cr
txenb[2 avdh_cr qavd
avdh_cr
avdh_tx
avdh_cs avdh_cs avdl_2
avdh_tx
refclk[ refclk[ avdl_2
vddo
vddo
sd[0]
txenb[0 c0[2]
txenb[1 c1[2]
avdl_2
rxd[2]+ rxd[2]-
txd[2]- txd[2]+
avdl_2
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CRSU4x2488 Telecom Standard Product Data Sheet Released
DescriptiPin Name
REFCLK[3]+ REFCLK[3]REFCLK[2]+ REFCLK[2]REFCLK[1]+ REFCLK[1]REFCLK[0]+ REFCLK[0]-
Type
Differential PECL Input
TXD[3]+ TXD[3]TXD[2]+ TXD[2]TXD[1]+ TXD[1]TXD[0]+ TXD[0]SD[3] SD[2] SD[1] SD[0]
Differential Output
AP10 AP23 AP24 AD34 AC34
Input
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AM17 AL17 AK17 AP17
TXENB[3] TXENB[2] TXENB[1] TXENB[0]
Output
AM16 AL16 AN16 AP16
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transmit differential data outputs (TXD[3:0]+/-) contain four 2488.32 Mbit/s nominal transmit streams. Each four TXD+/- outputs driven using synthesized clock from corresponding CSU. Signal swing 2/3rd standard PECL compatible with requirements most Optical Modules.
receive signal detect inputs (SD[3:0]) indicates presence valid receive signal power from Optical Physical Medium Dependent Device associated with corresponding receive differential data PECL inputs (RXD[3:0]+/-). Logic high indicates presence valid data. logic indicates loss signal. transmit enable outputs (TXENB[3:0]) controls downstream optical modules. TXENB[3:0] signals reflect value written TX_ENB[3:0] register bits. When TXENB[X] low, associated optical module enabled. When TXENB[X] high, associated optical module disabled. TXENB[3:0] asynchronous outputs. Connect. This should left unconnected.
RXD[3]+ RXD[3]RXD[2]+ RXD[2]RXD[1]+ RXD[1]RXD[0]+ RXD[0]-
Please refer Operation section discussion PECL interfacing issues.
Differential PECL Input
AP13 AP12 AP27 AP26 AA34
receive differential data PECL inputs (RXD[3:0]+/-) contain four serial receive streams. Each four receive clocks recovered from corresponding RXD[3:0]+/- stream. receive inputs internally terminated with differential 100- termination.
Note: jitter REFCLK_P REFCLK_N about will also appear transmit data output. Please refer Operation section discussion PECL interfacing issues.
AM22 AM21 AE32 AF32
differential reference clock inputs (REFCLK[3:0]+/-) provide jitter-free 155.52 nominal reference clock both clock recovery clock synthesis circuits each four independent line interfaces. practice, jitter REFCLK_P REFCLK_N inputs must less than psec 12KHz 20MHz band order CRSU4x2488 comply with Bellcore GR-253 intrinsic jitter specs transmit data outputs.
Functi
Serial Line Side Interface Signals (33)
CRSU4x2488 Telecom Standard Product Data Sheet Released
RCLK[3] RCLK[2] RCLK[1] RCLK[0]
This clock derived from digital source subject jitter. spec data frequency will cause unstable clock, section 13.2.2 TCLK[3] TCLK[2] TCLK[1] TCLK[0] Output
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SALM[3] SALM[2] SALM[1] SALM[0]
Output
section alarm (SALM[3:0]) signals report alarms four independent receive interfaces. SALM[X] configurable high when frame (OOF), loss signal (LOS), loss frame (LOF), line alarm indication signal (AIS-L), line remote defect indication (RDI-L), signal fail (SF) signal degrade (SD) alarm detected. Each alarm indication independently enabled using register bits corresponding SALM Enables Master Register 0011H 0012H. SALM when none enabled alarms active.
This clock derived from digital source subject jitter.
NOTE: TCLK[X] default disabled, enabled programming TCLKEN logic corresponding STLI Clock Configuration register 1090H, 1290H, 1490H, 1690H KILL_TX_CLK[x] register 000EH logic `0'.
TCLK[X] equal TXD[X] data clock frequency divided (nominal 77.76MHz duty cycle clock).
transmit clock (TCLK[3:0]) signals provide timing reference four independent transmit line interfaces.
NOTE: RCLK[X] default disabled, enabled programming RCLKEN logic corresponding Receive SRLI Clock Configuration register 1110H, 1310H, 1510H 1710H KILL_RX_CLK[x] register 000EH logic `0'.
Each RCLK[X] equal RXD[X] recovered clock divided (nominal 77.76 duty cycle clock).
Output
receive clock (RCLK[3:0]) signals provide timing reference four independent receive interfaces.
Name
Type
Functi
Clocks Alarms (12)
CRSU4x2488 Telecom Standard Product Data Sheet Released
RXDATA0[3:0]+/- signals updated rising edge RXCLK0+/-.
RXDATA1[3]+ RXDATA1[3]RXDATA1[2]+ RXDATA1[2]RXDATA1[1]+ RXDATA1[1]RXDATA1[0]+ RXDATA1[0]-
Analog LVDS Output
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NOTE: spec data frequency will cause unstable clock, section 13.2.2 channel receive data (RXDATA1[3:0]+/-) signals carry data received serial line interface channel (RXD[1]+/-). When SONET/SDH framing used RXDATA1[3]+/- most significant (corresponding each SONET/SDH octet, first fifth transmitted). RXDATA1[0]+/- least significant (corresponding each octet, fourth last transmitted). When SONET/SDH framing used setting RX_BYPASS_CH[1] register logic '1', RXDATA1[3]+/- first fifth transmitted, while RXDATA1[0]+/- last transmitted. choice nibble boundaries relation serial data stream RXD[1]+/- arbitrary. RXDATA1[3:0]+/- updated rising edge RXCLK1+/-.
RXCLK0+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock recovered from RXD[0]+/-.
RXCLK0+ RXCLK0-
Analog LVDS Output
channel receive clock (RXCLK0+/-) signal provide timing reference channel receive data stream.
RXDATA0[3:0]+/- updated rising edge RXCLK0+/-.
When SONET/SDH framing used setting RX_BYPASS_CH[0] register logic '1', RXDATA0[3]+/- first fifth transmitted, while RXDATA0[0]+/- last transmitted. choice nibble boundaries relation serial data stream RXD[0]+/- arbitrary.
RXDATA0[3]+ RXDATA0[3]RXDATA0[2]+ RXDATA0[2]RXDATA0[1]+ RXDATA0[1]RXDATA0[0]+ RXDATA0[0]-
When SONET/SDH framing used RXDATA0[3]+/- most significant (corresponding each SONET/SDH octet, first fifth transmitted). RXDATA0[0]+/- least significant (corresponding each octet, fourth last transmitted).
Analog LVDS Output
channel receive data (RXDATA0[3:0]+/-) signals carry data received serial line interface channel (RXD[0]+/-).
Name
Type
Functi
System Side Interface Signals (100)
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
RXCLK1+ RXCLK1-
Type
Analog LVDS Output
Functi
RXDATA3[3]+ RXDATA3[3]RXDATA3[2]+ RXDATA3[2]RXDATA3[1]+ RXDATA3[1]RXDATA3[0]+ RXDATA3[0]-
Analog LVDS Output
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RXCLK2+ RXCLK2-
Analog LVDS Output
channel receive clock (RXCLK2+/-) signal provide timing reference channel receive data stream. RXCLK1 nominal 622.08 MHz, duty cycle clock that divide line rate clock recovered from RXD[2]+/-. RXDATA2[3:0]+/- signals updated rising edge RXCLK2+/-. NOTE: spec data frequency will cause unstable clock, section 13.2.2 channel receive data (RXDATA3[3:0]+/-) signals carry data received serial line interface channel (RXD[3]+/-). When SONET/SDH framing used RXDATA3[3]+/- most significant (corresponding each SONET/SDH octet, first fifth transmitted). RXDATA3[0]+/- least significant (corresponding each octet, fourth last transmitted). When SONET/SDH framing used setting RX_BYPASS_CH[3] register logic '1', RXDATA3[3]+/- first fifth transmitted, while RXDATA3[0]+/- last transmitted. choice nibble boundaries relation serial data stream RXD[3]+/- arbitrary. RXDATA3[3:0]+/- updated rising edge RXCLK3+/-.
RXDATA2[3:0]+/- updated rising edge RXCLK2+/-.
When SONET/SDH framing used setting RX_BYPASS_CH[2] register logic '1', RXDATA2[3]+/- first fifth transmitted, while RXDATA2[0]+/- last transmitted. choice nibble boundaries relation serial data stream RXD[2]+/- arbitrary.
RXDATA2[3]+ RXDATA2[3]RXDATA2[2]+ RXDATA2[2]RXDATA2[1]+ RXDATA2[1]RXDATA2[0]+ RXDATA2[0]-
When SONET/SDH framing used RXDATA2[3]+/- most significant (corresponding each SONET/SDH octet, first fifth transmitted). RXDATA2[0]+/- least significant (corresponding each octet, fourth last transmitted).
Analog LVDS Output
channel receive data (RXDATA2[3:0]+/-) signals carry data received serial line interface channel (RXD[2]+/-).
NOTE: spec data frequency will cause unstable clock, section 13.2.2
RXDATA1[3:0]+/- signals updated rising edge RXCLK1+/-.
RXCLK1 nominal 622.08 MHz, duty cycle clock that divide line rate clock recovered from RXD[1]+/-.
channel receive clock (RXCLK1+/-) signal provide timing reference channel receive data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
RXCLK3+ RXCLK3-
Type
Analog LVDS Output
Functi
TXCLK_SRC[0]+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[0]+/-. expected that upstream device would TXCLK_SRC[0]+/as timing reference TXCLK0+/- TXDATA0[3:0]+/-.
TXDATA0[3]+ TXDATA0[3]TXDATA0[2]+ TXDATA0[2]TXDATA0[1]+ TXDATA0[1]TXDATA0[0]+ TXDATA0[0]-
Analog LVDS Input
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channel transmit data (TXDATA0[3:0]+/-) signals carry data transmitted serial line interface channel (TXD[0]+/-). When SONET/SDH framing used TXDATA0[3]+/- most significant (corresponding each SONET/SDH octet, first fifth received, example). TXDATA0[0]+/- least significant (corresponding each octet, fourth last received, example). actual nibble boundaries relation serial data stream TXD[0]+/- arbitrary. When SONET/SDH framing used setting enabling setting TX_BYPASS_CH[0] register logic '1', TXDATA0[3]+/- first fifth received, while TXDATA0[0]+/- last received. choice nibble boundaries relation serial data stream TXD[0]+/- arbitrary. TXDATA0[3:0]+/- sampled rising edge TXCLK0+/-.
TXDATA0[3:0]+/- signals sampled rising edge TXCLK0+/-.
TXCLK0+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[0]+/-. expected that TXCLK0+/- buffered version TXCLK_SRC[0]+/-.
TXCLK0+ TXCLK0-
Analog LVDS Input
channel transmit clock (TXCLK0+/-) signal provide timing reference channel transmit data stream.
TXCLK_SRC0+ TXCLK_SRC0-
Analog LVDS Output
channel transmit source clock (TXCLK_SRC[0]+/-) signal provide timing reference channel transmit data stream.
NOTE: spec data frequency will cause unstable clock, section 13.2.2
RXDATA3[3:0]+/- signals updated rising edge RXCLK3+/-.
RXCLK3+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock recovered from RXD[3]+/-.
channel receive clock (RXCLK3+/-) signal provide timing reference channel receive data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
TXCLK_SRC1+ TXCLK_SRC1-
Type
Analog LVDS Output
Functi
TXCLK_SRC2+ TXCLK_SRC2-
Analog LVDS Output
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When SONET/SDH framing used setting enabling setting TX_BYPASS_CH[1] register logic '1', TXDATA1[3]+/- first fifth received, while TXDATA1[0]+/- last received. choice nibble boundaries relation serial data stream TXD[1]+/- arbitrary. TXDATA1[3:0]+/- sampled rising edge TXCLK1+/-. channel transmit source clock (TXCLK_SRC[2]+/-) signal provide timing reference channel transmit data stream. TXCLK_SRC[2]+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[2]+/-. expected that upstream device would TXCLK_SRC[2]+/as timing reference TXCLK2+/- TXDATA2[3:0]+/-.
TXDATA1[3]+ TXDATA1[3]TXDATA1[2]+ TXDATA1[2]TXDATA1[1]+ TXDATA1[1]TXDATA1[0]+ TXDATA1[0]-
When SONET/SDH framing used TXDATA1[3]+/- most significant (corresponding each SONET/SDH octet, first fifth received, example). TXDATA1[0]+/- least significant (corresponding each octet, fourth last received, example). actual nibble boundaries relation serial data stream TXD[1]+/- arbitrary.
Analog LVDS Input
channel transmit data (TXDATA1[3:0]+/-) signals carry data transmitted serial line interface channel (TXD[1]+/-).
TXDATA1[3:0]+/- signals sampled rising edge TXCLK1+/-.
TXCLK1+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[1]+/-. expected that TXCLK1+/- buffered version TXCLK_SRC[1]+/-.
TXCLK1+ TXCLK1-
Analog LVDS Input
channel transmit clock (TXCLK1+/-) signal provide timing reference channel transmit data stream.
TXCLK_SRC[1]+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[1]+/-. expected that upstream device would TXCLK_SRC[1]+/as timing reference TXCLK1+/- TXDATA1[3:0]+/-.
channel transmit source clock (TXCLK_SRC[1]+/-) signal provide timing reference channel transmit data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
TXCLK2+ TXCLK2-
Type
Analog LVDS Input
Functi
TXCLK_SRC3+ TXCLK_SRC3-
Analog LVDS Output
TXCLK3+ TXCLK3-
Analog LVDS Input
ilic
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When SONET/SDH framing used setting enabling setting TX_BYPASS_CH[2] register logic '1', TXDATA2[3]+/- first fifth received, while TXDATA2[0]+/- last received. choice nibble boundaries relation serial data stream TXD[2]+/- arbitrary. TXDATA2[3:0]+/- sampled rising edge TXCLK2+/-. channel transmit source clock (TXCLK_SRC[3]+/-) signal provide timing reference channel transmit data stream. TXCLK_SRC[3]+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[3]+/-. expected that upstream device would TXCLK_SRC[3]+/as timing reference TXCLK3+/- TXDATA3[3:0]+/-. channel transmit clock (TXCLK3+/-) signal provide timing reference channel transmit data stream. TXCLK3+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[3]+/-. expected that TXCLK3+/- buffered version TXCLK_SRC[3]+/-. TXDATA3[3:0]+/- signals sampled rising edge TXCLK3+/-.
TXDATA2[3]+ TXDATA2[3]TXDATA2[2]+ TXDATA2[2]TXDATA2[1]+ TXDATA2[1]TXDATA2[0]+ TXDATA2[0]-
When SONET/SDH framing used TXDATA2[3]+/- most significant (corresponding each SONET/SDH octet, first fifth received, example). TXDATA2[0]+/- least significant (corresponding each octet, fourth last received, example). actual nibble boundaries relation serial data stream TXD[2]+/- arbitrary.
Analog LVDS Input
channel transmit data (TXDATA2[3:0]+/-) signals carry data transmitted serial line interface channel (TXD[2]+/-).
TXDATA2[3:0]+/- signals sampled rising edge TXCLK2+/-.
TXCLK2+/- nominal 622.08 MHz, duty cycle clock that divide line rate clock used time TXD[2]+/-. expected that TXCLK2+/- buffered version TXCLK_SRC[2]+/-.
channel transmit clock (TXCLK2+/-) signal provide timing reference channel transmit data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
TXDATA3[3]+ TXDATA3[3]TXDATA3[2]+ TXDATA3[2]TXDATA3[1]+ TXDATA3[1]TXDATA3[0]+ TXDATA3[0]-
Type
Analog LVDS Input
Functi
When SONET/SDH framing used setting enabling setting TX_BYPASS_CH[3] register logic '1', TXDATA3[3]+/- first fifth received, while TXDATA3[0]+/- last received. choice nibble boundaries relation serial data stream TXD[3]+/- arbitrary.
SYNC_ERR[3] SYNC_ERR[2] SYNC_ERR[1] SYNC_ERR[0]
PHASE_INIT[3] PHASE_INIT[2] PHASE_INIT[1] PHASE_INIT[0]
Input
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PHASE_ERR[3] PHASE_ERR[2] PHASE_ERR[1] PHASE_ERR[0]
Output
phase initialization signals indicate phase relationship between TXDATA TXCLK stable locked allowing greatest tolerance phase shift during operation. When PHASE_INIT[3:0] logic associated channel FIFO re-centered, holding fifo read write pointers same location. operation PHASE_INIT[3:0] controlled PHASE_EN QSFIM_2488 Control Register 1001H, 1201H, 1401H 1601H. phase error signals indicate phase relationship between TXDATA TXCLK exceed limits FIFO cause FIFO overflow underflow. When PHASE_ERR[3:0] logic associated channel FIFO error. Once PHASE_ERR[3:0] assert will remain asserted until cleared either associated PHASE_INIT[3:0] signal reading QSFIM_2488 Status register 1000H, 1200H, 1400H 1600H.
Output
synchronization error signal indicates associated RXCLK[3:0]+/- clock signal derived from associated RXD[3:0]+/- input signal. This signal follows state SD[3:0] input signals from optical modules well Data Lock signal. SYNC_ERR[3:0] disabled setting SYNC_ERR_EN_CH[n] TXENB Control register 0013H logic '0'. SYNC_ERR[3:0] inversion Configuration Clock Monitor register 000BH invert polarity SYNC_ERR[3:0] output pins. After reset SYNC_ERR[3:0] pins enabled logic '1'.
TXDATA3[3:0]+/- sampled rising edge TXCLK3+/-.
When SONET/SDH framing used TXDATA3[3]+/- most significant (corresponding each SONET/SDH octet, first fifth received, example). TXDATA3[0]+/- least significant (corresponding each octet, fourth last received, example). actual nibble boundaries relation serial data stream TXD[3]+/- arbitrary.
channel transmit data (TXDATA3[3:0]+/-) signals carry data transmitted serial line interface channel (TXD[3]+/-).
CRSU4x2488 Telecom Standard Product Data Sheet Released
Input
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[13]
Input
A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Input
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RSTB
Schmidt Input
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address used test register select signal which selects between normal test mode register accesses. When A[13] high, value A[12:0] selects test register access. When A[13] low, normal mode register accesses enabled. normal operation A[13] tied low. address (A[12:0]) selects specific registers during CRSU 4x2488 register accesses.
active reset (RSTB) signal provides asynchronous CRSU 4x2488 reset. RSTB Schmidt triggered input with integral pull-up resistor.
bi-directional data bus, D[15:0], used during CRSU 4x2488 read write accesses.
active write strobe (WRB) signal during CRSU 4x2488 register write access. D[15:0] contents clocked into addressed register rising edge while low.
Input
active read enable (RDB) signal during CRSU 4x2488 read access. CRSU 4x2488 drives D[15:0] with contents addressed register while low.
required (i.e. register accesses controlled using signals only), must connected inverted version RSTB input.
Input
active chip select (CSB) signal during CRSU 4x2488 register accesses.
Name
Type
Functi
Microprocessor Interface Signals (36)
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
Type
Input
Functi
Name
Type
Input Input
Analog Miscellaneous Signals (32)
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Name
Type
TRSTB
Schmidt Input
AN14 AM14 AN28 AM28
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
Analog Signal
Tri-state Output
test data output (TDO) signal carries test data CRSU 4x2488 IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. active test reset (TRSTB) signal provides asynchronous CRSU 4x2488 test access port reset IEEE P1149.1 test access port. TRSTB Schmidt triggered input with integral pull resistor. event that TRSTB used, must connected RSTB.
FunctiThese pins must tied ground during normal operation.
Input
When CRSU 4x2488 configured JTAG operation, test data input (TDI) signal carries test data into CRSU 4x2488 IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
test mode select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
test clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port.
Functi
JTAG Test Access Port (TAP) Signals
INTB tri-stated when interrupt acknowledged appropriate register access. INTB open drain output.
INTB
Output
active interrupt (INTB) when CRSU 4x2488 enabled interrupt source active. CRSU 4x2488 enabled report many alarms events interrupts.
address latch enable (ALE) active-high signal latches address A[15:0] when low. When high, internal address latches transparent. allows CRSU 4x2488 interface multiplexed address/data bus. input integral pull resistor.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
C0[3] C1[3] C0[2] C1[2] C0[1] C1[1] C0[0] C1[0]
Type
Analog Signal
AP15 AN15 AP29 AN29 AN18 AP19 AM18 AN19 AM19 AL19
Functi
Output
Connect. These pins should left unconnected.
Name
QAVD
Analog Power (120)
Type
AL14 AL28
Analog Power
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AVDH_CRU_0
Analog Power
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RESK
Analog Signal
off-chip 3.16k resistor connected between positive resistor reference Kelvin ground contact RESK QSFI-4 LVDS reference circuitry. on-chip negative feedback path will force internal 0.80V reference voltage onto RES, therefore forcing current flow through resistor.
FunctiThe quiet power (QAVD) pins analog core. QAVD should connected well-decoupled analog +3.3V supply. Please Operation section detailed information. volt analog power (AVDH) pins channel PECL data receiver, Clock Recovery Unit (CRU) Recovered Jitter Attenuator. AVDH_CRU_0 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information.
NOTE: LCRUTO[X] default disabled, enabled programming LCRUTO_EN_CHx logic register 0013H.
LCRUTO[3] LCRUTO[2] LCRUTO[1] LCRUTO[0]
Each LCRUTO [[X] equal RXD[X] recovered clock divided (nominal 155.56 duty cycle clock). Derived directly from clock recovery unit(CRU). Provides clock reference, subject less jitter than RCLK[3:0] (divide-by-32, 77.76 MHz).
Output
155Mhz recovered clock (LCRUTO [3:0]) signals provide timing reference four independent receive interfaces.
Input
Must connected ground during normal mode operation.
analog clock synthesis capacitor port (C0[3:0] C1[3:0]) pins provided four independent transmit serial streams that must meet SONET/SDH jitter transfer specifications. non-polarized capacitor attached across C0[X] C1[X].
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
AVDH_CRU_1
Type
Analog Power
AM27 AL27 AK27 AM29 AL29 AK29 AM13 AL13 AK13 AM15 AL15 AK15 AB32 AB31 AB30
Functi
Please Operation section detailed information. volt analog power (AVDH) pins channel PECL data receiver, Clock Recovery Unit (CRU) Recovered Jitter Attenuator. AVDH_CRU_2 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. volt analog power (AVDH) pins channel PECL data receiver, Clock Recovery Unit (CRU) Recovered Jitter Attenuator. AVDH_CRU_3 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. volt analog power (AVDH) pins channel PECL data Transmitter. AVDH_TX_0 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information. volt analog power (AVDH) pins channel PECL data Transmitter. AVDH_TX_1 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information. volt analog power (AVDH) pins channel PECL data Transmitter. AVDH_TX_2 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information. volt analog power (AVDH) pins channel PECL data Transmitter. AVDH_TX_3 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information. volt analog power (AVDH) pins channel PECL Clock Synthesizer Unit (CSU) PECL Reference Clock Receiver. AVDH_CSU_0 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information.
AVDH_CRU_3
Analog Power
AVDH_TX_3
Analog Power
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AVDH_CSU_0
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Analog Power
AVDH_TX_2
Analog Power
AM11 AL11 AK11
AF31 AF30 AE31 AE30
AVDH_TX_1
Analog Power
AM25 AL25 AK25
AVDH_TX_0
Analog Power
Please Operation section detailed information.
Please Operation section detailed information.
AVDH_CRU_2
Analog Power
volt analog power (AVDH) pins channel PECL data receiver, Clock Recovery Unit (CRU) Recovered Jitter Attenuator. AVDH_CRU_1 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
AVDH_CSU_1
Type
Analog Power
AL21 AK21 AL22 AK22
Functi
Please Operation section detailed information.
AVDH_CSU_3
Analog Power
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AVDL_0
Analog Power
AA30 AC30 AD30 AG34 AG33 AG32 AG31 AG30 AK28 AK26 AK24 AK23 AL20 AM20 AN20 AP20
AVDL_1
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
Analog Power
volt analog power (AVDL) pins channel AVDL_0 pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
volt analog power (AVDL) pins channel AVDL_1 pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
AVDH_QSFIM (13)
Analog Power
volt analog power (AVDH) pins channels QSFI-4 interface. AVDH_QSFIM pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information.
Please Operation section detailed information.
volt analog power (AVDH) pins channel PECL Clock Synthesizer Unit (CSU) PECL Reference Clock Receiver. AVDH_CSU_3 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply.
Please Operation section detailed information.
AVDH_CSU_2
Analog Power
volt analog power (AVDH) pins channel PECL Clock Synthesizer Unit (CSU) PECL Reference Clock Receiver. AVDH_CSU_2 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply.
volt analog power (AVDH) pins channel PECL Clock Synthesizer Unit (CSU) PECL Reference Clock Receiver. AVDH_CSU_1 pins should connected through passive filtering networks well-decoupled +3.3V analog power supply.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
AVDL_2
Type
Analog Power
AK14 AK12 AK10
Functi
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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AVDL_QSFIM (16)
Analog Power
volt analog power (AVDL) pins channels QSFI-4 interface. AVDL_QSFIM pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
AVDL_3
Analog Power
volt analog power (AVDL) pins channel AVDL_3 pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
volt analog power (AVDL) pins channel AVDL_2 pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
CRSU4x2488 Telecom Standard Product Data Sheet Released
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VDDO (33)
Digital Switching Power
AP18 AN17 AK20
digital switching power (VDDO) pins should connected well-decoupled +3.3V digital power supply.
Name
Type
Functi
Digital Power (56)
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
VDDI (23)
Type
Digital Core Power
AK19 AK18 AL18 AK16 AH30 AH31
Functi
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digital core power (VDDI) pins should connected welldecoupled +1.8V digital power supply.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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Please Operation section detailed information.
(186)
Digital Ground
ground (VSS) pins should connected inductance ground plane connected both digital analog power supplies.
Name
Type
Functi
Ground (186)
CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
(continued)
Type
AL10 AM10 AN10 AN11 AP11 AL12 AM12 AN12 AN13 AP14 AN21 AP21
Functi
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
(continued)
Type
AN22 AP22 AL23 AM23 AN23 AL24 AM24 AN24 AN25 AP25 AL26 AM26 AN26 AP30 AP31 AP32 AP33 AP34 AN30 AN31 AN32 AN33 AN34 AM30 AM31 AM32 AM33 AM34 AL30 AL31 AL32 AL33 AL34 AK30 AK31 AK32 AK33 AK34 AJ30 AJ31 AJ32 AJ33
Functi
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
(continued)
Type
AJ34 AH32 AH33 AH34 AF33 AF34 AE33 AE34 AD31 AD32 AD33 AC31 AC32 AC33 AB33 AB34 AA31 AA32 AA33
Functi
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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CRSU4x2488 Telecom Standard Product Data Sheet Released
Name
(continued)
Type
AP28 AN27
Functi
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
Notes Description CRSU 4x2488 inputs bidirectionals present minimum capacitive loading operate CMOS/TTL logic levels except: REFCLK+/-, RXD[3:0]+/- pins which operate pseudo-ECL (PECL) logic levels, TXD[3:0]+/- pins which operate 3.3-V levels RXDATA(3.0)[3:0]+/-, RXCLK(3.0)+/-, TXDATA(3.0)[3:0]+/-, TXCLK(3.0)+/-, TXCLK(3.0)_SRC+/- which operate LVDS logic levels.
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Digital Digital Digital LVDS LVDS PECL PECL Inputs Outputs Bidir Input Output Input Output Analog Total Interface Serial Line Side Interface SFI-4 Interface Clocks Alarms Microprocassor JTAG Test Access Port Analog misc Analog Power Analog Power Digital Power Digital Power Ground Totals
9.10
Summary
CRSU4x2488 Telecom Standard Product Data Sheet Released
CRSU 4x2488 digital inputs 3.3V tolerant. Inputs ALE, RSTB, TMS, TRSTB have internal pull-up resistors.
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Hold device reset condition until device power supplies within their nominal voltage range.
Before input activity occurs, ensure that device power supplies within their nominal voltage range.
protection structures pads necessary exercise caution when powering device down. protection devices behave diodes between power supply pins from pins power supply pins. Under extreme conditions possible damage these protection devices trigger latch Please adhere recommended power supply sequencing described Operation section this document.
analog power pins sensitive noise. They must isolated from digital power pins. Care must taken correctly decouple these pins. (Please refer Note: PMC-2011065).
mandatory that every Analog power (QAVD, AVDH, AVDL) connected printed circuit board power plane ensure reliable device operation.
mandatory that every digital power (VDDI, VDDO) connected printed circuit board power plane ensure reliable device operation.
mandatory that every digital ground (VSS) connected printed circuit board ground plane ensure reliable device operation.
CRSU 4x2488 digital outputs bidirectionals which have 12mA drive capability are: D[15:0].
CRSU 4x2488 digital outputs bidirectionals which have drive capability are: RCLK[3:0], TCLK[3:0], INTB.
CRSU 4x2488 digital outputs bidirectionals which have drive capability are: SALM[3:0], TXENB[3:0], SYNC_ERR[3:0], PHASE_ERR[3:0].
CRSU4x2488 Telecom Standard Product Data Sheet Released
Functional Descripti
Operational Mode
SERDES Mode PMON Mode
Functional Blocks
RXLI, CRU, QSFI-4 TXLI, line CSU, QSFI-4 TXLI, line CSU, STLI, TRSP, RSOP, QSFI-4
Optional Blocks
RXLI, CRU, SRLI, RRMP, SBER, QSFI-4
Regenerator Mode
RXLI, TXLI, line
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
Initially upon start-up, locks reference clock, REFCLK. When frequency recovered clock within approximately reference clock, attempts lock data. Once data lock loss signal detector enabled (register 1103 10), reverts reference clock data transitions occur within programmable number periods recovered clock drifts beyond 1000 reference clock.
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clock recovery unit (CRU) recovers clock from incoming serial data stream compliant with SONET jitter tolerance requirements. clock recovery unit utilizes 155.52 reference clock train monitor clock recovery PLL. Under loss signal conditions, clock recovery unit continues output line rate clock that locked this reference keep alive purposes. clock recovery unit provides status bits that indicate whether locked data reference, register 1103 Channel also supports serial loop-back, register 1102 signal detect input, when deasserted squelches normal input data.
four Receive Line Interface blocks (RXLI) allow direct interface CRSU 4x2488 four independent optical data link modules (ODLs) other medium interfaces. Each block performs clock data recovery incoming 2488.32 Mbit/s data stream converts data into 16-bit wide format.
10.1
Receive Line Interface (RXLI)
FEC: RIFD, TIFE PMON: SRLI, RRMP, SBER, QSFI-4 STLI, TRSP, RSOP, QSFI-4 FEC: RIFD, TIFE
Table Functional Block Mode
This section provides detail functional description CRSU 4x2488. Table outlines blocks that used main modes operation optional functions their corresponding blocks.
CRSU4x2488 Telecom Standard Product Data Sheet Released
Figure Typical STS-48c (STM-16c) Jitter Tolerance
Amplitude Tolerable Jitter (UI)
GR-253 Specificati
PM5395 CRSU-4x2488
1000
10000
100000
1000000
Jitter Tolerance
10000000
loop filter transfer function optimized enable track jitter, tolerate minimum transition density expected received SONET data signal. total loop dynamics clock recovery yield jitter tolerance that exceeds minimum tolerance specified SONET equipment GR-253-CORE. Please refer Figure below.
Frequency (Hz)
10.2
SONET/SDH Receive Line Interface (SRLI)
four SONET/SDH receive line interface blocks perform initial byte frame alignment four independent incoming 2488 Mbit/s data streams based SONET/SDH A1/A2 framing pattern.
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When transmit clock derived from recovered clock (loop timing), accuracy transmit clock directly related REFCLK reference accuracy case loss signal condition. meet Bellcore GR-253-CORE SONET Network Element free-run accuracy specification, reference must within +/-4.6 ppm. When loop timed, REFCLK accuracy relaxed +/-20 ppm.
100000000
CRSU4x2488 Telecom Standard Product Data Sheet Released
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performance these framing algorithms presence errors random data robust. When looking frame alignment performance each algorithm dominated alignment algorithm used SRLI which always examines framing bytes. probability falsely framing random data less than 0.00001% either algorithm. Once frame alignment, RRMP continuously monitors framing pattern. When incoming stream contains 10-3 BER, first algorithm provides 99.75% probability that mean time between occurrences seconds second algorithm provides 99.75% probability that mean time between occurrences minutes.
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RRMP frames data stream operating with upstream pattern detector (SRLI) that searches occurrences A1/A2 framing pattern. Once SRLI found A1/A2 framing pattern, RRMP monitors next occurrence framing pattern 125µs later. framing pattern algorithms provided improve performance presence errors. selection algorithm done setting ALGO2 RRMP Configuration Register, 1120H, 1320H, 1520H 1720H. algorithm (ALGO2 logic RRMP declares frame alignment (removes defect) when bytes seen error-free first STS-12 (STM-4) STS-48 (STM-16) stream. algorithm (ALGO2 logic RRMP declares frame alignment (removes defect) when only last byte first four bits first byte seen error-free first STS-12 (STM-4) STS-48 (STM-16) stream. Once frame, RRMP monitors framing pattern declares when more errors framing pattern detected four consecutive frames. Again, depending upon algorithm either framing bytes framing bits examined errors framing pattern.
CRSU 4x2488 contains Receive Regenerator Multiplex section Processor (RRMP) blocks. They grouped into four sets RRMPs each. Each group processes transport overhead four independent received data streams. Within each RRMPs, first RRMP processes first STS-3 (STM-1) multiplexing structure STS-48 (STM-16) stream. second RRMP processes next STS-3 (STM-1) streams
10.3
Receive Regenerator Multiplexor Processor (RRMP)
While frame, SRLI monitors receive data stream occurrence A1/A2 framing pattern. SRLI adjusts byte frame alignment when three consecutive bytes followed three consecutive bytes occur data stream. SRLI informs downstream RRMP framer blocks when framing pattern been detected reinitialize transport frame alignment. While frame, SRLI maintains same byte frame alignment until RRMP declares frame.
CRSU4x2488 Telecom Standard Product Data Sheet Released
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RRMP extracts filters K1/K2 bytes three frames. filtered K1/K2 bytes accessible through microprocessor readable registers. RRMP also monitors unfiltered K1/K2 bytes detect byte failure (APSBF) defect, line alarm indication signal (AIS-L) defect line remote defect indication (RDI-L) defect. byte failure declared when twelve consecutive frames have been received where three consecutive frames contain identical bytes. byte failure removed upon detection three consecutive frames containing identical bytes. detection invalid codes must done software polling K1/K2 register. Line declared when pattern observed bits byte three five consecutive frames. Line removed when pattern other than observed three five consecutive frames. Line declared when pattern observed bits byte three five consecutive frames. Line removed when pattern other than observed three five consecutive frames. RRMP extracts filters synchronization status message (SSM) eight frames. filtered accessible through microprocessor readable registers.
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RRMP extracts line remote error indication (REI-L) errors from byte STS-1 (STM-0) accumulates them microprocessor readable 24-bit saturating counter second accumulation time). Optionally, block line errors accumulated.
RRMP calculates line BIP-8 error detection codes (B2) de-scrambled line overhead synchronous payload envelope bytes constituent STS-1 (STM-0). line BIP-8 code based interleaved parity calculation using even parity. calculated BIP8 codes compared with BIP-8 codes extracted from byte constituent STS-1 (STM-0) following frame after de-scrambling. difference indicates line BIP-8 error. RRMP accumulates line BIP-8 errors microprocessor readable saturating counter second accumulation time). Optionally, block errors accumulated.
RRMP optionally de-scrambles received data stream.
RRMP calculates section BIP-8 error detection code (B1) scrambled data complete frame. section BIP-8 code based interleaved parity calculation using even parity. calculated BIP-8 code compared with BIP-8 code extracted from byte STS-1 (STM-0) following frame after de-scrambling. difference indicates section BIP-8 error. RRMP accumulates section BIP-8 errors microprocessor readable 16-bit saturating counter second accumulation time). Optionally, block section BIP-8 errors accumulated.
RRMP also detects loss frame (LOF) defect loss signal (LOS) defect. declared when frame (OOF) condition exists total period during which there continuous frame period output removed when frame condition exists continuous period declared when continuous period without transitions received data stream detected. removed when consecutive framing patterns found (based algorithm algorithm during intervening time (one frame) there continuous periods without transitions received data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
RIFD block decodes In-band Forward Error Correction checksum bytes imbedded section line overhead bytes performs error correction received stream. Each RIFD block processes four STS-48 receive streams interfaces four upstream RRMP blocks. Error correction disabled under LOS, AIS-L alarm conditions.
10.4.1
Decoder
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RIFD provides performance monitors: line monitor error correction monitor.
10.4.2
Performance Monitors
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decoder extracts Status Indication (FSI) byte from transport overhead determine whether error correction enabled disabled transmitter. Section defects such loss frame, loss signal, AIS-L/MS-AIS cause decoder disable error correction beginning next frame boundary. Microprocessor control provided disable error correction with decoder delay added removed. decoder optionally programmed generate interrupt when enables disables decoder.
decoding function adds 14.6 delay data when running nominal STS48/STM-16 data rate.
decoder performs error correction using (4359, 4320) shortened code derived from (8191, 8152) binary code. uses extracted check bits assemble eight interleaved (4359,4320) code blocks provide coverage each STS-48/STM-16 row.
Decoder extracts check bits from in-band compliant data streams uses them correct random errors each STS-48/STM-16 row. check bits located transport overhead. decoder corrects payload bytes, line/MS overhead bytes, check bits. Section/RS overhead bytes corrected because they included in-band coverage.
10.4
Receive In-band Forward Error Correction Decoder (RIFD)
RRMP block provides de-scrambled data frame alignment indication signals Receive In-band Forward Error Correction Decoder blocks (RIFD).
maskable interrupt activated indicate change status frame (OOF), loss frame (LOF), loss signal (LOS), line remote defect indication (RDI-L), line alarm indication signal (AIS-L), change synchronization status message (COSSM), change bytes (COAPS), byte failure (APSBF), section BIP-8 errors, line BIP-8 errors line remote error indication (REI-L) events.
RRMP optionally inserts line alarm indication signal (AIS-L).
CRSU4x2488 Telecom Standard Product Data Sheet Released
SBER block provides independent error rate monitoring circuits (BERM block). used monitor Multiplexer Section (B2) with BERM block dedicated monitor Signal Degrade (SD) alarm other BERM block dedicated monitor Signal Fail (SF) alarm. These alarms then used control system level features such Automatic Protection Switching (APS). BERM block utilizes sliding window based algorithm. This algorithm provides much superior detection, clearing false detection performance than simple jumping window (i.e. using counter that reset polled regular interval) algorithm.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
Each 4-bit slice ReceiveQSFI-4 interface uses 2.488 Gbit/s recovered clock from associated it's timing source associated receive QSFI-4 interface. frequency RXCLK[n] therefore locked line side clock phase RXCLK[n] guaranteed locked line side clock.
10.6.1
Receive QSFI-4 Clock Output
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Each four independent Receive QSFI-4 Interface blocks carries received data from associated 2.488 Gbit/s input data stream nibble-wide format. clock data phase locked associated receive data stream. When CRSU 4x2488 processing SONET/SDH data, nibbles software configured aligned incoming octets. When processing arbitrary data streams, nibbles aligned underlying structure received data stream.
10.6
Receive QSFI-4 Interface QSFI-4 I/F)
10.5
SONET/SDH Error Rate Monitor (SBER)
performance monitors optionally programmed generate interrupts when errors and/or corrected errors detected.
correction monitor counts number errors that have been corrected. error count accumulated 21-bit register which allows second accumulation time frames contain maximum number errors that correctable RIFD. This register read microprocessor, value used find from last decoding point network.
line monitor calculates line received STS-48/STM-16 frame compares bytes following received frame. differences comparison indicate error. monitor counts either BIP-8 block BIP-24 errors accumulates number errors 22-bit register which allows second accumulation time BIP-8 errors second accumulation time block BIP-24 errors. This register read microprocessor. calculations performed either corrected data stream uncorrected data stream.
CRSU4x2488 Telecom Standard Product Data Sheet Released
10.7.1
Transmit QSFI-4 Clock Synthesis Unit QSFI-4 CSU)
RSOP frames data stream operating with upstream pattern detector, SRLI, that searches occurrences SONET framing pattern bit-serial data stream. RSOP provides framing algorithms that provide improved performance presence errors. RSOP provides appropriate clock frame alignment indication signals downstream circuitry.
TIFE inserts parity bits into section line overhead bytes. Consequently, bytes carried transmit QSFI-4 interface longer valid must compensated. compensation block maintains registers. first scratch register cleared start every frame. accumulates changes (XOR) between line overhead bytes delivered transmit QSFI-4 interface modification TIFE parity bits insertion. second register history register. maintains record modifications line overhead bytes parity positions. every frame, contents scratch history register XOR'ed together result stored back history register. bytes delivered downstream transmit regenerator section processor block (TRSP) bytes carried transmit QSFI-4 interface contents history register. compensated bytes used calculate parity bits. TRSP should recalculate bytes frame after TIFE placed bytes frame. This requires that B2DISABLE register registers 1052, 1062, 1072 1082 channel equivalent registers other channels.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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10.9.1
Compensati
Transmit In-band Forward Error Correction block inserts In-band Forward Error Correction checksum bytes into section line overhead bytes SONET/SDH frame. Each TIFE block processes four STS-48 transmit streams interfaces four downstream TRSP blocks.
10.9
Transmit In-band Forward Error Correction Encoder (TIFE)
10.8
Receive Section Overhead Processor (RSOP)
Each four independent Transmit QSFI-4 interface slices provides timing external devices which connected TXDATAn[3:0] buses. expected that external devices buffer source clock (TXCLK_SRC[n]) generated CRSU 4x2488 return (TXCLK[n]) synchronously with data (TXCLKn[3:0]). TXCLK_SRC[n] clock signal slaved associated transmit line interface clock synthesis unit. Thus, each transmit QSFI-4 interface slice frequency locked associated transmit data stream (TXD[n]+/-).
Each four independent Transmit QSFI-4 Interface blocks carries transmit data associated 2.488 Gbit/s data stream nibble-wide format. clock data phase locked associated transmit data stream.
10.7
Transmit QSFI-4 Interface QSFI-4 I/F)
CRSU4x2488 Telecom Standard Product Data Sheet Released
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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TRSP insert most section overhead bytes from internal registers. Since there multiple sources same overhead byte, bytes prioritized according Figure before being inserted into data stream
TRSP calculates section BIP-8 error detection code transmit data stream. section BIP-8 byte calculated scrambled bytes complete frame. section BIP-8 byte based interleaved parity calculation using even parity. calculated BIP-8 error detection code inserted byte STS-1 (STM-0) following frame before scrambling. TRSP scrambles transmit data stream with frame synchronous scrambler
CRSU 4x2488 contains Transmit Regenerator Section Processor (TRSP) blocks. They grouped into four sets TRSP blocks each. Each group processes section overhead four independent transmit data streams. Within each TRSPs, first TRSP processes first STS-3 (STM-1) multiplexing structure STS-48 (STM-16) stream. second TRSP processes next STS-3 (STM-1) streams
10.10 Transmit Regenerator Section Processor (TRSP)
encoder block inserts parity bits section line overhead bytes transmit stream. encoder block also sets status indication (FSI) bits. encoder block contains parallel encoder circuits, each which operate eight bitinterleaved code blocks. Each encoder circuit consists 39-bit long division circuit that finds remainder, R(x) given R(x) I(x) G(x). information bits represented I(x) a4358x4358 a39x39 where (n=4358 39). most significant term polynomial (a4358x4358) associated with first transmitted least significant term (a39x39) associated with last transmitted. generator polynomial given parity bits this remainder, R(x) inserted into transport overhead bytes.
10.9.2
Encoder
TIFE will always recalculate insert byte into frame whether state state defined STATE[1:0] bits Register 1040H. result must always recalculated TRSP TIFE block placed either state.
CRSU4x2488 Telecom Standard Product Data Sheet Released
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
Figure STS-48 (STM-16) SOH, Master TRSP
Order transmission Unused bytes
National bytes National bytes Line Overhead Bytes
(A1ERR
BYTE
HIGHEST priority
Figure Insertion Priority
Note, only overhead from first STS-12 (STM-4) STS-48 (STM-16) source. Overhead from other three STS-12's (STM-4's) internally generated assigned default values described below.
(A1A2EN= (A1A2EN=
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STS-1/STM-0 (J0Z0INCEN=1) pass through (B1DISABLE=1)
STS-1/STM-0 (J0Z0INCEN=1)
J0[7:0] (TRACE EN=1)
(J0REGEN (Z0REGEN
(E1REGEN (F1REGEN
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
LOWEST priority
pass through
pass through
pass through
pass through
Calculated B1MASK pass through
pass through
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
STS-1/STM-0
CRSU4x2488 Telecom Standard Product Data Sheet Released
BYTE
D1-D3
HIGHEST priority
D1D3V (D1D3REG EN=1) UnusedV (UnusedE N=1)
LOWEST priority
D1-D3 pass through
Unused
Unused pass through
Figure Z0/National Growth Bytes Definition
STS-48 (STM-16) National From STS-1/STM-0 None
TRSP
Type
Z0DEF
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
TRSP calculates section BIP-8 error detection code transmit data stream. section BIP-8 byte calculated scrambled bytes complete frame. section BIP-8 byte based interleaved parity calculation using even parity. calculated BIP-8 error detection code inserted byte STS-1 (STM-0) following frame before scrambling.
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Transmit Encoder enabled line BIP-8 (B2) calculation should disabled TRSP. correct byte calculated inserted into frame after bytes added frame TIFE encoder. TRSP line BIP-8 calculation should only used transmit encoder disabled. order disable TRSP line BIP-8 insertion B2DISABLE TRSP Error Insertion Register 1052H, 1062H, 1072H 1082H must logic '1'.
TRSP calculates line BIP-8 error detection codes transmit data stream. line BIP-8 error detection code calculated each constituent STS-1 (STM-0). line BIP-8 byte calculated unscrambled bytes STS-1 (STM-0) except bytes. line BIP-8 byte based interleaved parity calculation using even parity. each STS-1 (STM-0), calculated BIP-8 error detection code inserted byte following frame before scrambling. Optionally TRSP scramble transmit data stream not. scrambling controlled DS_CD[3:0] bits Diagnostics Register 0010H.
Z0DEF
From STS-1/STM-0 From STS-1/STM-0
Z0DEF register defines Z0/NATIONAL growth bytes When Z0DEF logic one, Z0/NATIONAL bytes defined according ITU. When Z0DEF logic zero, Z0/NATIONAL bytes defined according Telcordia.
pass through
National
National pass through
CRSU4x2488 Telecom Standard Product Data Sheet Released
10.12
Transmit Line Interface (TXLI)
REFCLK reference should within meet SONET free-run accuracy requirements specified GR-253-CORE.
Microprocessor Interface Block provides logic required interface generic microprocessor with normal mode test mode registers within CRSU 4x2488. normal mode registers used during normal operation configure monitor CRSU 4x2488. test mode registers used enhance testability CRSU 4x2488. register accessed shown below. corresponding memory address identified address column table. Addresses that shown used must treated Reserved.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
10.14
Microprocessor Interface
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JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. CRSU 4x2488 identification code 153950CD hexadecimal.
10.13
JTAG Test Access Port Interface
fully integrated clock synthesis unit. generates jitter multi-phase differential clocks 2488.32 usage transmitter. REFCLK used jitter reference clock CSU.
10.12.1 Transmit Line Interface Clock Synthesis Unit Line CSU)
Parallel Serial Converter (PISO) converts transmit byte serial data stream serial stream. transmit serial stream appears associated TXD+/- output.
transmit clock synthesized from 155.52. reference. transfer function yields typical pass corner above which reference jitter attenuated octave. design loop filter optimized minimum intrinsic jitter. With jitter 155.52MHz reference, intrinsic jitter typically less than 0.075 0.005UI RMSwhen measured using 12K-20MHz filter. section 19.5 OC-48 Interface Timing Characteristics reference clock specifications.
Each four independent Transmit Line Interface (TXLI) blocks allows CRSU 4x2488 interface directly Optical Data Link (ODL) modules other medium interfaces. This block performs clock synthesis performs parallel serial conversion outgoing 2488.32 Mbit/s data streams.
Each four independent SONET/SDH transmit line interface block properly formats associated outgoing 2488 Mbit/s data stream. This block interfaces TRSP blocks Transmit Line Interface block.
10.11
SONET/SDH Transmit Line Interface (STLI)
CRSU4x2488 Telecom Standard Product Data Sheet Released
0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015-0FFF
Identity, Global Performance Monitor Update Trigger Master Reset Master Interrupt Status Master Interrupt Status Master Interrupt Status Master Interrupt Status Master Interrupt Status Master Interrupt Status Master Interrupt Status Master Interrupt Status Channel Interrupt Status Configuration Clock Monitor Bypass Fiber Order Bypass modes Clock Control Bypass Channel Loopback Diagnostics Channel SALM Enables TXENB Control Device Number Unused
QSFIM_2488 1000 1001 1002 1003-101F 1020 1021
QSFIM_2488 Status QSFIM_2488 Control QSFIM_2488 Reserved
1022-102F
1030 1031 1032
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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Unused
Reserved Reserved Unused RSOP
RSOP Control RSOP Interrupt Status RSOP Reserved
CHANNEL REGISTERS
Channel SALM Enables
Address
Register Descripti
Table Register Memory
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1033 1034-103F
Register DescriptiRSOP Reserved Unused TIFE
1040 1041 1042 1043 1044 1045 1046-104F
TIFE Configuration TIFE Control TIFE Error Insertion Byte TIFE Error Insertion Byte TIFE Error Insertion Byte TIFE Error Insertion Byte Unused TRSP
1054 1055 1056 1057 1058 1059 105A 105B-105F 1060 1061 1062 1063 1064-106A 106B-106F 1070 1071 1072 1073
TRSP Transmit TRSP Transmit D1D3 TRSP Reserved TRSP Reserved TRSP Reserved TRSP Reserved TRSP Mask Unused
TRSP Aux1 Configuration TRSP Aux1 Error Insertion TRSP Aux1 Transmit TRSP Aux1 Reserved Unused TRSP Aux2 Configurati
1074-107A 107B-107F 1080 1081
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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TRSP Aux2 Reserved TRSP Aux2 Error Insertion TRSP Aux2 Transmit TRSP Aux2 Reserved Unused TRSP Aux3 Configuration TRSP Aux3 Reserved
TRSP Aux1 Reserved
1053
TRSP Transmit
1052
TRSP Error Inserti
1051
TRSP Register Inserti
1050
TRSP Configurati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1082 1083 1084-108A 108B-108F
Register DescriptiTRSP Aux3 Error Insertion TRSP Aux2 Transmit TRSP Aux3 Reserved Unused STLI
1091 1092-109F
STLI Reserved Unused TXLI
10A0 10A1 10A2 10A3- 10FF
TXLI Control/Status TXLI Control TXLI Pattern Register Unused CHANNEL REGISTERS RXLI
1103 1104 1105 1106-110F
RXLI Clock Training Configuration Status RXLI Pattern Unused SRLI
1110 1111 1112-111F
SRLI Clock Configurati
1122 1123
1121
1120
1124 1125
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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SRLI Reserved Unused
RRMP RRMP Configuration RRMP Status RRMP Interrupt Enable RRMP Interrupt Status RRMP Received RRMP Received
RXLI PRBS Control
1102
RXLI Control
1101
RXLI Interrupt Control
1100
RXLI Interrupt Status
1090
STLI Clock Configurati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1126 1127 1128 1129 112A 112B 112C-112F 1130-1135 1140-1145 1150-1155 1136 1146 1156 1137-113B 1147-114B 1157-115B 113C-113F 114C-114F 115C-115F
Register DescriptiRRMP enable RRMP Section Error Counter RRMP Line Error Counter (LSB) RRMP Line Error Counter (MSB) RRMP Line Error Counter (LSB) RRMP Line Error Counter (MSB) Unused RRMP Reserved 2(slave) RRMP Reserved 3(slave) RRMP Reserved 4(slave) RRMP enable (Slave) RRMP enable (Slave) RRMP enable (Slave) RRMP Reserved 2(slave) RRMP Reserved 3(slave) RRMP Reserved 4(slave) Unused Unused Unused RIFD
1161 1162 1163 1164 1165 1166 1167 1168-117F
RIFD Status
RIFD interrupt status RIFD correctable error count RIFD Line error count RIFD Line error count Unused
1180 1181 1182
1183 1184 1185 1186
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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SBER
SBER Configuration SBER Status SBER Interrupt Enable SBER Interrupt Status SBER BERM Accumulation Period (LSB) SBER BERM Accumulation Period (MSB) SBER BERM Saturation Threshold (LSB)
RIFD correctable error count
RIFD interrupt enable
1160
RIFD Configurati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1187 1188 1189 118A 118B 118C 118D 118E 118F 1190 1191 1192 1193 1194-11FF
Register DescriptiSBER BERM Saturation Threshold (MSB) SBER BERM Declaring Threshold (LSB) SBER BERM Declaring Threshold (MSB) SBER BERM Clearing Threshold (LSB) SBER BERM Clearing Threshold (MSB) SBER BERM Accumulation Period (LSB) SBER BERM Accumulation Period (MSB) SBER BERM Saturation Threshold (LSB) SBER BERM Saturation Threshold (MSB) SBER BERM Declaring Threshold (LSB) SBER BERM Declaring Threshold (MSB) SBER BERM Clearing Threshold (LSB) SBER BERM Clearing Threshold (MSB) Unused CHANNEL REGISTERS QSFIM_2488
1200 1201 1202 1203-121F 1220 1221 1222-122F
QSFIM_2488 Status QSFIM_2488 Control QSFIM_2488 Reserved Unused Reserved Reserved Unused RSOP
1230 1231 1232 1233 1234-123F
RSOP Control
1240 1241 1242 1243
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RSOP Interrupt Status RSOP Reserved RSOP Reserved Unused TIFE TIFE Configuration TIFE Control
TIFE Error Insertion Byte TIFE Error Insertion Byte
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1244 1245 1246-124F
Register DescriptiTIFE Error Insertion Byte TIFE Error Insertion Byte Unused TRSP
1252 1253 1254 1255 1256 1257 1258 1259 125A 125B-125F 1260 1261 1262 1263 1264-126A 126B-126F 1270 1271 1272 1273 1274-127A 127B-127F 1280 1281 1282 1283
TRSP Error Insertion TRSP Transmit TRSP Transmit TRSP Transmit D1D3 TRSP Reserved TRSP Reserved TRSP Reserved TRSP Reserved TRSP Mask Unused TRSP Aux1 Configuration TRSP Aux1 Register Insertion TRSP Aux1 Error Insertion TRSP Aux1 Transmit Unused TRSP Aux1 Reserved
TRSP Aux2 Register Insertion TRSP Aux2 Error Insertion TRSP Aux2 Reserved Unused TRSP Aux3 Configuration TRSP Aux3 Register Inserti
128B-128F
1284-128A
1290 1291
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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TRSP Aux3 Error Insertion TRSP Aux2 Transmit
TRSP Aux3 Reserved Unused STLI STLI Clock Configuration STLI Reserved
TRSP Aux2 Transmit
TRSP Aux2 Configurati
1251
TRSP Register Inserti
1250
TRSP Configurati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1292-129F
Register DescriptiUnused TXLI
12A1 12A2 12A3-12FF
TXLI Control TXLI Pattern Register Unused CHANNEL REGISTERS RXLI
1300 1301 1302 1303 1304 1305 1306-130F
RXLI Interrupt Status RXLI Interrupt Control RXLI Control RXLI PRBS Control RXLI Pattern Unused SRLI
1312-111F
Unused RRMP
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
RRMP Configuration RRMP Interrupt Enable RRMP Interrupt Status RRMP Received RRMP Received
132A 132B
132C-132F 1330-1335
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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RRMP enable
RRMP Section Error Counter RRMP Line Error Counter (LSB) RRMP Line Error Counter (MSB) RRMP Line Error Counter (LSB) RRMP Line Error Counter (MSB) Unused RRMP Reserved 2(slave)
RRMP Status
1311
SRLI Reserved
1310
SRLI Clock Configurati
RXLI Clock Training Configuration Status
12A0
TXLI Control/Status
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
1340-1345 1350-1355 1336 1346 1356 1337-133B 1347-134B 1357-135B 133C-133F 134C-134F 135C-135F
Register DescriptiRRMP Reserved 3(slave) RRMP Reserved 4(slave) RRMP enable (Slave) RRMP enable (Slave) RRMP enable (Slave) RRMP Reserved 2(slave) RRMP Reserved 3(slave) RRMP Reserved 4(slave) Unused Unused Unused RIFD
1364 1365 1366 1367 1368-137F
RIFD correctable error count RIFD Line error count Unused SBER
RIFD correctable error count RIFD Line error count
1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 138A
SBER Configuration SBER Status
SBER Interrupt Status SBER BERM Accumulation Period (LSB) SBER BERM Accumulation Period (MSB) SBER BERM Saturation Threshold (LSB) SBER BERM Saturation Threshold (MSB)
138B
138C 138D 138E
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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SBER BERM Declaring Threshold (LSB) SBER BERM Declaring Threshold (MSB) SBER BERM Clearing Threshold (LSB) SBER BERM Clearing Threshold (MSB) SBER BERM Accumulation Period (LSB) SBER BERM Accumulation Period (MSB) SBER BERM Saturation Threshold (LSB)
SBER Interrupt Enable
1363
RIFD interrupt status
1362
RIFD interrupt enable
1361
RIFD Status
1360
RIFD Configurati
CRSU4x2488 Telecom Standard Product Data Sheet Released
Address
138F 1390 1391 1392 1393 1394-13FF
Register DescriptiSBER BERM Saturation Threshold (MSB) SBER BERM Declaring Threshold (LSB) SBER BERM Declaring Threshold (MSB) SBER BERM Clearing Threshold (LSB) SBER BERM Clearing Threshold (MSB) Unused CHANNEL REGISTERS QSFIM_2488
1401 1402 1403-141F
QSFIM_2488 Control QSFIM_2488 Reserved Unused
1421 1422-142F
Reserved Unused RSOP
1431 1432 1433 1434-143F
RSOP Interrupt Status RSOP Reserved Unused TIFE
1440 1441 1442 1443 1444 1445
TIFE Configurati
1446-144F
1450 1451
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2001972, Issue
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TIFE Control
TIFE Error Insertion Byte TIFE Error Insertion Byte TIFE Error Insertion Byte TIFE Error Insertion Byte Unused TRSP TRSP Configuration TRSP Register Inserti
RSOP Reserved
1430
RSOP Control
1420
Reserved
1400
QSFIM_2488 Statu
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