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Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Proprietary Confidential Released Issue 2002
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
Data Sheet
Octal E1/T1/J1 Line Interface Device Telecom Standard Product
OCTLIU
PM4318
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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Product company names mentioned herein trademarks their respective owners.
U.S. Application US5973977. Canadian Application CA2242152. Other relevant patent grants also exist.
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technology discussed this document protected more following patent grants:
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event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
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Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
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Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
April 2001
Update, including: Hiding STB, VCLK FBLOW Modified diagram marketing. Change line protection diagram Removed production registers.
2002
Released. Changes Revision
Change bars relative issue
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
Update, including changes release production. Update latest version template.
Added TXHIZ/LLB pins associated registers Updated diagram block diagram, pins
March 2002
Update, including:
De-documented SBI2CLK mode Updated TX/RX tables Updated mechanical infomration Recommended N1/N2 values JATs Manual fuse load procedure
November 2001
Update, including:
January 2001
Updated.
October 2000
Document created.
Issue
Issue Date
Details Change
Revision History
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Trademarks
Revision History Table Contents List Registers
List Tables Features Each Receiver Section
Applications References Application Examples Block Diagram Description Diagram.26 Description Functional Description.41 9.10 Octants
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Receive Interface.41 Clock Data Recovery (CDRC) Receive Jitter Attenuator (RJAT) Inband Loopback Code Detector (IBCD) Pulse Density Violation Detector (PDVD) Performance Monitor Counters (PMON) Pseudo Random Binary Sequence Generation Detection (PRBS).44 Inband Loopback Code Generator (XIBC) Pulse Density Enforcer (XPDE).45
Each Transmitter Section
List Figures
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Table Contents
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20
Line Transmitter
External Analogue Interface Circuits
Extracter PISO.53
Microprocessor Interface
Normal Mode Register Description 10.1 Normal Mode Register Memory
Test Features Description.171 11.1 JTAG Test Port.171
Operation.174 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuring OCTLIU from Reset .174
Using Performance Monitoring Features.175 Using Transmit Line Pulse Generator .175 Using Line Receiver .197
Loopback Modes .205 Initialization RJAT TJAT.206 Configuring with .206
12.10 JTAG Support .207 Functional Timing .214
Absolute Maximum Ratings.219
D.C. Characteristics .220 Microprocessor Interface Timing Characteristics .223 OCTLIU Timing Characteristics.227 17.1 17.2 RSTB Timing (Figure 31).227 XCLK Input Timing (Figure .227
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13.3
13.2
13.1
Interface Timing.214 Line Code Violation Insertion.215 Alarm Interface .218
Using PRBS Generator Detector.205
Servicing Interrupts.174
JTAG Test Access Port
Serial PROM Interface.53
Inserter SIPO
Scaleable Bandwidth Interconnect (SBI) Interface.52
Timing Options (TOPS)
9.11
Transmit Jitter Attenuator (TJAT).45
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
17.4 17.5 17.6 17.7 17.8
Receive Serial Interface (Figure 34).229
Serial PROM (SPI) Interface (Figure 38).232
JTAG Port Interface (Figure .233
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
Notes
Mechanical Information .237
Ordering Thermal Information .236
Alarm Interface (Figure 39).233
Interface (Figure Figure 37).230
17.3
Transmit Serial Interface (Figure 33).228
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Register 003H: Master Interrupt Source #2.67
Register 310H: INSBI Control.86 Register 311H: INSBI FIFO Underrun Interrupt Status Register 312H: INSBI FIFO Overrun Interrupt Status Register 313H 31AH: INSBI Page Octant Tributary Mapping
Register 325H 32CH: INSBI Tributary Control
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Register 32DH: INSBI Minimum Depth.95 Register 32EH: INSBI FIFO Thresholds Register 331H: INSBI Depth Check Interrupt Status.97 Register 332H: INSBI Master Interrupt Status.98 Register 390H: EXSBI Control.99
Register 324H: INSBI Link Enable Busy.93
Register 323H: INSBI Link Enable.92
Register 31BH 322H: INSBI Page Octant Tributary Mapping
Register 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: Line Interface PRBS Position.85
Register 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH: Line Interface Diagnostics
Register 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: Line Interface Interrupt Source #2.82
Register 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH: Line Interface Interrupt Source PMON Update
Register 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH: Transmit Timing Options Clock Monitor Pulse Template Selection
Register 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: Transmit Line Interface Configuration
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: Receive Line Interface Configuration
Register 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: Receive Line Interface Configuration
Register 006H: Configuration.70
Register 005H: Master Test Control
Register 004H: Master Test Control
Register 002H: Master Interrupt Source #1.66
Register 001H: Global Configuration Clock Monitor.64
Register 000H: Reset Revision Device
List Registers
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Register 392H: EXSBI FIFO Overrun Interrupt Status .102
Register 394H: EXSBI Depth Check Interrupt Status.104
Register 396H: EXSBI Minimum Depth .106
Register 3A0H 3A7H: EXSBI Tributary Control #8.110 Register 3A8H 3AFH: EXSBI Page Octant Tributary Mapping #8.111 Register 3B0H 3B7H: EXSBI Page Octant Tributary Mapping #8.112
Register 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH: TJAT Output Clock Divisor (N2) Control.125 Register 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: TJAT Configuration .126 Register 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: IBCD Configuration .128 Register 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: IBCD Interrupt Enable/Status .129
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Register 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: TJAT Reference Clock Divisor (N1) Control .124
Register 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: TJAT Interrupt Status.123
Register 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH: RJAT Configuration .121
Register 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH: RJAT Output Clock Divisor (N2) Control.120
Register 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H: RJAT Reference Clock Divisor (N1) Control .119
Register 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H: RJAT Interrupt Status .118
Register 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: XIBC Loopback Code .117
Register 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: XIBC Control .116
Register 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H: XPDE Interrupt Enable/Status.114
Register 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: PDVD Interrupt Enable/Status.113
Register 399H: EXSBI Link Enable Busy .109
Register 398H: EXSBI Link Enable .108
Register 397H: EXSBI FIFO Thresholds .107
Register 395H: EXSBI Master Interrupt Status .105
Register 393H: EXSBI Parity Error Interrupt Reason .103
Register 391H: EXSBI FIFO Underrun Interrupt Status .101
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRBS Generator/Checker Control .141
Register 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H: PRBS Error Count .147
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: XLPG Control/Status.149
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Register 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH: XLPG Pulse Waveform Storage Write Address #2.152 Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH: XLPG Pulse Waveform Storage Data.153 Register 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH: XLPG Fuse Control .154
Register 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH: XLPG Pulse Waveform Storage Write Address #1.151
Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: XLPG Pulse Waveform Scale .150
Register 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H: PRBS Error Count .148
Register 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRBS Error Count .146
Register 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRBS Pattern Select.145
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRBS Checker Interrupt Enable/Status.143
Register 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH: PMON Count (MSB).140
Register 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH: PMON Count (LSB).139
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: PMON Interrupt Enable/Status .138
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H: CDRC Alternate Loss Signal Status .137
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: CDRC Interrupt Status .136
Register 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: CDRC Interrupt Control .135
Register 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: CDRC Configuration .133
Register 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: IBCD Deactivate Code.132
Register 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: IBCD Activate Code .131
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Register 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H: RLPS Equalization Indirect Data .165
Register 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH: RLPS Equalizer Voltage Thresholds .169
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Register 07EH, 0FEH, 17EH, 1FEH, 27EH, 2FEH, 37EH, 3FEH: RLPS Fuse Control .170
Register 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH: RLPS Equalizer Voltage Thresholds .168
Register 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH: RLPS Equalization Indirect Data .167
Register 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH: RLPS Equalization Indirect Data .166
Register 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H: RLPS Equalization Indirect Data .164
Register 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H: RLPS Equalizer Configuration .163
Register 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H: RLPS Equalizer Loop Status Control.162
Register 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H: RLPS Equalization Read/WriteB Select .161
Register 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H: RLPS Equalization Indirect Address.160
Register 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H: RLPS ALOS Clearance Period.159
Register 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H: RLPS ALOS Detection Period.158
Register 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H: RLPS ALOS Detection/Clearance Threshold.157
Register 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H: RLPS Configuration Status.155
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Figure Metro Optical Access Equipment
Figure Compliance with ITU-T Specification G.823 Input Jitter Figure TJAT Jitter Tolerance Figure TJAT Minimum Jitter Tolerance XCLK Accuracy
Figure External Analogue Interface Circuits Figure Serial PROM Cascade Interface Figure Serial PROM Command Format
Figure Line Loopback .205 Figure Diagnostic Digital Loopback .206 Figure Boundary Scan Architecture.207 Figure Controller Finite State Machine .209 Figure Input Observation Cell (IN_CELL).212 Figure Output Cell (OUT_CELL) Enable Cell (ENABLE) .212 Figure Bidirectional Cell (IO_CELL).213 Figure Layout Output Enable Bidirectional Cells.213 Figure Functional Timing .214
Figure Alarm Serial Output .218
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Figure Microprocessor Interface Read Timing .224 Figure Microprocessor Interface Write Timing.225 Figure RSTB Timing .227 Figure XCLK Input Timing .227 Figure Transmit Serial Interface Timing Diagram.228
Figure Line Code Violation Insertion .217
Figure HDB3 Line Code Violation Insertion.216
Figure B8ZS Line Code Violation Insertion .215
Figure Transmit Timing Options
Figure TJAT Jitter Transfer.49
Figure Jitter Tolerance.42
Figure Diagram (Bottom View)
Figure OCTLIU Block Diagram
Figure High Density Leased Line Circuit Emulation Application
Figure High Density T1/E1 Framer/Transceiver Application
Figure T1/E1 Framer/Transceiver Application.22
List Figures
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Figure Frame Pulse Timing.230
Figure DROP Timing .231
Figure Alarm Interface Timing .233
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Figure JTAG Port Interface Timing .234
Figure Interface Timing .232
Figure Timing .231
Figure Receive Serial Interface Timing Diagram.229
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Table Normal Mode Register Memory Map.56
Table EXSBI Clock Generation Options.110 Table Transmit In-band Code Length.116 Table Recommended N1/N2 values.120
Table Loopback Code Configurations .128 Table Loss Signal Thresholds .134 Table Transmit Output Amplitude .150
Table Boundary Scan Register.171 Table Default Settings .174 Table T1.102 Transmit Waveform Values Long Haul (LBO .178 Table T1.102 Transmit Waveform Values Long Haul (LBO .179 Table T1.102 Transmit Waveform Values Long Haul (LBO .180 Table T1.102 Transmit Waveform Values Long Haul (LBO 22.5 dB).181 Table T1.102 Transmit Waveform Values Short Haul ft.) .182 Table T1.102 Transmit Waveform Values Short Haul (110 ft.) .183 Table T1.102 Transmit Waveform Values Short Haul (220 ft.) .184
Table TR62411 Transmit Waveform Values Long Haul (LBO .188
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Table TR62411 Transmit Waveform Values Short Haul ft.) .189 Table TR62411 Transmit Waveform Values Short Haul (110 ft.) .190 Table TR62411 Transmit Waveform Values Short Haul (220 ft.) .191
Table T1.102 Transmit Waveform Values Short Haul (550 ft.) .187
Table T1.102 Transmit Waveform Values Short Haul (440 ft.) .186
Table T1.102 Transmit Waveform Values Short Haul (330 ft.) .185
Table ALOS Detection/Clearance Thresholds.157
Table Recommended N1/N2 values.125
Table TJAT Source
Table TJAT FIFO Output Clock Source.79
Table Clock Synthesis Mode
Table Serial PROM Special Commands
Table Serial PROM Commands Code Bits.54
Table External Component Descriptions
List Tables
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Table Transmit Waveform Values Ohm.195
Table RLPS Equalizer Table mode) .201 Table Absolute Maximum Ratings .219 Table D.C. Characteristics.220
Table Microprocessor Interface Write Access .225 Table RTSB Timing .227 Table XCLK Input Timing.227
Table Receive Serial Interface.229 Table Clocks Frame Pulse.230 Table .230 Table DROP .231 Table Interface .232 Table Alarm Interface .233 Table JTAG Port Interface .233 Table Ordering Information.236 Table OCTLIU Theta Jc.236
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Table OCTLIU Theta Airflow .236
Table OCTLIU Junction Temperature .236
Table Transmit Serial Interface.228
Table Microprocessor Interface Read Access.223
Table RLPS Equalizer Table mode).198
Table RLPS Register Programming .197
Table Transmit Waveform Values Ohm.196
Table TR62411 Transmit Waveform Values Short Haul (550 ft.) .194
Table TR62411 Transmit Waveform Values Short Haul (440 ft.) .193
Table TR62411 Transmit Waveform Values Short Haul (330 ft.) .192
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Provides encoding decoding B8ZS, HDB3 line codes.
Uses line rate system clock.
Implemented power tolerant 1.8/3.3 CMOS technology.
Each Receiver Section
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Supports signal reception distances with cable attenuation nominal conditions using gauge cable emulation. Supports signal reception distances with cable attenuation nominal conditions using gauge cable emulation. Supports G.772 compliant non-intrusive protected monitoring points.
Provides Industrial temperature operating range.
Available high density 288-pin Tape-SBGA package.
Provides IEEE 1149.1 (JTAG) compliant Test Access Port (TAP) controller boundary scan test.
Provides hardware-only microprocessor) mode which configuration data read from SPI-compatible serial PROM. PROM interface cascaded such that multiple OCTLIU devices configured simultaneously from single PROM.
Provides 8-bit microprocessor interface configuration, control, status monitoring.
Provides either serial clock/data parallel Scaleable Bandwidth Interconnect (SBI) interfaces system side.
Provides PRBS generators detectors each tributary error testing rates recommended ITU-T O.151.
Provides selectable, channel independent de-jittered recovered clock system timing redundancy.
Provides digitally programmable long haul short haul line build out.
Provides transmit receive jitter attenuation.
Provides receive equalization, clock recovery line performance monitoring.
Meets exceeds T1/J1 shorthaul longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T 62411, ITU-T G.703, G.704 well ETSI 300-011, CTR-4, CTR-12 CTR-13.
Software switchable between T1/J1 operation per-device basis.
Monolithic device which integrates eight T1/J1 short haul long haul line interface circuits.
Features
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Detects loss signal (LOS), which defined successive zeros. Detects programmable inband loopback activate deactivate code sequences received DS-1 data stream when they present seconds. Optionally, enters loopback mode automatically detection inband loopback code.
Generates pulses compliant G.703 recommendations.
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Provides line outputs that current limited tristated protection redundant applications. Provides digital phase locked loop generation jitter transmit clock complying with jitter attenuation, jitter transfer residual jitter specifications AT&T 62411 ETSI Provides FIFO buffer jitter attenuation rate conversion transmit path.
Allows bipolar violation (BPV) transparent operation error restoring regenerator applications.
Provides digitally programmable pulse shape extending transmitted periods custom long haul pulse shaping applications.
Generates DSX-1 shorthaul DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI requirements.
Supports transfer transmitted single rail signaling data from 1.544 Mbit/s 2.048 Mbit/s backplane buses.
Each Transmitter Section
pseudo-random sequence user selectable from detected T1/E1 stream either receive transmit directions. detector counts pattern errors using 24-bit saturating PRBS error counter.
Detects violations ANSI T1.403 12.5% pulse density rule over moving 192-bit window.
Accumulates 8191 line code violations (LCVs), performance monitoring purposes, over accumulation intervals defined period between software write accesses register.
Detects line code violations (LCVs), B8ZS/HDB3 line code signatures, (E1), (T1+B8ZS) AMI) successive zeros.
Performs B8ZS decoding when processing bipolar DS-1 signal HDB3 decoding when processing bipolar signal.
Outputs either dual rail recovered line pulses, single rail DS-1/E1 signal parallel data format.
Tolerates more than peak-to-peak; high frequency jitter required AT&T 62411 Bellcore TR-TSY-000170.
Recovers clock data using digital phase locked loop high jitter tolerance.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Supports ones transmission alarm indication signal (AIS) generation.
Performs B8ZS encoding when processing single rail SBI-sourced DS-1 signal HDB3 encoding when processing single rail SBI-sourced signal. pseudo-random sequence user selectable from inserted into detected from stream either receive transmit directions. Detects violations ANSI T1.403 12.5% pulse density rule over moving 192-bit window optionally stuffs ones maintain minimum ones density.
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Supports transmission programmable unframed inband loopback code sequence.
Accepts either dual rail single rail DS-1/E1 signals parallel data from interface.
Allows bipolar violation (BPV) insertion diagnostic testing purposes.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Base Transceiver Stations (BTS) Digital Private Branch Exchanges (PBX)
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Test Equipment
T1/E1 Repeaters
Digital Access Cross-Connect Systems (DACS) Electronic Cross-Connect Systems (EDSX)
Base Station Controllers (BSC)
Multiservice ASwitch Linecards
Edge Router Linecards
Metro Optical Access Equipment
Applications
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
References
ANSI T1.107-1995 American National Standard Telecommunications Digital Hierarchy Formats Specification.
TR-TSY-000499 Bell Communications Research Transport Systems Generic Requirements (TSGR): Common Requirement, Issue December, 1993. ETSI ISDN Primary Rate User-Network Interface Specification Test Principles, 1992. ETSI Access Digital Section ISDN Primary Rates. ETSI Integrated Services Digital Network (ISDN); Attachment requirements terminal equipment connect ISDN using ISDN primary rate access, November 1995. ETSI Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; kbit/s digital unstructured leased lines (D2048U) Attachment requirements terminal equipment interface, December 1993.
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TR-NWT-000303 Bell Communications Research Integrated Digital Loop Carrier Generic Requirements, Objectives, Interface, Issue December, 1992.
TR-N1WT-000233 Bell Communications Research Wideband Broadband Digital Cross-Connect Systems Generic Criteria, Issue November 1993.
TR-TSY-000170 Bellcore Digital Cross-Connect System Requirements Objectives, Issue November 1985.
AT&T 62411 Accunet T1.5 Service Description Interface Specification, Addendum October 1992.
AT&T 62411 Accunet T1.5 Service Description Interface Specification, Addendum March 1991.
AT&T 62411 Accunet T1.5 Service Description Interface Specification, December 1990.
ANSI T1.408-1990 American National Standard Telecommunications Integrated Services Digital Network (ISDN) Primary Rate Customer Installation Metallic Interfaces Layer Specification.
ANSI T1.403-1999 American National Standard Telecommunications Carrier Customer Installation DS-1 Metallic Interface Specification.
ANSI T1.102-1993 American National Standard Telecommunications Digital Hierarchy Electrical Interfaces.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
ITU-T Recommendation G.703 Physical/Electrical Characteristics Hierarchical Digital Interface, Geneva, 1998. ITU-T Recommendation G.704 Synchronous Frame Structures Used Primary Hierarchical Levels, July 1998.
Nippon Telegraph Telephone Corporation Technical Reference High-Speed Digital Leased Circuit Services, Third Edition, 1990.
PMC-Sierra Application Note: "Configuring Compatible Devices", PMC-2020180.
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ITU-T Recommendation G.824, Control Jitter Wander within Digital Networks which based 1544 kbit/s Hierarchy (March 1993).
Standard JT-I431 ISDN Primary Rate User-Network Interface Layer Specification, 1995.
Standard JT-G704 Frame Structures Primary Secondary Hierarchical Digital Interfaces, 1995.
Standard JT-G703 Physical/Electrical Characteristics Hierarchical Digital Interfaces, 1995.
ITU-T Recommendation O.151, Error Performance Measuring Equipment Digital Systems Primary Rate Above, 1992.
ITU-T Recommendation I.431 Primary Rate User-Network Interface Layer Specification, 1993.
ITU-T Recommendation G.823, Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy, 1993.
ITU-T Recommendation G.775 Loss Signal (LOS), November 1998.
ITU-T Recommendation G.772 Protected Monitoring Points Provided Digital Transmission Systems, 1992.
Rules Part 68.308 Signal Power Limitations.
ETSI Business Telecommunications (BTC); kbit/s digital structured leased lines (D2048S); Attachment requirements terminal equipment interface, January 1996.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Clock Data lines
Backplane
PM4318
PM6388
OCTLIU
OCTLIU
PM4318 PM4318 PM4318
OCTLIU
T1/J1 lines
OCTLIU
Figure High Density T1/E1 Framer/Transceiver Application
H-MVIP
Octal Framer
4xOCTLIU
T1/J1/E1 Framer
Figure High Density Leased Line Circuit Emulation Application
Utopia
T1/J1 lines
lines
OCTLIU
EOCTL
PM4332
Clock Data
Octal Framer
TE32
PM4318
PM4388
Backplane
ABackbone
OCTLIU
TOCTL
OCTLIU
OCTLIU
OCTLIU
PM4318 PM4318 PM4318 PM4318
4xOCTLIU
OCTLIU
AAL1gator
PM73122
AAL1
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Figure T1/E1 Framer/Transceiver Application
Application Examples
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318
PM5366
T1/E1 VT/TU Mapper
11xOCTLIU
Cross Connect
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TEMAP-84
T1/J1 lines
OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU PM4318 PM4318
Telecom
Figure Metro Optical Access Equipment
TDN[8:1] TDP[8:1] TCLK[8:1] ADATA[7:0] EXSBI-8 Extract PRBS Pattern Generator Detector REFCLK AC1FP DC1FP C1FPOUT DDATA[7:0] INSBI-8 Insert DACTIVE RDP[8:1] RDN/RLCV[8:1] RCLK[8:1] Octant TJAT Digital Jitter Attenuator
TXTIP1[8:1] TXTIP2[8:1] LCODE B8ZS HDB3 Line Encoder
Block Diagra
TXRING1[8:1] TXRING2[8:1]
XLPG Transmit
only Auto-config RJAT Digital Jitter Attenuator XPDE Pulse Density Enforcer XIBC Inband Loopback Code Generator
Figure OCTLIU Block Diagra
(Diagnostic Digital Loopback) PMON Performance Monitor (Line Loopback)
RXTIP[8:1] CDRC Clk/Data Recovery PDVD Pulse Density Viol. Detector
RXRING[8:1]
RLPS Receive
IBCD Inband Loop back Code Detector
TXHIZ/LLB SBI_EN RSTB
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XCLK JTAG Interface
RSYNC
Clock Synthesis Distribution TOPS Timing Options Serial Output
INTB SREN SRCEN SRCDO SRCLK SRCCLK SRDI/PO LEN8[2:0] LEN7[2:0] LEN6[2:0] LEN5[2:0] LEN4[2:0] SRDO/PI SRCASC HW_ONLY SRCODE
LEN3[2:0] LEN2[2:0]
LEN1[2:0]
D[7:0]
A[10:0]
TRSTB
LOS_L1
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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OCTLIU configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. Alternatively, device operated `hardware only' mode which microprocessor required. this case, OCTLIU reads configuration information from SPI-compatible serial PROM interface power Multiple OCTLIUs configured from single serial PROM cascade interface OCTLIU.
Serial interfaces each T1/E1 allow 1.544 Mbit/s 2.048 Mbit/s backplane receive/backplane transmit system interfaces directly supported. Data transferred either dual rail line pulses single rail DS-1/E1 data. Alternatively, OCTLIU supports 8-bit parallel interface interfacing high-density framers.
Each channel OCTLIU generate jitter transmit clock from input clock source also provide jitter attenuation receive path. jitter recovered clock routed outside OCTLIU network timing applications.
Internal analogue circuitry allows direct transmission long haul short haul compatible signals using minimum external components. Typically, only line protection, transformer optional line termination resistor required. Digitally programmable pulse shaping allows transmission DSX-1 compatible signals feet from crossconnect, short haul pulses into twisted pair coaxial cable, long haul pulses into twisted pair well long haul DS-1 pulses into twisted pair with integrated support filtering required rules. addition, programmable pulse shape extending over 5-bit periods allows customization short haul long haul line interface circuits application requirements.
OCTLIU supports detection loss signal, pulse density violation line code violation alarm conditions. Line code violations accumulated performance monitoring purposes.
OCTLIU recovers clock data from line. Decoding AMI, HDB3 B8ZS line codes supported. mode, OCTLIU also detects presence in-band loop back codes.
Analogue circuitry provided allow direct reception long haul compatible signals with cable loss 1.024 MHz) mode cable loss kHz) mode using minimum external components. Typically, only line protection, transformer line termination resistor required.
PM4318 Octal E1/T1/J1 Line Interface Device (OCTLIU) monolithic integrated circuit suitable long haul short haul systems with minimum external circuitry. OCTLIU configurable microprocessor control SPI-compatible serial PROM interface, allowing feature selection without changes external wiring.
Description
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Figure Diagram (Bottom View)
ALE/ LEN4[2] D[1]/ LEN6[2] CSB/ LEN5[2]
OCTLIU packaged 288-pin Tape-SBGA package having body size 23mm 23mm.
TXRING2 TXRING1 TAVD3[1] TXTIP1[1 TXTIP2[1 TXTIP2[8 TXRING1 TXRING2 TXTIP1[8] TAVS3[8] TAVD2[8] QAVD[4] VDD1V8 VDD3V3 RES_0
Diagra
VDD3V3 INTB/ LEN6[0]
TAVD2[1]
TAVS3[1] TAVD3[8] TAVS2[8]
A[8]/ LEN3[2] A[4]/ LEN2[1] A[0]/ LEN1[0] RAVS1[1]
A[9]/ A[10]/ LEN4[0] LEN4[1] A[5]/ A[6]/ LEN2[2] LEN3[0] A[1]/ A[2]/ LEN1[1] LEN1[2] RAVD2[1 QAVD[1]
RDB/ VDD3V3 LEN5[1] A[7]/ LEN3[1] A[3]/ LEN2[0] VDD3V3 RXRING[ RXRING[ TAVS1[2] WRB/ LEN5[0]
D[7]/ CAVD LEN8[2] D[5]/ CAVS LEN8[0]
LOS_L1
VDD3V3 VDD3V3
D[0]/ D[3]/ LEN6[1] LEN7[1]
D[6]/ SBI_EN LEN8[1]
QAVS[4] RES_0
D[2]/ D[4]/ LEN7[0] LEN7[2]
VDD1V8
TAVS2[1]
RSTB
SRCCLK
SRCLK
VDD3V3
RES_0
SRCDO SDRO/PI
SRCASC
HW_ONLY
SRCODE SRCEN
SREN
TXHIZ/LLB
TAVS1[1]
TAVD1[1] TAVD1[8] TAVS1[8] XCLK
RSYNC
VDD3V3
SRDI/PO
VDD3V3 RAVS1[8]
TRSTB
RAVD2[8 RAVD2[7] RAVS2[7] TXRING2 TXRING1
QAVS[3]
RES_0
RAVD1[1] RXTIP[1] RAVS2[1] TXRING2 RAVD2[2 RAVS2[2] TXRING1 RXTIP[2] RAVS1[2] RAVD1[2 TAVS2[2]
RAVS2[8]
RXTIP[8] RAVS1[7]
RXRING[8]
RAVD1[8 RAVD1[7 TXTIP1[7]
RXRING[7] RXTIP[7] TAVS2[7] TXTIP2[7]
TXTIP1[2]
TAVS1[7]
TAVD2[7] TAVD3[7] TXTIP2[6]
TXTIP2[2] TAVD2[2] TAVD3[2]
TAVD1[2]
TAVD1[7]
TAVS3[7] TAVS3[6] TXTIP1[6] TXRING1
TXTIP2[3] TAVS3[2] TAVS3[3]
TAVD1[3]
TAVD1[6]
TAVD3[6] TAVD2[6]
TXTIP1[3] TAVD3[3] TAVD2[3]
TAVS1[3]
TAVS1[6]
TAVS2[6]
RAVD1[6 TXRING2 RAVD2[6 RXTIP[6]
TXRING1 RXRING[ TAVS2[3] RAVD1[3] TXRING2 RXTIP[3] RAVD2[3] RXTIP[4] RAVS1[3] RAVS2[3] RAVD1[4] RAVS2[4]
RXRING[6] RAVS1[6]
RXTIP[5]
RXRING[ RAVD1[5 RAVS2[6] RAVS2[5] RAVD2[5 RAVS1[5] TDP[8]/ ADATA[7 TCLK[8]
RXRING[ RAVS1[4] RAVD2[4] TCLK[1] TDP[2]/ ADATA[1 TDN[4]/
QAVD[3]
TCLK[7]
TDN[8]
RES_0
QAVS[1]
TDN[6]/ RDP[5]/ DDATA[4 RCLK[6] RDN[5]/ RLCV[5]/ VDD3V3 QAVS[2] RDP[8]/ RCLK[7] DDATA[7 RDP[7]/ RDN[8]/ DDATA[6 RLCV[8]/ DACTIVE
TCLK[6] TDN[7]
VDD3V3
VDD3V3 VDD3V3
TDP[1]/ TDN[1]/ TCLK[2] ADATA[0] REFCLK TDP[3]/ ADATA[2 VDD3V3 TDN[3]/ DC1FP TCLK[4]
RDN[3]/ RLCV[3]/ C1FPOU
TAVS1[4]
TAVD1[4] TAVD1[5] TAVS1[5] VDD1V8
VDD3V3 TCLK[5]
TDP[7]/ ADATA[6]
TDN[2]/ AC1FP
TDP[4]/ ADATA[3
RDP[2]/ DDATA[1 RCLK[3]
RDN[4]/ VDD3V3 RLCV[4]/ TAVS2[4] RCLK[4] VDD1V8 QAVD[2]
TAVD3[4] TAVS3[5] TAVD2[5] RES_0
TDP[5]/ TDP[6]/ ADATA[4 ADATA[5] TDN[5]/
TCLK[3]
RCLK[1] RCLK[2]
TAVD2[4] TAVS3[4] TAVD3[5] TAVS2[5]
RDP[6]/ RDN[7]/RL DDATA[5 VDD3V3 CV[7]
RDP[1]/ RDP[4]/ RDN[1]/RL RDN[2]/R RDP[3]/ TXRING2 TXRING1 DDATA[0 DDATA[3 CV[1] LCV[2] DDATA[2]
TXTIP1[4 TXTIP2[4 TXTIP2[5 TXRING1 TXRING2 TXTIP1[5]
RDN[6]/ RCLK[5] RLCV[6]/ VDD3V3
RCLK[8] VDD3V3
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Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Name
TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TDP[1]/ADATA[0] TDP[2]/ADATA[1] TDP[3]/ADATA[2] TDP[4]/ADATA[3] TDP[5]/ADATA[4] TDP[6]/ADATA[5] TDP[7]/ADATA[6] TDP[8]/ADATA[7]
Type
Input
Function
AA22 AA20
RDP[1]/DDATA[0] RDP[2]/DDATA[1] RDP[3]/DDATA[2] RDP[4]/DDATA[3] RDP[5]/DDATA[4] RDP[6]/DDATA[5] RDP[7]/DDATA[6] RDP[8]/DDATA[7]
RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8]
TDN[1]/REFCLK TDN[2]/AC1FP TDN[3]/DC1FP TDN[4]/ADP TDN[5]/APL TDN[6]/AV5 TDN[7] TDN[8]
Input
AA21 AA19 AA18 AA15 AB19 AB16 AB15
Output
Output
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TDP[8:1] sampled either rising falling edges corresponding TCLK[8:1]. TDP[8:1] share same pins ADATA[7:0] inputs. TDP[8:1] selected when SBI_EN tied low.
Transmit Negative Data (TDN[8:1]). When dual-rail mode, these inputs negative data signals transmitted. These inputs sampled either rising falling edges corresponding TCLK[8:1]. These input pins ignored device configured single-rail (unipolar) transmit mode. TDN[6:1] share same pins REFCLK, AC1FP, DC1FP, ADP, inputs. TDN[6:1] selected when SBI_EN tied low. Recovered Clock Output (RCLK[8:1]). RCLK[8:1] clock recovered from RXTIP[8:1] RXRING[8:1] input signals.
Receive Digital Positive Data (RDP[8:1]). When single rail mode, RDP[8:1] output sampled DS-1 data which been decoded AMI, B8ZS, HDB3 line code rules. When dual rail mode, RDP[8:1] output sampled bipolar positive pulses. RDP[8:1] updated either falling rising RCLK[8:1] edge. RDP[8:1] share same pins DDATA[7:0] outputs. RDP[8:1] selected when SBI_EN tied low.
Input
Transmit Positive Data (TDP[8:1]). When single-rail mode, these inputs data signals transmitted. These inputs configured active high active low. When dual-rail mode, these inputs positive data signals transmitted.
Transmit Clock inputs (TCLK[8:1]) should 1.544 2.048 data streams used sample corresponding TDP[8:1] TDN[8:1] signals.
System Side Serial Clock Data Interface
convention, where eight pins indexed [8:1] present, index indicates which octant applies. With TCLK[8:1], example, TCLK[1] applies octant TCLK[2] applies octant etc.
Description
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
RDN/RLCV[1] RDN/RLCV[2] RDN/RLCV[3]/C1FPOUT RDN/RLCV[4]/DDP RDN/RLCV[5]/DPL RDN/RLCV[6]/DV5 RDN/RLCV[7] RDN/RLCV[8]/DACTIVE
Output
AB18 AB17
AC1FP/TDN[2]
Input
DC1FP/TDN[3]
Input
AA21
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REFCLK nominally duty cycle clock frequency 19.44 ±50ppm. REFCLK shares same TDN[1] input. REFCLK selected when SBI_EN tied high.
octet frame pulse signal (AC1FP) provides frame synchronisation devices connected interface. AC1FP must asserted REFCLK cycle every multiples thereof (i.e. every 9720 REFCLK cycles, where positive integer). devices connected must synchronised AC1FP signal from single source. AC1FP sampled rising edge REFCLK. AC1FP shares same TDN[2] input. AC1FP selected when SBI_EN tied high. DROP octet frame pulse signal (DC1FP) provides frame synchronisation devices connected interface. DC1FP must asserted REFCLK cycle every multiples thereof (i.e. every 9720 REFCLK cycles, where positive integer). devices connected DROP must synchronised DC1FP signal from single source. DC1FP sampled rising edge REFCLK. DC1FP shares same TDN[3] input. DC1FP selected when SBI_EN tied high.
REFCLK/TDN[1]
Input
reference clock signal (REFCLK) provides reference timing DROP busses.
SBI_EN
SBI_EN
Input
interface enable signal (SBI_EN) selects between serial clock/data system side interfaces. This signal selects device operating mode follows: Mode Clk/data selected system side. interface selected system side.
System Side Interface
RDN/RLCV[3:6] RDN/RLCV[8] share same pins C1FPOUT, DDP, DPL, DACTIVE outputs. RDN/RLCV[3:6] RDN/RLCV[8] selected when SBI_EN tied low.
RDN/RLCV[8:1] updated either falling rising RCLK[8:1] edge.
Receive Digital Negative Data/Line Code Violation Indication (RDN/RLCV[8:1]). When dual rail mode, RDN/RLCV[8:1] output sampled bipolar negative pulses. When single rail mode, RDN/RLCV[8:1] output pulse whenever line code violation excess zeros condition detected.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
C1FPOUT/RDN/RLCV[3]
Output
APL/TDN[5]
Input
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Multiple devices drive uniquely assigned tributary column positions. This parity signal intended detect accidental driver clashes column assignment. sampled rising edge REFCLK.
shares same TDN[4] input. selected when SBI_EN tied high. payload signal (APL) indicates valid data within structure. This signal asserted during octets making tributary. This signal asserted during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal deasserted during octet following octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. sampled rising edge REFCLK. shares same TDN[5] input. selected when SBI_EN tied high.
ADP/TDN[4]
Input
parity signal (ADP) carries even parity signals. parity calculation encompasses ADATA[7:0], signals.
ADATA[7:0] share same pins TDP[8:1] inputs. ADATA[7:0] selected when SBI_EN tied high.
ADATA[0]/TDP[1] ADATA[1]/TDP[2] ADATA[2]/TDP[3] ADATA[3]/TDP[4] ADATA[4]/TDP[5] ADATA[5]/TDP[6] ADATA[6]/TDP[7] ADATA[7]/TDP[8]
ADATA[7:0] sampled rising edge REFCLK.
Input
data signals (ADATA[7:0]) contain time division multiplexed transmit data from independently timed links. Link data transported tributaries within structure. OCTLIU configured extract data from tributaries within structure.
C1FPOUT shares same RDN/RLCV[3] output. C1FPOUT selected when SBI_EN tied high.
C1FPOUT updated rising edge REFCLK.
octet frame pulse output signal (C1FPOUT) used provide frame synchronisation devices interconnected interface. C1FPOUT asserted REFCLK cycle every (i.e. every 9720 REFCLK cycles). C1FPOUT used synchronisation, must connected A/DC1FP inputs devices connected DROP bus.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
AV5/TDN[6]
Input
payload indicator signal (AV5) locates position floating payloads each tributary within structure. Timing differences between port timing timing indicated adjustments this payload indicator relative fixed structure. movements indicated this signal must accompanied appropriate adjustments signal. shares same TDN[6] input. selected when SBI_EN tied high.
DDP/RDN/RLCV[4]
Tristate Output
DPL/RDN/RLCV[5]
Tristate Output
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DDATA[7:0] updated rising edge REFCLK. DDATA[7:0] share same pins RDP[8:1] outputs. DDATA[7:0] selected when SBI_EN tied high. DROP parity signal (DDP) carries even parity DROP signals. parity calculation encompasses DDATA[7:0], signals. Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column. This parity signal intended detect accidental source clashes column assignment. updated rising edge REFCLK. shares same RDN/RLCV[4] output. selected when SBI_EN tied high. DROP payload signal (DPL) indicates valid data within structure. This signal asserted during octets making tributary. This signal asserted during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal deasserted during octet following octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column. updated rising edge REFCLK. shares same RDN/RLCV[5] output. selected when SBI_EN tied high.
DDATA[0]/RDP[1] DDATA[1]/RDP[2] DDATA[2]/RDP[3] DDATA[3]/RDP[4] DDATA[4]/RDP[5] DDATA[5]/RDP[6] DDATA[6]/RDP[7] DDATA[7]/RDP[8]
Tristate Output
AB19 AB16 AB15
DROP data signals (DDATA[7:0]) contain time division multiplexed receive data from independently timed links. Link data transported tributaries within structure. OCTLIU configured insert data into tributaries within structure. Multiple devices drive DROP uniquely assigned tributary column positions. DDATA[7:0] tristated when OCTLIU outputting data particular tributary column.
sampled rising edge REFCLK.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
DV5/RDN/RLCV[6]
updated rising edge REFCLK.
Transmit Line Interface
TXTIP1[1] TXTIP1[2] TXTIP1[3] TXTIP1[4] TXTIP1[5] TXTIP1[6] TXTIP1[7] TXTIP1[8] TXTIP2[1] TXTIP2[2] TXTIP2[3] TXTIP2[4] TXTIP2[5] TXTIP2[6] TXTIP2[7] TXTIP2[8] TXRING1[1] TXRING1[2] TXRING1[3] TXRING1[4] TXRING1[5] TXRING1[6] TXRING1[7] TXRING1[8] TXRING2[1] TXRING2[2] TXRING2[3] TXRING2[4] TXRING2[5] TXRING2[6] TXRING2[7] TXRING2[8] Analogue Output AB12 AB11 AB10 AB13 AB14
Analogue Output
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Transmit Analogue Positive Pulse (TXTIP1[8:1] TXTIP2[8:1]). When transmit analogue line interface enabled, TXTIP1[x] TXTIP2[x] analogue outputs drive transmit line pulse signal through external matching transformer. Both TXTIP1[x] TXTIP2[x] normally connected positive lead transformer primary. outputs provided better signal integrity must shorted together board. After reset, TXTIP1[x] TXTIP2[x] high impedance. HIGHZ octant's XLPG Line Driver Configuration register must programmed logic remove high impedance state.
Transmit Analogue Negative Pulse (TXRING1[8:1] TXRING2[8:1]). When transmit analogue line interface enabled, TXRING1[x] TXRING2[x] analogue outputs drive transmit line pulse signal through external matching transformer. Both TXRING1[x] TXRING2[x] normally connected negative lead transformer primary. outputs provided better signal integrity must shorted together board. After reset, TXRING1[x] TXRING2[x] high impedance. HIGHZ octant's XLPG Line Driver Configuration register must programmed logic remove high impedance state.
DACTIVE shares same RDN/RLCV[8] output. DACTIVE selected when SBI_EN tied high.
DACTIVE updated rising edge REFCLK.
DACTIVE/RDN/RLCV[8]
Output
DROP active indicator signal (DACTIVE) asserted whenever OCTLIU driving DROP signals, DDATA[7:0], DDP, DV5.
shares same RDN/RLCV[6] output. selected when SBI_EN tied high.
Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column.
Tristate output
DROP payload indicator signal (DV5) locates position floating payloads each tributary within structure. Timing differences between port timing timing indicated adjustments this payload indicator relative fixed structure.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Receive Line Interface
RXTIP[1] RXTIP[2] RXTIP[3] RXTIP[4] RXTIP[5] RXTIP[6] RXTIP[7] RXTIP[8] RXRING[1] RXRING[2] RXRING[3] RXRING[4] RXRING[5] RXRING[6] RXRING[7] RXRING[8]
RSYNC
Output
Alarm Interface
Output
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
mode, 2.048 clock used reference. When used this way, however, jitter transfer specifications AT&T TR62411 met.
Recovered Clock Synchronization Signal (RSYNC). This output signal recovered, jitter attenuated, receiver line rate clock (1.544 2.048 MHz) eight channels optionally, recovered, jitter attenuated clock synchronously divided mode) mode) create timing reference signal. default source RSYNC from octant When OCTLIU loss signal state, RSYNC derived from XCLK input optionally, held high.
Loss Signal Alarm (LOS). This signal outputs status octants serial format which repeats every XCLK cycles. presence status this output indicated LOS_L1 output pulsing high. following XCLK cycle, status output, then This signal intended Hardware Only mode. When microprocessor interface enabled, status alarm also determined reading LOSV CDRC Interrupt Status register. updated falling edge XCLK.
XCLK
Input
Crystal Clock Input (XCLK). This signal provides stable, global timing reference OCTLIU internal circuitry internal clock synthesizer. XCLK nominally jitter free clock 1.544 mode 2.048 mode.
Timing Options Control
Analogue Input
Receive Analogue Negative Pulse (RXRING[8:1]). When analogue receive line interface enabled, RXRING[x] samples received line pulse signal from external isolation transformer. RXRING[x] normally connected directly negative lead receive transformer secondary.
Analogue Input
Receive Analogue Positive Pulse (RXTIP[8:1]). When analogue receive line interface enabled, RXTIP[x] samples received line pulse signal from external isolation transformer. RXTIP[x] normally connected directly positive lead receive transformer secondary.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
LOS_L1
Output
Misc. Control Signals
RSTB Input
RES_0[1] RES_0[2] RES_0[3] RES_0[4] RES_0[5] RES_0[6] TXHIZ/LLB
Input Analogue
This must tied normal operation.
Input Input
This must tied ground normal operation. Transmitter tri-state enable (TXHIZ) Line Loopback enable (LLB). mode TXHIZ/LLB controlled register 005H, (TXHIZ_LLB_EN). this (TXHIZ_LLB_EN) logic setting TXHIZ/LLB=1 forces each transmitters into high impedance state (i.e. TXTIP1[8:1], TXTIP2[8:1], TXRING1[8:1] TXRING2[8:1]). Optionally, TXHIZ_LLB_EN logic setting TXHIZ/LLB=1 forces each LIU's into line loopback. When line loopback enabled recovered data internally directed digital inputs transmit jitter attenuator.
Microprocessor Interface
A[0]/LEN1[0] A[1]/LEN1[1] A[2]/LEN1[2] A[3]/LEN2[0] A[4]/LEN2[1] A[5]/LEN2[2] A[6]/LEN3[0] A[7]/LEN3[1] A[8]/LEN3[2] A[9]/LEN4[0] A[10]/LEN4[1] ALE/LEN4[2] Input
Input
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Address (A[10:0]). This selects specific registers during OCTLIU register accesses. Signal A[10] selects between normal mode test mode register access. A[10] internal pull down resistor. A[10:0] share same pins some LENx[2:0] inputs. A[10:0] selected when HW_ONLY tied low.
Address Latch Enable (ALE). This signal active high latches address contents, A[10:0], when low. When high, internal address latches transparent. allows OCTLIU interface multiplexed address/data bus. input internal pull resistor. shares same LEN4[2] input. selected when HW_ONLY tied low.
These pins must connected analogue ground normal operation.
Active Reset (RSTB). This signal provides asynchronous OCTLIU reset. RSTB Schmidt triggered input with internal pull resistor.
LOS_L1 updated falling edge XCLK.
Loss Signal indicator (LOS_L1). This signal pulsed high XCLK cycle every XCLK cycles indicates that status being output LOS.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
WRB/LEN5[0]
Input
RDB/LEN5[1]
Input
CSB/LEN5[2]
Input
INTB/LEN6[0]
Open-drain Output
D[0]/LEN6[1] D[1]/LEN6[2] D[2]/LEN7[0] D[3]/LEN7[1] D[4]/LEN7[2] D[5]/LEN8[0] D[6]/LEN8[1] D[7]/LEN8[2] PO/SRDI
Output
PI/SRDO
Input
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Active Open-Drain Interrupt (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source which time, INTB will tristate. INTB shares same LEN6[0] input. INTB selected when HW_ONLY tied low. Bi-directional Data (D[7:0]). This provides OCTLIU register read write accesses. D[7:0] share same pins some LENx[2:0] inputs. D[7:0] selected when HW_ONLY tied low.
Programmable Output (PO). programmable output controlled register 00EH, (PO_EN). When PO_EN logic logic Otherwise when PO_EN logic logic shares same SRDI output. selected when HW_ONLY tied low. Programmable Input (PI). status programmable input observed register 00EH, (PI_S). Reading PI_S register latches state input. shares same SRDO input. selected when HW_ONLY tied low.
shares same LEN5[2] input. selected when HW_ONLY tied low.
Active Chip Select (CSB). must enable OCTLIU register accesses. must high least once after power clear internal test modes. used, should tied inverted version RSTB, which case, determine register accesses.
shares same LEN5[1] input. selected when HW_ONLY tied low.
Active Read Enable (RDB). This signal during OCTLIU register read accesses. OCTLIU drives D[7:0] with contents addressed register while low.
shares same LEN5[0] input. selected when HW_ONLY tied low.
Active Write Strobe (WRB). This signal during OCTLIU register write access. D[7:0] contents clocked into addressed register rising edge while low. Alternatively, D[7:0] contents clocked into addressed register rising edge while low.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Hardware-Only Control Interface
HW_ONLY Input
Hardware Only mode enable signal (HW_ONLY) selects between microprocessor-controlled hardware-only modes operation. When HW_ONLY tied low, microprocessor interface enabled. When HW_ONLY tied high, hardware-only control interface enabled microprocessor interface unused. Serial PROM Cascade Control (SRCASC). When SRCASC tied low, OCTLIU acts Serial PROM master controller SREN, SRCLK, SRDI SRDO pins should connected serial PROM. When SRCASC tied high, OCTLIU acts Serial PROM cascade slave SREN, SRCLK SRDO pins should connected SRCEN, SRCCLK SRCDO pins another OCTLIU device upstream cascade. Serial PROM Enable (SREN). When operating Serial PROM master (SRCASC tied low), SREN functions output generates active chip select signal serial PROM. When operating Serial PROM slave (SRCASC tied high), SREN functions input indicates validity cascade data SRDO input.
SRCLK
SRDI/PO
Output
SRDO/PI
Input
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When configured output, SREN updated falling edge SRCLK. When configured input, SREN sampled rising edge SRCLK.
Serial PROM Clock (SRCLK). When operating Serial PROM master (SRCASC tied low), SRCLK functions output generates clock serial PROM. When operating Serial PROM slave (SRCASC tied high), SRCLK functions input connected SRCCLK output OCTLIU device upstream serial PROM cascade. Serial PROM Data (SRDI). When operating Serial PROM master (SRCASC tied low), SRDI output used send read commands serial PROM. When operating Serial PROM slave (SRCASC tied high), SRDI unused. SRDI updated falling edge SRCLK. SRDI shares same output. SRDI selected when HW_ONLY logic Serial PROM Data (SRDO). When operating Serial PROM master (SRCASC tied low), SRDO input receives data from serial PROM. When operating Serial PROM slave (SRCASC tied high), SRDO input receives data from SRCDO output OCTLIU device upstream serial PROM cascade. SRDO sampled rising edge SRCLK. SRDO shares same input. SRDO selected when HW_ONLY logic
SREN
SRCASC
Input
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
SRCEN
Output
SRCEN updated falling edge SRCCLK. SRCCLK Output Serial PROM Cascade Clock (SRCCLK). When operating Serial PROM master (SRCASC tied low), SRCCLK output copy SRCLK output. When operating Serial PROM slave (SRCASC tied high), SRCCLK output copy SRCLK input. Serial PROM Cascade Data (SRCDO). SRCDO output buffered, retimed copy SRDO input. Serial PROM Code (SRCODE). SRCODE input provides means controlling execution configuration instructions stored serial PROM. Instructions coded execute only SRCODE logic only SRCODE logic unconditionally. SRCODE input thus allows selection different configuration sequences within single PROM load. This could used, example, store configurations operation within serial PROM.
SRCODE
Input
LEN3[0]/A[6] LEN3[1]/A[7] LEN3[2]/A[8] LEN4[0]/A[9] LEN4[1]/A[10] LEN4[2]/ALE
LEN2[0]/A[3] LEN2[1]/A[4] LEN2[2]/A[5]
JTAG Interface
Tristate Output Test Data Output (TDO). This signal carries test data OCTLIU IEEE 1149.1 test access port. updated falling edge TCK. tri-state output that tri-stated except when scanning data progress.
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LEN8[0]/D[5] LEN8[1]/D[6] LEN8[2]/D[7]
LEN7[0]/D[2] LEN7[1]/D[3] LEN7[2]/D[4]
LEN6[0]/INTB LEN6[1]/D[0] LEN6[2]/D[1]
LEN5[0]/WRB LEN5[1]/RDB LEN5[2]/CSB
LEN1[0]/A[0] LEN1[1]/A[1] LEN1[2]/A[2]
Input
Line Length Build-out Select (LENn[2:0]). These signals preset select eight different pulse templates used line transmitters, depending line length, etc. LENn[2:0] selects pulse template line transmitter octant LENn[2:0] share same pins microprocessor interface signals. LENn[2:0] selected when HW_ONLY tied high. LENn[2:0] inputs latched following reset OCTLIU changes their value will have effect operation OCTLIU until subsequent reset.
SRCDO updated falling edge SRCCLK.
SRCDO
Output
Serial PROM Cascade Enable (SRCEN). SRCEN output asserted when valid data being output SRCDO.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Input
TRSTB
Input
Analogue Power Ground Pins
TAVD1[1] TAVD1[2] TAVD1[3] TAVD1[4] TAVD1[5] TAVD1[6] TAVD1[7] TAVD1[8] TAVD2[1] TAVD2[2] TAVD2[3] TAVD2[4] TAVD2[5] TAVD2[6] TAVD2[7] TAVD2[8] TAVD3[1] TAVD3[2] TAVD3[3] TAVD3[4] TAVD3[5] TAVD3[6] TAVD3[7] TAVD3[8] CAVD
Analogue Power
AA12 AA10
Analogue Power
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Analogue Power
Transmit Analogue Power (TAVD1[8:1]). TAVD1[8:1] provide power transmit analogue circuitry. TAVD1[8:1] should connected analogue +3.3
Transmit Analogue Power (TAVD2[8:1], TAVD3[8:1]). TAVD2[8:1] TAVD3[8:1] supply power transmit current DACs. They should connected analogue +3.3
Clock Synthesis Unit Analogue Power (CAVD). CAVD supplies power transmit clock synthesis unit. CAVD should connected analogue +3.3
Note that used, TRSTB should connected RSTB input.
Active Test Reset (TRSTB). This signal provides asynchronous OCTLIU test access port reset IEEE 1149.1 test access port. TRSTB Schmidt triggered input with internal pull resistor. TRSTB must asserted during power sequence.
Input
Test Mode Select (TMS). This signal controls test operations that carried using IEEE 1149.1 test access port. sampled rising edge TCK. internal pull resistor.
Input
Test Clock (TCK). This signal provides timing test operations that carried using IEEE 1149.1 test access port.
Test Data Input (TDI). This signal carries test data into OCTLIU IEEE 1149.1 test access port. sampled rising edge TCK. internal pull resistor.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
TAVS1[1] TAVS1[2] TAVS1[3] TAVS1[4] TAVS1[5] TAVS1[6] TAVS1[7] TAVS1[8] TAVS2[1] TAVS2[2] TAVS2[3] TAVS2[4] TAVS2[5] TAVS2[6] TAVS2[7] TAVS2[8] TAVS3[1] TAVS3[2] TAVS3[3] TAVS3[4] TAVS3[5] TAVS3[6] TAVS3[7] TAVS3[8] CAVS
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RAVS1[1] RAVS1[2] RAVS1[3] RAVS1[4] RAVS1[5] RAVS1[6] RAVS1[7] RAVS1[8]
RAVD2[1] RAVD2[2] RAVD2[3] RAVD2[4] RAVD2[5] RAVD2[6] RAVD2[7] RAVD2[8]
Analogue Power
RAVD1[1] RAVD1[2] RAVD1[3] RAVD1[4] RAVD1[5] RAVD1[6] RAVD1[7] RAVD1[8]
Analogue Power
Analogue Ground
Analogue Ground
AA11
Clock Synthesis Unit Analogue Ground (CAVS). CAVS supplies ground transmit clock synthesis unit. CAVS should connected analogue GND. Receive Analogue Power (RAVD1[8:1]). RAVD1[8:1] supplies power receive input equalizer. RAVD1[8:1] should connected analogue +3.3
Receive Analogue Power (RAVD2[8:1]). RAVD2[8:1] supplies power receive peak detect slicer. RAVD2[8:1] should connected analogue +3.3
Receive Analogue Ground (RAVS1[8:1]). RAVS1[8:1] supplies ground receive input equalizer. RAVS1[8:1] should connected analogue GND.
Analogue Ground
Transmit Analogue Ground (TAVS2[8:1], TAVS3[8:1]). TAVS2[8:1] TAVS3[8:1] supply ground transmit current DACs. They should connected analogue GND.
Analogue Ground
Transmit Analogue Ground (TAVS1[8:1]). TAVS1[8:1] provide ground transmit analogue circuitry. TAVS1[8:1] should connected analogue GND.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
RAVS2[1] RAVS2[2] RAVS2[3] RAVS2[4] RAVS2[5] RAVS2[6] RAVS2[7] RAVS2[8] QAVD[1] QAVD[2] QAVD[3] QAVD[4] QAVS[1] QAVS[2] QAVS[3] QAVS[4]
Digital Power Ground Pins
VDD1V8[1] VDD1V8[2] VDD1V8[3] VDD1V8[4] VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14] VDD3V3[15] VDD3V3[16] VDD3V3[17] VDD3V3[18] VDD3V3[19] Power AA14
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Power
Power (VDD3V3[19:1]). VDD3V3[19:1] pins should connected well decoupled +3.3V power supply.
Core Power (VDD1V8[4:1]). VDD1V8[4:1] pins should connected well decoupled +1.8V power supply.
Analogue Ground
Quiet Analogue Ground (QAVS[4:1]). QAVS[4:1] supplies ground core analogue circuitry. QAVS[4:1] should connected analogue GND.
Analogue Power
AA13
Quiet Analogue Power (QAVD[4:1]). QAVD[4:1] supplies power core analogue circuitry. QAVD[4:1] should connected analogue +3.3
Analogue Ground
Receive Analogue Ground (RAVS2[8:1]). RAVS2[8:1] supplies ground receive peak detect slicer. RAVS2[8:1] should connected analogue GND.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
unused inputs should connected GROUND. Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, VDD3V3) will collectively referred VDDall33 this document.
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analogue digital ground pins (i.e., TAVS1, TAVS2, TAVS3, CAVS, QAVS, RAVS1, RAVS2 VSS) must connected common impedance ground plane.
VDDall33 voltage level should allowed drop below VDD1V8 voltage level except when VDD1V8 powered.
Power VDDall33 should applied before power VDD1V8 pins applied. Similarly, power VDD1V8 pins should removed before power VDDall33 removed.
Inputs A[10], RES_0[1], RES_0[6] have internal pull-down resistors.
Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors.
OCTLIU outputs bi-directionals have least drive capability, except LOS, LOS_L1, serial PROM interface outputs, which have least drive capability. transmit analogue outputs (TXTIP TXRING) have built-in short circuit current limiting.
OCTLIU inputs bi-directionals, when configured inputs, tolerate logic levels.
OCTLIU inputs bi-directionals present minimum capacitive loading.
Notes Descriptions
Open
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25]
Ground
AA16 AA17 AB20 AB21 AB22
These pins must left unconnected.
Ground (VSS [25:1]). VSS[25:1] pins should connected Ground.
Name
Type
Function
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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Clock Data Recovery function provided Clock Data Recovery (CDRC) block. CDRC provides clock data recovery, B8ZS HDB3 decoding, line code violation detection, loss signal detection. recovers clock from incoming data pulses using digital phase-locked-loop reconstructs data. Loss signal indicated after programmable threshold consecutive periods absence pulses both positive negative line pulse inputs cleared after occurrence single line pulse. alternate loss signal indication provided which cleared upon meeting 1-in-8 pulse density criteria 1-in-4 pulse density criteria enabled, microprocessor interrupt generated when loss signal detected when signal returns. line code violation defined bipolar violation (BPV) AMI-coded signals, defined that part zero substitution code B8ZS-coded signals, defined bipolar violation same polarity last bipolar violation HDB3-coded signals. mode, input jitter tolerance OCTLIU complies with Bellcore Document TA-TSY-000170 with AT&T specification TR62411, shown Figure tolerance measured with QRSS sequence (220-1 with zero restriction).
Clock Data Recovery (CDRC)
short-haul, slicing threshold fraction input signal's peak amplitude, adapts changes this amplitude. slicing threshold programmable, typically DSX-1 applications, respectively. Abnormally input signals detected when input level below programmable threshold, which typically
long-haul signals, unequalized long- short-haul bipolar alternate mark inversion (AMI) signals received differential voltage between RXTIP RXRING inputs. OCTLIU typically accepts unequalized signals that attenuated both signals non-linearly distorted typical cables.
analogue receive interface configurable operate both short-haul longhaul applications. Short-haul defined transmission over less than cable. Shorthaul defined transmission cable that attenuates signal less than
Receive Interface
OCTLIU's eight E1/T1 line interface units operate independently configured operate uniquely. octants share common XCLK clock input internal clock synthesizer; hence only single Configuration register present. Additionally, octants share common E1/T1B mode register select between operation.
Octants
Functional Description
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Acceptable Range Sine Wave Jitter Amplitude (UI) Scale
0.30 0.31
Sine Wave Jitter Frequency (kHz) Scale
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applications, input jitter tolerance complies with ITU-T Recommendation G.823 "The Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy." Figure illustrates this specification performance phase-locked loop.
Bellcore Spec. AT&T Spec.
Figure Jitter Tolerance
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
REC. G823 JITTER TOLERANCE SPECIFICATION
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jitter characteristics Receive Jitter Attenuator (RJAT) same Transmit Jitter Attenuator (TJAT).
Receive Jitter Attenuator (RJAT) digital attenuates jitter present RXTIP/RXRING inputs. attenuation only performed when RJATBYP register logic
Receive Jitter Attenuator (RJAT)
SINEWAVE JITTER FREQUENCY, SCALE
SINEWAVE JITTER AMPLITUDE (UI) SCALE
SPEC REGION
DPLL TOLERANCE WITH HDB3 ENCODED PRBS
DPLL TOLERANCE WITH ENCODED PRBS
Figure Compliance with ITU-T Specification G.823 Input Jitter
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Pulse Density Violation Detector (PDVD)
Pulse Density Violation Detection function provided PDVD block. block detects pulse density violations requirement that there ones each every time window 8(N+1) data bits (where equal through 23). PDVD also detects periods consecutive zeros incoming data. Pulse density violation detection provided through internal register bit. interrupt generated signal consecutive zero event, and/or change state pulse density violation indication.
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Pseudo Random Binary Sequence Generator/Detector (PRBS) block software selectable PRBS generator checker 211-1, 215-1 220-1 PRBS polynomials links. PRBS patterns generated detected either transmit receive directions.
Pseudo Random Binary Sequence Generation Detection (PRBS)
Triggering counter transfer within octant performed writing counter register location within octant writing "Line Interface Interrupt Source PMON Update" register.
Performance Monitor block accumulates line code violation events with saturating counter over consecutive intervals defined period between writes trigger registers (typically second). When trigger applied, PMON transfers counter value into holding registers resets counter begin accumulating events interval. counter reset such manner that error events occurring during reset missed.
Performance Monitor Counters (PMON)
Inband Loopback Code Detection function provided IBCD block. This block detects presence either programmable INBAND LOOPBACK ACTIVATE DEACTIVATE code sequences receive data stream. Each INBAND LOOPBACK code sequence defined repetition programmed code stream least seconds. detection algorithm tolerates more than minimum number discrepancy bits order detect framed data presence 10-2 error rate. code sequence detection timing compatible with specifications defined T1.403-1993, TA-TSY000312, TR-TSY-000303. LOOPBACK ACTIVATE DEACTIVATE code indication provided through internal register bits. interrupt generated indicate when either code status changed.
Inband Loopback Code Detector (IBCD)
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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jitter attenuator generates jitter-free 1.544 2.048 Transmit clock output adjusting Transmit clock's phase 1/96 increments minimize phase difference between generated Transmit clock input data clock TJAT. Jitter fluctuations phase input data clock attenuated phase-locked loop within TJAT that frequency Transmit clock equal average frequency input data clock. applications, best jitter attenuation transfer function recommended 62411, phase fluctuations with jitter frequency above attenuated octave jitter frequency. Wandering phase fluctuations with frequencies below tracked generated Transmit clock. applications, corner frequency provide smooth flow data TJAT, Transmit clock used read data FIFO.
Transmit Jitter Attenuation function provided digital phase lock loop 80-bit deep FIFO. TJAT receives jittery, dual-rail data format separate inputs, which allows bipolar violations pass through block uncorrected. incoming data streams stored FIFO timed transmit clock. respective input data emerges from FIFO timed jitter attenuated clock.
9.11 Transmit Jitter Attenuator (TJAT)
This block monitors digital output transmitter detects when stream about violate ANSI T1.403 12.5% pulse density rule over moving 192-bit window. density violation detected, block enabled insert logic into digital stream ensure resultant output longer violates pulse density requirement. When XPDE disabled from inserting logic digital stream from transmitter passed through unaltered.
Pulse Density Enforcer function provided XPDE block. Pulse density enforcement enabled register within XPDE.
9.10 Pulse Density Enforcer (XPDE)
Inband Loopback Code Generator (XIBC) block generates stream inband loopback codes (IBC) inserted into data stream. stream consists continuous repetitions specific code. contents code length programmable from bits.
Inband Loopback Code Generator (XIBC)
PRBS block perform auto synchronization expected PRBS pattern accumulates total number errors 24-bit counters. error count accumulates over interval defined successive writes Line Interface Interrupt Source PMON Update register. When accumulation forced, holding register updated, counter reset begin accumulating next interval. counter reset such that events missed. data then available Error Count registers until next accumulation.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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Jitter tolerance maximum input phase jitter given jitter frequency that device accept without exceeding linear operating range, corrupting data. TJAT, input jitter tolerance Unit Intervals peak-to-peak (Uipp) with worst case frequency offset Uipp with frequency offset. frequency offset difference between frequency XCLK that input data clock.
9.11.2 Jitter Tolerance
TJAT exhibits negligible jitter gain jitter frequencies below (7.6 E1), attenuates jitter frequencies above (7.6 decade. most applications, TJAT block will determine jitter attenuation higher jitter frequencies only. Wander, below example, will essentially passed unattenuated through TJAT. Jitter, above example, will attenuated specified, however, outgoing jitter dominated generated residual jitter cases where incoming jitter insignificant. This generated residual jitter directly related 1/96 phase adjustment quantum. TJAT meets jitter attenuation requirements AT&T 62411. block allows implied jitter attenuation requirements given ANSI Standard T1.408, implied jitter attenuation requirements type customer interface given ANSI T1.403 met.
TJAT Block provides excellent jitter tolerance jitter attenuation while generating minimal residual jitter. accommodate Uipp input jitter jitter frequencies above (7.6 E1). jitter frequencies below (7.6 E1), more correctly called wander, tolerance increases decade. most applications TJAT Block will limit jitter tolerance lower jitter frequencies only. high frequency jitter, above example, other factors such clock data recovery circuitry limit jitter tolerance must considered. frequency wander, below example, other factors such slip buffer hysteresis limit wander tolerance must considered. TJAT block meets stringent frequency jitter tolerance requirements AT&T 62411 thus allows compliance with this standard other less stringent jitter tolerance standards cited references.
9.11.1 Jitter Characteristics
FIFO read pointer (timed Transmit clock) comes within write pointer (timed input data clock), TJAT will track jitter input clock. This permits phase jitter pass through unattenuated, inhibiting loss data.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
MIN.TOLER ANCE acceptable
JITTER AMPLITUDE,
Figure TJAT Jitter Tolerance
0.01
unacceptable
100k
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accuracy XCLK frequency that TJAT reference input clock used generate jitter-free Transmit clock output have effect minimum jitter tolerance. Given that TJAT reference clock accuracy ±200 that XCLK input accuracy ppm, minimum jitter tolerance various differences between frequency reference clock XCLK shown Figure
JITTER FREQUENCY,
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
MIN. JITTER TOLERANCE,
pp48
Figure TJAT Minimum Jitter Tolerance XCLK Accuracy
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applications, output jitter jitter frequencies from (7.6 more than greater than input jitter, excluding residual jitter. Jitter frequencies above (7.6 attenuated level octave, shown Figure figure valid case where TJAT Jitter Attenuator Divider Control register TJAT Divider Control register.
9.11.3 Jitter Transfer
XCLK ACCURACY
MAX. FREQUENCY OFFSET
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
guaranteed linear operating range jittered input clock 1.544 with worst case jitter Uipp), maximum system clock frequency offset ppm). nominal range 1.544 with jitter system clock frequency offset.
non-attenuating mode, when FIFO within overrunning underrunning, tracking range 2.13 1.97 MHz. guaranteed linear operating range jittered input clock 2.048 with worst case jitter Uipp), maximum system clock frequency offset ppm). nominal range 2.048 1277 with jitter system clock frequency offset.
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Jitter Generation absence input jitter, output jitter shall less than 0.025 Uipp. This complies with AT&T 62411 requirement less than 0.025 Uipp jitter generation.
non-attenuating mode, when FIFO within overrunning underrunning, tracking range 1.48 1.608 MHz.
JITTER FREQUENCY
JITTER GAIN
response
62411
62411
43802
Figure TJAT Jitter Transfer
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
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Timing Options block provides means selecting source internal input clock TJAT block, reference clock TJAT digital PLL.
9.13 Timing Options (TOPS)
Refer Operation section details creating synthesized pulse shape.
pulse shape user programmable. short haul, cable length between OCTLIU cross-connect (where pulse template specifications given) greatly affects resulting pulse shapes. Hence, data applied converter must account different cable lengths. CEPT applications pulse template specified transmitter, thus only setting required. long haul with previous bits effect what transmitter must drive compensate inter-symbol interference; LBO's 22.5 previous bits effect what transmitter must send out.
output pulse shape synthesized digitally with current digital-to-analogue (DAC) converters, which produce samples symbol. current DAC's produce differential bipolar outputs that directly drive TXTIP1[x], TXTIP2[x], TXRING1[x] TXRING2[x] pins. current output applied terminating resistor line-coupling transformer differential manner, which when viewed from line side transformer produce output pulses required levels ensures small positive negative pulse imbalance.
line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable DSX-1 (short haul T1), short haul long haul long haul environments. voltage pulses produced applying current known termination (termination resistor plus line impedance). current (instead voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) transmit tri-stating.
9.12 Line Transmitter
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
TTip chassis TRing outB center outA
TXTIP TXRING
Phantom Feed Circuit Vsupply required RTip RRing
RXTIP RXRING
outB
center
chassis
outA
Table descriptions components Figure Note that crowbar devices required transformer's isolation rating exceeded.
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systems requiring phantom feed inter-building line protection, Bi-directional Transient Surge Suppressors (Z1-Z4), their associated ground connection center transformer removed from circuit.
Figure gives recommended external protection circuitry designs required meet major surge immunity electrical safety standards including Part UL1950, Bellcore TR-NWT-001089.
Eight LIUs
Figure External Analogue Interface Circuits
9.14 External Analogue Interface Circuits
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Component
Description
36.0 ±1%, 0.25W Resistor 27.0 ±1%, 0.25W Resistor Surge Protector Diode Array Transformers Bi-directional Transient Surge Suppressors Bi-directional Transient Surge Suppressors Dual Choke, 47µH Telecom/Time Fuses
Part
ERJ-14NF36R0U ERJ-14NF27R0U SRDA3.3-4 T9023 P1800SC P0720SC
PE-68624
9.15 Scaleable Bandwidth Interconnect (SBI) Interface
Scaleable Bandwidth Interconnect synchronous, time-division multiplexed designed transfer, pin-efficient manner, data belonging number independently timed links varying bandwidth. timed reference 19.44MHz clock fraction thereof) frame pulse. sources sinks data timed reference clock frame pulse. Timing communicated across Scaleable Bandwidth Interconnect floating data structures. Payload indicator signals control position floating data structure therefore timing. When sources running faster than floating payload structure advanced octet passing extra octet octet locations octet mappings which used OCTLIU). When source slower than floating payload retarded leaving octet after octet unused. Both these rate adjustments indicated control signals. multiplexing structure modeled SONET/SDH standards. SONET/SDH virtual tributary structure used carry T1/J1 links. Unchannelized payloads (not used OCTLIU) follow byte synchronous structure modeled SONET/SDH format. structure uses locked SONET/SDH structure fixing position TUG-3/TU-3 relative STS-3/STM-1 transport frame. also fixed frequency alignment determined reference clock (REFCLK) frame indicator signal (C1FP). Frequency deviations compensated adjusting location T1/J1/E1/DS3 channels using floating tributaries determined indicator payload signals (DV5, AV5, APL). Note that OCTLIU always operates clock slave clock master DROP bus, i.e. does support AJUST_REQ DJUST_REQ timing adjustment request signals defined specification.
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When operating mode with cable, 1:1.58 turns ratio transformer specified above table. fact also possible turns ratio transformer, which case value must changed 22.0 value must changed 18.0 ±1%.
F1250T
Pulse Pulse
Table External Component Descriptions
Source
Panasonic Panasonic
Semtech Teccor Teccor Teccor
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
AC1FP signal generated downstream transmit path blocks disabled, since clock will generated.
9.18 Serial PROM Interface
Figure Serial PROM Cascade Interface
serial PROM interface used configure OCTLIU absence microprocessor. single SPI-compatible serial PROM used configure number OCTLIU devices simultaneously (provided such devices intended configured identically) connecting devices cascade shown Figure
Insert block receives serial data from octants inserts DROP BUS. Insert block configured enable disable transmission individual tributaries DROP bus.
9.17 Inserter SIPO
SRCASC
HOLD
SREN SRCLK SRDI SRDO
SRCEN SRCCLK n.c. SRCDO
Extract block receives data from converts serial streams transmission. Extract block configured enable disable extraction individual tributaries within bus. also configured generate all-1s output transmit when alarm indication signalled particular tributary bus.
SRCASC SREN SRCLK SRDI SRDO SRCEN SRCCLK SRCDO
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PROM
OCTLIU Cascade Master
SPI-compatible PROMs organised 8-bit words. contents PROM read sequentially starting address continuing until specially coded stop command encountered. Each configuration command coded 3-bytes follows:
OCTLIU Cascade Slave
9.16 Extracter PISO
multiplexed links separated into three Synchronous Payload Envelopes (SPE). Each envelope configured independently carry T1/J1s, DS3. OCTLIU configured eight T1/J1 tributaries eight tributaries from three SPE's. eight tributaries need selected from same SPE. single OCTLIU device cannot, however, T1/J1 tributaries simultaneously.
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Code1
Code0
Action
Special Command
Write Data[7:0] Reg[13:0] regardless value SRCODE
3FFC 3FFD
3FFE 3FFF
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`ignore subsequent register write commands' command used configure multiple OCTLIU's cascade individually (for example, allocate different tributaries different OCTLIU devices). provides means progressively `switch off' each device cascade once been configured. Consider example following sequence configuration commands:
No-op.
Ignore subsequent register write commands. This command only acted upon first OCTLIU cascade which receives which already ignoring register write commands. OCTLIU which acts upon this command does propagate command down cascade, instead substitutes 3FFC special command. Pause Data[7:0] 4096 XCLK periods before reading next PROM command.
Stop, i.e. configuration OCTLIU finished.
3FFB
Resume acting upon register write commands. Only meaningful 3FFD command (see below) previously been received.
Reg[13:0]
Action
Table Serial PROM Special Commands
When Code1 Code0 `0', Reg[13:0] Data[7:0] fields interpreted special command, register/data pair. following special commands defined:
SRCODE input OCTLIU provides means execute configuration instructions conditionally. different configuration sequences stored single PROM (for operation, example) SRCODE input used select which will applied. Different OCTLIU devices cascade have their SRCODE inputs different values.
Write Data[7:0] Reg[13:0] only SRCODE
Write Data[7:0] Reg[13:0] only SRCODE
Table Serial PROM Commands Code Bits
Reg[13:0] specifies OCTLIU registers defined Table Data[7:0] value written specified register. Commands interpreted depending Code1 Code0 bits follows:
Data[7:0]
Reg[7:0]
Code1
Code0
Reg[13:8]
Figure Serial PROM Command Format
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
3FFD00 C00103 3FFD00 C00104
First device cascade ignores further register writes.
Write register devices cascade except first, regardless SRCODE.
Second device cascade ignores further register writes.
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Microprocessor Interface Block provides normal test mode registers, interrupt logic, logic required connect Microprocessor Interface. normal mode registers required normal operation, test mode registers used enhance testability OCTLIU.
9.20 Microprocessor Interface
JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported.
9.19 JTAG Test Access Port
pause command used, example, allow clock synthesis circuitry within block time stablise before configuring rest device.
(Subsequent configuration commands acted upon devices cascade except first second.)
Write register devices cascade except first two, regardless SRCODE.
(Subsequent configuration commands acted upon devices cascade except first.)
(Subsequent configuration commands acted upon devices cascade.)
C00102
Write register devices cascade, regardless SRCODE.
Command (hex)
Explanation
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Notes Normal Mode Register Bits:
Writeable normal mode register bits cleared zero upon reset unless otherwise noted.
10.1 Normal Mode Register Memory
000H
Addr
Table Normal Mode Register Memory Register
Reset Revision Device Reserved Global Configuration Clock Monitor Reserved Master Interrupt Source Reserved Master Interrupt Source Reserved Master Test Control
001H
002H
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082H, 102H, 182H, 202H, 282H, 302H, 382H 003H 083H, 103H, 183H, 203H, 283H, 303H, 383H 004H
081H, 101H, 181H, 201H, 281H, 301H, 381H
080H, 100H, 180H, 200H, 280H, 300H, 380H
Certain register bits reserved. These bits associated with functions that unused this application. ensure that OCTLIU operates intended, reserved register bits must only written with their default values unless otherwise stated. Similarly, writing reserved registers should avoided unless otherwise stated.
Writing into read-only normal mode register locations does affect OCTLIU operation unless otherwise noted.
configuration bits that written into also read back. This allows processor controlling OCTLIU determine programming state chip.
Writing values into unused register bits effect. Reading back unused bits produce either logic logic hence, unused register bits should masked software when read.
reset OCTLIU defaults mode. proper operation some register configuration expected. default interrupts will enabled, automatic alarm generation disabled.
Register Memory Table below shows where normal mode registers accessed. OCTLIU contains master configuration, SBI, registers sets T1/E1 registers. Where only present, registers apply entire device. Where sets present, each registers apply single octant OCTLIU. convention, where sets registers present, address space 000H 07FH applies octant 080H 0FFH applies octant etc, 380H 3FFH octant
Normal mode registers used configure monitor operation OCTLIU. Normal mode registers opposed test mode registers) selected when A[10] low.
Normal Mode Register Description
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
006H 086H, 106H, 186H, 206H, 286H, 306H, 386H 007H 087H, 107H, 187H, 207H, 287H, 307H, 387H 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH 010H 03FH 090H 0BFH 110H 13FH 190H 1BFH 210H 23FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 290H 2BFH
Configuration Reserv
Receive Line Interface Configuration
Transmit Line Interface Configuration
Line Interface Interrupt Source PMON Update
Line Interface Diagnostics
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Line Interface PRBS Position Reserved Reserved Reserved Reserved Reserved Reserved INSBI Control INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping
Line Interface Interrupt Source
Transmit Line Interface Timing Options Clock Monitor Pulse Template Selection
Receive Line Interface Configuration
Reserv
Reserv
085H, 105H, 185H, 205H, 285H, 305H, 385H
Reserv
005H
Master Test Control
084H, 104H, 184H, 204H, 284H, 304H, 384H
Reserv
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
31AH 31BH 31CH 31DH 31EH 31FH 320H 321H 322H 323H 324H 325H 326H 327H 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 33FH 390H 391H 392H 393H 394H 395H 396H 397H 398H 399H
INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Link Enable INSBI Link Enable Busy INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Minimum Depth INSBI FIFO Thresholds INSBI Reserved INSBI Tributary Control INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping
39AH 39FH 3A0H 3A1H 3A2H 3A3H
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INSBI Depth Check Interrupt Status INSBI Master Interrupt Status INSBI Reserv
EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Parity Error Interrupt Reason EXSBI Depth Check Interrupt Status EXSBI Master Interrupt Status EXSBI Minimum Depth EXSBI FIFO Thresholds EXSBI Link Enable EXSBI Link Enable Busy EXSBI Reserved EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control
INSBI Tributary Control
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
3A4H 3A5H 3A6H 3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H 3B1H 3B2H 3B3H 3B4H 3B5H 3B6H 3B7H 3B8H 3BFH 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H
EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping
EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Reserved Reserved EXSBI Page Octant Tributary Mapping
044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H
043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H
047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H
046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H
045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H
048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH
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Reserved PDVD Reserved PDVD Interrupt Enable/Status XPDE Reserved XPDE Interrupt Enable/Status XIBC Control XIBC Loopback Code RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control
EXSBI Page Octant Tributary Mapping
EXSBI Page Octant Tributary Mapping
EXSBI Page Octant Tributary Mapping
EXSBI Page Octant Tributary Mapping
EXSBI Page Octant Tributary Mapping
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
05AH, 0DAH, 15AH, 1DAH, 25AH, 2DAH, 35AH, 3DAH 05BH, 0DBH, 15BH, 1DBH, 25BH, 2DBH, 35BH, 3DBH
059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H
05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH
05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH
05CH, 0DCH, 15CH, 1DCH, 25CH, 2DCH, 35CH, 3DCH
05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H
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058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H
PMON Interrupt Enable/Status PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON Count (LSB) PMON Count (MSB) PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status
057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H
CDRC Alternate Loss Signal
056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H
CDRC Interrupt Status
055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H
CDRC Interrupt Control
054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H
CDRC Configuration
053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H
IBCD Deactivate Code
052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H
IBCD Activate Code
051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H
IBCD Interrupt Enable/Status
050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H
IBCD Configuration
04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH
TJAT Configuration
04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH
TJAT Output Clock Divisor (N2) Control
04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH
TJAT Reference Clock Divisor (N1) Control
04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH
TJAT Interrupt Status
04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH
RJAT Configuration
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H
070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H
075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H
074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H
073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H
076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H
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06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH
XLPG Reserved RLPS Configuration Status RLPS ALOS Detection/Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization Read/WriteB Select RLPS Equalizer Loop Status Control RLPS Equalizer Configuration RLPS Equalization Indirect Data Register
06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH
XLPG Reserv
06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH
XLPG Fuse Control
06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH
XLPG Pulse Waveform Storage Data
06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH
XLPG Pulse Waveform Storage Write Address
06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH
XLPG Pulse Waveform Storage Write Address
069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H
XLPG Pulse Waveform Scale
068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H
XLPG Control/Status
067H, 0E7H, 167H, 1E7H, 267H, 2E7H, 367H, 3E7H
PRBS Reserv
066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H
PRBS Error Count
065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H
PRBS Error Count
064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H
PRBS Error Count
063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H
PRBS Reserv
062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H
PRBS Pattern Select
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
400H 7FFH
Reserved Test
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07FH, 0FFH, 17FH, 1FFH, 27FH, 2FFH, 37FH, 3FFH
RLPS Reserv
07EH, 0FEH, 17EH, 1FEH, 27EH, 2FEH, 37EH, 3FEH
RLPS Fuse Control
07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH
RLPS Voltage Thresholds
07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH
RLPS Voltage Thresholds
07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH
RLPS Indirect Data Register
07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH
RLPS Indirect Data Register
079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H
RLPS Equalization Indirect Data Register
Addr
Register
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0]
version identification bits, ID[3:0], fixed value representing version number OCTLIU.
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device identification bits, TYPE[2:0], fixed value "100" representing OCTLIU.
TYPE
RESET implements software reset. RESET logic OCTLIU held reset. This self-clearing; therefore, logic must written bring OCTLIU reset. Holding OCTLIU reset state effectively puts into lowpower, stand-by mode. hardware reset clears RESET bit, thus deasserting software reset. RESET must least 100ns.
RESET
Type
Function
Default
Register 000H: Reset Revision Device
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
XCLKA REFCLKA SIMUL_REGWR Reserved RSYNC_SEL[2] RSYNC_SEL[1] RSYNC_SEL[0] E1/T1B
REFCLKA
SIMUL_REGWR
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SIMUL_REGWR must prior reading OCTLIU register.
Note:
Simultaneous Register Write (SIMUL_REGWR) enables registers octants written simultaneously. When SIMUL_REGWR high, write octant register will result same data also being written simultaneously corresponding registers belonging other octants. When SIMUL_REGWR low, write register will result addressed register, that register only, being written.
REFCLK active (REFCLKA) detects high transitions REFCLK input. REFCLKA high rising edge REFCLK, when this register read. lack transitions indicated register reading low. This register read periodic intervals detect clock failures.
XCLK active (XCLKA) detects high transitions XCLK input. XCLKA high rising edge XCLK, when this register read. lack transitions indicated register reading low. This register read periodic intervals detect clock failures.
XCLKA
Type
Function
Default
Register 001H: Global Configuration Clock Monitor
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
E1/T1B
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reserved must default value normal operation.
RESERVED
global E1/T1B selects operating mode eight OCTLIU octants. E1/T1B logic 2.048 Mbit/s mode selected eight octants. E1/T1B logic 1.544 Mbit/s mode selected eight octants.
RSYNC Select register bits, RSYNC_SEL[2:0], select source RSYNC OCTLIU output. When RSYNC_SEL[2:0] "000", octant selected source. When RSYNC_SEL[2:0] "001", octant selected source. When RSYNC_SEL[2:0] "010", octant selected source. When RSYNC_SEL[2:0] "011", octant selected source. When RSYNC_SEL[2:0] "100", octant selected source. When RSYNC_SEL[2:0] "101", octant selected source. When RSYNC_SEL[2:0] "110", octant selected source. When RSYNC_SEL[2:0] "111", octant selected source.
RSYNC_SEL[2:0]
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
LIU[8] LIU[7] LIU[6] LIU[5] LIU[4] LIU[3] LIU[2] LIU[1]
Reading this register does remove interrupt indication; within corresponding octant, corresponding block's interrupt status register must read remove interrupt indication.
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LIU[8:1] register bits allow software determine which octant's LIU(s) is/are producing interrupt INTB output pin. logic indicates interrupt being produced from corresponding octant.
LIU[8:1]
Type
Function
Default
Register 002H: Master Interrupt Source
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Unused Unused Unused Unused Unused Unused EXSBI INSBI
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Reading this register does remove interrupt indication; corresponding block's interrupt status register must read remove interrupt indication.
INSBI EXSBI register bits allow software determine whether INSBI and/or EXSBI blocks producing interrupt INTB output pin. logic indicates interrupt being produced from corresponding block.
INSBI, EXSBI
Type
Function
Default
Register 003H: Master Interrupt Source
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Reserved Reserved Reserved Reserved Reserved Reserved HIZDATA HIZIO
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HIZIO HIZDATA bits control tri-state modes OCTLIU. While HIZIO logic digital output pins OCTLIU except data held high-impedance state. microprocessor interface still active. While HIZDATA logic data held high-impedance state which inhibits microprocessor read cycles. Note that HIZIO HIZDATA have affect analog transmit outputs (TXTIP1[1:8], TXTIP2[1:8], TXRING1[1:8] TXRING2[1:8]).
HIZIO, HIZDATA
This register used select OCTLIU test features. bits, except 7,6,5 reset zero hardware reset OCTLIU, software reset OCTLIU does affect state bits this register.
Type
Function
Default
Register 004H: Master Test Control
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
Reserved Reserved Reserved Reserved TXHIZ_LLB_EN Unused Unused Unus
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These bits must correct operation.
Reserv
Transmitter tri-state line loopback enable. This register used control functionality TXHIZ/LLB pin. TXHIZ_LLB_EN logic TXHIZ/LLB used force analogue transmitter outputs (TXTIP1[1:8], TXTIP2[1:8], TXRING1[1:8] TXRING2[1:8]) into high impedance state. Otherwise, logic TXHIZ/LLB used force octants into line loopback mode.
TXHIZ_LLB_EN
Type
Function
Default
Register 005H: Master Test Control
Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Releas
CSU_RESET IDDQ_EN Unused Unus
MODE[2] MODE[1] MODE[0]
MODE[2:0]
XCLK frequency
2.048 1.544 Reserved Reserved Reserved 2.048
Transmit clock frequency
CSU_LOCK
IDDQ_EN
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2001578, Issue
IDDQ enable (IDDQ_EN) used configure embedded IDDQ tests. When IDDQ_EN logic IDDQEN Master Test Control register logic digital outputs pulled ground. When either IDDQ_EN IDDQEN logic HIGHZ XLPG Line Driver Configuration register must also logic
CSU_LOCK used determine whether embedded clock synthesis unit (CSU) achieved phase frequency lock XCLK. CSU_LOCK polled repetitively persistently logic then divided down synthesized clock frequency within XCLK frequency. persistent logic indicate mismatch between actual expected XCLK frequency problem with analogue supplies (CAVS CAVD).
2.048 1.544 Reserved Reserv
Reserved 1.544
Table Clock Synthesis Mode
MODE[2:0] selects mode CSU. Table indicates required XCLK frequency, output frequencies each mode.
MODE[2:0]
CSU_LOCK
Type
Function<b
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