Bluetooth Baseband Controller PEDL7055LP-01 Issue Date: Aug.

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Bluetooth Baseband Controller PEDL7055LP-01 Issue Date: Aug.

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Semiconductor ML7055LP
Bluetooth Baseband Controller
PEDL7055LP-01
Issue Date: Aug. 2002
Preliminary
GENERAL DESCRIPTION
ML7055LP CMOS digital band Bluetoothsystems. This incorporates ARM7TDMI core, features highly expandable architecture, supports interfaces variety applications. Since ML7055LP Oki's Bluetooth protocol stack software installed, when used conjunction with Bluetooth transceiver data/voice communications possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
Designed based Bluetooth Specification (Ver. 1.1) Bluetooth Interfaces: OKI's RF-LSI interface (ML7050LA) CONEXANT's RF-LSI interface (CX72303) BROADCOM's RF-LSI interface (BCM2002X) ARM7TDMI installed 1-Ch, 16-bit auto-reload timer 1-Ch, 18-bit auto-reload timer Interrupt controller causes) Built-in kbyte programs Built-in kbyte Selectable master clock (12/13 MHz). PCM-CVSD transcoder installed. DETACH function provides control request change from STOP mode. Installed interfaces: UART interface 921.6 kbps) General-purpose interface (programmable interrupts) interface (PCM Linear/A-law/µ-law selected) JTAG interface Power supply voltage: 2.70 input-output 1.65 1.95 internal circuit Package: 84-pin (P-LFBGA84-0909-0.80) (Dimensions: pitch: 0.80
ARM7TDMI registered trademarks Ltd., Thumb trademark Ltd., BLUETOOTH trademark owned Bluetooth SIG, Inc. licensed Electric Industry. information contained herein change without notice owing product being under development.
PEDL7055LP-01
Semiconductor
ML7055LP
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol Tstg Conditions Rating -0.3 +4.5 (I/O) -0.3 +2.5 (Core) -0.3 +4.5 0.62 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter power supply voltage Core power supply voltage level input voltage level input voltage Operating temperature Symbol CoreVDD Conditions Min. 1.65 Typ. Max. 1.95 Unit
ELECTRICAL CHARACTERISTICS
Characteristics
(VDD +85°C) Parameter level output voltage level output voltage Input leakage current Output leakage current Power supply current (during operation) Power supply current (during stand-by) Symbol Iddo Idds Conditions During operation stopped Min. Typ. Max. Unit
PEDL7055LP-01
Semiconductor
ML7055LP
PLACEMENT
Core AVDD1 AGND1 AVDD0 AGND0 SCLKN RESET RFSEL0 RFSEL
XC32K AVDD1 AGND1 AGND0
XC32KN
RSSI
AVDD0
Core SCLKP DETACH RFSEL1 CLKOUT Core SYNC Core
SFRQ SCLK Core LOCK
PCMIN PCMCLK PLL_ LVDD Core TEST1
PLL_LE PLL_PS
PLL_
RSSI_ PLL_ PLL_ DATA
LPO_ SOUT
TEST0 TEST2
VIEW
PEDL7055LP-01
Semiconductor
ML7055LP
DESCRIPTIONS
Name Direction [*0] Internal Pull Up/Down Initial Value PLL_DATA PLL_CLK PLL_LE RSSI Pull down RSSI_CLK PLL_POW TX_POW RX_POW Placement Description ML7050 Transmit data output CX72303 Transmit data output BCM2002X Transmit data output ML7050 Receive data input CX72303 Receive data input BCM2002X Receive data input ML7050 Serial write data CX72303 Serial write data BCM2002X Transmit enable ML7050 Serial clock CX72303 Serial clock BCM2002X Serial clock ML7050 Serial road enable Negate, Assert CX72303 Serial enable Assert, Negate BCM2002X RF-LSI Synthesizer Negate, Assert ML7050 Receive field strength data input CX72303 Serial read data BCM2002X Serial read data ML7050 Receive field strength data clock CX72303 RF-LSI Receiving characteristic control BCM2002X system clock request ML7050 Local power control Assert, Negate CX72303 Power control Negate, Assert BCM2002X Select Serial Transmitmode ML7050 Transmit enable Assert, Negate CX72303 Transmit enable Negate, Assert BCM2002X Serial write data ML7050 Transmit enable Assert, Negate CX72303 Receive enable Negate, Assert BCM2002X Receive enable
[*0]
Input, Output, "I/O" Input/Output
PEDL7055LP-01
Semiconductor
ML7055LP
PLL_PS PLLLOCK Pull down LPO_CLK Pull down PLL_OFF ML7050 CX72303Power reset Assert (reset) Negate BCM2002XRF-LSI Receiving characteristic control ML7050 CX72303- BCM2002X1MHz clock ML7050 CX723033.2KHzclock BCM2002X3.2KHz clock (Pin shared with TCK) ML7050 loop comtrol 0:open loop 1closed loop CX72303Diversity Output BCM2002XPA Power control
Note: LPO_CLK used only when TEST_L0 state.
Name PCMOUT PCMIN PCMSYNC Direction Internal Pull Up/Down Pull Pull down Initial Value Placement Description data output data input sync signal kHz), Initial setting: input (can switched internal register) clock kHz/128 kHz) Initial setting: input (can switched internal register)
PCMCLK
Pull down
Note: sync signal kHz) must guaranteed accuracy PCMSYNC configured input. UART
Name SOUT Direction Internal Pull Up/Down Schmitt Initial Value Placement Description transmit serial data receive serial data transmit data ready (Pin shared with TRST) transmit ready (Pin shared with TDI)
Note: pins used only when TEST_L0 state.
PEDL7055LP-01
Semiconductor
ML7055LP
Configuration
Name SCLKP SCLKN XC32KP XC32KN SCLKSEL Direction Internal Pull Up/Down Pull down Initial Value Placement Description Master clock (12/13 MHz) pins (Power level: CMOS level) Subclock pins (for oscillator) System clock frequency select Master clock frequency select RF-LSI select pins 001: ML7050 (OKI) 010: CX72303 (Conexant) 101: BCM2002X (BROADCOM) Others: Unused Hardware reset (Reset Sleep (Sleep (Pin shared with TMS) serial clock serial data Master clock (12/13 MHz) output pins (Pin shared with TDO)
SFRQSEL
Pull down
RFSEL0-2
[*1]
RESET DETACH CLKOUT
Schmitt Schmitt
Note: DETACH CLKOUT pins used only when TEST_L0 state. [*1] RFSEL0: H10; RFSEL1: RFSEL2:
Internal Pull Up/Down Initial Value Placement
JTAG
Name TRST Direction Description Serial data input (Pin shared with CTS) Serial data output (Pin shared with CLKOUT) Reset (Pin shared with RTS) Mode setting (Pin shared with DETACH) Serial data clock (Pin shared with LPO_CLK)
Note: JTAG used only when TEST_L0 state.
PEDL7055LP-01
Semiconductor
ML7055LP
TEST
Name TEST_L0-2 Direction Internal Pull Up/Down Pull down Initial Value Placement [*2] [*3] Test pins Connection Description
[*2] [*3]
TEST_0: TEST_1: TEST_2:
Internal Pull Up/Down
Power,
Name CoreVDD LVDD AVDD0 AVDD1 AGND0 AGND1 Direction Initial Value Placement [*4] [*5] [*6] [*7] [*8] [*9] [*10] Description power supply 2.70 Power supply internal circuit 1.65 1.95 RF-I/O power suply (Same voltage RF-LSI) Digital block ground Analog block power supply 1.65 1.95 Analog block ground
[*4] [*5] [*6] [*7] [*8] [*9] [*10]
VDD: CoreVDD: J10, GND: A10, AVDD0: AVDD1: AGND0: E10, AGND1:
PEDL7055LP-01
Semiconductor
ML7055LP
REFERENCE VOLTAGE SUPPLY CIRCUIT
ML7055LP
AVDD0 0.1µF AGND0 AVDD1 0.1µF AGND1
CoreVDD
47µF
0.1µF
0.1µF
CoreVDD
47µF 0.1µF 0.1µF
Capacitors should locate close pins.
Feed lines should separated from pins.
Example ML7055LP voltage supply circuit
circuit subject change according specific board design. Please contact Electric Industry Co., Ltd. detailed information.
Semiconductor
BLOCK DIAGRAM
Default Slave AMBA AMBA PCM/ CVSD GPIO UART BT-BB Core DETACH ML7055LP Timer (1ch) Arbiter Default Slave Timer System Control IROMC IRAMC ARM7 TDMI
Clock AMBA Processor 176kB 24kB
RFLSI
CTL/
DETACH
GPIO
UART
PEDL7055LP-01
Codec
ML7055LP
PEDL7055LP-01
Semiconductor
ML7055LP
DESCRIPTION INTERNAL BLOCKS
CLKGEN Block Generates clock that supplied each block through SCLKP (12/13 MHz) STOP/HALT function CTL/WDT Block Control frequency division function internal main clock Control clock supplied each peripheral Control reset each peripheral STOP/HALT control Watchdog timer function (interrupt/reset)
Timer Block channel 18-bit timer counter Interrupt compare function shot, interval, free-run mode
Baseband Core Block
Audio Codec Buffer Buffer Packet Composer
Security Buffer Buffer
Timing
FHCNT
Packet Decomposer
Controller power supply control (PLL, Local frequency division ratio setting Receive clock regeneration function Synchronization detection (synchronizing within permissable error limit SyncWord) Receive clock re-timing function Controller hopping Sequence control Frequency hopping selection function computation's initial value selection function
10/10
PEDL7055LP-01
Semiconductor
ML7055LP
Timing Generator Bluetooth clock generation Operation interrupts depend mode (slot, scan, sniff, hold, park) Sync detection timing generation (sync window setting timing generation Transmit/Receive timing generation Multi-master timing management function Packet Composer Access code generation (SyncWord generation, appending PR*TRAILER) Packet header generation (HEC generation, scrambling, encoding) Payload generation (CRC generation, encryption, scrambling, encoding) Packet synthesis Packet Decomposer Packet decomposition (separating packet header payload) Packet header processing (FEC decoding, descrambling, error detection, header information separation) Payload processing (FEC decoding, descrambling, encryption decoding, judgement, payload separation) Security Various generation functions (initialization, link key, encryption key) Certification function Encryption function UART Block Full-duplex buffering method status reporting function Built-in 64-byte transmit/receive FIFO Modem control based Programmable serial interface 8-bit characters Generation verification parity, even parity, parity 1.5, stop bits Programmable Baud Rate Generator (1200 921.6 kbps) Error servicing parity, overrun, framing errors
PCM-CVSD Transcoder Block Application side I/O: Codec Application-side format: linear bits/sample, sampling frequency)/A-law/µ-law Bluetooth-side format: CVSD/A-law/µ-law combinations above conversions supported PCMSYNC/PCMCLK switched (initial setting: input) DETACH Interface Block Generation request change (from) stop mode detection rising (falling) edge DETACH signal Generation request change from stop mode detection signal level change
11/11
PEDL7055LP-01
Semiconductor
ML7055LP
APPLICATION NOTES
Clock Selection master clock frequency selected according external SFRQSEL. SFRQSEL SFRQSEL clock input external pins SCLKP. clock input external pins SCLKP.
clock supply source selected according external SCLKSEL. SCLKSEL SCLKSEL clock that divided down from internal output that generated from external pins SCLKP. (Dividing ratios selectable range 1/16. Initial value MHz).) external pins XC32KP.
Note: clock supply source CLKCNTL register CTL/WDT block once powered RESET signal input RESET pin. level pulse (more than 10usec width) must input after power supply stable. after oscillator generates stabilized master clock, enters internal reset condition 1.9msec (@SCLKP:13MHz) 2msec(@SCLKP:12MHz). Setting UART Baud Rate possible UART baud rate using Vendor Specific Commands. Available baud rate settings: (Initial value 115.2 kbps.) Setting PCM-CVSD Transcoder possible PCM-CVSD transcoders using Vendor Specific Commands. command details, contact Electric Industry Co., Ltd. possible following parameters using VCCTL command: PCMSYNC/PCMCLK mode (initial setting: input) Mute reception (initial setting: OFF) Mute transmission (initial setting: OFF) coding CVSD (initial setting)/µ-law/A-law Interface coding Linear (initial setting)/µ-law/A-law format (data width Linear sample) 8-bit (initial setting)/14-bit/16-bit Serial interface format Short frame (initial setting)/long frame Application interface mode Codec (initial setting)/APB
12/12
PEDL7055LP-01
Semiconductor
ML7055LP
Required processes when interface pins unused following tables show processes that should performed when interface pins used. pins that included following table should left open.
Name RSSI PLLLOCK LPO_CLK Process When Used Open Open Open This shared with TCK. Comments
UART
Name Process When Used This shared with TDI. Comments
Name PCMIN PCMSYNC PCMCLK Process When Used Open Open Open Comments
Processes Other Pins TEST etc.
Name TEST_L0-2 RESET DETACH Process When Used Pull Pull This shared with TMS. Comments
13/13
System Configuration Exam
ML7055LP
RFVDD RFVDD
ML7050LA VDD_D
L7055LP/M L7050LA
RESET LVDD
Power-on reset
Semiconductor
Hardware reset
Microphone PCMO PCMIN PCMSYNC PCMCLK MCLK
Voice input/ output peripherals
Speaker
PCMIN PCMO RSYNC XSYNC BCLK
PLL_LE PLL_DAT PLL_CLK PLL_O PLL_PO RX_PO X_POW
MSM7702-01
PLL_LE PLL_DAT PLL_CLK PLL_O PLL_PO RX_PO X_POW RSSI RSSI_CLK PLL_PS PLLLO _CLK(T CLKO UT(T SCLKN
20ppm
SCLKSEL SFRQ SCLKP
XC32KN
RFSEL-2 RFSEL-1 RFSEL-0 XC32KP ACH(TMS) AVDD0
32KHz 32.768KHz 250ppm
AVDD1
Separate, possible, wiring from board pins.
RTS(T RST) CTS(T
UART
R1IN R2IN MAX3245
DSUB9PIN
CoreVDD
CoreVDD
EST_L2 EST_L1 EST_L0
24C02
PEDL7055LP-01
ML7055LP
Separate, possible, wiring from board pins.
14/14
L7055LP/BCM 2002X
ML7055LP BCM2002X VDD_D RESET LVDD
Power-on reset
Semiconductor
Hardware reset
Microphone
PCMO PCMIN PCMSYNC PCMCLK PCMIN PCMO RSYNC XSYNC BCLK MSM7702-01
Voice input/ output peripherals
Speaker
PLL_LE PLL_DATA PLL_CLK PLL_OFF PLL_PO RX_POW TX_PO RSSI RSSI_CLK PLL_PS PLLLOCK _CLK(TCK) FSKD SYNTH_PU TX_PU SRI_CLK PA_RAMP SRI_E RX_PU SRI_DI SRI_DO XTAL_PU SL_CTRL TX_CLK _CLK XTAL_OUT
20ppm
JTAG CLKO UT(TDO) SCLKN SYS_CLK SCLKP XTAL_IN
(TCK) (TMS) (TRST) (TDO (TDI)
SCLKSEL SFRQSEL
AGND
RFSEL-2 RFSEL-1 RFSEL-0 XC32KN XC32KP DETACH(TMS) AVDD0
32KHz 32.768KHz 250ppm
UART
AVDD1
RTS(TRST) CTS(TDI)
Separate, possible, wiring from board pins.
T1IN T1OUT T2IN T2OUT T3IN R1IN R2IN MAX3245
DSUB9PIN
oreVD
CoreVDD
TEST_L2 TEST_L1 TEST_L0
AT24C02
PEDL7055LP-01
ML7055LP
capacitors shouded close pins possible.
15/15
ML7055LP/CX72303
RESET LVDD VDD_D VDD_IF RX_DATA SPI_EN_BAR SPI_DATA_IN SPI_CLK_IN TX_DATA RX_EN TX_EN SPI_DATA_OUT XTAL_B
13MHz 20ppm
L7055LP
RFVDD
RFVDD
CX72303
Power-on reset
Semiconductor
Hardware reset
Microphone
SYNC
Voice input/ output peripherals
Speaker
RSYNC XSYNC BCLK
7702-01 XTAL_A SYNC_DETECT
PLL_LE PLL_DATA PLL_CLK PLL_OFF PLL_POW RX_POW TX_POW RSSI RSSI_CLK PLL_PS PLLLOCK LPO_CLK(TCK) CLKOUT(TDO) SCLKN
SCLKSEL SFRQSEL SCLKP LPXO_OP LPXO_IN
SYS_CLK_OUT _CLK_OUT
XC32KN
RFSEL-2 RFSEL-1 RFSEL-0 XC32KP DETACH(S)
32KHz 32.768KHz 250ppm
AVDD0 AGND0 AVDD1 AGND1
UART
SOUT RTS(TRST) CTS(TDI)
T1OUT T2OUT
Separate, possible, wiring from board pins.
T1IN T2IN T3IN R1OUT R2OUT
R1IN R2IN AX3245
DSUB9PIN
CoreVDD
CoreVDD
TEST_L2 TEST_L1 TEST_L0
AT24C02
PEDL7055LP-01
capacitors shouded close pins possible.
ML7055LP
16/16
PEDL7055LP-01
Semiconductor
ML7055LP
PACKAGE DIMENSIONS
(Unit:
P-LFBGA84-0909-0.80
Package material Ball material Package weight Rev. No./Last Revised
Epoxy resin Sn/Pb 0.20 TYP. 1/May 2000
Caution regarding installation surface mounted type packages:
Surface mounted type packages very susceptible heat during reflow mounting package moisture content when storage. Therefore, please contact your Electric Industry Co., Ltd. sales representative when considering reflow experiments know product name, package name, count, package code, desired mounting conditions (reflow method, temperature, count), storage conditions, etc.
17/17
PEDL7055LP-01
Semiconductor
ML7055LP
REVISION HISTORY
Document
PEDL7055LP-01
Date
Aug. 2002
Page Previous Current Edition Edition
Description
Preliminary edition
18/18
PEDL7055LP-01
Semiconductor
ML7055LP
NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2002 Electric Industry Co., Ltd.
19/19

Bluetooth Baseband Controller PEDL7055LP-01 Issue Date: Aug.

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