Bluetooth Baseband Controller PEDL70512HB-01 Issue Date: Aug
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Semiconductor ML70512HB
Bluetooth Baseband Controller
PEDL70512HB-01
Issue Date: Aug. 2002
Preliminary
GENERAL DESCRIPTION
ML70512HB CMOS digital band Bluetoothsystems. This incorporates ARM7TDMI core, features highly expandable architecture, supports interfaces variety applications. Since ML70512HB Oki's Bluetooth protocol stack software installed, when used conjunction with Bluetooth transceiver data/voice communications possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
Designed based Bluetooth Specification (Ver. 1.1) Bluetooth Interfaces: OKI's RF-LSI interface (ML7050LA) CONEXANT's RF-LSI interface (CX72303) BROADCOM's RF-LSI interface (BCM2002X) ARM7TDMI installed 1-Ch, 16-bit auto-reload timer 3-Ch, 18-bit auto-reload timer Interrupt controller causes) Built-in kbyte programs Built-in kbyte Selectable master clock (12/13 MHz). PCM-CVSD transcoder installed. DETACH function provides control request change from STOP mode. Installed interfaces: UART interface 921.6 kbps) General-purpose interface (programmable interrupts) interface (PCM Linear/A-law/µ-law selected) JTAG interface Power supply voltage: 2.70 input-output 1.65 1.95 internal circuit Package: 83-pin WCSP (Dimensions: 6.22 6.22 0.52 pitch: 0.50
ARM7TDMI registered trademarks Ltd., Thumb trademark Ltd., BLUETOOTH trademark owned Bluetooth SIG, Inc. licensed Electric Industry. information contained herein change without notice owing product being under development.
PEDL70512HB-01
Semiconductor
ML70512HB
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage (I/O) Power supply voltage (Core) Input voltage Allowable power dissipation Storage temperature Symbol CoreVDD Tstg Conditions Rating -0.3 +4.5 -0.3 +2.5 -0.3 +4.5 0.62 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter power supply voltage Core power supply voltage level input voltage level input voltage Operating temperature Symbol CoreVDD Conditions Min. 1.65 Typ. Max. 1.95 Unit
ELECTRICAL CHARACTERISTICS
Characteristics
(VDD +85°C) Parameter level output voltage level output voltage Input leakage current Output leakage current Power supply current (during operation) Power supply current (during stand-by) Symbol Iddo Idds Conditions During operation stopped Min. Typ. Max. Unit
PEDL70512HB-01
Semiconductor
ML70512HB
PLACEMENT
SCLKO
Core
SYNC
Core CIO5
CIO0 (SCL)
Core CIO1 (SDA)
RFSEL2
TEST1 TEST2
CIO4 RFSEL0
Core
CIO3 TEST0 CIO6 SOUT PLL_ PLL_ Core LVDD RSSI _CLK
PCMIN
CIO2 RFSEL1 DETACH RESET SCLKN
LPO_
AGND0 SCLKP AVDD0 AGND0 Core
AVDD1 AGND1 AVDD0 Core RSSI Core
TRST
PLL_ DATA
SFRQ
AVDD1 AGND1 LOCK Core
PLL_
PLL_PS
PLL_
SCLK XC32KN XC32KP
VIEW
PEDL70512HB-01
Semiconductor
ML70512HB
DESCRIPTIONS
Name Direction [*0] Internal Pull Up/Down Initial Value PLL_DATA PLL_CLK PLL_LE RSSI Pull down RSSI_CLK PLL_POW TX_POW RX_POW Placement Description ML7050 Transmit data output CX72303 Transmit data output BCM2002X Transmit data output ML7050 Receive data input CX72303 Receive data input BCM2002X Receive data input ML7050 Serial write data CX72303 Serial write data BCM2002X Transmit enable ML7050 Serial clock CX72303 Serial clock BCM2002X Serial clock ML7050 Serial road enable Negate, Assert CX72303 Serial enable Assert, Negate BCM2002X RF-LSI Synthesizer Negate, Assert ML7050 Receive field strength data input CX72303 Serial read data BCM2002X Serial read data ML7050 Receive field strength data clock CX72303 RF-LSI Receiving characteristic control BCM2002X system clock request ML7050 Local power control Assert, Negate CX72303 Power control Negate, Assert BCM2002X Select Serial Transmitmode ML7050 Transmit enable Assert, Negate CX72303 Transmit enable Negate, Assert BCM2002X Serial write data ML7050 Transmit enable Assert, Negate CX72303 Receive enable Negate, Assert BCM2002X Receive enable
[*0]
Input, Output, "I/O" Input/Output
PEDL70512HB-01
Semiconductor
ML70512HB
PLL_PS PLLLOCK Pull down LPO_CLK Pull down PLL_OFF ML7050 :"L" CX72303 Power reset Assert (reset) Negate BCM2002X RF-LSI Receiving characteristic control ML7050 CX72303 BCM2002X 1MHz clock ML7050 CX72303 3.2KHzclock BCM2002X 3.2KHz clock ML7050 loop comtrol open loop CX72303 Diversity Output BCM2002X Power control closed loop
Name PCMOUT PCMIN PCMSYNC Direction Internal Pull Up/Down Pull Pull down Initial Value Placement Description data output data input sync signal kHz), Initial setting: input (can switched internal register) clock kHz/128 kHz) Initial setting: input (can switched internal register)
PCMCLK
Pull down
Note: sync signal kHz) must guaranteed accuracy PCMSYNC configured input. UART
Name SOUT Direction Internal Pull Up/Down Schmitt Initial Value Placement Description transmit serial data receive serial data transmit data ready transmit ready
PEDL70512HB-01
Semiconductor
ML70512HB
Port
Name CIO0 (SCL) CIO1 (SDA) CIO2 CIO3 CIO4 CIO5 CIO6 Direction Internal Pull Up/Down Initial Value Placement Description serial clock (output) serial data (input) reserved General port (initial state: output) General port (initial state: output) General port (initial state: input) General port (initial state: input)
Configuration
Name SCLKP SCLKN XC32KP XC32KN SCLKSEL Direction Internal Pull Up/Down Pull down Initial Value Placement Description Master clock (13/12 MHz) pins (Power level: CMOS level) Subclock pins (for oscillator) System clock frequency select Select divided internal Select subclock Master clock frequency select RF-LSI select pins 001: ML7050 (OKI) 010: CX72303 (Conexant) 101: BCM2002X (BROADCOM) Others: Unused Hardware reset (Reset Sleep (Sleep Master clock (13/12 MHz) output
SFRQSEL
Pull down
RFSEL0-2
[*1]
RESET DETACH SCLKO
Schmitt Schmitt
[*1]
RFSEL0: RFSEL1: RFSEL2:
Internal Pull Up/Down Pull Pull Pull down Initial Value Placement
JTAG
Name TRST Direction Description Serial data input Serial data output Reset Mode setting Serial data clock
PEDL70512HB-01
Semiconductor
ML70512HB
TEST
Name TEST_L0-2 Direction Internal Pull Up/Down Pull down Initial Value Placement [*2] Test pins Description
[*2]
TEST0: TEST1: TEST2:
Internal Pull Up/Down
Power,
Name CoreVDD LVDD AVDD0 AVDD1 AGND0 AGND1 Direction Initial Value Placement [*3] [*4] [*5] [*6] [*7] [*8] [*9] Description power supply 2.70 Power supply internal circuit 1.65 1.95 RF-I/O power suply (Same voltage RF-LSI) Digital block ground Analog block power supply 1.65 1.95 Analog block ground
[*3] [*4] [*5] [*6] [*7] [*8] [*9]
VDD: CoreVDD: C10, E10, G10, GND: A10, F10, H10, AVDD0: AVDD1: AGND0: AGND1:
PEDL70512HB-01
Semiconductor
ML70512HB
REFERENCE VOLTAGE SUPPLY CIRCUIT
ML70512HB
AVDD0 0.1µF AGND0 AVDD1 0.1µF AGND1
CoreVDD
47µF
0.1µF
0.1µF
CoreVDD
47µF 0.1µF 0.1µF
Capacitors should locate close pins.
Feed lines should separated from pins.
Example ML70512HB voltage supply circuit
circuit subject change according specific board design. Please contact Electric Industry Co., Ltd. detailed information.
Semiconductor
BLOCK DIAGRAM
Default Slave AMBA AMBA PCM/ CVSD GPIO UART BT-BB Core DETACH Arbiter Default Slave 72KB Timer System Control IROMC ARM7 TDMI IRAMC
Clock AMBA Processor 384KB
ML70512HB
RFLSI
CTL/
Timer2 (3ch)
DETACH
GPIO
UART
PEDL70512HB-01
Codec
ML70512HB
PEDL70512HB-01
Semiconductor
ML70512HB
DESCRIPTION INTERNAL BLOCKS
CLKGEN Block Generates clock that supplied each block through SCLKP (12/13 MHz) STOP/HALT function CTL/WDT Block Control frequency division function internal main clock Control clock supplied each peripheral Control reset each peripheral STOP/HALT control Watchdog timer function (interrupt/reset)
Timer Block channel 18-bit timer counter Interrupt compare function shot, interval, free-run mode
Baseband Core Block
Audio Codec Buffer Buffer Packet Composer
Security Buffer Buffer
Timing
FHCNT
Packet Decomposer
Controller power supply control (PLL, Local frequency division ratio setting Receive clock regeneration function Synchronization detection (synchronizing within permissable error limit SyncWord) Receive clock re-timing function Controller hopping Sequence control Frequency hopping selection function computation's initial value selection function
10/10
PEDL70512HB-01
Semiconductor
ML70512HB
Timing Generator Bluetooth clock generation Operation interrupts depend mode (slot, scan, sniff, hold, park) Sync detection timing generation (sync window setting timing generation Transmit/Receive timing generation Multi-master timing management function Packet Composer Access code generation (SyncWord generation, appending PR*TRAILER) Packet header generation (HEC generation, scrambling, encoding) Payload generation (CRC generation, encryption, scrambling, encoding) Packet synthesis Packet Decomposer Packet decomposition (separating packet header payload) Packet header processing (FEC decoding, descrambling, error detection, header information separation) Payload processing (FEC decoding, descrambling, encryption decoding, judgement, payload separation) Security Various generation functions (initialization, link key, encryption key) Certification function Encryption function UART Block Full-duplex buffering method status reporting function Built-in 64-byte transmit/receive FIFO Modem control based Programmable serial interface 8-bit characters Generation verification parity, even parity, parity 1.5, stop bits Programmable Baud Rate Generator (1200 921.6 kbps) Error servicing parity, overrun, framing errors
PCM-CVSD Transcoder Block Application side I/O: Codec Application-side format: linear bits/sample, sampling frequency)/A-law/µ-law Bluetooth-side format: CVSD/A-law/µ-law combinations above conversions supported PCMSYNC/PCMCLK switched (initial setting: input) DETACH Interface Block Generation request change (from) stop mode detection rising (falling) edge DETACH signal Generation request change from stop mode detection signal level change
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PEDL70512HB-01
Semiconductor
ML70512HB
APPLICATION NOTES
Clock Selection master clock frequency selected according external SFRQSEL. SFRQSEL SFRQSEL clock input external pins SCLKP. clock input external pins SCLKP.
clock supply source selected according external SCLKSEL. SCLKSEL SCLKSEL clock that divided down from internal output that generated from external pins SCLKP. (Dividing ratios selectable range 1/16. Initial value MHz).) external pins XC32KP.
Note: clock supply source CLKCNTL register CTL/WDT block once powered RESET signal input RESET pin. level pulse (more than 10usec width) must input after power supply stable. after oscillator generates stabilized master clock, enters internal reset condition 1.9msec (@SCLKP:13MHz) 2msec(@SCLKP:12MHz). Setting UART Baud Rate possible UART baud rate using Vendor Specific Commands. Available baud rate settings: (Initial value 115.2 kbps.) Setting PCM-CVSD Transcoder possible PCM-CVSD transcoders using Vendor Specific Commands. command details, contact Electric Industry Co., Ltd. possible following parameters using VCCTL command: PCMSYNC/PCMCLK mode (initial setting: input) Mute reception (initial setting: OFF) Mute transmission (initial setting: OFF) coding CVSD (initial setting)/µ-law/A-law Interface coding Linear (initial setting)/µ-law/A-law format (data width Linear sample) 8-bit (initial setting)/14-bit/16-bit Serial interface format Short frame (initial setting)/long frame Application interface mode Codec (initial setting)/APB
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PEDL70512HB-01
Semiconductor
ML70512HB
Required processes when interface pins unused following tables show processes that should performed when interface pins used.
Name PLL_DATA PLL_CLK PLL_LE RSSI RSSI_CLK PLL_POW TX_POW RX_POW PLL_PS PLLLOCK LPO_CLK PLL_OFF Process When Used Open Open Open Open Open Open Open Open Open Open Open Open Open Comments
Name PCMOUT PCMIN PCMSYNC PCMCLK Process When Used Open Open Open Open Comments
UART
Name SOUT Process When Used Open Open Comments
JTAG
Name TRST Process When Used Open Open Open Open Open Comments
13/13
PEDL70512HB-01
Semiconductor
ML70512HB
Port
Name CIO0 (SCL) CIO1 (SDA) CIO2 CIO3 CIO4 CIO5 CIO6 Process When Used Open Open Open Open Open Open Open Comments
Processes Other Pins TEST etc.
Name TEST_L0-2 RESET DETACH SCLKO Process When Used Pull Pull Open Comments
14/14
System Configuration Exam
ML70512HB ML7050LA VDD_D RESET LVDD
RFVDD RFVDD
ML70512HB/ML7050LA
Power-on reset
Semiconductor
Hardware reset
Microphone PCMOUT PCMIN PCMSYNC PCMCLK MCLK PCMIN PCMOUT RSYNC XSYNC BCLK MSM7702-01
Voice input/ output peripherals
PLL_LE PLL_DAT PLL_CLK PLL_O PLL_PO RX_POW X_PO
Speaker
PLL_LE PLL_DAT PLL_CLK PLL_O PLL_PO RX_POW X_PO RSSI RSSI_CLK PLL_PS PLLLO _CLK SCLKO SCLKN
Hz±20ppm
SCLKP XC32KN
SCLKSEL SFRQSEL RFSEL-2 RFSEL-1 RFSEL-0 XC32KP
32KHz 32.768KHz 250ppm
AVDD0
UART
1OUT 2OUT R1IN R2IN
AGND0
SOUT
Separate, possible, wiring from board pins. AVDD1
CIO6 CIO5
DSUB9PIN MAX3245
AGND1 CIO4(LED1) CoreVDD
CoreVDD
CIO3(LED0) CIO2 SDA(CIO1) SCL(CIO0)
24C02
capacitors shouded close pins possible.
PEDL70512HB-01
ML70512HB
15/15
ML70512HB BCM2002X
ML70512HB BCM2002X VDD_D
RFVDD RFVDD
RESET
LVDD
Power-on reset
Semiconductor
Hardware reset
Microphone
Voice input/ output peripherals PCMCLK
Speaker MSM7702-01
PCMIN PCMOUT RSYNC XSYNC BCLK PCMOUT PCMIN PCMSYNC
PLL_LE PLL_DATA PLL_CLK PLL_OFF PLL_POW RX_POW TX_POW RSSI RSSI_CLK PLL_PS PLLLOCK LPO_CLK FSKD SYNTH_PU TX_PU SRI_CLK PA_RAMP SRI_E RX_PU SRI_DI SRI_DO XTAL_PU SL_CTRL TX_CLK LPO_CLK XTAL_OUT
13MHz± 20ppm
JTAG SCLKO SCLKN XTAL_IN SCLKP SYS_CLK XC32KN
TRST
SCLKSEL SFRQSEL
AGND
RFSEL-2 RFSEL-1 RFSEL-0 XC32KP
32KHz 32.768KHz±250ppm
DETACH AVDD0
UART
AGND0
SOUT
T1OUT T2OUT R1IN R2IN
T1IN T2IN T3IN R1OUT R2OUT
Separate, possible, wiring from board pins. AVDD1
CIO6 CIO5
DSUB9PIN MAX3245
CoreVDD
AGND1 CIO4(LED1) CoreVDD
CIO3(LED0) CIO2 SDA(CIO1) SCL(CIO0)
TEST_L2 TEST_L1 TEST_L0
AT24C02
capacitors shouded close pins possible.
PEDL70512HB-01
ML70512HB
16/16
ML70512HB CX72303
RESET LVDD
ML70512HB CX72303
Power-on reset
Semiconductor
Hardware reset
X_DAT RX_EN X_EN SPI_DAT AL_B
13MHz 20ppm
VDD_D VDD_IF RX_DAT SPI_EN_BAR SPI_DAT A_IN SPI_CLK_IN
Microphone
PCMO PCMIN PCMSYNC PCMCLK
Speaker
Voice input/ output peripheral
PCMIN PCMO RSYNC XSYN BCLK
MSM7702-01 AL_A SYNC_DET SYS_CLK_O _CLK_O
PLL_LE PLL_DAT PLL_CLK PLL_O PLL_PO RX_PO X_PO RSSI RSSI_C PLL_PS PLLLO _CLK
SCLKO SCLKN SCLKP
AGND
XC32KN
LPXO LPXO
SCLKSEL SFRQ RFSEL-2 RFSEL-1 RFSEL-0 XC32KP
32KHz 32.768KHz 250ppm AGND
UART
AVDD0
R1IN R2IN
Separate, possible, wiring from board pins.
AVDD1
DSUB9PIN
CoreVDD
4(LED1) CoreVDD
MAX3245
3(LED0) SDA(C SCL(CIO
EST_L2 EST_L1 EST_L0
capacitors shouded close pins possible.
PEDL70512HB-01
ML70512HB
17/17
PEDL70512HB-01
Semiconductor
ML70512HB
PACKAGE DIMENSIONS
(Unit:
Package material Lead frame material treatment Package weight Rev. No./Last Revised
Epoxy resin Sn/Pb Solder plating (5µm) 0.04 TYP. 1/July 2002
Caution regarding installation surface mounted type packages:
Surface mounted type packages very susceptible heat during reflow mounting package moisture content when storage. Therefore, please contact your Electric Industry Co., Ltd. sales representative when considering reflow experiments know product name, package name, count, package code, desired mounting conditions (reflow method, temperature, count), storage conditions, etc.
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PEDL70512HB-01
Semiconductor
ML70512HB
REVISION HISTORY
Document
PEDL70512HB-01
Date
Aug. 2002
Page Previous Current Edition Edition
Description
Preliminary edition
19/19
PEDL70512HB-01
Semiconductor
ML70512HB
NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2002 Electric Industry Co., Ltd.
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