MG73N/74N/75N 0.22µm Customer Structure Array Semiconductor
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MG73N/74N/75N 0.22µm Customer Structure Array
MG73N/74N/75N
0.22µm Customer Structure Array
Semiconductor
CONTENTS
DESCRIPTION.5 FEATURES MG73N/74N/75N FAMILY LISTING.6 ARRAY ARCHITECTURE MG73N/74N/75N LAYOUT METHODOLOGY.8 ELECTRICAL CHARACTERISTICS MACRO LIBRARY.12 ADVANCED DESIGN CENTER TOOLS DESIGN PROCESS.15 AUTOMATIC TEST PATTERN GENERATION FLOORPLANNING DESIGN FLOW.16 IEEE JTAG BOUNDARY SCAN SUPPORT.18 PACKAGE OPTIONS.19 TQFP, LQFP Package Menu.19
Semiconductor
MG73N/74N/75N
0.22 Customer Structure Array
DESCRIPTION
Oki's 0.22µm Application-Specific Integrated Circuit (ASIC) products available Customer Structured Array (CSA) architectures. CSA-based MG75N series five-layer metal process 0.22µm drawn CMOS technology. MG73N/74N series uses three four metal layers, respectively. 0.22µm families provide significant performance, density, power improvement over previous 0.25µm technologies. innovative 4-transistor cell structure provides less power more usable gates than traditional cell designs. 0.22µm family operates using 2.5-V core with optimized buffers. 5-layer metal MG73N/74N/75N series contains array bases, offering pads over 9.3M gates. These array sizes designed most popular quad flat pack (QFP), profile QFPs (LQFPs), thin QFPs (TQFPs), plastic ball grid array (PBGA). 3-layer-metal MG73N, 4-layer-metal MG74N 5-layer-metal MG75N series contains array bases, offering wider span gate counts. uses Virage Components memory compiler which provides high performance, embedded synchronous single- dual-port macrocells designs. such, MG73N/74N/75N series suited memory-intensive ASICs high-volume designs where fine-tuning package size produces significant cost real estate savings.
FEATURES
0.22µm drawn 5-layer metal CMOS Optimized 2.5-V core Optimized Optimized Tolerant architecture availability 50-ps typical gate propagation delay (for drive inverter gate with fanout wire, operating Over 9.3M gates pads using staggered User-configurable with VSS, VDD, TTL, 3state, 24-mA options Slew-rate-controlled outputs low-radiated noise Clock tree cells which reduces maximum skew clock signals Gated clock 0.2µW/MHz/gate power dissipation User-configurable single- dual-port memories Specialized cores macrocells including 32-bit ARM7TDMI CPU, phaselocked loop (PLL), peripheral component interconnect (PCI) cells Floorplanning front-end simulation, backend layout controls, link synthesis Joint Test Action Group (JTAG) boundary scan scan path Automatic Test Pattern Generation (ATPG) Built-In Self Test (BIST) memory testing Support popular systems including Cadence, Model Technology, Inc. (MTI), Synopsys
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
MG73N/74N/75N FAMILY LISTING
Base Array MG7XNB02 MG7XNB04 MG7XNB06 MG7XNB08 MG7XNB10 MG7XNB12 MG7XNB14 MG7XNB16 MG7XNB18 MG7XNB20 MG7XNB22 MG7XNB24 MG7XNB26 MG7XNB28 MG7XNB30 MG7XNB32 MG7XNB34 MG7XNB36 MG7XNB38 MG7XNB40 MG7XNB42
Pads
Rows 1,040 1,124 1,206 1,290 1,374 1,456 1,540 1,624 1,706 1,790
Column 1,088 1,336 1,576 1,824 2,064 2,312 2,552 2,800 3,040 3,288 3,528 3,776 4,016 4,264 4,504 4,752 4,992 5,240
Gates 44,640 123,600 245,920 406,912 609,216 851,040 1,138,176 1,457,184 1,826,480 2,230,448 2,676,800 3,161,600 3,695,712 4,254,768 4,871,040 5,517,984 6,208,384 6,936,160 7,717,248 8,516,352 9,379,600
MG73N Family Usable Gates 36,158 86,520 157,389 236,009 322,884 425,520 534,943 655,733 785,386 914,484 1,070,720 1,201,408 1,330,456 1,489,169 1,656,154 1,820,935 1,986,683 2,150,210 2,315,174 2,469,742 2,626,288
MG74N Family Usable Gates 42,408 117,420 223,787 329,599 444,728 561,686 694,287 830,595 986,299 1,137,528 1,311,632 1,485,952 1,663,070 1,829,550 1,997,126 2,207,194 2,421,270 2,635,741 2,855,382 3,065,887 3,282,860
MG75N Family Usable Gates 42,408 117,420 233,624 382,497 523,926 663,811 830,868 990,885 1,168,947 1,360,573 1,552,544 1,770,496 1,958,727 2,169,932 2,435,520 2,648,632 2,855,857 3,121,272 3,395,589 3,662,031 3,939,432
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
ARRAY ARCHITECTURE
primary components 0.22µm MG73N/74N/75N circuit include: base cells 60µm pitch Configurable pads VDD, VSS, (optimized I/O) pads dedicated wafer probing Separate power output buffers Separate power internal core logic input buffers Core base cells containing N-channel P-channel pairs, arranged column gates Isolated gate structure reduced input capacitance increased routing flexibility Each array dedicated corner pads power ground during wafer probing, with four pads corner. arrays also have separate power rings internal core functions (VDDCORE VSS) output drive transistors (VDDO VSSO).
base cells
Separate power (VDDC, VSSC) Internal core logic (2nd metal metal)
Configurable pads VDD,
layer metal interconnection core area
Core library cell
VDD, pads each Corner wafer probing only
Separate power (VDDO, VSSO) over cell output buffers (2nd metal metal)
Figure MG75N Array Architecture
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
MG73N/74N/75N LAYOUT METHODOLOGY
procedure design, place, route follows. Select suitable base array frame from available predefined sizes. select array size: Identify macrocell functions required minimum array size hold macrocell functions. together area occupied required random logic macrocells select optimum array. Make floor plan design's megacells. Design Center engineers verify master slice review simulation. Design Center customer engineers floorplan array using Oki's supported floorplanner customer performance specifications. Using software, Design Center engineers remove transistors replace them with diffused memory macrocells customer's specifications Figure shows array base after placement optimized memory macrocells.
Mega Macro cells
High-density RAMs
Figure Optimized Memory Macrocell Floor Plan
Place route logic into array transistors. Design Center engineers layout software customer performance specifications connect random logic optimized memory macrocells Figure marks area which placement routing performed with cross hatching.
Figure Random Logic Place Route
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Vss 25°C)
Parameter Supply Voltage Input Voltage Core Normal buffer Tolerant Buffer Symbol VDDCORE VDDIO Condition VDDIO VDDIO Output Voltage Normal buffer Tolerant Buffer VDDIO VDDIO Input Current
Rated Value +3.6 +4.6 VDDIO +0.3 +6.0 DDIO +0.3 DDIO +0.3 +6.0 DDIO +0.3
Unit
buffer buffer buffer buffer buffer buffer buffer
Output Current
Storage Temperature
TSTG
+150
Notes: Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted conditions other specifications this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability. drive inputs while Driving with positive signal while would result current through protection diode cause device failure.
Recommended Operating Conditions (Vss
Paramater Supply Voltage Junction Temperture Input rise time/ fall time Symbol VDDcore VDDIO 2.25 2.75 Unit
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
Characteristics (VDDCORE 2.5V 0.25 VDDIO 3.3V +85°C)
Parameter Normal buffer Tolerant Low-level Input Voltage Normal buffer Tolerant TTL-level Schmitt Trigger Input buffer Threshold Voltage (Normal buffer) TTL-level Schmitt Trigger Input buffer Threshold Voltage Tolerant buffer) High-level Output Voltage (Normal buffer) High-level Input Voltage Symbol Condition level Input level Input -100 VDDio pull down) High-level Input current Tolerant) k/50 pull pull down) Low-level Input current (Normal buffer) Low-level Input current Tolerant) pull pull pull pull VDDCORE VDDIO 25°C typical process. VDDio pull down) Rated Value Unit Typ[1] VDD+0.3 VDDIO VDDIO -0.3 -0.3
High-level Output Voltage Tolerant buffer)
Low-level Output Voltage (Normal buffer) Low-level Output Voltage Tolerant buffer)
High-level Input current (Normal buffer)
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
Characteristics (VDDcore
Paramater Internal gate propagation delay Inverter Driving Type 2-input NAND Inverter 2-input NAND Toggle Frequency
Input transition time 0.15 (Internal gate) Typical condition DDCORE DDIO typical process. Rated value calculated average delay times each macro type typical process.
Condition[1][2]
Rated Value[3] Unit 0.073 0.062 0.05 0.094 0.077
0.067 0.317 0.224 0.133 0.376 0.218
Standard wire length
0.139 1830
Characteristics (I/O
Paramater Input buffer propagation delay Output buffer propagation delay Driving Type Condition[1][2] Standard wire length Rated Value[3] Unit 0.391 0.708 1.88 2.072 2.597 2.193 2.689 2.82 3.524 3.526 3.571 3.466 TTL-level normal buffer TTL-level Tolerant buffer push-pull Normal output buffer Tri-state tolerant output buffer Output buffer traisition time
push-pull Normal output buffer Tri-state tolerant output buffer
Input transition time 0.2ns 3.3V(Input buffer) Rated value calculated average delay times each macro type typical process. Output rising falling times both specified over range.
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
MACRO LIBRARY
Semiconductor supports wide range macrocells macrofunctions, ranging from simple hard macrocells basic Boolean operations large, user-parameterizable macrofunctions. following figure illustrates main classes macrocells macrofunctions available.
Examples
Basic Macrocells
NANDs NORs
EXORs Latches
Flip-Flops Combination Logic
Basic Macrocells with Scan test
Flip-Flops
Clock Tree Driver Macrocells Macrocells Output Macro cells 3-State Outputs Push-Pull Outputs Open Drain Outputs Slew rate control Outputs Outputs
Macrocells
Counters Shift Registers
Macro Library
Mega/Special Macro cells
ARM7TDMI
Input Macrocells
Inputs Inputs with Pull-Downs Inputs with Pull-Up
Bi-Directional macrocells
with Pull-Downs with Pull-Up
Oscillator Macrocells
Gated Oscillator
Memory Macrocells
Optimized Diffusion RAMs Single port RAMs Dual port RAMs
Macrofunctions
Macrofunctions
4-Bit Registers/Latches
Figure Macrocell Macrofunction Library
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
Macrocells Driving Clock Trees
offers Envisiaclock-tree clock tree generator (CT-Gen). CT-Gen generates post placement buffered clock trees that help minimize problems associated with clock skew. CT-Gen optimizes following when generates clock trees: Maximum load, maximum transition, wire self-heat, electron constraints Maximum insertion delay Maximum skew Clock tree size above constraints met) Minimum insertion delay (satisfied padding root)
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
ADVANCED DESIGN CENTER TOOLS
Oki's advanced design center tools include support following: Floorplanning front-end simulation back-end layout control Clock tree structures improve first-time silicon success eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions accurately model package requirements
Design Availability
Vender Platform Operating System[1] Solaris Solaris Vender Software Ambit Buildgates Cadence Syntest Sun® Sun® NC_Verilog Verilog_XL Turbo Fault Design Compiler Ultra Tetramax/ATPG Synopsys Sun® Solaris Primetime Compiler/Test Compiler Analyzer Model Technology Inc. (MTI) Verplex Sun®
Description Design Synthesis Design Simulation Design Simulation Fault Simulation Design Synthesis Test Synthesis Static Timing Analysis Test Synthesis Check Design Simulation Design Simulation Design Simulation Floor Planning Formal Verification
Solaris WinNT4.0 Solaris Solaris
MTI-VHDL MTI-Verilog Floorplanner Conformal
Sun®
Contact Application Engineering current software versions Sun-compatible
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
DESIGN PROCESS
following figure illustrates overall design process, also indicating three main interface points between external design houses ASIC Application Engineering.
Synopsys Timing script (Optional)
VHDL/Verilog Description
Functional Test Vectors
Level
Synthesis Power Synthesis (Optional) Floorplanning
Front-End
Gate-Level Simulation
Level
Netlist Conversion (EDIF 200) Test Vector Conversion (Oki
Scan Insertion (Optional)
Formal Verification
Floorplanning
Pre-Layout Simulation
Level Fault Simulation
Layout Timing Driven Layout (optional
Automatic Test Pattern Generation
Interface
Static Timing Analysis
Verification (Design rule Check /Formal verification)
Post-Layout Simulation
Level
Manufacturing Prototype Test program Conversion
Circuit Data Check program (CDC) verifies logic design rules Test Data Check program (TDC) verifies test vector rules Test Pattern Language (TPL) Ultimate Customer-OKI design Interface available addition standard level Standard design process Includes fault simulation Requires Synopsys timing script Timing driven layout
Figure Design Process
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
AUTOMATIC TEST PATTERN GENERATION
Oki's 0.22µm ASIC technologies support ATPG using full scan-path design techniques, including following: Increases fault coverage Uses Synopsys Test Compiler Tetramax Automatically inserts scan structures Connects scan chains Traces reports scan chains Checks rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction ATPG methodology described detail Oki's Scan Path Application Note.
Combination Logic FD1AS FD1AS Scan Data
Scan Data
Scan Select
Figure Full Scan Path Configuration
FLOORPLANNING DESIGN FLOW
offers floorplanning tool (OKI high-density ASIC design. three main purposes Oki's floorplanning tool Ensure conformance critical circuit performance specifications Shorten overall design Hierarchical Layout traditional design approach with synthesis tools, timing violations after layout simulation fixed manual editing list. This process difficult time consuming. Also, there physical cluster information provided synthesis tool, difficult synthesize logic using predicted interconnection delay wire length. Synthesis tools therefore create over-optimized result Floorplanning allows designers control parasitic capacitance circuit participating physical design process. Designers partition their ASIC circuit most efficient hierarchical manner, and/or specify exact placement critical timing paths guarantee high-speed performance. Floorplanning also allows reduction layout iterations, minimizing designs overall TAT. parasitic capacitance dominates circuit's timing sub-micron technologies, accurate capacitance estimation crucial accurate pre-layout timing simulation. Quite often, designers have iterate circuit layout because unexpected post-layout capacitance causes unacceptable circuit performance. More information Oki's floorplanning capabilities available Oki's Application Note, Using Oki's Floorplanner: Standalone Operation Links Synopsys.
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
Entry
Constrains
Synthesis (Initial)
Chip Level Netlist
Floor Plan
Synthesis (Detail) Chip Level Netlist
Floor Plan Delay Calculation Block Level Netlist Spec? Block-level Layout Chip-level Layout DSPF Delay Calculation Block Level Optimization (Option) Spec? Block-level Delay Calculation DSPF
Supports SPEF DSPF
Sign
Figure Design Flow
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
IEEE JTAG BOUNDARY SCAN SUPPORT
Boundary scan offers efficient board-level chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into design include: Improved chip-level board-level testing failure diagnostic capabilities Support testing components with limited probe access Easy-to-maintain testability system self-test capability with on-board software Capability fully isolate test components scan path Built-in test logic that activated monitored optional Boundary Scan Identification (ID) Register Oki's boundary scan methodology meets JTAG Boundary Scan standard, IEEE 1149.1-1990. supports boundary scan both Gates (SOG) Customer Structured Array (CSA) ASIC technologies. Either customer perform boundary-scan insertion. More information available Oki's JTAG Boundary Scan Application Note. (Contact Application Engineering Department interface options.)
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
PACKAGE OPTIONS
TQFP, LQFP Package Menu
Product Name MG7xNB02 MG7xNB04 MG7xNB06 MG7xNB08 MG7xNB10 MG7xNB12 MG7xNB14 MG7xNB16 MG7xNB18 MG7xNB20 MG7xNB22 MG7xNB24 MG7xNB26 MG7xNB28 MG7xNB30 MG7xNB32 MG7xNB34 MG7xNB36 MG7xNB38 MG7xNB40 MG7xNB42
Body size (mm) Lead Pitch (mm)
Pads
TQFP
LQFP
Pads used input, output, bi-directional, power, ground
Available now.
Semiconductor
MG73N/74N/75N
0.22µm Customer Structure Array
PBGA MBGA Package Menu
Product Name MG7xNB02 MG7xNB04 MG7xNB06 MG7xNB08 MG7xNB10 MG7xNB12 MG7xNB14 MG7xNB16 MG7xNB18 MG7xNB20 MG7xNB22 MG7xNB24 MG7xNB26 MG7xNB28 MG7xNB30 MG7xNB32 MG7xNB34 MG7xNB36 MG7xNB38 MG7xNB40 MG7xNB42
Body size (mm) Ball pitch (mm) Ball count Signal Power Ball Ball
Pads
1.27
PBGA
1.27
1.27
Pads used input, output, bi-directional, power, ground
Available now.
Semiconductor
information contained herein change without notice owing product and/or technical improvements. Please make sure before using product that information referring up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When actually plan product, please ensure that outside conditions reflected actual circuit assembly designs. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters outside specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right,etc.is granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. When designing your product, please product below specified maximum ratings within specified operating ranges, including limited operating voltage, power dissipation, operating temperature. products listed this document intended general electronics equipment commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property death injury humans. Such applications include, limited traffic control, automotive, safety, aerospace, nuclear power control, medical, including life support maintenance. Certain parts this document need governmental approval before they exported certain countries. purchaser assumes responsibility determining legality export these parts will take appropriate necessary steps, their expense, export another country. Copyright 2002 Semiconductor Semiconductor reserves right make changes specifications anytime without notice. This information furnished Semiconductor this publication believed accurate reliable. However, responsibility assumed Semiconductor use; infringements patents other rights third parties resulting from use. license granted under patents patent rights Oki.
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