Tuned Receiver Data Transfer Applications (U.S.) (Europe) Applica

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Tuned Receiver Data Transfer Applications
(U.S.) (Europe) Applications External Components, Adjustment Operation -102 Sensitivity (90% Recovered Data) High Image Cancelling Mixer Typical Rejection) Integrated Bandpass Filter: Center Frequency, Bandwidth Integrated Selectable Pass Data Filter Internal Strobe Oscillator (Duty Cycle Power Saving) Fast Wake-Up European Compliance Digital Block Features: Manchester Coding Activated Wake-Up Message Four Selectable Data Rates 9.6/4.8/2.4/1.2 kbits/s Rate Selectable Internal Digital Filter Data Clock Generation Four Data Rates Clock Output
MC33590
TUNED RECEIVER DATA TRANSFER APPLICATIONS
SEMICONDUCTOR TECHNICAL DATA
SUFFIX PLASTIC PACKAGE CASE 873A (TQFP-32)
SIMPLIFIED BLOCK DIAGRAM
REXT CEXT Strobe DATA1 Wake-Up DATACLK DATA2
CONNECTIONS
DATACLK Wake-Up CLKGND µPCLK FRQPIN DGND2 OSC2 OSC1 DGND1 C2AGC NPCAP FCAP1 AFCCAP FCAP2 DMDAT XTAL1 XTALSYS DATA2 DATA1 Strobe CEXT VCCR RFBIASDC RFIN RFDEC MIXAGC MIXOUT RGND C1AGC FRQPIN µPCLK OSC1 OSC2 REXT
MIXAGC RFBIAS MIXOUT AFCCAP
Bandgap
Strobe Oscillator Timer
Digital Filter
Wake-Up Header Detection Clocks Generation
Data Clock Regeneration
Image Cancelling Mixer
Divider
Ampl. Bandpass Filter Envelope Detector
Data Slicer
Divider
C1AGC
Peak Detect.
C2AGC NPCAP DMDAT
Analog Low-Pass Filter
FCAP1 FCAP2
Reference Crystal Oscillator
ORDERING INFORMATION
XTAL1 XTALSYS
Device MC33590FTB
Operating Temperature Range -40° 85°C
Package TQFP-32
Motorola, Inc. 2000
MOTOROLA
MC33590
FUNCTION DESCRIPTIONS
Function VCCR RFBIASDC RFIN RFDEC MIXAGC MIXOUT RGND C1AGC C2AGC NPCAP AFCCAP DMDAT FCAP1 FCAP2 XTAL1 XTALSYS VCCD DGND1 OSC1 OSC2 DGND2 FRQPIN µPCLK CLKGND DATA1 DATACLK Wake-Up DATA2 Strobe REXT CEXT Description Radio section supply voltage bias decoupling capacitor Input decoupling Mixer capacitor Mixer output Ground (radio section) Positive peak filter capacitor time constant control Negative peak filter capacitor filter capacitor Demodulated data output Analog pass filter capacitor Analog pass filter capacitor Reference oscillator input Reference oscillator input/system select Digital section supply voltage loop filter Ground (digital section) tank tank Ground (digital section) Data rate selection Microprocessor clock drive output Ground (microprocessor clock) Non-processed data output Selected clock output Wake-up pulse output Filtered data output State machine control input bias setting resistor Strobe oscillator capacitor
MAXIMUM RATINGS
Parameter Supply Voltage Maximum Voltage Allowed Each (Unless Otherwise Specified) Voltage Capability (Note Solder Heat Resistance Test Operating Temperature Range Storage Temperature Junction Temperature Tstg Symbol VCCR, VCCD Value -0.5 ±2000 260°C/10 Unit
NOTE: Human Body Model, MIL-STD 883C, Method 3015.7.
MOTOROLA
MC33590
ELECTRICAL CHARACTERISTICS (Operating Temperature Range -40° 85°C, Operating Frequency
433.92 MHz, Unless Otherwise Specified) (See Note Spec. Mean Supply Current Supply Current: Awake Supply Current: Asleep Supply Current: Awake Strobe Oscillator Period (STper) Sleep/Wake Period (SWper) Awake Start Correct Operation Delay Strobe High Correct Operation Delay Reference Voltage External Current Reference Resistance Strobe Oscillator Charge Current (for CEXT) Strobe Oscillator Discharge Resistance Strobe Oscillator Upper Threshold Strobe Oscillator Lower Threshold Difference Between Thresholds Strobe Oscillator Period Wake-up detected, µPCLK current included Defined external capacitor Mask programmable: Correct decode wake-up; preamble crystal intrinsic resistance: Starts after this delay crystal intrinsic resistance: REXT REXT Measured Rdis Vhigh Vlow Vamp T=REXT CEXT Vamp/Vbg 35/40 Rdis CEXT (Vhigh/Vlow); Measured with REXT CEXT Target Limits Parameter Test Conditions, Comments High Unit
Type
General Parameters wake-up detected: determined sleep:wake ratio. wake-up detected 0.82 1.05 STper 1,17 1,17 1,17 1,17
1.91 1.10 1.101 1.11 1.12 1.13 1.131
1.16 1.20 0.41 0.77 4.15
1.20 4.15 1.25 0.44 0.81 4.55
1.24 1.30 0.47 0.85 4.95
1.14 1.15 2.01
Strobe Sleep Mode Delay Time After Valid Wake-Up From normal awake time
STper SWper
Parameters: General Front (see Note Sensitivity global (cyclic,1 byte) 9600 bits/s, Mod. depth 100%, rise time Spec. 2.01; modulation depth Spec. 2.01; modulation depth Spec. 2.01 Measured with input matching network Measured MIXOUT
2.02 2.03 2.04 2.40
Sensitivity Sensitivity Sensitivity with Input Matching Network Noise Figure
-102
Input Impedance: Resistance
MOTOROLA
MC33590
ELECTRICAL CHARACTERISTICS (Operating Temperature Range -40° 85°C, Operating Frequency
433.92 MHz, Unless Otherwise Specified) (See Note (continued) Spec. 2.41 2.42 2.43 2.52 2.53 2.61 Target Limits Parameter Input Impedance: Capacitance Test Conditions, Comments 1200 High Unit
Type
Input Impedance: Resistance Input Impedance: Capacitance Mixer Conversion Gain Total Gain Image Frequency Rejection Image Frequency Rejection Max. Detectable Input Signal Voltage gain: RFIN MIXOUT (pad) From RFIN DMDAT Frequency range missed Wake-Up, mod. depth Strobe control: level medium MIXOUT: gain reduced external from MIXOUT Image rejection unspecified 25°C
2.10 2.11 2.12 2.14 2.15 2.16 2.17 2.181 2.182 2.191
Mixer Output Resistance Minimum Mixer Operating Freq. Mixer Range Mixer Input: Gain Reduced Mixer AGC: Static Loop Error Mixer Attack Time Mixer Decay Rate Local Oscillator Radiation Local Oscillator Phase Noise
-100 -104.5
mV/ms dBc/Hz dBc/Hz
MIXAGC rise time <400 slope With matching network 434.37 away from L.O. away from L.O.
Desensitization Interfering Signals
Jammer level sensitivity reduced relative Pemitter -500
3.21 3.31 3.41 3.61 3.10 Gain From MIXOUT Cut-Off Freq. Cut-Off High Freq. Cut-Off Freq. Cut-Off High Freq. Cut-Off Freq. Cut-Off High Freq. Ripple Within Passband Threshold Dynamic Range Static Loop Error DMDAT Settling Time Decay Slew Rate Normal Driving MIXOUT Driving MIXOUT
Filter AGC, Detector Measured DMDAT Max. level DMDAT: constant output; input adjusted; reference C1AGC mV/ms
MOTOROLA
MC33590
ELECTRICAL CHARACTERISTICS (Operating Temperature Range -40° 85°C, Operating Frequency
433.92 MHz, Unless Otherwise Specified) (See Note (continued) Spec. 3.11 3.12 3.135 3.136 3.14 3.15 3.16 Local Oscillator Lock-In Range Local: Reference Oscillator Freq. Ratio Reference Oscillator Freq. Range Currents Maximum XTAL Series Resistance Target Limits Parameter Time Release After Faster Change Release Time Detector Output Signal Amplitude Detector Output: Level DATA1 Negative Detect Attack Time Constant Negative Detect Decay Negative Detect Hold Time Time-out when input Pass Filter Stage Filter Dynamic Range: Lower Limit Filter Dynamic Range: Upper Limit Cut-Off Frequency 25°, state machine ext. caps FCAP1 FCAP2 FCAP2: described given test conditions (freq. dependent) Digital Processing µPCLK: Reference Oscillator Freq. Ratio µPCLK Output: µPCLK Output: DATA2, DATACLK, Wake-Up Outputs: DATA1 Output: DATA2, DATACLK, Wake-Up Outputs: DATA1 Output: Strobe Control: Level Strobe Control: Medium Level Strobe Control: High Level Internal strobing Forces AWAKE; Forces Wake-Up detected µPCLK Open collector with external pull-up Sinking Internal pull-up resistance; active Internal pull-up resistance; active data freq. Test Conditions, Comments C2AGC full range sweep onset: (Vpos Vneg); modulation depth 100% NPCAP High Unit mVpk-pk mV/ms
Type
5.11 5.12
Output Impedance
6.41 6.42 6.51 6.52 6.71
MOTOROLA
MC33590
ELECTRICAL CHARACTERISTICS (Operating Temperature Range -40° 85°C, Operating Frequency
433.92 MHz, Unless Otherwise Specified) (See Note (continued) Spec. Target Limits Parameter Data Rate: FRQPIN Resistance Connect Test Conditions, Comments selection selection selection selection 6.91 6.10 Allowed High:Low Ratio Each Data Allowed High:Low Ratio Each Data Manchester coded; amplitude, RFIN. Manchester coded; amplitude, FCAP2 48:52 48:52 High 52:48 52:48 bits Unit
Type 6.12 6.12
Max. Allowed Message Length systems, >-70 RFIN; values cover oscillator errors allowed Max. Allowed Message Length systems, >-70dBm RFIN; values cover oscillator errors allowed Max. Allowed Message Length: Measured following Max. Initial Delay Between header, data rate DATA2 Mid-Bit DATACLK Falling Edge Wake-Up Word Header Word Message Word Duration Wake-Up; Active Digital Filter Clock Frequency Manchester coded Manchester coded
6.11
bits
6.12
27,29
6.13 6.14 6.141 6.16 6.19
11111
11001000 0110
fdata
NOTES: Values refer circuit shown recommended application diagram. Parameter type: 100% tested, 100% correlation tested, characterized samples, measured some samples information only, design parameter. Unless otherwise specified, parameters assume load input parallel with D.U.T. losses will need correction.
MOTOROLA
MC33590 RADIO SECTION
IMAGE CANCELLING MIXER
down conversion performed means mixers, driven parallel with phase difference. signal directly feeds mixer inputs. RFIN impedance (S11 parameter) given ANNEXE1. outputs phase-shifted relative each other through phase shift network, then summed. This structure allows rejection upper image response, typical expected rejection image noise suppressed along with image signal. mixer gain about dynamic range extended adding mixer block, which variable resistance load across mixer outputs. This load resistance value reduced times, giving range. Furthermore, diode limiter provides signal clipping mixer outputs. With this capability, signal exceed peak output. mixer action starts (typ) input level. attack time typically decay time slope around dB/ms. filter, whose behavior similar active ones, driven reference signal. center frequency, output signal this filter phase-shifted with respect input. mixer compares these signals, output represents phase error. After filtering, signal used correct bandpass center frequency. loop filter consists capacitor connected AFCCAP pin. frequency reference obtained division XTAL oscillator output. resulting bandwidth typically kHz, internal voltage gain kHz, range
DEMODULATOR
demodulation performed envelope detector, having fairly high ripple, which smoothed internal pass filter. This combination gives short delay detection, reduces overshoot loop response. Following unity gain buffer, signal available DMDAT pin.
BANDPASS FILTER
filter consists identical sections, each containing second-order bandpass filters (four cascaded two-integrator loops), respectively, centered kHz. Each filter section electrically tuned correct center frequency, preceded attenuator cell allow gain control. simple frequency locked loop used correct internal spreads. consists auxiliary bandpass
Positive Peak Detector 400K 7.5K DMDAT C2AGC
GENERATOR POS/NEG PEAK DETECTOR
This block purposes: generation voltage control amplifier gain generation reference voltage, that used data slicer. positive peak detector from DMDAT signal, charging capacitor connected C1AGC pin. threshold corresponds output level peak, giving ratio.
Fast Pre-Biasing
GEN.
C1AGC
Ref.
NPCAP 140K
Figure Generator Pos/Neg Peak Detector
ensure fast attack time, time constant charging C1AGC switched. When voltage across C1AGC below threshold level Vbe), short time constant selected. Above this threshold, longer time constant selected. When signal falls, charge C1AGC capacitor remains constant except leakage. This sustaining time determined another capacitor, connected C2AGC pin. This capacitor kept discharged long DMDAT level least peak amplitude. With lower signal, C2AGC capacitor starts charge, when voltage reaches Vbe, turns switch which connects resistors discharging both C1AGC NPCAP capacitors. typical value gives delay time. negative peak detector provides minimum value DMDAT signal, charging capacitor connected NPCAP pin. voltage reference average value between maximum value minimum demodulated signal. These positive negative peaks should correspond levels digital data stream.
MOTOROLA
MC33590
ANALOG LOWPASS FILTER
Reducing demodulated signal bandwidth improves global receiver performance filtering signal coming from detector. This lowpass filter second-order Butterworth low-pass. external capacitors connected FCAP1 FCAP2 pins define cut-off frequency. cut-off frequency adapted data rate, internally switched according FRQPIN, octave steps over range. Manchester coded data, cut-off frequency times data rate.
DATA SLICER
data slicer consists comparator, input coupled analog filter output other receives reference voltage, derived from detector provided Pos/Neg Peak detector (refer Figure output signal slew rate around mV/µs.
Reference Voltage DMDAT DATA1 NPCAP
C1AGC
Low-Pass Analog Filter
FCAP1
FCAP2
Figure Data Slicer SECTION
oscillator core two-transistor symmetrical stage, driven with maximum positive feedback. tank, defining center frequency, connected between pins OSC1 OSC2. oscillation amplitude controlled circuit, that OSC1/OSC2 voltage maintained mVpk-pk. tuning method follows: quadrature currents added in-phase flowing through OSC1 OSC2. amplitude these quadrature currents depend desired detuning, phase (anti-phase) allows frequency increased decreased). resonance, current tuning capacitor cancels that inductor. that current increased decreased) adding quadrature signals, cancellation occurs lower higher) frequency. tuning action increases tuned circuit decreases, tuning range limited maximum quadrature currents available. This allows selection between operating frequency, keeping reference XTAL oscillator frequency range MHz.
DIVIDERS
frequency then divided 5-stage circuit, giving 32-fixed division. dividers conventional circuits, identical except that bias currents reduced frequency reduces.
PHASE FREQUENCY DETECTOR
block implemented with gates. performs phase/frequency comparison reference oscillator signal divider 32-chain output. both block output frequency control input. external second-order loop filter connected this pin.
REFERENCE OSCILLATOR
total phase shift, oscillation condition, assured resonance adding on-chip off-chip (external capacitor XTAL1 pin), plus inversion amplifier. circuit controls peak voltage. internal outputs symmetrical. resistor connected between XTAL0SYS VCC, order switch internal divider from
MICROPROCESSOR CLOCK DRIVE
output drive microprocessor clock fourth reference XTAL frequency provided. Dividers similar dividers described above. output stage consists open collector circuit. Output clock signal characteristics, i.e., rise time, falling time correct, total parasitic capacitance µPCLK lower than
MOTOROLA
MC33590 DIGITAL SECTION
DIGITAL FILTER
NOTE: following description should read conjunction with block diagram (see Figure DATA1 signal, output comparator following analog filter, passes digital filter block. This up-down counter performing majority vote filter function previous values comparator output. algorithm implemented filter output counter without hysteresis. filter clock times data rate, there clock cycles each half Manchester coded bit. counter counts when input latched down when until limit counts reached, then counter clock blocked. keep reasonable delay filter presence noisy signal, last counts each range allowed. output signal used detection wake-up block. data stream from Manchester coded format used message described below. Recognition wake-up word, wake-up system. Selection best eight available data clocks, using message header. Then coded data output digital filter DATA2, selected DATACLOCK DCLK signals output data recovery microcontroller. end-of-message code must detected, before wake-up header sequence treated. not, time-out counter will reset system sleep mode.
CLOCKS GENERATION
This block generates clocks required exact sub-multiple XTAL oscillator frequency. Eight clocks generated, having exactly same frequency, being equally spaced in-phase. operational flexibility data rate selection, four different data frequencies selected connecting FRQPIN ground different resistor values. This input then converted into internal digital control signals. Figure shows clock generation diagram.
WAKE-UP DETECTION
This block three purposes: recognition 8-bit wake-up word, present data; header detection; selection DATACLOCK, synchronous with this message header. This clock will used recover
µPCLK Drive
Clock
433/315 System Selection
Internal Clock
Data Rate Selection
DATACLOCK Generator
DATACLOCK
Figure Generation Clocks BANDGAP REFERENCE
This block contains internal voltage reference having bandgap structure. This bandgap controlled external resistor REXT, REXT pin. Parasitic capacitance REXT should minimized, values above cause instability. bandgap voltage required noise-free radio section, copied onto RFBIAS pass filter. internal resistor, external capacitor connected RFBIAS pin. This block operates long voltage applied.
MOTOROLA
MC33590
STROBE OSCILLATOR TIMER
strobe oscillator operates successively charging discharging capacitor connected CEXT pin. CEXT voltage sensed comparator, whose threshold voltage switched according charge- discharge state. peak-to-peak signal CEXT about oscillator period defined following formula: Period CEXT REXT V/Vbg (35/40) Rdis CEXT (V1/V2) where: V1and upper lower threshold voltages, bandgap voltage, REXT, CEXT external resistor capacitor, and, Rdis strobe oscillator discharge resistance, typically timer counter operating strobe oscillator frequency. controls wake/sleep timing entire circuit until valid wake-up word detected, then controls time-out after valid wake-up recognition. main part 9-bit ripple counter. Five bits this counter used wake/sleep ratio, metal mask sets divider last part counter time-out section, which gives seven, depending counter uncertainty) sleep/wake cycles after awake signal, when valid wake-up identified. example, with strobe clock, normal cycle wake, sleep, with time-out ms). start-up block generates signals which allow sequential start-up various mixer blocks, after crystal oscillator started (i.e., after clocks this block start working). start-up sequence blocks first switched except block, which switched clock cycle later. reason when XTAL oscillator running (initial start-up case) clock generated block does frequency reference. Analog blocks switched only when frequency reference present. NOTE: Some figures given description, time constants time periods, dependent component values application.
MOTOROLA
MC33590 COMMUNICATION PROTOCOL
MANCHESTER CODING DESCRIPTION
Manchester coding used this device defined follows. Data sent during first half-bit. Complementary data sent during second half-bit.
Original Signal Manchester Encoded
Figure
Consequently, there single transition bit, average voltage value constant. This allows clock recover from data stream itself. Considered transmitter side, means that average consumption power also constant, C.W. signal. This coding allows suppression, transfer truly coupled. This allows long series consecutive correctly recovered data comparator.
settle. preamble content must carefully defined order decoded wake-up header word data rate). followed preamble recommended. preamble data rate critical four possible header word 4-bit Manchester coded (metal masked) message 0110 sent desired data rate. decoding clocks have correct data rate, means FRQPIN control. wake-up word, preamble least bits recommended. Data sent after header. Then, end-of-message word, consisting five sent. There gaps inside data stream, complete message, i.e., header, data, end-of-message bits have coded synchronously with transmitter master DATACLOCK. Another complete message follow immediately, eventually coded different data rate, least wake-up word sent first, resetting time-out counter.
WAKE-UP HEADER PREAMBLES
following example (see Figure wake-up word, header word followed data bits, then five end-of-message shown, preamble bits placed beginning both wake-up header words. These preambles required only when period between consecutive messages becomes greater than receiver release time constant. not, preambles just recommended.
Bits Header Data Bits Bits DATA1
WAKE-UP, HEADER WORDS, MESSAGE DESCRIPTION
wake-up word 8-bit Manchester coded (metal masked) message 11001000 sent data rate kbits/s. preamble least bits recommended before wake-up word, allow enough time
Preamble Bits Wake-Up Preamble
Figure Wake-Up Headers with Preambles MESSAGE PROTOCOL
case where receiver continuously sleep/ awake cycling, wake-up message burst recognized receiver. Consequently, burst length long enough include consecutive receiver awake cycles. Refer Figure After wake-up recognition, digital block sends wake-up pulse both Wake-Up DATA2 pins order wake microcontroller. Consequently, least break necessary message between last wake-up word beginning header word.
Signal
Wake-Up Words kbits/s Awake Asleep
Header
Data
Message
Wake-Up Detected State Machine
Figure Typical Telegram
MOTOROLA
MC33590
RECEIVER START-UP DELAY
When strobe oscillator awakes radio blocks, some delay necessary XTAL oscillator start-up, then acquire lock condition, finally block, AGC, demodulator stages stabilized. This delay typically lower than around 25°C. Consequentially, start-up time decreases available awake cycle approximately This means that least complete wake-up word received during this time window. Figure shows typical wake-up frame receiver sleep/awake case.
Awake Sleep Start-Up Delay Wake- Wake- Wake- Wake- Wake- Sleep
MICROCONTROLLER SIGNAL INTERFACE
Four digital outputs available ensure communication between receiver microcontroller port. Figure shows example these signals. When successful, wake-up complete message received.
Figure
Preamble
Bits Wake-Up
Preamble
Bits Header
Data Bits
Bits DATA1 Wake-Up DATA2 DATACLK
Figure
MOTOROLA
MC33590 STATE MACHINE DESCRIPTION SECTION
QUICK DESCRIPTION
state machine describes receiver behavior various possible situation cases. Following explanation different states, associated transitions between them. This also refers corresponding state diagram (Figure
Power-On Sleep Mode Activate Strobe Strobe Counter Running Strobe Counter Reset Strobe Counter Strobe Strobe
Strobe Counter
STATE Awake Mode Waiting Wake-Up Code
Strobe
Wake-Up Message Identified Wake-Up Message Identified STATE Reset Time-out Send Wake-Up Pulse Activate Clock Time-out STATE Clock Activated Waiting Wake-Up Code Time-Out After Clock Period Lowest Data Rate STATE Select Data Rate Activate Clock Waiting Header Header Received STATE Output Selected Clock Output Recovered Data Waiting E-of-M End-of-Message Received Strobe
Time-Out
Strobe
Strobe
Figure STATE
Imposed power-on reset every time circuit wakes circuit searching valid 8-bit wake-up message. valid wake-up word identified, state machine advances State not, will back into sleep mode strobe period.
STATE
valid wake-up been found time-out counter activated. clock output activated. wake-up pulse sent microcontroller. Then state machine advances State (always).
MOTOROLA
MC33590
STATE
circuit searching valid 4-bit header, selects best DATACLOCK phase with received header word. valid header word identified, state machine advances State not, will back into sleep mode time-out. this 1/1000 clock difference transmit/receive data rate single message, message length limited about bits case (and about bits case).
STATE
This state similar State except microcontroller clock output kept activated.
STATE STATES
header been found. Data clock signals sent decoding, until sequence four indicates that data sequence ended circuit should return State receiver higher than transmitted about 1/1000 case) same divider ratio used generate data clocks both transmitter receiver, frequency receiver clocks DCLK (8:1) 1000 higher than data rate from transmitter.
Preamble Data Clock
time circuit fall back sleep mode time-out.
STATE MACHINE DETAILED DESCRIPTION State
wake-up code specified following Manchester coded message (see Figure 10).
Bits Wake-Up
Figure
Below four possible clocks generated internally, with phase shift relative each other, with random phase with respect transmitted signal. filtered data clocked along each register four dephased clocks. Note that here, only four eight clocks generated used, shift registers configured four parallel 8-bit shift registers. wake-up message always sent highest four possible data rates (approximately kHz),
DATA
clocks always this frequency, irrespective data frequency chosen with FRQPIN. Data sampled falling edge four clocks. following example (see Figure 11), registers clocked DCLK1 DCLK3 would identify wake-up, others would complement. happen that only register sees wake-up word, clock preceding/following register falls sufficiently near edge data transition.
DCLK1 DCLK3 DCLK5 DCLK7
Figure
best noise immunity minimum false wake-ups, incoming signal considered contain valid wake-up, register sees wake-up word opposite register sees complement (when looking wake-up, phase relative receiver clocks important). When wake-up found, state machine passes State
State
When entering this state, time-out part strobe counter activated. This counter will count seven) times natural sleep-awake period (called period). whole digital part forced lowest clock frequency, i.e., kbits/s. wake-up pulse sent
MOTOROLA
MC33590
Wake-Up DATA2 output. wake-up pulse duration clock pulse, typically following clock pulse, state machine passes State general, four eight DCLKs detect header. necessary know which DCLKs have found header, since they used clock data, which synchronized with message following header. second last valid DCLK output DATACLOCK signal. more clocks eligible. second last clock compromise choice, selecting last data clock would ideal dangerous, since close edge data. header word 0110 Manchester coded. DATA2 DATACLK outputs enabled. next clock cycle state machine advances State
State
Entering State enables µPCLK output, reconfigures registers eight 4-bit registers. allowed output clock frequency selected according FRQPIN current. 4-bit header searched for, same wake-up State header valid complement must also detected opposite register.
DATA Selected Clock DCLK1 DCLK2 DCLK3 DCLK4 DCLK5 Eligible Clocks DCLK6 DCLK7 DCLK8
Figure State
DATA2 DATACLK outputs enabled. desired send messages longer than those permitted transmitter/receiver clock drifts (roughly bits operation), receiver clock must resynchronized. Four sent, then state machine passes back State deselecting selected clocks. Then simplified wake-up/header sequence (i.e., only wake-up word) sent allow block data. Otherwise, long data received (and time-out) circuit stays State enabling DATA2 DATACLK outputs permitted when entering State using selected clock from header. first four bits message header 0110, during fifth that falling edge selected clock advances state machine into State Therefore, some part fifth always passed time DATA2 DATACLK outputs enabled. correct value value DATA2 falling edge DATACLK. case fifth bit, uncertainty could occur. user's choice manage with this uncertainty, begin message sixth bit.
Miscellaneous Information
DATA1 output always allowed. high:low ratio DATACLOCK, when active, 1:15. test mode implemented Wake-Up pin. This function activated when voltage equal higher than recommend take care application layout, minimize crosstalks between digital outputs.
MOTOROLA
MC33590 SCHEMATICS
Name
RFBIASDC
from
MIXAGC
from MIXER OUTPUT
MIXOUT
C1AGC
C2AGC
MOTOROLA
MC33590
Name
140K
AFCCAP
DMDAT
FCAP1/
XTAL1
XTAL0SYS
Mode Test
MOTOROLA
MC33590
Name
OSC1/2
0.5p
DGND1/2
122K
122K
FRQPIN
when Wake- detecte
µPCLK
DATA1
MOTOROLA
MC33590
Name
WAKE-UP DATACLK DATA2
STROB
104K
150K
MOTOROLA
MC33590 APPLICATION DIAGRAM
DATA1 DATACLK DATA2 Wake-Up CEXT REXT Strobe DATACLK DATA1 INPUT MATCH CLKGND Wake-Up DATA2 Strobe
433MHz ANTENNA
VCCR
UPCLK
µPCLK FRQPIN
RFBIASDC RFIN RFDEC MIXAGC MIXOUT RGND NPCAP AFCCAP DMDAT FCAP1 C2AGC FCAP2 XTAL1 C1AGC
FRQPIN DGND2 OSC2 OSC1 DGND1 XTAL0SYS VCCD
OPTIONAL FILTER*
XTAL
DATA FILTER Depending System performance requirements
315MHz Option
COMPONENT VALUES
Component XTAL C5,C6 Function tank coil tank capacitor loop filter loop filter loop filter operation Reference oscillator crystal XTAL load capacitor Lowpass filter loop filter Value 13.574 Unit Component C19,C16 Function NPCAP capacitor time-out capacitor Main capacitor MIXAGC capacitor RFDEC decoupling RFBIAS decoupling Strobe oscillator Current reference Strobe decoupling decoupling Value Unit
NOTE: Specific components: capacitor recommended with leakage (i.e., mylar). capacitor recommended with tolerance. resistor recommended with tolerance. following table gives component values 433.92 315.00 applications.
Inductor References MLR1608M39NJT ±10%; MHz; (433.92 application). MLR1608M47NJT ±10%; MHz; (315.00 application). Crystal Specifications
433.92 Coil XTAL Freq. ±10% 13.5740
315.00 47nH ±10% 9.8578
13.5740 crystal used characterization total load capacitance, frequency tolerance ppm. 9.8578 crystal used characterization total load capacitance, frequency tolerance ppm.
MOTOROLA
MC33590 ANNEXE INPUT PARAMETER
Below typical values input referenced equivalent parallel network devices
Frequency (MHz) Reflexion Coefficient Real 0.8867 0.8771 0.8779 0.8668 0.8575 0.8473 0.8466 0.8371 0.8345 0.8212 0.8186 0.8075 0.7999 0.7917 0.7828 0.7798 0.776 0.7619 0.7489 0.7447 0.7385 0.7295 0.7174 0.7086 0.7025 0.6922 0.6823 0.6724 0.669 0.6598 0.6485 0.636 0.6218 0.615 0.6097 0.6008 0.5914 0.58 0.5703 0.5634 0.5521 0.5436
average, ambient temperature, RFDEC decoupled ground with nF).
1948.8 1726.6 1880 1623.8 1477 1396.1 1485.9 1388.7 1383.6 1189.7 1207.1 1148.3 1065.4 1075.7 997.3 992.6 998.1 861.6 842.2 849.8 806.1 722.9 712.7 689.2 660.6 633.1 634.6 590.6 558.1 520.8 516.7 511.9 495.2 478.5 453.5 445.1 432.3 418.8 410.1 (pF) 2.57 2.56 2.54 2.53 2.53 2.57 2.56 2.57 2.54 2.52 2.51 2.54 2.51 2.55 2.53 2.49 2.54 2.51 2.52 2.51 2.51 2.51 2.51 2.52 2.52 2.52 2.49 2.51 2.52 2.52 2.52 2.51 2.51 2.51 2.51 2.49 2.51
Reflexion Coefficient Imaginary -0.3456 -0.3536 -0.3632 -0.3704 -0.3783 -0.3929 -0.4038 -0.4143 -0.4191 -0.4228 -0.4304 -0.444 -0.4459 -0.4626 -0.4658 -0.4704 -0.4778 -0.4836 -0.4973 -0.4998 -0.5112 -0.5156 -0.518 -0.5261 -0.5322 -0.5403 -0.5456 -0.5505 -0.5556 -0.5587 -0.5676 -0.5714 -0.5738 -0.5803 -0.5846 -0.5877 -0.5908 -0.5914 -0.598 -0.5986 -0.6033 -0.6074
MOTOROLA
MC33590
Frequency (MHz) Reflexion Coefficient Real 0.5355 0.53 0.5209 0.5078 0.5001 0.4936 0.485 0.4771 0.4638 Reflexion Coefficient Imaginary -0.6115 -0.6121 -0.615 -0.6166 -0.619 -0.622 -0.6235 -0.624 -0.6241 402.6 394.3 366.6 358.9 354.2 344.9 335.8 320.2 (pF) 2.49 2.49 2.49 2.49 2.48 2.48 2.47 2.48
MOTOROLA
MC33590
PACKAGE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 873A (TQFP-32) ISSUE
0.20 (0.008)
DETAIL
DETAIL
0.20 (0.008)
-AB-
SEATING PLANE
DETAIL
-AC-
BASE METAL
0.20 (0.008)
0.10 (0.004)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE -AB- LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -T-, -U-, DETERMINED DATUM PLANE -AB-. DIMENSIONS DETERMINED SEATING PLANE -AC-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.250 (0.010) SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -AB-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.520 (0.020). MINIMUM SOLDER PLATE THICKNESS SHALL 0.0076 (0.0003). EXACT SHAPE EACH CORNER VARY FROM DEPICTION. MILLIMETERS 7.000 3.500 7.000 3.500 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 0.050 0.150 0.090 0.200 0.500 0.700 0.090 0.160 0.400 0.150 0.250 9.000 4.500 9.000 4.500 0.200 1.000 INCHES 0.276 0.138 0.276 0.138 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 0.002 0.006 0.004 0.008 0.020 0.028 0.004 0.006 0.016 0.006 0.010 0.354 0.177 0.354 0.177 0.008 0.039
SECTION AE-AE
DETAIL
GAUGE PLANE
0.250 (0.010)
MOTOROLA
-T-, -U-,
MC33590
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MOTOROLA
MC33590/D

Tuned Receiver Data Transfer Applications (U.S.) (Europe) Applica

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