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Product Preview 2.5/3.3V Differential LVPECL Clock Switch Fanout Buffer
Motorola MC100ES6254 bipolar monolithic differential clock switch fanout buffer. Designed most demanding clock distribution systems, MC100ES6254 supports various applications that require drive precisely aligned clock signals. device capable driving switching differential LVPECL signals. Using SiGe technology fully differential architecture, device offers superior digitial signal characteristics very clock skew error. Target applications this clock driver high performance clock/data switching, clock distribution data loopback computing, networking telecommunication systems. Features: Fully differential architecture from input outputs
MC100ES6254
2.5V/3.3V DIFFERENTIAL LVPECL CLOCK SWITCH FANOUT BUFFER
SiGe technology supports near-zero output skew Supports 3GHz operation1 clock data signals LVPECL compatible differential clock inputs outputs LVCMOS compatible control inputs Single 3.3V 2.5V supply maximum output skew (within output bank)1 maximum device skew1
SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Synchronous output enable eliminating output runt pulse generation metastability Standard lead LQFP package
Industrial temperature range Functional Description MC100ES6254 designed very skew critical differential clock distribution systems supports clock frequencies from GHz. Typical applications MC100ES6254 primary clock distribution, switching loopback systems high-performance computer, networking telecommunication systems, well on-board clocking OC-3, OC-12 OC-48 speed communication systems. Primary purpose MC100ES6254 high-speed clock switching applications. addition, MC100ES6254 configured single dual LVPECL fanout buffer clock signals, loopback device high-speed data applications. MC100ES6254 operated from 3.3V 2.5V positive supply without requirement negative supply line.
specifications design targets subject change
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
09/01
Motorola, Inc. 2001
MC100ES6254
CLK0 CLK0
Bank
CLK1 CLK1 SEL0 SEL1
Bank
Sync
Figure MC100ES6254 Logic Diagram
CLK0
CLK0
SEL0
MC100ES6254 (Pinout subject change)
SEL1
CLK1
Figure 32-Lead Package Pinout (Top View)
CLK1
TIMING SOLUTIONS
MC100ES6254
TABLE CONFIGURATION
CLK0, CLK0 CLK1, CLK1 OEA, SEL0, SEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] Input Input Input Input Output Supply Supply Type LVPECL LVPECL LVCMOS LVCMOS LVPECL Differential reference clock signal input Differential reference clock signal input Output enable Clock switch select Differential clock outputs (banks Negative power supply Positive power supply. pins must connected positive power supply correct operation Function
TABLE FUNCTION TABLE
Control Default QA[0-2], Qx[0-2] active. Deassertion asynchronous reference clock without generation output runt pulses QA[0-2], Qx[0-2] active. Deassertion asynchronous reference clock without generation output runt pulses QA[0-2] QA[0-2] (outputs disabled). Assertion asynchronous reference clock without generation output runt pulses QA[0-2] QA[0-2] (outputs disabled). Assertion asynchronous reference clock without generation output runt pulses
SEL0, SEL1
Following Table
TABLE CLOCK SELECT CONTROL
SEL0
SEL1
CLK0 routed
CLK1 routed
Application Mode fanout CLK0 fanout CLK1 Dual buffer Dual buffer (crossed)
QA[0:2] QB[0:2] QA[0:2] QB[0:2]
QA[0:2] QB[0:2] QB[0:2] QA[0:2]
TABLE ABSOLUTE MAXIMUM RATINGSa
Symbol VOUT IOUT Supply Voltage Input Voltage Output Voltage Input Current Output Current Storage temperature Characteristics -0.3 -0.3 -0.3 VCC+0.3 VCC+0.3 Unit Condition
Absolute maximum continuous ratings those maximum values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation absolute-maximum-rated conditions implied.
TIMING SOLUTIONS
MC100ES6254
TABLE GENERAL SPECIFICATIONS
Symbol Thermal resistance junction ambient JESD 51-3, single layer test board Characteristics Output termination voltage Protection (Machine model) Protection (Human body model) Protection (Charged device model) Latch-up immunity 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Inputs Natural convection ft/min ft/min ft/min ft/min Natural convection ft/min ft/min ft/min ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
Thermal resistance junction case Operating junction temperatureb (continuous operation) MTBF years
Output termination voltage VCC=2.5V operation supported power consumption device will increase. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should selected according application life time requirements (See application note AN1545 more information). device parameters specified 110°C junction temperature allowing MC100ES6254 used applications requiring industrial temperature range. recommended that users MC100ES6254 employ thermal modeling analysis assist applying junction temperature specifications their particular application.
TABLE CHARACTERISTICS (VCC 3.3V 2.5V +110°C)a
Symbol Characteristics Unit Condition LVCMOS control inputs (OEA, OEB, SEL0, SEL1) VCMR IGND Input voltage Input voltage high Input Currentb CLK1)c VCC-0.3 ±TBD VCC-1.005 VCC-1.705 Termination Termination Pins Differential operation Differential operation differential input voltaged Differential cross point Input high voltage Input voltage Input Current voltagee ±TBD
LVPECL clock inputs (CLK0, CLK0, CLK1,
LVPECL clock outputs (QA0-2, QA0-2, QB0-2, QB0-2) Output High Voltage Output Voltage Maximum Quiescent Supply Current without output termination current Maximum Quiescent Supply Current, outputs terminated
characterisitics design targets pending characterization. Input have internal pullup/pulldown resistors which affect input current. Clock inputs driven LVPECL compatible signals. minimum differential input voltage swing required maintain characteristic. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification.
TIMING SOLUTIONS
MC100ES6254
TABLE CHARACTERISTICS (VCC 3.3V 2.5V +110°C)a
Symbol VCMR VO(P-P) Characteristics Differential input voltagec (peak-to-peak) Differential input crosspoint voltaged Differential output voltage (peak-to-peak) Input Frequency Propagation Delay CLKX QA[] QB[] Output-to-output skew Output-to-output skew Output cycle-to-cycle jitter Output duty cycle Output Rise/Fall Time Output disable time Output enable time (within bank) (within device) (part-to-part) (SEL0 0.05 2.5T 0-3000 VCC-0.3 3.5T Unit Differential Differential Differential Differential Differential DCfref= T=CLK period T=CLK period Condition
fCLK tsk(O) tsk(PP) tJIT(CC) tPDLe tPLDf
characterisitics design targets pending characterization. characteristics apply parallel output termination VTT. minimum differential input voltage swing required maintain characteristics including device-to-device skew. VCMR (AC) crosspoint differential input signal. Normal operation obtained when crosspoint within VCMR (AC) range input swing lies within (AC) specification. Violation VCMR (AC) (AC) impacts device propagation delay, device part-to-part skew. Propagation delay deassertion differential output disabled (differential low: true output low, complementary output high). Propagation delay assertion output enabled (active).
CLKX CLKX
Qx[] Qx[] tPDL (OEX Qx[]) tPLD (OEX Qx[]) Outputs disabled
Figure MC100ES6254 output disable/enable timing
Differential Pulse Generator
MC100ES6254
Figure MC100ES6254 test reference
TIMING SOLUTIONS
MC100ES6254
APPLICATIONS INFORMATION
Example Configurations
clock switch CLK0 CLK1 SEL0 SEL1 MC100ES6254 SEL0 SEL1 Switch configuration CLK0 clocks system system CLK1 clocks system system CLK0 clocks system CLK1 clocks system CLK1 clocks system CLK1 clocks system System
System
Maintaining Lowest Device Skew MC100ES6254 guarantees output-to-output bank skew part-to-part skew max. ensure skew clock signals application, both outputs differential output pair need terminated identically, even only output used. When fewer than nine output pairs used, identical termination output pairs within output bank recommended. entire output bank used, recommended leave these outputs open unterminated. This will reduce device power consumption while maintaining minimum output skew. Power Supply Bypassing MC100ES6254 mixed analog/digital product. differential architecture MC100ES6254 supports noise signal operation high frequencies. order maintain superior signal quality, pins should bypassed high-frequency ceramic capacitors connected GND. spectral frequencies internally generated switching noise supply pins cross series resonant point individual bypass capacitor, overall impedance begins look inductive thus increases with increasing frequency. parallel capacitor combination shown ensures that impedance path ground exists frequencies well above noise bandwidth.
Clock Fanout Buffer CLK0 CLK1 SEL0 SEL1 MC100ES6254
33.100
MC100ES6254
Loopback device System-Tx CLK0 SEL0 SEL1 System-Rx QB[] CLK1 Receiver QA[] Transmitter
Figure Power Supply Bypass
Pending final characterization
MC100ES6254 SEL0 SEL1 Switch configuration System loopback Line loopback Transmit Receive operation System line loopback
TIMING SOLUTIONS
MC100ES6254
OUTLINE DIMENSIONS
SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE
0.20 (0.008)
DETAIL
DETAIL
0.20 (0.008)
DETAIL -AB-
SEATING PLANE
-AC-
BASE METAL
SECTION AE-AE
DETAIL
TIMING SOLUTIONS
GAUGE PLANE
0.250 (0.010)
0.20 (0.008)
0.10 (0.004)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE -AB- LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -T-, -U-, DETERMINED DATUM PLANE -AB-. DIMENSIONS DETERMINED SEATING PLANE -AC-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.250 (0.010) SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -AB-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.520 (0.020). MINIMUM SOLDER PLATE THICKNESS SHALL 0.0076 (0.0003). EXACT SHAPE EACH CORNER VARY FROM DEPICTION. MILLIMETERS 7.000 3.500 7.000 3.500 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 0.050 0.150 0.090 0.200 0.500 0.700 0.090 0.160 0.400 0.150 0.250 9.000 4.500 9.000 4.500 0.200 1.000 INCHES 0.276 0.138 0.276 0.138 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 0.002 0.006 0.004 0.008 0.020 0.028 0.004 0.006 0.016 0.006 0.010 0.354 0.177 0.354 0.177 0.008 0.039
-T-, -U-,
MC100ES6254
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. 2001. reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
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